hypercalls.c 9.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* hypercalls: Check the ARM64's psuedo-firmware bitmap register interface.
  3. *
  4. * The test validates the basic hypercall functionalities that are exposed
  5. * via the psuedo-firmware bitmap register. This includes the registers'
  6. * read/write behavior before and after the VM has started, and if the
  7. * hypercalls are properly masked or unmasked to the guest when disabled or
  8. * enabled from the KVM userspace, respectively.
  9. */
  10. #include <errno.h>
  11. #include <linux/arm-smccc.h>
  12. #include <asm/kvm.h>
  13. #include <kvm_util.h>
  14. #include "processor.h"
  15. #define FW_REG_ULIMIT_VAL(max_feat_bit) (GENMASK(max_feat_bit, 0))
  16. /* Last valid bits of the bitmapped firmware registers */
  17. #define KVM_REG_ARM_STD_BMAP_BIT_MAX 0
  18. #define KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX 0
  19. #define KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_MAX 1
  20. #define KVM_REG_ARM_VENDOR_HYP_BMAP_2_BIT_MAX 1
  21. #define KVM_REG_ARM_STD_BMAP_RESET_VAL FW_REG_ULIMIT_VAL(KVM_REG_ARM_STD_BMAP_BIT_MAX)
  22. #define KVM_REG_ARM_STD_HYP_BMAP_RESET_VAL FW_REG_ULIMIT_VAL(KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX)
  23. #define KVM_REG_ARM_VENDOR_HYP_BMAP_RESET_VAL FW_REG_ULIMIT_VAL(KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_MAX)
  24. #define KVM_REG_ARM_VENDOR_HYP_BMAP_2_RESET_VAL 0
  25. struct kvm_fw_reg_info {
  26. uint64_t reg; /* Register definition */
  27. uint64_t max_feat_bit; /* Bit that represents the upper limit of the feature-map */
  28. uint64_t reset_val; /* Reset value for the register */
  29. };
  30. #define FW_REG_INFO(r) \
  31. { \
  32. .reg = r, \
  33. .max_feat_bit = r##_BIT_MAX, \
  34. .reset_val = r##_RESET_VAL \
  35. }
  36. static const struct kvm_fw_reg_info fw_reg_info[] = {
  37. FW_REG_INFO(KVM_REG_ARM_STD_BMAP),
  38. FW_REG_INFO(KVM_REG_ARM_STD_HYP_BMAP),
  39. FW_REG_INFO(KVM_REG_ARM_VENDOR_HYP_BMAP),
  40. FW_REG_INFO(KVM_REG_ARM_VENDOR_HYP_BMAP_2),
  41. };
  42. enum test_stage {
  43. TEST_STAGE_REG_IFACE,
  44. TEST_STAGE_HVC_IFACE_FEAT_DISABLED,
  45. TEST_STAGE_HVC_IFACE_FEAT_ENABLED,
  46. TEST_STAGE_HVC_IFACE_FALSE_INFO,
  47. TEST_STAGE_END,
  48. };
  49. static int stage = TEST_STAGE_REG_IFACE;
  50. struct test_hvc_info {
  51. uint32_t func_id;
  52. uint64_t arg1;
  53. };
  54. #define TEST_HVC_INFO(f, a1) \
  55. { \
  56. .func_id = f, \
  57. .arg1 = a1, \
  58. }
  59. static const struct test_hvc_info hvc_info[] = {
  60. /* KVM_REG_ARM_STD_BMAP */
  61. TEST_HVC_INFO(ARM_SMCCC_TRNG_VERSION, 0),
  62. TEST_HVC_INFO(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND64),
  63. TEST_HVC_INFO(ARM_SMCCC_TRNG_GET_UUID, 0),
  64. TEST_HVC_INFO(ARM_SMCCC_TRNG_RND32, 0),
  65. TEST_HVC_INFO(ARM_SMCCC_TRNG_RND64, 0),
  66. /* KVM_REG_ARM_STD_HYP_BMAP */
  67. TEST_HVC_INFO(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_HV_PV_TIME_FEATURES),
  68. TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_FEATURES, ARM_SMCCC_HV_PV_TIME_ST),
  69. TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_ST, 0),
  70. /* KVM_REG_ARM_VENDOR_HYP_BMAP */
  71. TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_KVM_FEATURES_FUNC_ID,
  72. ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID),
  73. TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID, 0),
  74. TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID, KVM_PTP_VIRT_COUNTER),
  75. };
  76. /* Feed false hypercall info to test the KVM behavior */
  77. static const struct test_hvc_info false_hvc_info[] = {
  78. /* Feature support check against a different family of hypercalls */
  79. TEST_HVC_INFO(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID),
  80. TEST_HVC_INFO(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_TRNG_RND64),
  81. TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_FEATURES, ARM_SMCCC_TRNG_RND64),
  82. };
  83. static void guest_test_hvc(const struct test_hvc_info *hc_info)
  84. {
  85. unsigned int i;
  86. struct arm_smccc_res res;
  87. unsigned int hvc_info_arr_sz;
  88. hvc_info_arr_sz =
  89. hc_info == hvc_info ? ARRAY_SIZE(hvc_info) : ARRAY_SIZE(false_hvc_info);
  90. for (i = 0; i < hvc_info_arr_sz; i++, hc_info++) {
  91. memset(&res, 0, sizeof(res));
  92. do_smccc(hc_info->func_id, hc_info->arg1, 0, 0, 0, 0, 0, 0, &res);
  93. switch (stage) {
  94. case TEST_STAGE_HVC_IFACE_FEAT_DISABLED:
  95. case TEST_STAGE_HVC_IFACE_FALSE_INFO:
  96. __GUEST_ASSERT(res.a0 == SMCCC_RET_NOT_SUPPORTED,
  97. "a0 = 0x%lx, func_id = 0x%x, arg1 = 0x%lx, stage = %u",
  98. res.a0, hc_info->func_id, hc_info->arg1, stage);
  99. break;
  100. case TEST_STAGE_HVC_IFACE_FEAT_ENABLED:
  101. __GUEST_ASSERT(res.a0 != SMCCC_RET_NOT_SUPPORTED,
  102. "a0 = 0x%lx, func_id = 0x%x, arg1 = 0x%lx, stage = %u",
  103. res.a0, hc_info->func_id, hc_info->arg1, stage);
  104. break;
  105. default:
  106. GUEST_FAIL("Unexpected stage = %u", stage);
  107. }
  108. }
  109. }
  110. static void guest_code(void)
  111. {
  112. while (stage != TEST_STAGE_END) {
  113. switch (stage) {
  114. case TEST_STAGE_REG_IFACE:
  115. break;
  116. case TEST_STAGE_HVC_IFACE_FEAT_DISABLED:
  117. case TEST_STAGE_HVC_IFACE_FEAT_ENABLED:
  118. guest_test_hvc(hvc_info);
  119. break;
  120. case TEST_STAGE_HVC_IFACE_FALSE_INFO:
  121. guest_test_hvc(false_hvc_info);
  122. break;
  123. default:
  124. GUEST_FAIL("Unexpected stage = %u", stage);
  125. }
  126. GUEST_SYNC(stage);
  127. }
  128. GUEST_DONE();
  129. }
  130. struct st_time {
  131. uint32_t rev;
  132. uint32_t attr;
  133. uint64_t st_time;
  134. };
  135. #define STEAL_TIME_SIZE ((sizeof(struct st_time) + 63) & ~63)
  136. #define ST_GPA_BASE (1 << 30)
  137. static void steal_time_init(struct kvm_vcpu *vcpu)
  138. {
  139. uint64_t st_ipa = (ulong)ST_GPA_BASE;
  140. unsigned int gpages;
  141. gpages = vm_calc_num_guest_pages(VM_MODE_DEFAULT, STEAL_TIME_SIZE);
  142. vm_userspace_mem_region_add(vcpu->vm, VM_MEM_SRC_ANONYMOUS, ST_GPA_BASE, 1, gpages, 0);
  143. vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PVTIME_CTRL,
  144. KVM_ARM_VCPU_PVTIME_IPA, &st_ipa);
  145. }
  146. static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu)
  147. {
  148. uint64_t val;
  149. unsigned int i;
  150. int ret;
  151. for (i = 0; i < ARRAY_SIZE(fw_reg_info); i++) {
  152. const struct kvm_fw_reg_info *reg_info = &fw_reg_info[i];
  153. uint64_t set_val;
  154. /* First 'read' should be the reset value for the reg */
  155. val = vcpu_get_reg(vcpu, reg_info->reg);
  156. TEST_ASSERT(val == reg_info->reset_val,
  157. "Unexpected reset value for reg: 0x%lx; expected: 0x%lx; read: 0x%lx",
  158. reg_info->reg, reg_info->reset_val, val);
  159. if (reg_info->reset_val)
  160. set_val = 0;
  161. else
  162. set_val = FW_REG_ULIMIT_VAL(reg_info->max_feat_bit);
  163. ret = __vcpu_set_reg(vcpu, reg_info->reg, set_val);
  164. TEST_ASSERT(ret == 0,
  165. "Failed to %s all the features of reg: 0x%lx; ret: %d",
  166. (set_val ? "set" : "clear"), reg_info->reg, errno);
  167. val = vcpu_get_reg(vcpu, reg_info->reg);
  168. TEST_ASSERT(val == set_val,
  169. "Expected all the features to be %s for reg: 0x%lx",
  170. (set_val ? "set" : "cleared"), reg_info->reg);
  171. /*
  172. * If the reg has been set, clear it as test_fw_regs_after_vm_start()
  173. * expects it to be cleared.
  174. */
  175. if (set_val) {
  176. ret = __vcpu_set_reg(vcpu, reg_info->reg, 0);
  177. TEST_ASSERT(ret == 0,
  178. "Failed to clear all the features of reg: 0x%lx; ret: %d",
  179. reg_info->reg, errno);
  180. }
  181. /*
  182. * Test enabling a feature that's not supported.
  183. * Avoid this check if all the bits are occupied.
  184. */
  185. if (reg_info->max_feat_bit < 63) {
  186. ret = __vcpu_set_reg(vcpu, reg_info->reg, BIT(reg_info->max_feat_bit + 1));
  187. TEST_ASSERT(ret != 0 && errno == EINVAL,
  188. "Unexpected behavior or return value (%d) while setting an unsupported feature for reg: 0x%lx",
  189. errno, reg_info->reg);
  190. }
  191. }
  192. }
  193. static void test_fw_regs_after_vm_start(struct kvm_vcpu *vcpu)
  194. {
  195. uint64_t val;
  196. unsigned int i;
  197. int ret;
  198. for (i = 0; i < ARRAY_SIZE(fw_reg_info); i++) {
  199. const struct kvm_fw_reg_info *reg_info = &fw_reg_info[i];
  200. /*
  201. * Before starting the VM, the test clears all the bits.
  202. * Check if that's still the case.
  203. */
  204. val = vcpu_get_reg(vcpu, reg_info->reg);
  205. TEST_ASSERT(val == 0,
  206. "Expected all the features to be cleared for reg: 0x%lx",
  207. reg_info->reg);
  208. /*
  209. * Since the VM has run at least once, KVM shouldn't allow modification of
  210. * the registers and should return EBUSY. Set the registers and check for
  211. * the expected errno.
  212. */
  213. ret = __vcpu_set_reg(vcpu, reg_info->reg, FW_REG_ULIMIT_VAL(reg_info->max_feat_bit));
  214. TEST_ASSERT(ret != 0 && errno == EBUSY,
  215. "Unexpected behavior or return value (%d) while setting a feature while VM is running for reg: 0x%lx",
  216. errno, reg_info->reg);
  217. }
  218. }
  219. static struct kvm_vm *test_vm_create(struct kvm_vcpu **vcpu)
  220. {
  221. struct kvm_vm *vm;
  222. vm = vm_create_with_one_vcpu(vcpu, guest_code);
  223. steal_time_init(*vcpu);
  224. return vm;
  225. }
  226. static void test_guest_stage(struct kvm_vm **vm, struct kvm_vcpu **vcpu)
  227. {
  228. int prev_stage = stage;
  229. pr_debug("Stage: %d\n", prev_stage);
  230. /* Sync the stage early, the VM might be freed below. */
  231. stage++;
  232. sync_global_to_guest(*vm, stage);
  233. switch (prev_stage) {
  234. case TEST_STAGE_REG_IFACE:
  235. test_fw_regs_after_vm_start(*vcpu);
  236. break;
  237. case TEST_STAGE_HVC_IFACE_FEAT_DISABLED:
  238. /* Start a new VM so that all the features are now enabled by default */
  239. kvm_vm_free(*vm);
  240. *vm = test_vm_create(vcpu);
  241. break;
  242. case TEST_STAGE_HVC_IFACE_FEAT_ENABLED:
  243. case TEST_STAGE_HVC_IFACE_FALSE_INFO:
  244. break;
  245. default:
  246. TEST_FAIL("Unknown test stage: %d", prev_stage);
  247. }
  248. }
  249. static void test_run(void)
  250. {
  251. struct kvm_vcpu *vcpu;
  252. struct kvm_vm *vm;
  253. struct ucall uc;
  254. bool guest_done = false;
  255. vm = test_vm_create(&vcpu);
  256. test_fw_regs_before_vm_start(vcpu);
  257. while (!guest_done) {
  258. vcpu_run(vcpu);
  259. switch (get_ucall(vcpu, &uc)) {
  260. case UCALL_SYNC:
  261. test_guest_stage(&vm, &vcpu);
  262. break;
  263. case UCALL_DONE:
  264. guest_done = true;
  265. break;
  266. case UCALL_ABORT:
  267. REPORT_GUEST_ASSERT(uc);
  268. break;
  269. default:
  270. TEST_FAIL("Unexpected guest exit");
  271. }
  272. }
  273. kvm_vm_free(vm);
  274. }
  275. int main(void)
  276. {
  277. test_run();
  278. return 0;
  279. }