ipc3.c 30 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2. //
  3. // This file is provided under a dual BSD/GPLv2 license. When using or
  4. // redistributing this file, you may do so under either license.
  5. //
  6. // Copyright(c) 2021 Intel Corporation
  7. //
  8. //
  9. #include <sound/sof/stream.h>
  10. #include <sound/sof/control.h>
  11. #include <trace/events/sof.h>
  12. #include "sof-priv.h"
  13. #include "sof-audio.h"
  14. #include "ipc3-priv.h"
  15. #include "ops.h"
  16. typedef void (*ipc3_rx_callback)(struct snd_sof_dev *sdev, void *msg_buf);
  17. #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC)
  18. static void ipc3_log_header(struct device *dev, u8 *text, u32 cmd)
  19. {
  20. u8 *str;
  21. u8 *str2 = NULL;
  22. u32 glb;
  23. u32 type;
  24. bool is_sof_ipc_stream_position = false;
  25. glb = cmd & SOF_GLB_TYPE_MASK;
  26. type = cmd & SOF_CMD_TYPE_MASK;
  27. switch (glb) {
  28. case SOF_IPC_GLB_REPLY:
  29. str = "GLB_REPLY"; break;
  30. case SOF_IPC_GLB_COMPOUND:
  31. str = "GLB_COMPOUND"; break;
  32. case SOF_IPC_GLB_TPLG_MSG:
  33. str = "GLB_TPLG_MSG";
  34. switch (type) {
  35. case SOF_IPC_TPLG_COMP_NEW:
  36. str2 = "COMP_NEW"; break;
  37. case SOF_IPC_TPLG_COMP_FREE:
  38. str2 = "COMP_FREE"; break;
  39. case SOF_IPC_TPLG_COMP_CONNECT:
  40. str2 = "COMP_CONNECT"; break;
  41. case SOF_IPC_TPLG_PIPE_NEW:
  42. str2 = "PIPE_NEW"; break;
  43. case SOF_IPC_TPLG_PIPE_FREE:
  44. str2 = "PIPE_FREE"; break;
  45. case SOF_IPC_TPLG_PIPE_CONNECT:
  46. str2 = "PIPE_CONNECT"; break;
  47. case SOF_IPC_TPLG_PIPE_COMPLETE:
  48. str2 = "PIPE_COMPLETE"; break;
  49. case SOF_IPC_TPLG_BUFFER_NEW:
  50. str2 = "BUFFER_NEW"; break;
  51. case SOF_IPC_TPLG_BUFFER_FREE:
  52. str2 = "BUFFER_FREE"; break;
  53. default:
  54. str2 = "unknown type"; break;
  55. }
  56. break;
  57. case SOF_IPC_GLB_PM_MSG:
  58. str = "GLB_PM_MSG";
  59. switch (type) {
  60. case SOF_IPC_PM_CTX_SAVE:
  61. str2 = "CTX_SAVE"; break;
  62. case SOF_IPC_PM_CTX_RESTORE:
  63. str2 = "CTX_RESTORE"; break;
  64. case SOF_IPC_PM_CTX_SIZE:
  65. str2 = "CTX_SIZE"; break;
  66. case SOF_IPC_PM_CLK_SET:
  67. str2 = "CLK_SET"; break;
  68. case SOF_IPC_PM_CLK_GET:
  69. str2 = "CLK_GET"; break;
  70. case SOF_IPC_PM_CLK_REQ:
  71. str2 = "CLK_REQ"; break;
  72. case SOF_IPC_PM_CORE_ENABLE:
  73. str2 = "CORE_ENABLE"; break;
  74. case SOF_IPC_PM_GATE:
  75. str2 = "GATE"; break;
  76. default:
  77. str2 = "unknown type"; break;
  78. }
  79. break;
  80. case SOF_IPC_GLB_COMP_MSG:
  81. str = "GLB_COMP_MSG";
  82. switch (type) {
  83. case SOF_IPC_COMP_SET_VALUE:
  84. str2 = "SET_VALUE"; break;
  85. case SOF_IPC_COMP_GET_VALUE:
  86. str2 = "GET_VALUE"; break;
  87. case SOF_IPC_COMP_SET_DATA:
  88. str2 = "SET_DATA"; break;
  89. case SOF_IPC_COMP_GET_DATA:
  90. str2 = "GET_DATA"; break;
  91. default:
  92. str2 = "unknown type"; break;
  93. }
  94. break;
  95. case SOF_IPC_GLB_STREAM_MSG:
  96. str = "GLB_STREAM_MSG";
  97. switch (type) {
  98. case SOF_IPC_STREAM_PCM_PARAMS:
  99. str2 = "PCM_PARAMS"; break;
  100. case SOF_IPC_STREAM_PCM_PARAMS_REPLY:
  101. str2 = "PCM_REPLY"; break;
  102. case SOF_IPC_STREAM_PCM_FREE:
  103. str2 = "PCM_FREE"; break;
  104. case SOF_IPC_STREAM_TRIG_START:
  105. str2 = "TRIG_START"; break;
  106. case SOF_IPC_STREAM_TRIG_STOP:
  107. str2 = "TRIG_STOP"; break;
  108. case SOF_IPC_STREAM_TRIG_PAUSE:
  109. str2 = "TRIG_PAUSE"; break;
  110. case SOF_IPC_STREAM_TRIG_RELEASE:
  111. str2 = "TRIG_RELEASE"; break;
  112. case SOF_IPC_STREAM_TRIG_DRAIN:
  113. str2 = "TRIG_DRAIN"; break;
  114. case SOF_IPC_STREAM_TRIG_XRUN:
  115. str2 = "TRIG_XRUN"; break;
  116. case SOF_IPC_STREAM_POSITION:
  117. is_sof_ipc_stream_position = true;
  118. str2 = "POSITION"; break;
  119. case SOF_IPC_STREAM_VORBIS_PARAMS:
  120. str2 = "VORBIS_PARAMS"; break;
  121. case SOF_IPC_STREAM_VORBIS_FREE:
  122. str2 = "VORBIS_FREE"; break;
  123. default:
  124. str2 = "unknown type"; break;
  125. }
  126. break;
  127. case SOF_IPC_FW_READY:
  128. str = "FW_READY"; break;
  129. case SOF_IPC_GLB_DAI_MSG:
  130. str = "GLB_DAI_MSG";
  131. switch (type) {
  132. case SOF_IPC_DAI_CONFIG:
  133. str2 = "CONFIG"; break;
  134. case SOF_IPC_DAI_LOOPBACK:
  135. str2 = "LOOPBACK"; break;
  136. default:
  137. str2 = "unknown type"; break;
  138. }
  139. break;
  140. case SOF_IPC_GLB_TRACE_MSG:
  141. str = "GLB_TRACE_MSG";
  142. switch (type) {
  143. case SOF_IPC_TRACE_DMA_PARAMS:
  144. str2 = "DMA_PARAMS"; break;
  145. case SOF_IPC_TRACE_DMA_POSITION:
  146. if (!sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
  147. return;
  148. str2 = "DMA_POSITION"; break;
  149. case SOF_IPC_TRACE_DMA_PARAMS_EXT:
  150. str2 = "DMA_PARAMS_EXT"; break;
  151. case SOF_IPC_TRACE_FILTER_UPDATE:
  152. str2 = "FILTER_UPDATE"; break;
  153. case SOF_IPC_TRACE_DMA_FREE:
  154. str2 = "DMA_FREE"; break;
  155. default:
  156. str2 = "unknown type"; break;
  157. }
  158. break;
  159. case SOF_IPC_GLB_TEST_MSG:
  160. str = "GLB_TEST_MSG";
  161. switch (type) {
  162. case SOF_IPC_TEST_IPC_FLOOD:
  163. str2 = "IPC_FLOOD"; break;
  164. default:
  165. str2 = "unknown type"; break;
  166. }
  167. break;
  168. case SOF_IPC_GLB_DEBUG:
  169. str = "GLB_DEBUG";
  170. switch (type) {
  171. case SOF_IPC_DEBUG_MEM_USAGE:
  172. str2 = "MEM_USAGE"; break;
  173. default:
  174. str2 = "unknown type"; break;
  175. }
  176. break;
  177. case SOF_IPC_GLB_PROBE:
  178. str = "GLB_PROBE";
  179. switch (type) {
  180. case SOF_IPC_PROBE_INIT:
  181. str2 = "INIT"; break;
  182. case SOF_IPC_PROBE_DEINIT:
  183. str2 = "DEINIT"; break;
  184. case SOF_IPC_PROBE_DMA_ADD:
  185. str2 = "DMA_ADD"; break;
  186. case SOF_IPC_PROBE_DMA_INFO:
  187. str2 = "DMA_INFO"; break;
  188. case SOF_IPC_PROBE_DMA_REMOVE:
  189. str2 = "DMA_REMOVE"; break;
  190. case SOF_IPC_PROBE_POINT_ADD:
  191. str2 = "POINT_ADD"; break;
  192. case SOF_IPC_PROBE_POINT_INFO:
  193. str2 = "POINT_INFO"; break;
  194. case SOF_IPC_PROBE_POINT_REMOVE:
  195. str2 = "POINT_REMOVE"; break;
  196. default:
  197. str2 = "unknown type"; break;
  198. }
  199. break;
  200. default:
  201. str = "unknown GLB command"; break;
  202. }
  203. if (str2) {
  204. if (is_sof_ipc_stream_position)
  205. trace_sof_stream_position_ipc_rx(dev);
  206. else
  207. dev_dbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2);
  208. } else {
  209. dev_dbg(dev, "%s: 0x%x: %s\n", text, cmd, str);
  210. }
  211. }
  212. #else
  213. static inline void ipc3_log_header(struct device *dev, u8 *text, u32 cmd)
  214. {
  215. if ((cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_TRACE_MSG)
  216. dev_dbg(dev, "%s: 0x%x\n", text, cmd);
  217. }
  218. #endif
  219. static void sof_ipc3_dump_payload(struct snd_sof_dev *sdev,
  220. void *ipc_data, size_t size)
  221. {
  222. dev_dbg(sdev->dev, "Size of payload following the header: %zu\n", size);
  223. print_hex_dump_debug("Message payload: ", DUMP_PREFIX_OFFSET,
  224. 16, 4, ipc_data, size, false);
  225. }
  226. static int sof_ipc3_get_reply(struct snd_sof_dev *sdev)
  227. {
  228. struct snd_sof_ipc_msg *msg = sdev->msg;
  229. struct sof_ipc_reply *reply;
  230. int ret = 0;
  231. /* get the generic reply */
  232. reply = msg->reply_data;
  233. snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset, reply, sizeof(*reply));
  234. if (reply->error < 0)
  235. return reply->error;
  236. if (!reply->hdr.size) {
  237. /* Reply should always be >= sizeof(struct sof_ipc_reply) */
  238. if (msg->reply_size)
  239. dev_err(sdev->dev,
  240. "empty reply received, expected %zu bytes\n",
  241. msg->reply_size);
  242. else
  243. dev_err(sdev->dev, "empty reply received\n");
  244. return -EINVAL;
  245. }
  246. if (msg->reply_size > 0) {
  247. if (reply->hdr.size == msg->reply_size) {
  248. ret = 0;
  249. } else if (reply->hdr.size < msg->reply_size) {
  250. dev_dbg(sdev->dev,
  251. "reply size (%u) is less than expected (%zu)\n",
  252. reply->hdr.size, msg->reply_size);
  253. msg->reply_size = reply->hdr.size;
  254. ret = 0;
  255. } else {
  256. dev_err(sdev->dev,
  257. "reply size (%u) exceeds the buffer size (%zu)\n",
  258. reply->hdr.size, msg->reply_size);
  259. ret = -EINVAL;
  260. }
  261. /*
  262. * get the full message if reply->hdr.size <= msg->reply_size
  263. * and the reply->hdr.size > sizeof(struct sof_ipc_reply)
  264. */
  265. if (!ret && msg->reply_size > sizeof(*reply))
  266. snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset,
  267. msg->reply_data, msg->reply_size);
  268. }
  269. return ret;
  270. }
  271. /* wait for IPC message reply */
  272. static int ipc3_wait_tx_done(struct snd_sof_ipc *ipc, void *reply_data)
  273. {
  274. struct snd_sof_ipc_msg *msg = &ipc->msg;
  275. struct sof_ipc_cmd_hdr *hdr = msg->msg_data;
  276. struct snd_sof_dev *sdev = ipc->sdev;
  277. int ret;
  278. /* wait for DSP IPC completion */
  279. ret = wait_event_timeout(msg->waitq, msg->ipc_complete,
  280. msecs_to_jiffies(sdev->ipc_timeout));
  281. if (ret == 0) {
  282. dev_err(sdev->dev,
  283. "ipc tx timed out for %#x (msg/reply size: %d/%zu)\n",
  284. hdr->cmd, hdr->size, msg->reply_size);
  285. snd_sof_handle_fw_exception(ipc->sdev, "IPC timeout");
  286. ret = -ETIMEDOUT;
  287. } else {
  288. ret = msg->reply_error;
  289. if (ret < 0) {
  290. dev_err(sdev->dev,
  291. "ipc tx error for %#x (msg/reply size: %d/%zu): %d\n",
  292. hdr->cmd, hdr->size, msg->reply_size, ret);
  293. } else {
  294. if (sof_debug_check_flag(SOF_DBG_PRINT_IPC_SUCCESS_LOGS))
  295. ipc3_log_header(sdev->dev, "ipc tx succeeded", hdr->cmd);
  296. if (reply_data && msg->reply_size)
  297. /* copy the data returned from DSP */
  298. memcpy(reply_data, msg->reply_data,
  299. msg->reply_size);
  300. }
  301. /* re-enable dumps after successful IPC tx */
  302. if (sdev->ipc_dump_printed) {
  303. sdev->dbg_dump_printed = false;
  304. sdev->ipc_dump_printed = false;
  305. }
  306. }
  307. return ret;
  308. }
  309. /* send IPC message from host to DSP */
  310. static int ipc3_tx_msg_unlocked(struct snd_sof_ipc *ipc,
  311. void *msg_data, size_t msg_bytes,
  312. void *reply_data, size_t reply_bytes)
  313. {
  314. struct sof_ipc_cmd_hdr *hdr = msg_data;
  315. struct snd_sof_dev *sdev = ipc->sdev;
  316. int ret;
  317. ipc3_log_header(sdev->dev, "ipc tx", hdr->cmd);
  318. ret = sof_ipc_send_msg(sdev, msg_data, msg_bytes, reply_bytes);
  319. if (ret) {
  320. dev_err_ratelimited(sdev->dev,
  321. "%s: ipc message send for %#x failed: %d\n",
  322. __func__, hdr->cmd, ret);
  323. return ret;
  324. }
  325. /* now wait for completion */
  326. return ipc3_wait_tx_done(ipc, reply_data);
  327. }
  328. static int sof_ipc3_tx_msg(struct snd_sof_dev *sdev, void *msg_data, size_t msg_bytes,
  329. void *reply_data, size_t reply_bytes, bool no_pm)
  330. {
  331. struct snd_sof_ipc *ipc = sdev->ipc;
  332. int ret;
  333. if (!msg_data || msg_bytes < sizeof(struct sof_ipc_cmd_hdr)) {
  334. dev_err_ratelimited(sdev->dev, "No IPC message to send\n");
  335. return -EINVAL;
  336. }
  337. if (!no_pm) {
  338. const struct sof_dsp_power_state target_state = {
  339. .state = SOF_DSP_PM_D0,
  340. };
  341. /* ensure the DSP is in D0 before sending a new IPC */
  342. ret = snd_sof_dsp_set_power_state(sdev, &target_state);
  343. if (ret < 0) {
  344. dev_err(sdev->dev, "%s: resuming DSP failed: %d\n",
  345. __func__, ret);
  346. return ret;
  347. }
  348. }
  349. /* Serialise IPC TX */
  350. guard(mutex)(&ipc->tx_mutex);
  351. ret = ipc3_tx_msg_unlocked(ipc, msg_data, msg_bytes, reply_data, reply_bytes);
  352. if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
  353. size_t payload_bytes, header_bytes;
  354. char *payload = NULL;
  355. /* payload is indicated by non zero msg/reply_bytes */
  356. if (msg_bytes > sizeof(struct sof_ipc_cmd_hdr)) {
  357. payload = msg_data;
  358. header_bytes = sizeof(struct sof_ipc_cmd_hdr);
  359. payload_bytes = msg_bytes - header_bytes;
  360. } else if (reply_bytes > sizeof(struct sof_ipc_reply)) {
  361. payload = reply_data;
  362. header_bytes = sizeof(struct sof_ipc_reply);
  363. payload_bytes = reply_bytes - header_bytes;
  364. }
  365. if (payload) {
  366. payload += header_bytes;
  367. sof_ipc3_dump_payload(sdev, payload, payload_bytes);
  368. }
  369. }
  370. return ret;
  371. }
  372. static int sof_ipc3_set_get_data(struct snd_sof_dev *sdev, void *data, size_t data_bytes,
  373. bool set)
  374. {
  375. size_t msg_bytes, hdr_bytes, payload_size, send_bytes;
  376. struct sof_ipc_ctrl_data *cdata = data;
  377. struct sof_ipc_ctrl_data *cdata_chunk;
  378. struct snd_sof_ipc *ipc = sdev->ipc;
  379. size_t offset = 0;
  380. u8 *src, *dst;
  381. u32 num_msg;
  382. int ret = 0;
  383. int i;
  384. if (!cdata || data_bytes < sizeof(*cdata))
  385. return -EINVAL;
  386. if ((cdata->rhdr.hdr.cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_COMP_MSG) {
  387. dev_err(sdev->dev, "%s: Not supported message type of %#x\n",
  388. __func__, cdata->rhdr.hdr.cmd);
  389. return -EINVAL;
  390. }
  391. /* send normal size ipc in one part */
  392. if (cdata->rhdr.hdr.size <= ipc->max_payload_size)
  393. return sof_ipc3_tx_msg(sdev, cdata, cdata->rhdr.hdr.size,
  394. cdata, cdata->rhdr.hdr.size, false);
  395. cdata_chunk = kzalloc(ipc->max_payload_size, GFP_KERNEL);
  396. if (!cdata_chunk)
  397. return -ENOMEM;
  398. switch (cdata->type) {
  399. case SOF_CTRL_TYPE_VALUE_CHAN_GET:
  400. case SOF_CTRL_TYPE_VALUE_CHAN_SET:
  401. hdr_bytes = sizeof(struct sof_ipc_ctrl_data);
  402. if (set) {
  403. src = (u8 *)cdata->chanv;
  404. dst = (u8 *)cdata_chunk->chanv;
  405. } else {
  406. src = (u8 *)cdata_chunk->chanv;
  407. dst = (u8 *)cdata->chanv;
  408. }
  409. break;
  410. case SOF_CTRL_TYPE_DATA_GET:
  411. case SOF_CTRL_TYPE_DATA_SET:
  412. hdr_bytes = sizeof(struct sof_ipc_ctrl_data) + sizeof(struct sof_abi_hdr);
  413. if (set) {
  414. src = (u8 *)cdata->data->data;
  415. dst = (u8 *)cdata_chunk->data->data;
  416. } else {
  417. src = (u8 *)cdata_chunk->data->data;
  418. dst = (u8 *)cdata->data->data;
  419. }
  420. break;
  421. default:
  422. kfree(cdata_chunk);
  423. return -EINVAL;
  424. }
  425. msg_bytes = cdata->rhdr.hdr.size - hdr_bytes;
  426. payload_size = ipc->max_payload_size - hdr_bytes;
  427. num_msg = DIV_ROUND_UP(msg_bytes, payload_size);
  428. /* copy the header data */
  429. memcpy(cdata_chunk, cdata, hdr_bytes);
  430. /* Serialise IPC TX */
  431. guard(mutex)(&ipc->tx_mutex);
  432. /* copy the payload data in a loop */
  433. for (i = 0; i < num_msg; i++) {
  434. send_bytes = min(msg_bytes, payload_size);
  435. cdata_chunk->num_elems = send_bytes;
  436. cdata_chunk->rhdr.hdr.size = hdr_bytes + send_bytes;
  437. cdata_chunk->msg_index = i;
  438. msg_bytes -= send_bytes;
  439. cdata_chunk->elems_remaining = msg_bytes;
  440. if (set)
  441. memcpy(dst, src + offset, send_bytes);
  442. ret = ipc3_tx_msg_unlocked(sdev->ipc,
  443. cdata_chunk, cdata_chunk->rhdr.hdr.size,
  444. cdata_chunk, cdata_chunk->rhdr.hdr.size);
  445. if (ret < 0)
  446. break;
  447. if (!set)
  448. memcpy(dst + offset, src, send_bytes);
  449. offset += payload_size;
  450. }
  451. if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
  452. size_t header_bytes = sizeof(struct sof_ipc_reply);
  453. char *payload = (char *)cdata;
  454. payload += header_bytes;
  455. sof_ipc3_dump_payload(sdev, payload, data_bytes - header_bytes);
  456. }
  457. kfree(cdata_chunk);
  458. return ret;
  459. }
  460. int sof_ipc3_get_ext_windows(struct snd_sof_dev *sdev,
  461. const struct sof_ipc_ext_data_hdr *ext_hdr)
  462. {
  463. const struct sof_ipc_window *w =
  464. container_of(ext_hdr, struct sof_ipc_window, ext_hdr);
  465. if (w->num_windows == 0 || w->num_windows > SOF_IPC_MAX_ELEMS)
  466. return -EINVAL;
  467. if (sdev->info_window) {
  468. if (memcmp(sdev->info_window, w, ext_hdr->hdr.size)) {
  469. dev_err(sdev->dev, "mismatch between window descriptor from extended manifest and mailbox");
  470. return -EINVAL;
  471. }
  472. return 0;
  473. }
  474. /* keep a local copy of the data */
  475. sdev->info_window = devm_kmemdup(sdev->dev, w, ext_hdr->hdr.size, GFP_KERNEL);
  476. if (!sdev->info_window)
  477. return -ENOMEM;
  478. return 0;
  479. }
  480. int sof_ipc3_get_cc_info(struct snd_sof_dev *sdev,
  481. const struct sof_ipc_ext_data_hdr *ext_hdr)
  482. {
  483. int ret;
  484. const struct sof_ipc_cc_version *cc =
  485. container_of(ext_hdr, struct sof_ipc_cc_version, ext_hdr);
  486. if (sdev->cc_version) {
  487. if (memcmp(sdev->cc_version, cc, cc->ext_hdr.hdr.size)) {
  488. dev_err(sdev->dev,
  489. "Receive diverged cc_version descriptions");
  490. return -EINVAL;
  491. }
  492. return 0;
  493. }
  494. dev_dbg(sdev->dev,
  495. "Firmware info: used compiler %s %d:%d:%d%s used optimization flags %s\n",
  496. cc->name, cc->major, cc->minor, cc->micro, cc->desc, cc->optim);
  497. /* create read-only cc_version debugfs to store compiler version info */
  498. /* use local copy of the cc_version to prevent data corruption */
  499. if (sdev->first_boot) {
  500. sdev->cc_version = devm_kmemdup(sdev->dev, cc, cc->ext_hdr.hdr.size, GFP_KERNEL);
  501. if (!sdev->cc_version)
  502. return -ENOMEM;
  503. ret = snd_sof_debugfs_buf_item(sdev, sdev->cc_version,
  504. cc->ext_hdr.hdr.size,
  505. "cc_version", 0444);
  506. /* errors are only due to memory allocation, not debugfs */
  507. if (ret < 0) {
  508. dev_err(sdev->dev, "snd_sof_debugfs_buf_item failed\n");
  509. return ret;
  510. }
  511. }
  512. return 0;
  513. }
  514. /* parse the extended FW boot data structures from FW boot message */
  515. static int ipc3_fw_parse_ext_data(struct snd_sof_dev *sdev, u32 offset)
  516. {
  517. struct sof_ipc_ext_data_hdr *ext_hdr;
  518. void *ext_data;
  519. int ret = 0;
  520. ext_data = kzalloc(PAGE_SIZE, GFP_KERNEL);
  521. if (!ext_data)
  522. return -ENOMEM;
  523. /* get first header */
  524. snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, ext_data,
  525. sizeof(*ext_hdr));
  526. ext_hdr = ext_data;
  527. while (ext_hdr->hdr.cmd == SOF_IPC_FW_READY) {
  528. /* read in ext structure */
  529. snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM,
  530. offset + sizeof(*ext_hdr),
  531. (void *)((u8 *)ext_data + sizeof(*ext_hdr)),
  532. ext_hdr->hdr.size - sizeof(*ext_hdr));
  533. dev_dbg(sdev->dev, "found ext header type %d size 0x%x\n",
  534. ext_hdr->type, ext_hdr->hdr.size);
  535. /* process structure data */
  536. switch (ext_hdr->type) {
  537. case SOF_IPC_EXT_WINDOW:
  538. ret = sof_ipc3_get_ext_windows(sdev, ext_hdr);
  539. break;
  540. case SOF_IPC_EXT_CC_INFO:
  541. ret = sof_ipc3_get_cc_info(sdev, ext_hdr);
  542. break;
  543. case SOF_IPC_EXT_UNUSED:
  544. case SOF_IPC_EXT_PROBE_INFO:
  545. case SOF_IPC_EXT_USER_ABI_INFO:
  546. /* They are supported but we don't do anything here */
  547. break;
  548. default:
  549. dev_info(sdev->dev, "unknown ext header type %d size 0x%x\n",
  550. ext_hdr->type, ext_hdr->hdr.size);
  551. ret = 0;
  552. break;
  553. }
  554. if (ret < 0) {
  555. dev_err(sdev->dev, "Failed to parse ext data type %d\n",
  556. ext_hdr->type);
  557. break;
  558. }
  559. /* move to next header */
  560. offset += ext_hdr->hdr.size;
  561. snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, ext_data,
  562. sizeof(*ext_hdr));
  563. ext_hdr = ext_data;
  564. }
  565. kfree(ext_data);
  566. return ret;
  567. }
  568. static void ipc3_get_windows(struct snd_sof_dev *sdev)
  569. {
  570. struct sof_ipc_window_elem *elem;
  571. u32 outbox_offset = 0;
  572. u32 stream_offset = 0;
  573. u32 inbox_offset = 0;
  574. u32 outbox_size = 0;
  575. u32 stream_size = 0;
  576. u32 inbox_size = 0;
  577. u32 debug_size = 0;
  578. u32 debug_offset = 0;
  579. int window_offset;
  580. int i;
  581. if (!sdev->info_window) {
  582. dev_err(sdev->dev, "%s: No window info present\n", __func__);
  583. return;
  584. }
  585. for (i = 0; i < sdev->info_window->num_windows; i++) {
  586. elem = &sdev->info_window->window[i];
  587. window_offset = snd_sof_dsp_get_window_offset(sdev, elem->id);
  588. if (window_offset < 0) {
  589. dev_warn(sdev->dev, "No offset for window %d\n", elem->id);
  590. continue;
  591. }
  592. switch (elem->type) {
  593. case SOF_IPC_REGION_UPBOX:
  594. inbox_offset = window_offset + elem->offset;
  595. inbox_size = elem->size;
  596. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  597. inbox_offset,
  598. elem->size, "inbox",
  599. SOF_DEBUGFS_ACCESS_D0_ONLY);
  600. break;
  601. case SOF_IPC_REGION_DOWNBOX:
  602. outbox_offset = window_offset + elem->offset;
  603. outbox_size = elem->size;
  604. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  605. outbox_offset,
  606. elem->size, "outbox",
  607. SOF_DEBUGFS_ACCESS_D0_ONLY);
  608. break;
  609. case SOF_IPC_REGION_TRACE:
  610. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  611. window_offset + elem->offset,
  612. elem->size, "etrace",
  613. SOF_DEBUGFS_ACCESS_D0_ONLY);
  614. break;
  615. case SOF_IPC_REGION_DEBUG:
  616. debug_offset = window_offset + elem->offset;
  617. debug_size = elem->size;
  618. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  619. window_offset + elem->offset,
  620. elem->size, "debug",
  621. SOF_DEBUGFS_ACCESS_D0_ONLY);
  622. break;
  623. case SOF_IPC_REGION_STREAM:
  624. stream_offset = window_offset + elem->offset;
  625. stream_size = elem->size;
  626. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  627. stream_offset,
  628. elem->size, "stream",
  629. SOF_DEBUGFS_ACCESS_D0_ONLY);
  630. break;
  631. case SOF_IPC_REGION_REGS:
  632. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  633. window_offset + elem->offset,
  634. elem->size, "regs",
  635. SOF_DEBUGFS_ACCESS_D0_ONLY);
  636. break;
  637. case SOF_IPC_REGION_EXCEPTION:
  638. sdev->dsp_oops_offset = window_offset + elem->offset;
  639. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  640. window_offset + elem->offset,
  641. elem->size, "exception",
  642. SOF_DEBUGFS_ACCESS_D0_ONLY);
  643. break;
  644. default:
  645. dev_err(sdev->dev, "%s: Illegal window info: %u\n",
  646. __func__, elem->type);
  647. return;
  648. }
  649. }
  650. if (outbox_size == 0 || inbox_size == 0) {
  651. dev_err(sdev->dev, "%s: Illegal mailbox window\n", __func__);
  652. return;
  653. }
  654. sdev->dsp_box.offset = inbox_offset;
  655. sdev->dsp_box.size = inbox_size;
  656. sdev->host_box.offset = outbox_offset;
  657. sdev->host_box.size = outbox_size;
  658. sdev->stream_box.offset = stream_offset;
  659. sdev->stream_box.size = stream_size;
  660. sdev->debug_box.offset = debug_offset;
  661. sdev->debug_box.size = debug_size;
  662. dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n",
  663. inbox_offset, inbox_size);
  664. dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n",
  665. outbox_offset, outbox_size);
  666. dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n",
  667. stream_offset, stream_size);
  668. dev_dbg(sdev->dev, " debug region 0x%x - size 0x%x\n",
  669. debug_offset, debug_size);
  670. }
  671. static int ipc3_init_reply_data_buffer(struct snd_sof_dev *sdev)
  672. {
  673. struct snd_sof_ipc_msg *msg = &sdev->ipc->msg;
  674. msg->reply_data = devm_kzalloc(sdev->dev, SOF_IPC_MSG_MAX_SIZE, GFP_KERNEL);
  675. if (!msg->reply_data)
  676. return -ENOMEM;
  677. sdev->ipc->max_payload_size = SOF_IPC_MSG_MAX_SIZE;
  678. return 0;
  679. }
  680. int sof_ipc3_validate_fw_version(struct snd_sof_dev *sdev)
  681. {
  682. struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
  683. struct sof_ipc_fw_version *v = &ready->version;
  684. dev_info(sdev->dev,
  685. "Firmware info: version %d:%d:%d-%s\n", v->major, v->minor,
  686. v->micro, v->tag);
  687. dev_info(sdev->dev,
  688. "Firmware: ABI %d:%d:%d Kernel ABI %d:%d:%d\n",
  689. SOF_ABI_VERSION_MAJOR(v->abi_version),
  690. SOF_ABI_VERSION_MINOR(v->abi_version),
  691. SOF_ABI_VERSION_PATCH(v->abi_version),
  692. SOF_ABI_MAJOR, SOF_ABI_MINOR, SOF_ABI_PATCH);
  693. if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, v->abi_version)) {
  694. dev_err(sdev->dev, "incompatible FW ABI version\n");
  695. return -EINVAL;
  696. }
  697. if (IS_ENABLED(CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS) &&
  698. SOF_ABI_VERSION_MINOR(v->abi_version) > SOF_ABI_MINOR) {
  699. dev_err(sdev->dev, "FW ABI is more recent than kernel\n");
  700. return -EINVAL;
  701. }
  702. if (ready->flags & SOF_IPC_INFO_BUILD)
  703. dev_info(sdev->dev,
  704. "Firmware debug build %d on %s-%s - options:\n"
  705. " GDB: %s\n"
  706. " lock debug: %s\n"
  707. " lock vdebug: %s\n",
  708. v->build, v->date, v->time,
  709. str_enabled_disabled(ready->flags & SOF_IPC_INFO_GDB),
  710. str_enabled_disabled(ready->flags & SOF_IPC_INFO_LOCKS),
  711. str_enabled_disabled(ready->flags & SOF_IPC_INFO_LOCKSV));
  712. /* copy the fw_version into debugfs at first boot */
  713. memcpy(&sdev->fw_version, v, sizeof(*v));
  714. return 0;
  715. }
  716. static int ipc3_fw_ready(struct snd_sof_dev *sdev, u32 cmd)
  717. {
  718. struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready;
  719. int offset;
  720. int ret;
  721. /* mailbox must be on 4k boundary */
  722. offset = snd_sof_dsp_get_mailbox_offset(sdev);
  723. if (offset < 0) {
  724. dev_err(sdev->dev, "%s: no mailbox offset\n", __func__);
  725. return offset;
  726. }
  727. dev_dbg(sdev->dev, "DSP is ready 0x%8.8x offset 0x%x\n", cmd, offset);
  728. /* no need to re-check version/ABI for subsequent boots */
  729. if (!sdev->first_boot)
  730. return 0;
  731. /*
  732. * copy data from the DSP FW ready offset
  733. * Subsequent error handling is not needed for BLK_TYPE_SRAM
  734. */
  735. ret = snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, fw_ready,
  736. sizeof(*fw_ready));
  737. if (ret) {
  738. dev_err(sdev->dev,
  739. "Unable to read fw_ready, read from TYPE_SRAM failed\n");
  740. return ret;
  741. }
  742. /* make sure ABI version is compatible */
  743. ret = sof_ipc3_validate_fw_version(sdev);
  744. if (ret < 0)
  745. return ret;
  746. /* now check for extended data */
  747. ipc3_fw_parse_ext_data(sdev, offset + sizeof(struct sof_ipc_fw_ready));
  748. ipc3_get_windows(sdev);
  749. return ipc3_init_reply_data_buffer(sdev);
  750. }
  751. /* IPC stream position. */
  752. static void ipc3_period_elapsed(struct snd_sof_dev *sdev, u32 msg_id)
  753. {
  754. struct snd_soc_component *scomp = sdev->component;
  755. struct snd_sof_pcm_stream *stream;
  756. struct sof_ipc_stream_posn posn;
  757. struct snd_sof_pcm *spcm;
  758. int direction, ret;
  759. spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
  760. if (!spcm) {
  761. dev_err(sdev->dev, "period elapsed for unknown stream, msg_id %d\n",
  762. msg_id);
  763. return;
  764. }
  765. stream = &spcm->stream[direction];
  766. ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
  767. if (ret < 0) {
  768. dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
  769. return;
  770. }
  771. trace_sof_ipc3_period_elapsed_position(sdev, &posn);
  772. memcpy(&stream->posn, &posn, sizeof(posn));
  773. if (spcm->pcm.compress)
  774. snd_sof_compr_fragment_elapsed(stream->cstream);
  775. else if (stream->substream->runtime &&
  776. !stream->substream->runtime->no_period_wakeup)
  777. /* only inform ALSA for period_wakeup mode */
  778. snd_sof_pcm_period_elapsed(stream->substream);
  779. }
  780. /* DSP notifies host of an XRUN within FW */
  781. static void ipc3_xrun(struct snd_sof_dev *sdev, u32 msg_id)
  782. {
  783. struct snd_soc_component *scomp = sdev->component;
  784. struct snd_sof_pcm_stream *stream;
  785. struct sof_ipc_stream_posn posn;
  786. struct snd_sof_pcm *spcm;
  787. int direction, ret;
  788. spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
  789. if (!spcm) {
  790. dev_err(sdev->dev, "XRUN for unknown stream, msg_id %d\n",
  791. msg_id);
  792. return;
  793. }
  794. stream = &spcm->stream[direction];
  795. ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
  796. if (ret < 0) {
  797. dev_warn(sdev->dev, "failed to read overrun position: %d\n", ret);
  798. return;
  799. }
  800. dev_dbg(sdev->dev, "posn XRUN: host %llx comp %d size %d\n",
  801. posn.host_posn, posn.xrun_comp_id, posn.xrun_size);
  802. #if defined(CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP)
  803. /* stop PCM on XRUN - used for pipeline debug */
  804. memcpy(&stream->posn, &posn, sizeof(posn));
  805. snd_pcm_stop_xrun(stream->substream);
  806. #endif
  807. }
  808. /* stream notifications from firmware */
  809. static void ipc3_stream_message(struct snd_sof_dev *sdev, void *msg_buf)
  810. {
  811. struct sof_ipc_cmd_hdr *hdr = msg_buf;
  812. u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
  813. u32 msg_id = SOF_IPC_MESSAGE_ID(hdr->cmd);
  814. switch (msg_type) {
  815. case SOF_IPC_STREAM_POSITION:
  816. ipc3_period_elapsed(sdev, msg_id);
  817. break;
  818. case SOF_IPC_STREAM_TRIG_XRUN:
  819. ipc3_xrun(sdev, msg_id);
  820. break;
  821. default:
  822. dev_err(sdev->dev, "unhandled stream message %#x\n",
  823. msg_id);
  824. break;
  825. }
  826. }
  827. /* component notifications from firmware */
  828. static void ipc3_comp_notification(struct snd_sof_dev *sdev, void *msg_buf)
  829. {
  830. const struct sof_ipc_tplg_ops *tplg_ops = sdev->ipc->ops->tplg;
  831. struct sof_ipc_cmd_hdr *hdr = msg_buf;
  832. u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
  833. switch (msg_type) {
  834. case SOF_IPC_COMP_GET_VALUE:
  835. case SOF_IPC_COMP_GET_DATA:
  836. break;
  837. default:
  838. dev_err(sdev->dev, "unhandled component message %#x\n", msg_type);
  839. return;
  840. }
  841. if (tplg_ops->control->update)
  842. tplg_ops->control->update(sdev, msg_buf);
  843. }
  844. static void ipc3_trace_message(struct snd_sof_dev *sdev, void *msg_buf)
  845. {
  846. struct sof_ipc_cmd_hdr *hdr = msg_buf;
  847. u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
  848. switch (msg_type) {
  849. case SOF_IPC_TRACE_DMA_POSITION:
  850. ipc3_dtrace_posn_update(sdev, msg_buf);
  851. break;
  852. default:
  853. dev_err(sdev->dev, "unhandled trace message %#x\n", msg_type);
  854. break;
  855. }
  856. }
  857. void sof_ipc3_do_rx_work(struct snd_sof_dev *sdev, struct sof_ipc_cmd_hdr *hdr, void *msg_buf)
  858. {
  859. ipc3_rx_callback rx_callback = NULL;
  860. u32 cmd;
  861. int err;
  862. ipc3_log_header(sdev->dev, "ipc rx", hdr->cmd);
  863. if (hdr->size < sizeof(*hdr) || hdr->size > SOF_IPC_MSG_MAX_SIZE) {
  864. dev_err(sdev->dev, "The received message size is invalid: %u\n",
  865. hdr->size);
  866. return;
  867. }
  868. cmd = hdr->cmd & SOF_GLB_TYPE_MASK;
  869. /* check message type */
  870. switch (cmd) {
  871. case SOF_IPC_GLB_REPLY:
  872. dev_err(sdev->dev, "ipc reply unknown\n");
  873. break;
  874. case SOF_IPC_FW_READY:
  875. /* check for FW boot completion */
  876. if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) {
  877. err = ipc3_fw_ready(sdev, cmd);
  878. if (err < 0)
  879. sof_set_fw_state(sdev, SOF_FW_BOOT_READY_FAILED);
  880. else
  881. sof_set_fw_state(sdev, SOF_FW_BOOT_READY_OK);
  882. /* wake up firmware loader */
  883. wake_up(&sdev->boot_wait);
  884. }
  885. break;
  886. case SOF_IPC_GLB_COMPOUND:
  887. case SOF_IPC_GLB_TPLG_MSG:
  888. case SOF_IPC_GLB_PM_MSG:
  889. break;
  890. case SOF_IPC_GLB_COMP_MSG:
  891. rx_callback = ipc3_comp_notification;
  892. break;
  893. case SOF_IPC_GLB_STREAM_MSG:
  894. rx_callback = ipc3_stream_message;
  895. break;
  896. case SOF_IPC_GLB_TRACE_MSG:
  897. rx_callback = ipc3_trace_message;
  898. break;
  899. default:
  900. dev_err(sdev->dev, "%s: Unknown DSP message: 0x%x\n", __func__, cmd);
  901. break;
  902. }
  903. /* Call local handler for the message */
  904. if (rx_callback)
  905. rx_callback(sdev, msg_buf);
  906. /* Notify registered clients */
  907. sof_client_ipc_rx_dispatcher(sdev, msg_buf);
  908. ipc3_log_header(sdev->dev, "ipc rx done", hdr->cmd);
  909. }
  910. EXPORT_SYMBOL(sof_ipc3_do_rx_work);
  911. /* DSP firmware has sent host a message */
  912. static void sof_ipc3_rx_msg(struct snd_sof_dev *sdev)
  913. {
  914. struct sof_ipc_cmd_hdr hdr;
  915. void *msg_buf;
  916. int err;
  917. /* read back header */
  918. err = snd_sof_ipc_msg_data(sdev, NULL, &hdr, sizeof(hdr));
  919. if (err < 0) {
  920. dev_warn(sdev->dev, "failed to read IPC header: %d\n", err);
  921. return;
  922. }
  923. if (hdr.size < sizeof(hdr) || hdr.size > SOF_IPC_MSG_MAX_SIZE) {
  924. dev_err(sdev->dev, "The received message size is invalid\n");
  925. return;
  926. }
  927. /* read the full message */
  928. msg_buf = kmalloc(hdr.size, GFP_KERNEL);
  929. if (!msg_buf)
  930. return;
  931. err = snd_sof_ipc_msg_data(sdev, NULL, msg_buf, hdr.size);
  932. if (err < 0) {
  933. dev_err(sdev->dev, "%s: Failed to read message: %d\n", __func__, err);
  934. kfree(msg_buf);
  935. return;
  936. }
  937. sof_ipc3_do_rx_work(sdev, &hdr, msg_buf);
  938. kfree(msg_buf);
  939. }
  940. static int sof_ipc3_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on)
  941. {
  942. struct sof_ipc_pm_core_config core_cfg = {
  943. .hdr.size = sizeof(core_cfg),
  944. .hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,
  945. };
  946. if (on)
  947. core_cfg.enable_mask = sdev->enabled_cores_mask | BIT(core_idx);
  948. else
  949. core_cfg.enable_mask = sdev->enabled_cores_mask & ~BIT(core_idx);
  950. return sof_ipc3_tx_msg(sdev, &core_cfg, sizeof(core_cfg), NULL, 0, false);
  951. }
  952. static int sof_ipc3_ctx_ipc(struct snd_sof_dev *sdev, int cmd)
  953. {
  954. struct sof_ipc_pm_ctx pm_ctx = {
  955. .hdr.size = sizeof(pm_ctx),
  956. .hdr.cmd = SOF_IPC_GLB_PM_MSG | cmd,
  957. };
  958. /* send ctx save ipc to dsp */
  959. return sof_ipc3_tx_msg(sdev, &pm_ctx, sizeof(pm_ctx), NULL, 0, false);
  960. }
  961. static int sof_ipc3_ctx_save(struct snd_sof_dev *sdev)
  962. {
  963. return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_SAVE);
  964. }
  965. static int sof_ipc3_ctx_restore(struct snd_sof_dev *sdev)
  966. {
  967. return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_RESTORE);
  968. }
  969. static int sof_ipc3_set_pm_gate(struct snd_sof_dev *sdev, u32 flags)
  970. {
  971. struct sof_ipc_pm_gate pm_gate;
  972. memset(&pm_gate, 0, sizeof(pm_gate));
  973. /* configure pm_gate ipc message */
  974. pm_gate.hdr.size = sizeof(pm_gate);
  975. pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
  976. pm_gate.flags = flags;
  977. /* send pm_gate ipc to dsp */
  978. return sof_ipc_tx_message_no_pm_no_reply(sdev->ipc, &pm_gate, sizeof(pm_gate));
  979. }
  980. static const struct sof_ipc_pm_ops ipc3_pm_ops = {
  981. .ctx_save = sof_ipc3_ctx_save,
  982. .ctx_restore = sof_ipc3_ctx_restore,
  983. .set_core_state = sof_ipc3_set_core_state,
  984. .set_pm_gate = sof_ipc3_set_pm_gate,
  985. };
  986. const struct sof_ipc_ops ipc3_ops = {
  987. .tplg = &ipc3_tplg_ops,
  988. .pm = &ipc3_pm_ops,
  989. .pcm = &ipc3_pcm_ops,
  990. .fw_loader = &ipc3_loader_ops,
  991. .fw_tracing = &ipc3_dtrace_ops,
  992. .tx_msg = sof_ipc3_tx_msg,
  993. .rx_msg = sof_ipc3_rx_msg,
  994. .set_get_data = sof_ipc3_set_get_data,
  995. .get_reply = sof_ipc3_get_reply,
  996. };