gus_dma.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Routines for GF1 DMA control
  4. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  5. */
  6. #include <asm/dma.h>
  7. #include <linux/slab.h>
  8. #include <sound/core.h>
  9. #include <sound/gus.h>
  10. static void snd_gf1_dma_ack(struct snd_gus_card * gus)
  11. {
  12. guard(spinlock_irqsave)(&gus->reg_lock);
  13. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, 0x00);
  14. snd_gf1_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL);
  15. }
  16. static void snd_gf1_dma_program(struct snd_gus_card * gus,
  17. unsigned int addr,
  18. unsigned long buf_addr,
  19. unsigned int count,
  20. unsigned int cmd)
  21. {
  22. unsigned int address;
  23. unsigned char dma_cmd;
  24. unsigned int address_high;
  25. dev_dbg(gus->card->dev,
  26. "dma_transfer: addr=0x%x, buf=0x%lx, count=0x%x\n",
  27. addr, buf_addr, count);
  28. if (gus->gf1.dma1 > 3) {
  29. if (gus->gf1.enh_mode) {
  30. address = addr >> 1;
  31. } else {
  32. if (addr & 0x1f) {
  33. dev_dbg(gus->card->dev,
  34. "%s: unaligned address (0x%x)?\n",
  35. __func__, addr);
  36. return;
  37. }
  38. address = (addr & 0x000c0000) | ((addr & 0x0003ffff) >> 1);
  39. }
  40. } else {
  41. address = addr;
  42. }
  43. dma_cmd = SNDRV_GF1_DMA_ENABLE | (unsigned short) cmd;
  44. #if 0
  45. dma_cmd |= 0x08;
  46. #endif
  47. if (dma_cmd & SNDRV_GF1_DMA_16BIT) {
  48. count++;
  49. count &= ~1; /* align */
  50. }
  51. if (gus->gf1.dma1 > 3) {
  52. dma_cmd |= SNDRV_GF1_DMA_WIDTH16;
  53. count++;
  54. count &= ~1; /* align */
  55. }
  56. snd_gf1_dma_ack(gus);
  57. snd_dma_program(gus->gf1.dma1, buf_addr, count, dma_cmd & SNDRV_GF1_DMA_READ ? DMA_MODE_READ : DMA_MODE_WRITE);
  58. #if 0
  59. dev_dbg(gus->card->dev,
  60. "address = 0x%x, count = 0x%x, dma_cmd = 0x%x\n",
  61. address << 1, count, dma_cmd);
  62. #endif
  63. guard(spinlock_irqsave)(&gus->reg_lock);
  64. if (gus->gf1.enh_mode) {
  65. address_high = ((address >> 16) & 0x000000f0) | (address & 0x0000000f);
  66. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  67. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH, (unsigned char) address_high);
  68. } else
  69. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  70. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, dma_cmd);
  71. }
  72. static struct snd_gf1_dma_block *snd_gf1_dma_next_block(struct snd_gus_card * gus)
  73. {
  74. struct snd_gf1_dma_block *block;
  75. /* PCM block have bigger priority than synthesizer one */
  76. if (gus->gf1.dma_data_pcm) {
  77. block = gus->gf1.dma_data_pcm;
  78. if (gus->gf1.dma_data_pcm_last == block) {
  79. gus->gf1.dma_data_pcm =
  80. gus->gf1.dma_data_pcm_last = NULL;
  81. } else {
  82. gus->gf1.dma_data_pcm = block->next;
  83. }
  84. } else if (gus->gf1.dma_data_synth) {
  85. block = gus->gf1.dma_data_synth;
  86. if (gus->gf1.dma_data_synth_last == block) {
  87. gus->gf1.dma_data_synth =
  88. gus->gf1.dma_data_synth_last = NULL;
  89. } else {
  90. gus->gf1.dma_data_synth = block->next;
  91. }
  92. } else {
  93. block = NULL;
  94. }
  95. if (block) {
  96. gus->gf1.dma_ack = block->ack;
  97. gus->gf1.dma_private_data = block->private_data;
  98. }
  99. return block;
  100. }
  101. static void snd_gf1_dma_interrupt(struct snd_gus_card * gus)
  102. {
  103. struct snd_gf1_dma_block *block;
  104. snd_gf1_dma_ack(gus);
  105. if (gus->gf1.dma_ack)
  106. gus->gf1.dma_ack(gus, gus->gf1.dma_private_data);
  107. scoped_guard(spinlock, &gus->dma_lock) {
  108. if (gus->gf1.dma_data_pcm == NULL &&
  109. gus->gf1.dma_data_synth == NULL) {
  110. gus->gf1.dma_ack = NULL;
  111. gus->gf1.dma_flags &= ~SNDRV_GF1_DMA_TRIGGER;
  112. return;
  113. }
  114. block = snd_gf1_dma_next_block(gus);
  115. }
  116. if (!block)
  117. return;
  118. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  119. kfree(block);
  120. #if 0
  121. dev_dbg(gus->card->dev,
  122. "program dma (IRQ) - addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
  123. block->addr, block->buf_addr, block->count, block->cmd);
  124. #endif
  125. }
  126. int snd_gf1_dma_init(struct snd_gus_card * gus)
  127. {
  128. guard(mutex)(&gus->dma_mutex);
  129. gus->gf1.dma_shared++;
  130. if (gus->gf1.dma_shared > 1)
  131. return 0;
  132. gus->gf1.interrupt_handler_dma_write = snd_gf1_dma_interrupt;
  133. gus->gf1.dma_data_pcm =
  134. gus->gf1.dma_data_pcm_last =
  135. gus->gf1.dma_data_synth =
  136. gus->gf1.dma_data_synth_last = NULL;
  137. return 0;
  138. }
  139. int snd_gf1_dma_done(struct snd_gus_card * gus)
  140. {
  141. struct snd_gf1_dma_block *block;
  142. guard(mutex)(&gus->dma_mutex);
  143. gus->gf1.dma_shared--;
  144. if (!gus->gf1.dma_shared) {
  145. snd_dma_disable(gus->gf1.dma1);
  146. snd_gf1_set_default_handlers(gus, SNDRV_GF1_HANDLER_DMA_WRITE);
  147. snd_gf1_dma_ack(gus);
  148. while ((block = gus->gf1.dma_data_pcm)) {
  149. gus->gf1.dma_data_pcm = block->next;
  150. kfree(block);
  151. }
  152. while ((block = gus->gf1.dma_data_synth)) {
  153. gus->gf1.dma_data_synth = block->next;
  154. kfree(block);
  155. }
  156. gus->gf1.dma_data_pcm_last =
  157. gus->gf1.dma_data_synth_last = NULL;
  158. }
  159. return 0;
  160. }
  161. int snd_gf1_dma_transfer_block(struct snd_gus_card * gus,
  162. struct snd_gf1_dma_block * __block,
  163. int atomic,
  164. int synth)
  165. {
  166. struct snd_gf1_dma_block *block;
  167. struct snd_gf1_dma_block *free_block = NULL;
  168. block = kmalloc(sizeof(*block), atomic ? GFP_ATOMIC : GFP_KERNEL);
  169. if (!block)
  170. return -ENOMEM;
  171. *block = *__block;
  172. block->next = NULL;
  173. dev_dbg(gus->card->dev,
  174. "addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
  175. block->addr, (long) block->buffer, block->count,
  176. block->cmd);
  177. dev_dbg(gus->card->dev,
  178. "gus->gf1.dma_data_pcm_last = 0x%lx\n",
  179. (long)gus->gf1.dma_data_pcm_last);
  180. dev_dbg(gus->card->dev,
  181. "gus->gf1.dma_data_pcm = 0x%lx\n",
  182. (long)gus->gf1.dma_data_pcm);
  183. scoped_guard(spinlock_irqsave, &gus->dma_lock) {
  184. if (synth) {
  185. if (gus->gf1.dma_data_synth_last) {
  186. gus->gf1.dma_data_synth_last->next = block;
  187. gus->gf1.dma_data_synth_last = block;
  188. } else {
  189. gus->gf1.dma_data_synth =
  190. gus->gf1.dma_data_synth_last = block;
  191. }
  192. } else {
  193. if (gus->gf1.dma_data_pcm_last) {
  194. gus->gf1.dma_data_pcm_last->next = block;
  195. gus->gf1.dma_data_pcm_last = block;
  196. } else {
  197. gus->gf1.dma_data_pcm =
  198. gus->gf1.dma_data_pcm_last = block;
  199. }
  200. }
  201. if (!(gus->gf1.dma_flags & SNDRV_GF1_DMA_TRIGGER)) {
  202. gus->gf1.dma_flags |= SNDRV_GF1_DMA_TRIGGER;
  203. free_block = snd_gf1_dma_next_block(gus);
  204. }
  205. }
  206. if (free_block) {
  207. snd_gf1_dma_program(gus, free_block->addr, free_block->buf_addr,
  208. free_block->count,
  209. (unsigned short)free_block->cmd);
  210. kfree(free_block);
  211. }
  212. return 0;
  213. }