ufs.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Universal Flash Storage Host controller driver
  4. * Copyright (C) 2011-2013 Samsung India Software Operations
  5. *
  6. * Authors:
  7. * Santosh Yaraganavi <santosh.sy@samsung.com>
  8. * Vinayak Holikatti <h.vinayak@samsung.com>
  9. */
  10. #ifndef _UFS_H
  11. #define _UFS_H
  12. #include <linux/bitops.h>
  13. #include <linux/types.h>
  14. #include <uapi/scsi/scsi_bsg_ufs.h>
  15. #include <linux/time64.h>
  16. /*
  17. * Using static_assert() is not allowed in UAPI header files. Hence the check
  18. * in this header file of the size of struct utp_upiu_header.
  19. */
  20. static_assert(sizeof(struct utp_upiu_header) == 12);
  21. static_assert(sizeof(struct utp_upiu_query) == 20);
  22. #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
  23. #define QUERY_DESC_MAX_SIZE 255
  24. #define QUERY_DESC_MIN_SIZE 2
  25. #define QUERY_DESC_HDR_SIZE 2
  26. #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
  27. (sizeof(struct utp_upiu_header)))
  28. #define UFS_SENSE_SIZE 18
  29. /*
  30. * UFS device may have standard LUs and LUN id could be from 0x00 to
  31. * 0x7F. Standard LUs use "Peripheral Device Addressing Format".
  32. * UFS device may also have the Well Known LUs (also referred as W-LU)
  33. * which again could be from 0x00 to 0x7F. For W-LUs, device only use
  34. * the "Extended Addressing Format" which means the W-LUNs would be
  35. * from 0xc100 (SCSI_W_LUN_BASE) onwards.
  36. * This means max. LUN number reported from UFS device could be 0xC17F.
  37. */
  38. #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
  39. #define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
  40. #define UFS_UPIU_WLUN_ID (1 << 7)
  41. /* WriteBooster buffer is available only for the logical unit from 0 to 7 */
  42. #define UFS_UPIU_MAX_WB_LUN_ID 8
  43. /*
  44. * WriteBooster buffer lifetime has a limit setted by vendor.
  45. * If it is over the limit, WriteBooster feature will be disabled.
  46. */
  47. #define UFS_WB_EXCEED_LIFETIME 0x0B
  48. /*
  49. * In UFS Spec, the Extra Header Segment (EHS) starts from byte 32 in UPIU request/response packet
  50. */
  51. #define EHS_OFFSET_IN_RESPONSE 32
  52. /* Well known logical unit id in LUN field of UPIU */
  53. enum {
  54. UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
  55. UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
  56. UFS_UPIU_BOOT_WLUN = 0xB0,
  57. UFS_UPIU_RPMB_WLUN = 0xC4,
  58. };
  59. /*
  60. * UFS Protocol Information Unit related definitions
  61. */
  62. /* Task management functions */
  63. enum {
  64. UFS_ABORT_TASK = 0x01,
  65. UFS_ABORT_TASK_SET = 0x02,
  66. UFS_CLEAR_TASK_SET = 0x04,
  67. UFS_LOGICAL_RESET = 0x08,
  68. UFS_QUERY_TASK = 0x80,
  69. UFS_QUERY_TASK_SET = 0x81,
  70. };
  71. /* UTP UPIU Transaction Codes Initiator to Target */
  72. enum upiu_request_transaction {
  73. UPIU_TRANSACTION_NOP_OUT = 0x00,
  74. UPIU_TRANSACTION_COMMAND = 0x01,
  75. UPIU_TRANSACTION_DATA_OUT = 0x02,
  76. UPIU_TRANSACTION_TASK_REQ = 0x04,
  77. UPIU_TRANSACTION_QUERY_REQ = 0x16,
  78. };
  79. /* UTP UPIU Transaction Codes Target to Initiator */
  80. enum upiu_response_transaction {
  81. UPIU_TRANSACTION_NOP_IN = 0x20,
  82. UPIU_TRANSACTION_RESPONSE = 0x21,
  83. UPIU_TRANSACTION_DATA_IN = 0x22,
  84. UPIU_TRANSACTION_TASK_RSP = 0x24,
  85. UPIU_TRANSACTION_READY_XFER = 0x31,
  86. UPIU_TRANSACTION_QUERY_RSP = 0x36,
  87. UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
  88. };
  89. /* UPIU Read/Write flags. See also table "UPIU Flags" in the UFS standard. */
  90. enum {
  91. UPIU_CMD_FLAGS_NONE = 0x00,
  92. UPIU_CMD_FLAGS_CP = 0x04,
  93. UPIU_CMD_FLAGS_WRITE = 0x20,
  94. UPIU_CMD_FLAGS_READ = 0x40,
  95. };
  96. /* UPIU response flags */
  97. enum {
  98. UPIU_RSP_FLAG_UNDERFLOW = 0x20,
  99. UPIU_RSP_FLAG_OVERFLOW = 0x40,
  100. };
  101. /* UPIU Task Attributes */
  102. enum {
  103. UPIU_TASK_ATTR_SIMPLE = 0x00,
  104. UPIU_TASK_ATTR_ORDERED = 0x01,
  105. UPIU_TASK_ATTR_HEADQ = 0x02,
  106. UPIU_TASK_ATTR_ACA = 0x03,
  107. };
  108. /* UPIU Query request function */
  109. enum {
  110. UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
  111. UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
  112. };
  113. /* Flag idn for Query Requests*/
  114. enum flag_idn {
  115. QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
  116. QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
  117. QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
  118. QUERY_FLAG_IDN_BKOPS_EN = 0x04,
  119. QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
  120. QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
  121. QUERY_FLAG_IDN_RESERVED2 = 0x07,
  122. QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
  123. QUERY_FLAG_IDN_BUSY_RTC = 0x09,
  124. QUERY_FLAG_IDN_RESERVED3 = 0x0A,
  125. QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
  126. QUERY_FLAG_IDN_WB_EN = 0x0E,
  127. QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
  128. QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
  129. QUERY_FLAG_IDN_HPB_RESET = 0x11,
  130. QUERY_FLAG_IDN_HPB_EN = 0x12,
  131. };
  132. /* Attribute idn for Query requests */
  133. enum attr_idn {
  134. QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
  135. QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
  136. QUERY_ATTR_IDN_POWER_MODE = 0x02,
  137. QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
  138. QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
  139. QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
  140. QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
  141. QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
  142. QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
  143. QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
  144. QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
  145. QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
  146. QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
  147. QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
  148. QUERY_ATTR_IDN_EE_STATUS = 0x0E,
  149. QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
  150. QUERY_ATTR_IDN_CNTX_CONF = 0x10,
  151. QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
  152. QUERY_ATTR_IDN_RESERVED2 = 0x12,
  153. QUERY_ATTR_IDN_RESERVED3 = 0x13,
  154. QUERY_ATTR_IDN_FFU_STATUS = 0x14,
  155. QUERY_ATTR_IDN_PSA_STATE = 0x15,
  156. QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
  157. QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
  158. QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18,
  159. QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19,
  160. QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A,
  161. QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
  162. QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
  163. QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
  164. QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
  165. QUERY_ATTR_IDN_TIMESTAMP = 0x30,
  166. QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID = 0x34,
  167. QUERY_ATTR_IDN_HID_DEFRAG_OPERATION = 0x35,
  168. QUERY_ATTR_IDN_HID_AVAILABLE_SIZE = 0x36,
  169. QUERY_ATTR_IDN_HID_SIZE = 0x37,
  170. QUERY_ATTR_IDN_HID_PROGRESS_RATIO = 0x38,
  171. QUERY_ATTR_IDN_HID_STATE = 0x39,
  172. QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT = 0x3C,
  173. QUERY_ATTR_IDN_WB_BUF_RESIZE_EN = 0x3D,
  174. QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS = 0x3E,
  175. };
  176. /* Descriptor idn for Query requests */
  177. enum desc_idn {
  178. QUERY_DESC_IDN_DEVICE = 0x0,
  179. QUERY_DESC_IDN_CONFIGURATION = 0x1,
  180. QUERY_DESC_IDN_UNIT = 0x2,
  181. QUERY_DESC_IDN_RFU_0 = 0x3,
  182. QUERY_DESC_IDN_INTERCONNECT = 0x4,
  183. QUERY_DESC_IDN_STRING = 0x5,
  184. QUERY_DESC_IDN_RFU_1 = 0x6,
  185. QUERY_DESC_IDN_GEOMETRY = 0x7,
  186. QUERY_DESC_IDN_POWER = 0x8,
  187. QUERY_DESC_IDN_HEALTH = 0x9,
  188. QUERY_DESC_IDN_MAX,
  189. };
  190. enum desc_header_offset {
  191. QUERY_DESC_LENGTH_OFFSET = 0x00,
  192. QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
  193. };
  194. /* Unit descriptor parameters offsets in bytes*/
  195. enum unit_desc_param {
  196. UNIT_DESC_PARAM_LEN = 0x0,
  197. UNIT_DESC_PARAM_TYPE = 0x1,
  198. UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
  199. UNIT_DESC_PARAM_LU_ENABLE = 0x3,
  200. UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
  201. UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
  202. UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
  203. UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
  204. UNIT_DESC_PARAM_MEM_TYPE = 0x8,
  205. UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
  206. UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
  207. UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
  208. UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
  209. UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
  210. UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
  211. UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
  212. UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
  213. UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
  214. UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
  215. UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
  216. UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
  217. };
  218. /* RPMB Unit descriptor parameters offsets in bytes*/
  219. enum rpmb_unit_desc_param {
  220. RPMB_UNIT_DESC_PARAM_LEN = 0x0,
  221. RPMB_UNIT_DESC_PARAM_TYPE = 0x1,
  222. RPMB_UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
  223. RPMB_UNIT_DESC_PARAM_LU_ENABLE = 0x3,
  224. RPMB_UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
  225. RPMB_UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
  226. RPMB_UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
  227. RPMB_UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
  228. RPMB_UNIT_DESC_PARAM_MEM_TYPE = 0x8,
  229. RPMB_UNIT_DESC_PARAM_REGION_EN = 0x9,
  230. RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
  231. RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
  232. RPMB_UNIT_DESC_PARAM_REGION0_SIZE = 0x13,
  233. RPMB_UNIT_DESC_PARAM_REGION1_SIZE = 0x14,
  234. RPMB_UNIT_DESC_PARAM_REGION2_SIZE = 0x15,
  235. RPMB_UNIT_DESC_PARAM_REGION3_SIZE = 0x16,
  236. RPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
  237. RPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
  238. };
  239. /* Device descriptor parameters offsets in bytes*/
  240. enum device_desc_param {
  241. DEVICE_DESC_PARAM_LEN = 0x0,
  242. DEVICE_DESC_PARAM_TYPE = 0x1,
  243. DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
  244. DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
  245. DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
  246. DEVICE_DESC_PARAM_PRTCL = 0x5,
  247. DEVICE_DESC_PARAM_NUM_LU = 0x6,
  248. DEVICE_DESC_PARAM_NUM_WLU = 0x7,
  249. DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
  250. DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
  251. DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
  252. DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
  253. DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
  254. DEVICE_DESC_PARAM_SEC_LU = 0xD,
  255. DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
  256. DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
  257. DEVICE_DESC_PARAM_SPEC_VER = 0x10,
  258. DEVICE_DESC_PARAM_MANF_DATE = 0x12,
  259. DEVICE_DESC_PARAM_MANF_NAME = 0x14,
  260. DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
  261. DEVICE_DESC_PARAM_SN = 0x16,
  262. DEVICE_DESC_PARAM_OEM_ID = 0x17,
  263. DEVICE_DESC_PARAM_MANF_ID = 0x18,
  264. DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
  265. DEVICE_DESC_PARAM_UD_LEN = 0x1B,
  266. DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
  267. DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
  268. DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
  269. DEVICE_DESC_PARAM_FFU_TMT = 0x20,
  270. DEVICE_DESC_PARAM_Q_DPTH = 0x21,
  271. DEVICE_DESC_PARAM_DEV_VER = 0x22,
  272. DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
  273. DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
  274. DEVICE_DESC_PARAM_PSA_TMT = 0x29,
  275. DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
  276. DEVICE_DESC_PARAM_HPB_VER = 0x40,
  277. DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
  278. DEVICE_DESC_PARAM_EXT_WB_SUP = 0x4D,
  279. DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
  280. DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
  281. DEVICE_DESC_PARAM_WB_TYPE = 0x54,
  282. DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
  283. };
  284. /* Interconnect descriptor parameters offsets in bytes*/
  285. enum interconnect_desc_param {
  286. INTERCONNECT_DESC_PARAM_LEN = 0x0,
  287. INTERCONNECT_DESC_PARAM_TYPE = 0x1,
  288. INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
  289. INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
  290. };
  291. /* Geometry descriptor parameters offsets in bytes*/
  292. enum geometry_desc_param {
  293. GEOMETRY_DESC_PARAM_LEN = 0x0,
  294. GEOMETRY_DESC_PARAM_TYPE = 0x1,
  295. GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
  296. GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
  297. GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
  298. GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
  299. GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
  300. GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
  301. GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
  302. GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
  303. GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
  304. GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
  305. GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
  306. GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
  307. GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
  308. GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
  309. GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
  310. GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
  311. GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
  312. GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
  313. GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
  314. GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
  315. GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
  316. GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
  317. GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
  318. GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
  319. GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
  320. GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
  321. GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
  322. GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
  323. GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
  324. GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
  325. GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
  326. GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
  327. GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
  328. GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
  329. GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
  330. GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
  331. GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
  332. GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
  333. GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
  334. };
  335. /* Health descriptor parameters offsets in bytes*/
  336. enum health_desc_param {
  337. HEALTH_DESC_PARAM_LEN = 0x0,
  338. HEALTH_DESC_PARAM_TYPE = 0x1,
  339. HEALTH_DESC_PARAM_EOL_INFO = 0x2,
  340. HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
  341. HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
  342. };
  343. /* WriteBooster buffer mode */
  344. enum {
  345. WB_BUF_MODE_LU_DEDICATED = 0x0,
  346. WB_BUF_MODE_SHARED = 0x1,
  347. };
  348. /*
  349. * Logical Unit Write Protect
  350. * 00h: LU not write protected
  351. * 01h: LU write protected when fPowerOnWPEn =1
  352. * 02h: LU permanently write protected when fPermanentWPEn =1
  353. */
  354. enum ufs_lu_wp_type {
  355. UFS_LU_NO_WP = 0x00,
  356. UFS_LU_POWER_ON_WP = 0x01,
  357. UFS_LU_PERM_WP = 0x02,
  358. };
  359. /* bActiveICCLevel parameter current units */
  360. enum {
  361. UFSHCD_NANO_AMP = 0,
  362. UFSHCD_MICRO_AMP = 1,
  363. UFSHCD_MILI_AMP = 2,
  364. UFSHCD_AMP = 3,
  365. };
  366. /* Possible values for wExtendedWriteBoosterSupport */
  367. enum {
  368. UFS_DEV_WB_BUF_RESIZE = BIT(0),
  369. };
  370. /* Possible values for dExtendedUFSFeaturesSupport */
  371. enum {
  372. UFS_DEV_HIGH_TEMP_NOTIF = BIT(4),
  373. UFS_DEV_LOW_TEMP_NOTIF = BIT(5),
  374. UFS_DEV_EXT_TEMP_NOTIF = BIT(6),
  375. UFS_DEV_HPB_SUPPORT = BIT(7),
  376. UFS_DEV_WRITE_BOOSTER_SUP = BIT(8),
  377. UFS_DEV_LVL_EXCEPTION_SUP = BIT(12),
  378. UFS_DEV_HID_SUPPORT = BIT(13),
  379. };
  380. #define UFS_DEV_HPB_SUPPORT_VERSION 0x310
  381. #define POWER_DESC_MAX_ACTV_ICC_LVLS 16
  382. /* Attribute bActiveICCLevel parameter bit masks definitions */
  383. #define ATTR_ICC_LVL_UNIT_OFFSET 14
  384. #define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
  385. #define ATTR_ICC_LVL_VALUE_MASK 0x3FF
  386. /* Power descriptor parameters offsets in bytes */
  387. enum power_desc_param_offset {
  388. PWR_DESC_LEN = 0x0,
  389. PWR_DESC_TYPE = 0x1,
  390. PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2,
  391. PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22,
  392. PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42,
  393. };
  394. /* Exception event mask values */
  395. enum {
  396. MASK_EE_STATUS = 0xFFFF,
  397. MASK_EE_DYNCAP_EVENT = BIT(0),
  398. MASK_EE_SYSPOOL_EVENT = BIT(1),
  399. MASK_EE_URGENT_BKOPS = BIT(2),
  400. MASK_EE_TOO_HIGH_TEMP = BIT(3),
  401. MASK_EE_TOO_LOW_TEMP = BIT(4),
  402. MASK_EE_WRITEBOOSTER_EVENT = BIT(5),
  403. MASK_EE_PERFORMANCE_THROTTLING = BIT(6),
  404. MASK_EE_DEV_LVL_EXCEPTION = BIT(7),
  405. MASK_EE_HEALTH_CRITICAL = BIT(9),
  406. };
  407. #define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP)
  408. /* Background operation status */
  409. enum bkops_status {
  410. BKOPS_STATUS_NO_OP = 0x0,
  411. BKOPS_STATUS_NON_CRITICAL = 0x1,
  412. BKOPS_STATUS_PERF_IMPACT = 0x2,
  413. BKOPS_STATUS_CRITICAL = 0x3,
  414. BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL,
  415. };
  416. /* UTP QUERY Transaction Specific Fields OpCode */
  417. enum query_opcode {
  418. UPIU_QUERY_OPCODE_NOP = 0x0,
  419. UPIU_QUERY_OPCODE_READ_DESC = 0x1,
  420. UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
  421. UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
  422. UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
  423. UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
  424. UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
  425. UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
  426. UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
  427. };
  428. /* bRefClkFreq attribute values */
  429. enum ufs_ref_clk_freq {
  430. REF_CLK_FREQ_19_2_MHZ = 0,
  431. REF_CLK_FREQ_26_MHZ = 1,
  432. REF_CLK_FREQ_38_4_MHZ = 2,
  433. REF_CLK_FREQ_52_MHZ = 3,
  434. REF_CLK_FREQ_INVAL = -1,
  435. };
  436. /* bDefragOperation attribute values */
  437. enum ufs_hid_defrag_operation {
  438. HID_ANALYSIS_AND_DEFRAG_DISABLE = 0,
  439. HID_ANALYSIS_ENABLE = 1,
  440. HID_ANALYSIS_AND_DEFRAG_ENABLE = 2,
  441. };
  442. /* bHIDState attribute values */
  443. enum ufs_hid_state {
  444. HID_IDLE = 0,
  445. ANALYSIS_IN_PROGRESS = 1,
  446. DEFRAG_REQUIRED = 2,
  447. DEFRAG_IN_PROGRESS = 3,
  448. DEFRAG_COMPLETED = 4,
  449. DEFRAG_NOT_REQUIRED = 5,
  450. NUM_UFS_HID_STATES = 6,
  451. };
  452. /* bWriteBoosterBufferResizeEn attribute */
  453. enum wb_resize_en {
  454. WB_RESIZE_EN_IDLE = 0,
  455. WB_RESIZE_EN_DECREASE = 1,
  456. WB_RESIZE_EN_INCREASE = 2,
  457. };
  458. /* bWriteBoosterBufferResizeHint attribute */
  459. enum wb_resize_hint {
  460. WB_RESIZE_HINT_KEEP = 0,
  461. WB_RESIZE_HINT_DECREASE = 1,
  462. WB_RESIZE_HINT_INCREASE = 2,
  463. };
  464. /* bWriteBoosterBufferResizeStatus attribute */
  465. enum wb_resize_status {
  466. WB_RESIZE_STATUS_IDLE = 0,
  467. WB_RESIZE_STATUS_IN_PROGRESS = 1,
  468. WB_RESIZE_STATUS_COMPLETE_SUCCESS = 2,
  469. WB_RESIZE_STATUS_GENERAL_FAILURE = 3,
  470. };
  471. /* Query response result code */
  472. enum {
  473. QUERY_RESULT_SUCCESS = 0x00,
  474. QUERY_RESULT_NOT_READABLE = 0xF6,
  475. QUERY_RESULT_NOT_WRITEABLE = 0xF7,
  476. QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
  477. QUERY_RESULT_INVALID_LENGTH = 0xF9,
  478. QUERY_RESULT_INVALID_VALUE = 0xFA,
  479. QUERY_RESULT_INVALID_SELECTOR = 0xFB,
  480. QUERY_RESULT_INVALID_INDEX = 0xFC,
  481. QUERY_RESULT_INVALID_IDN = 0xFD,
  482. QUERY_RESULT_INVALID_OPCODE = 0xFE,
  483. QUERY_RESULT_GENERAL_FAILURE = 0xFF,
  484. };
  485. /* UTP Transfer Request Command Type (CT) */
  486. enum {
  487. UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
  488. UPIU_COMMAND_SET_TYPE_UFS = 0x1,
  489. UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
  490. };
  491. /* Offset of the response code in the UPIU header */
  492. #define UPIU_RSP_CODE_OFFSET 8
  493. enum {
  494. MASK_TM_SERVICE_RESP = 0xFF,
  495. };
  496. /* Task management service response */
  497. enum {
  498. UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
  499. UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
  500. UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
  501. UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
  502. UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
  503. };
  504. /* UFS device power modes */
  505. enum ufs_dev_pwr_mode {
  506. UFS_ACTIVE_PWR_MODE = 1,
  507. UFS_SLEEP_PWR_MODE = 2,
  508. UFS_POWERDOWN_PWR_MODE = 3,
  509. UFS_DEEPSLEEP_PWR_MODE = 4,
  510. };
  511. #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
  512. /**
  513. * struct utp_cmd_rsp - RESPONSE UPIU structure
  514. * @residual_transfer_count: Residual transfer count DW-3
  515. * @reserved: Reserved double words DW-4 to DW-7
  516. * @sense_data_len: Sense data length DW-8 U16
  517. * @sense_data: Sense data field DW-8 to DW-12
  518. */
  519. struct utp_cmd_rsp {
  520. __be32 residual_transfer_count;
  521. __be32 reserved[4];
  522. __be16 sense_data_len;
  523. u8 sense_data[UFS_SENSE_SIZE];
  524. };
  525. static_assert(sizeof(struct utp_cmd_rsp) == 40);
  526. /**
  527. * struct utp_upiu_rsp - general upiu response structure
  528. * @header: UPIU header structure DW-0 to DW-2
  529. * @sr: fields structure for scsi command DW-3 to DW-12
  530. * @qr: fields structure for query request DW-3 to DW-7
  531. */
  532. struct utp_upiu_rsp {
  533. struct utp_upiu_header header;
  534. union {
  535. struct utp_cmd_rsp sr;
  536. struct utp_upiu_query qr;
  537. };
  538. };
  539. /*
  540. * VCCQ & VCCQ2 current requirement when UFS device is in sleep state
  541. * and link is in Hibern8 state.
  542. */
  543. #define UFS_VREG_LPM_LOAD_UA 1000 /* uA */
  544. struct ufs_vreg {
  545. struct regulator *reg;
  546. const char *name;
  547. bool always_on;
  548. bool enabled;
  549. int max_uA;
  550. };
  551. struct ufs_vreg_info {
  552. struct ufs_vreg *vcc;
  553. struct ufs_vreg *vccq;
  554. struct ufs_vreg *vccq2;
  555. struct ufs_vreg *vdd_hba;
  556. };
  557. /* UFS device descriptor wPeriodicRTCUpdate bit9 defines RTC time baseline */
  558. #define UFS_RTC_TIME_BASELINE BIT(9)
  559. enum ufs_rtc_time {
  560. UFS_RTC_RELATIVE,
  561. UFS_RTC_ABSOLUTE
  562. };
  563. struct ufs_dev_info {
  564. bool f_power_on_wp_en;
  565. /* Keeps information if any of the LU is power on write protected */
  566. bool is_lu_power_on_wp;
  567. /* Maximum number of general LU supported by the UFS device */
  568. u8 max_lu_supported;
  569. u16 wmanufacturerid;
  570. /*UFS device Product Name */
  571. u8 *model;
  572. u16 wspecversion;
  573. u32 clk_gating_wait_us;
  574. /* Stores the depth of queue in UFS device */
  575. u8 bqueuedepth;
  576. /* UFS WB related flags */
  577. bool wb_enabled;
  578. bool wb_buf_flush_enabled;
  579. u8 wb_dedicated_lu;
  580. u8 wb_buffer_type;
  581. u16 ext_wb_sup;
  582. bool b_rpm_dev_flush_capable;
  583. u8 b_presrv_uspc_en;
  584. bool b_advanced_rpmb_en;
  585. /* UFS RTC */
  586. enum ufs_rtc_time rtc_type;
  587. time64_t rtc_time_baseline;
  588. u32 rtc_update_period;
  589. u8 rtt_cap; /* bDeviceRTTCap */
  590. bool hid_sup;
  591. /* Unique device ID string (manufacturer+model+serial+version+date) */
  592. char *device_id;
  593. u8 rpmb_io_size;
  594. u8 rpmb_region_size[4];
  595. };
  596. #endif /* End of Header */