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- /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
- #ifndef INTERCONNECT_QCOM_IPQ5424_H
- #define INTERCONNECT_QCOM_IPQ5424_H
- #define MASTER_ANOC_PCIE0 0
- #define SLAVE_ANOC_PCIE0 1
- #define MASTER_CNOC_PCIE0 2
- #define SLAVE_CNOC_PCIE0 3
- #define MASTER_ANOC_PCIE1 4
- #define SLAVE_ANOC_PCIE1 5
- #define MASTER_CNOC_PCIE1 6
- #define SLAVE_CNOC_PCIE1 7
- #define MASTER_ANOC_PCIE2 8
- #define SLAVE_ANOC_PCIE2 9
- #define MASTER_CNOC_PCIE2 10
- #define SLAVE_CNOC_PCIE2 11
- #define MASTER_ANOC_PCIE3 12
- #define SLAVE_ANOC_PCIE3 13
- #define MASTER_CNOC_PCIE3 14
- #define SLAVE_CNOC_PCIE3 15
- #define MASTER_CNOC_USB 16
- #define SLAVE_CNOC_USB 17
- #define MASTER_NSSNOC_NSSCC 18
- #define SLAVE_NSSNOC_NSSCC 19
- #define MASTER_NSSNOC_SNOC_0 20
- #define SLAVE_NSSNOC_SNOC_0 21
- #define MASTER_NSSNOC_SNOC_1 22
- #define SLAVE_NSSNOC_SNOC_1 23
- #define MASTER_NSSNOC_PCNOC_1 24
- #define SLAVE_NSSNOC_PCNOC_1 25
- #define MASTER_NSSNOC_QOSGEN_REF 26
- #define SLAVE_NSSNOC_QOSGEN_REF 27
- #define MASTER_NSSNOC_TIMEOUT_REF 28
- #define SLAVE_NSSNOC_TIMEOUT_REF 29
- #define MASTER_NSSNOC_XO_DCD 30
- #define SLAVE_NSSNOC_XO_DCD 31
- #define MASTER_NSSNOC_ATB 32
- #define SLAVE_NSSNOC_ATB 33
- #define MASTER_CNOC_LPASS_CFG 34
- #define SLAVE_CNOC_LPASS_CFG 35
- #define MASTER_SNOC_LPASS 36
- #define SLAVE_SNOC_LPASS 37
- #define MASTER_CPU 0
- #define SLAVE_L3 1
- #define MASTER_NSSNOC_PPE 0
- #define SLAVE_NSSNOC_PPE 1
- #define MASTER_NSSNOC_PPE_CFG 2
- #define SLAVE_NSSNOC_PPE_CFG 3
- #define MASTER_NSSNOC_NSS_CSR 4
- #define SLAVE_NSSNOC_NSS_CSR 5
- #define MASTER_NSSNOC_CE_AXI 6
- #define SLAVE_NSSNOC_CE_AXI 7
- #define MASTER_NSSNOC_CE_APB 8
- #define SLAVE_NSSNOC_CE_APB 9
- #define MASTER_NSSNOC_EIP 10
- #define SLAVE_NSSNOC_EIP 11
- #endif /* INTERCONNECT_QCOM_IPQ5424_H */
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