ili922x.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * (C) Copyright 2008
  4. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  5. *
  6. * This driver implements a lcd device for the ILITEK 922x display
  7. * controller. The interface to the display is SPI and the display's
  8. * memory is cyclically updated over the RGB interface.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/lcd.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/slab.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/string.h>
  20. /* Register offset, see manual section 8.2 */
  21. #define REG_START_OSCILLATION 0x00
  22. #define REG_DRIVER_CODE_READ 0x00
  23. #define REG_DRIVER_OUTPUT_CONTROL 0x01
  24. #define REG_LCD_AC_DRIVEING_CONTROL 0x02
  25. #define REG_ENTRY_MODE 0x03
  26. #define REG_COMPARE_1 0x04
  27. #define REG_COMPARE_2 0x05
  28. #define REG_DISPLAY_CONTROL_1 0x07
  29. #define REG_DISPLAY_CONTROL_2 0x08
  30. #define REG_DISPLAY_CONTROL_3 0x09
  31. #define REG_FRAME_CYCLE_CONTROL 0x0B
  32. #define REG_EXT_INTF_CONTROL 0x0C
  33. #define REG_POWER_CONTROL_1 0x10
  34. #define REG_POWER_CONTROL_2 0x11
  35. #define REG_POWER_CONTROL_3 0x12
  36. #define REG_POWER_CONTROL_4 0x13
  37. #define REG_RAM_ADDRESS_SET 0x21
  38. #define REG_WRITE_DATA_TO_GRAM 0x22
  39. #define REG_RAM_WRITE_MASK1 0x23
  40. #define REG_RAM_WRITE_MASK2 0x24
  41. #define REG_GAMMA_CONTROL_1 0x30
  42. #define REG_GAMMA_CONTROL_2 0x31
  43. #define REG_GAMMA_CONTROL_3 0x32
  44. #define REG_GAMMA_CONTROL_4 0x33
  45. #define REG_GAMMA_CONTROL_5 0x34
  46. #define REG_GAMMA_CONTROL_6 0x35
  47. #define REG_GAMMA_CONTROL_7 0x36
  48. #define REG_GAMMA_CONTROL_8 0x37
  49. #define REG_GAMMA_CONTROL_9 0x38
  50. #define REG_GAMMA_CONTROL_10 0x39
  51. #define REG_GATE_SCAN_CONTROL 0x40
  52. #define REG_VERT_SCROLL_CONTROL 0x41
  53. #define REG_FIRST_SCREEN_DRIVE_POS 0x42
  54. #define REG_SECOND_SCREEN_DRIVE_POS 0x43
  55. #define REG_RAM_ADDR_POS_H 0x44
  56. #define REG_RAM_ADDR_POS_V 0x45
  57. #define REG_OSCILLATOR_CONTROL 0x4F
  58. #define REG_GPIO 0x60
  59. #define REG_OTP_VCM_PROGRAMMING 0x61
  60. #define REG_OTP_VCM_STATUS_ENABLE 0x62
  61. #define REG_OTP_PROGRAMMING_ID_KEY 0x65
  62. /*
  63. * maximum frequency for register access
  64. * (not for the GRAM access)
  65. */
  66. #define ILITEK_MAX_FREQ_REG 4000000
  67. /*
  68. * Device ID as found in the datasheet (supports 9221 and 9222)
  69. */
  70. #define ILITEK_DEVICE_ID 0x9220
  71. #define ILITEK_DEVICE_ID_MASK 0xFFF0
  72. /* Last two bits in the START BYTE */
  73. #define START_RS_INDEX 0
  74. #define START_RS_REG 1
  75. #define START_RW_WRITE 0
  76. #define START_RW_READ 1
  77. /*
  78. * START_BYTE(id, rs, rw)
  79. *
  80. * Set the start byte according to the required operation.
  81. * The start byte is defined as:
  82. * ----------------------------------
  83. * | 0 | 1 | 1 | 1 | 0 | ID | RS | RW |
  84. * ----------------------------------
  85. * @id: display's id as set by the manufacturer
  86. * @rs: operation type bit, one of:
  87. * - START_RS_INDEX set the index register
  88. * - START_RS_REG write/read registers/GRAM
  89. * @rw: read/write operation
  90. * - START_RW_WRITE write
  91. * - START_RW_READ read
  92. */
  93. #define START_BYTE(id, rs, rw) \
  94. (0x70 | (((id) & 0x01) << 2) | (((rs) & 0x01) << 1) | ((rw) & 0x01))
  95. /*
  96. * CHECK_FREQ_REG(spi_device s, spi_transfer x) - Check the frequency
  97. * for the SPI transfer. According to the datasheet, the controller
  98. * accept higher frequency for the GRAM transfer, but it requires
  99. * lower frequency when the registers are read/written.
  100. * The macro sets the frequency in the spi_transfer structure if
  101. * the frequency exceeds the maximum value.
  102. * @s: pointer to an SPI device
  103. * @x: pointer to the read/write buffer pair
  104. */
  105. #define CHECK_FREQ_REG(s, x) \
  106. do { \
  107. if (s->max_speed_hz > ILITEK_MAX_FREQ_REG) \
  108. ((struct spi_transfer *)x)->speed_hz = \
  109. ILITEK_MAX_FREQ_REG; \
  110. } while (0)
  111. #define CMD_BUFSIZE 16
  112. #define POWER_IS_ON(pwr) ((pwr) <= LCD_POWER_REDUCED)
  113. #define set_tx_byte(b) (tx_invert ? ~(b) : b)
  114. /*
  115. * ili922x_id - id as set by manufacturer
  116. */
  117. static int ili922x_id = 1;
  118. module_param(ili922x_id, int, 0);
  119. static int tx_invert;
  120. module_param(tx_invert, int, 0);
  121. /*
  122. * driver's private structure
  123. */
  124. struct ili922x {
  125. struct spi_device *spi;
  126. struct lcd_device *ld;
  127. int power;
  128. };
  129. /**
  130. * ili922x_read_status - read status register from display
  131. * @spi: spi device
  132. * @rs: output value
  133. */
  134. static int ili922x_read_status(struct spi_device *spi, u16 *rs)
  135. {
  136. struct spi_message msg;
  137. struct spi_transfer xfer;
  138. unsigned char tbuf[CMD_BUFSIZE];
  139. unsigned char rbuf[CMD_BUFSIZE];
  140. int ret, i;
  141. memset(&xfer, 0, sizeof(struct spi_transfer));
  142. spi_message_init(&msg);
  143. xfer.tx_buf = tbuf;
  144. xfer.rx_buf = rbuf;
  145. xfer.cs_change = 1;
  146. CHECK_FREQ_REG(spi, &xfer);
  147. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
  148. START_RW_READ));
  149. /*
  150. * we need 4-byte xfer here due to invalid dummy byte
  151. * received after start byte
  152. */
  153. for (i = 1; i < 4; i++)
  154. tbuf[i] = set_tx_byte(0); /* dummy */
  155. xfer.bits_per_word = 8;
  156. xfer.len = 4;
  157. spi_message_add_tail(&xfer, &msg);
  158. ret = spi_sync(spi, &msg);
  159. if (ret < 0) {
  160. dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
  161. return ret;
  162. }
  163. *rs = (rbuf[2] << 8) + rbuf[3];
  164. return 0;
  165. }
  166. /**
  167. * ili922x_read - read register from display
  168. * @spi: spi device
  169. * @reg: offset of the register to be read
  170. * @rx: output value
  171. */
  172. static int ili922x_read(struct spi_device *spi, u8 reg, u16 *rx)
  173. {
  174. struct spi_message msg;
  175. struct spi_transfer xfer_regindex, xfer_regvalue;
  176. unsigned char tbuf[CMD_BUFSIZE];
  177. unsigned char rbuf[CMD_BUFSIZE];
  178. int ret, len = 0, send_bytes;
  179. memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
  180. memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
  181. spi_message_init(&msg);
  182. xfer_regindex.tx_buf = tbuf;
  183. xfer_regindex.rx_buf = rbuf;
  184. xfer_regindex.cs_change = 1;
  185. CHECK_FREQ_REG(spi, &xfer_regindex);
  186. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
  187. START_RW_WRITE));
  188. tbuf[1] = set_tx_byte(0);
  189. tbuf[2] = set_tx_byte(reg);
  190. xfer_regindex.bits_per_word = 8;
  191. len = xfer_regindex.len = 3;
  192. spi_message_add_tail(&xfer_regindex, &msg);
  193. send_bytes = len;
  194. tbuf[len++] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
  195. START_RW_READ));
  196. tbuf[len++] = set_tx_byte(0);
  197. tbuf[len] = set_tx_byte(0);
  198. xfer_regvalue.cs_change = 1;
  199. xfer_regvalue.len = 3;
  200. xfer_regvalue.tx_buf = &tbuf[send_bytes];
  201. xfer_regvalue.rx_buf = &rbuf[send_bytes];
  202. CHECK_FREQ_REG(spi, &xfer_regvalue);
  203. spi_message_add_tail(&xfer_regvalue, &msg);
  204. ret = spi_sync(spi, &msg);
  205. if (ret < 0) {
  206. dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
  207. return ret;
  208. }
  209. *rx = (rbuf[1 + send_bytes] << 8) + rbuf[2 + send_bytes];
  210. return 0;
  211. }
  212. /**
  213. * ili922x_write - write a controller register
  214. * @spi: struct spi_device *
  215. * @reg: offset of the register to be written
  216. * @value: value to be written
  217. */
  218. static int ili922x_write(struct spi_device *spi, u8 reg, u16 value)
  219. {
  220. struct spi_message msg;
  221. struct spi_transfer xfer_regindex, xfer_regvalue;
  222. unsigned char tbuf[CMD_BUFSIZE];
  223. unsigned char rbuf[CMD_BUFSIZE];
  224. int ret;
  225. memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
  226. memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
  227. spi_message_init(&msg);
  228. xfer_regindex.tx_buf = tbuf;
  229. xfer_regindex.rx_buf = rbuf;
  230. xfer_regindex.cs_change = 1;
  231. CHECK_FREQ_REG(spi, &xfer_regindex);
  232. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
  233. START_RW_WRITE));
  234. tbuf[1] = set_tx_byte(0);
  235. tbuf[2] = set_tx_byte(reg);
  236. xfer_regindex.bits_per_word = 8;
  237. xfer_regindex.len = 3;
  238. spi_message_add_tail(&xfer_regindex, &msg);
  239. ret = spi_sync(spi, &msg);
  240. if (ret < 0) {
  241. dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
  242. return ret;
  243. }
  244. spi_message_init(&msg);
  245. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
  246. START_RW_WRITE));
  247. tbuf[1] = set_tx_byte((value & 0xFF00) >> 8);
  248. tbuf[2] = set_tx_byte(value & 0x00FF);
  249. xfer_regvalue.cs_change = 1;
  250. xfer_regvalue.len = 3;
  251. xfer_regvalue.tx_buf = tbuf;
  252. xfer_regvalue.rx_buf = rbuf;
  253. CHECK_FREQ_REG(spi, &xfer_regvalue);
  254. spi_message_add_tail(&xfer_regvalue, &msg);
  255. ret = spi_sync(spi, &msg);
  256. if (ret < 0) {
  257. dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
  258. return ret;
  259. }
  260. return 0;
  261. }
  262. #ifdef DEBUG
  263. /**
  264. * ili922x_reg_dump - dump all registers
  265. *
  266. * @spi: pointer to an SPI device
  267. */
  268. static void ili922x_reg_dump(struct spi_device *spi)
  269. {
  270. u8 reg;
  271. u16 rx;
  272. dev_dbg(&spi->dev, "ILI922x configuration registers:\n");
  273. for (reg = REG_START_OSCILLATION;
  274. reg <= REG_OTP_PROGRAMMING_ID_KEY; reg++) {
  275. ili922x_read(spi, reg, &rx);
  276. dev_dbg(&spi->dev, "reg @ 0x%02X: 0x%04X\n", reg, rx);
  277. }
  278. }
  279. #else
  280. static inline void ili922x_reg_dump(struct spi_device *spi) {}
  281. #endif
  282. /**
  283. * set_write_to_gram_reg - initialize the display to write the GRAM
  284. * @spi: spi device
  285. */
  286. static void set_write_to_gram_reg(struct spi_device *spi)
  287. {
  288. struct spi_message msg;
  289. struct spi_transfer xfer;
  290. unsigned char tbuf[CMD_BUFSIZE];
  291. memset(&xfer, 0, sizeof(struct spi_transfer));
  292. spi_message_init(&msg);
  293. xfer.tx_buf = tbuf;
  294. xfer.rx_buf = NULL;
  295. xfer.cs_change = 1;
  296. tbuf[0] = START_BYTE(ili922x_id, START_RS_INDEX, START_RW_WRITE);
  297. tbuf[1] = 0;
  298. tbuf[2] = REG_WRITE_DATA_TO_GRAM;
  299. xfer.bits_per_word = 8;
  300. xfer.len = 3;
  301. spi_message_add_tail(&xfer, &msg);
  302. spi_sync(spi, &msg);
  303. }
  304. /**
  305. * ili922x_poweron - turn the display on
  306. * @spi: spi device
  307. *
  308. * The sequence to turn on the display is taken from
  309. * the datasheet and/or the example code provided by the
  310. * manufacturer.
  311. */
  312. static int ili922x_poweron(struct spi_device *spi)
  313. {
  314. int ret;
  315. /* Power on */
  316. ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
  317. usleep_range(10000, 10500);
  318. ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
  319. ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
  320. msleep(40);
  321. ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
  322. msleep(40);
  323. /* register 0x56 is not documented in the datasheet */
  324. ret += ili922x_write(spi, 0x56, 0x080F);
  325. ret += ili922x_write(spi, REG_POWER_CONTROL_1, 0x4240);
  326. usleep_range(10000, 10500);
  327. ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
  328. ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0014);
  329. msleep(40);
  330. ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x1319);
  331. msleep(40);
  332. return ret;
  333. }
  334. /**
  335. * ili922x_poweroff - turn the display off
  336. * @spi: spi device
  337. */
  338. static int ili922x_poweroff(struct spi_device *spi)
  339. {
  340. int ret;
  341. /* Power off */
  342. ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
  343. usleep_range(10000, 10500);
  344. ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
  345. ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
  346. msleep(40);
  347. ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
  348. msleep(40);
  349. return ret;
  350. }
  351. /**
  352. * ili922x_display_init - initialize the display by setting
  353. * the configuration registers
  354. * @spi: spi device
  355. */
  356. static void ili922x_display_init(struct spi_device *spi)
  357. {
  358. ili922x_write(spi, REG_START_OSCILLATION, 1);
  359. usleep_range(10000, 10500);
  360. ili922x_write(spi, REG_DRIVER_OUTPUT_CONTROL, 0x691B);
  361. ili922x_write(spi, REG_LCD_AC_DRIVEING_CONTROL, 0x0700);
  362. ili922x_write(spi, REG_ENTRY_MODE, 0x1030);
  363. ili922x_write(spi, REG_COMPARE_1, 0x0000);
  364. ili922x_write(spi, REG_COMPARE_2, 0x0000);
  365. ili922x_write(spi, REG_DISPLAY_CONTROL_1, 0x0037);
  366. ili922x_write(spi, REG_DISPLAY_CONTROL_2, 0x0202);
  367. ili922x_write(spi, REG_DISPLAY_CONTROL_3, 0x0000);
  368. ili922x_write(spi, REG_FRAME_CYCLE_CONTROL, 0x0000);
  369. /* Set RGB interface */
  370. ili922x_write(spi, REG_EXT_INTF_CONTROL, 0x0110);
  371. ili922x_poweron(spi);
  372. ili922x_write(spi, REG_GAMMA_CONTROL_1, 0x0302);
  373. ili922x_write(spi, REG_GAMMA_CONTROL_2, 0x0407);
  374. ili922x_write(spi, REG_GAMMA_CONTROL_3, 0x0304);
  375. ili922x_write(spi, REG_GAMMA_CONTROL_4, 0x0203);
  376. ili922x_write(spi, REG_GAMMA_CONTROL_5, 0x0706);
  377. ili922x_write(spi, REG_GAMMA_CONTROL_6, 0x0407);
  378. ili922x_write(spi, REG_GAMMA_CONTROL_7, 0x0706);
  379. ili922x_write(spi, REG_GAMMA_CONTROL_8, 0x0000);
  380. ili922x_write(spi, REG_GAMMA_CONTROL_9, 0x0C06);
  381. ili922x_write(spi, REG_GAMMA_CONTROL_10, 0x0F00);
  382. ili922x_write(spi, REG_RAM_ADDRESS_SET, 0x0000);
  383. ili922x_write(spi, REG_GATE_SCAN_CONTROL, 0x0000);
  384. ili922x_write(spi, REG_VERT_SCROLL_CONTROL, 0x0000);
  385. ili922x_write(spi, REG_FIRST_SCREEN_DRIVE_POS, 0xDB00);
  386. ili922x_write(spi, REG_SECOND_SCREEN_DRIVE_POS, 0xDB00);
  387. ili922x_write(spi, REG_RAM_ADDR_POS_H, 0xAF00);
  388. ili922x_write(spi, REG_RAM_ADDR_POS_V, 0xDB00);
  389. ili922x_reg_dump(spi);
  390. set_write_to_gram_reg(spi);
  391. }
  392. static int ili922x_lcd_power(struct ili922x *lcd, int power)
  393. {
  394. int ret = 0;
  395. if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
  396. ret = ili922x_poweron(lcd->spi);
  397. else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
  398. ret = ili922x_poweroff(lcd->spi);
  399. if (!ret)
  400. lcd->power = power;
  401. return ret;
  402. }
  403. static int ili922x_set_power(struct lcd_device *ld, int power)
  404. {
  405. struct ili922x *ili = lcd_get_data(ld);
  406. return ili922x_lcd_power(ili, power);
  407. }
  408. static int ili922x_get_power(struct lcd_device *ld)
  409. {
  410. struct ili922x *ili = lcd_get_data(ld);
  411. return ili->power;
  412. }
  413. static const struct lcd_ops ili922x_ops = {
  414. .get_power = ili922x_get_power,
  415. .set_power = ili922x_set_power,
  416. };
  417. static int ili922x_probe(struct spi_device *spi)
  418. {
  419. struct ili922x *ili;
  420. struct lcd_device *lcd;
  421. int ret;
  422. u16 reg = 0;
  423. ili = devm_kzalloc(&spi->dev, sizeof(*ili), GFP_KERNEL);
  424. if (!ili)
  425. return -ENOMEM;
  426. ili->spi = spi;
  427. spi_set_drvdata(spi, ili);
  428. /* check if the device is connected */
  429. ret = ili922x_read(spi, REG_DRIVER_CODE_READ, &reg);
  430. if (ret || ((reg & ILITEK_DEVICE_ID_MASK) != ILITEK_DEVICE_ID)) {
  431. dev_err(&spi->dev,
  432. "no LCD found: Chip ID 0x%x, ret %d\n",
  433. reg, ret);
  434. return -ENODEV;
  435. }
  436. dev_info(&spi->dev, "ILI%x found, SPI freq %d, mode %d\n",
  437. reg, spi->max_speed_hz, spi->mode);
  438. ret = ili922x_read_status(spi, &reg);
  439. if (ret) {
  440. dev_err(&spi->dev, "reading RS failed...\n");
  441. return ret;
  442. }
  443. dev_dbg(&spi->dev, "status: 0x%x\n", reg);
  444. ili922x_display_init(spi);
  445. ili->power = LCD_POWER_OFF;
  446. lcd = devm_lcd_device_register(&spi->dev, "ili922xlcd", &spi->dev, ili,
  447. &ili922x_ops);
  448. if (IS_ERR(lcd)) {
  449. dev_err(&spi->dev, "cannot register LCD\n");
  450. return PTR_ERR(lcd);
  451. }
  452. ili->ld = lcd;
  453. spi_set_drvdata(spi, ili);
  454. ili922x_lcd_power(ili, LCD_POWER_ON);
  455. return 0;
  456. }
  457. static void ili922x_remove(struct spi_device *spi)
  458. {
  459. ili922x_poweroff(spi);
  460. }
  461. static struct spi_driver ili922x_driver = {
  462. .driver = {
  463. .name = "ili922x",
  464. },
  465. .probe = ili922x_probe,
  466. .remove = ili922x_remove,
  467. };
  468. module_spi_driver(ili922x_driver);
  469. MODULE_AUTHOR("Stefano Babic <sbabic@denx.de>");
  470. MODULE_DESCRIPTION("ILI9221/9222 LCD driver");
  471. MODULE_LICENSE("GPL");
  472. MODULE_PARM_DESC(ili922x_id, "set controller identifier (default=1)");
  473. MODULE_PARM_DESC(tx_invert, "invert bytes before sending");