ifcvf_base.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel IFC VF NIC driver for virtio dataplane offloading
  4. *
  5. * Copyright (C) 2020 Intel Corporation.
  6. *
  7. * Author: Zhu Lingshan <lingshan.zhu@intel.com>
  8. *
  9. */
  10. #include "ifcvf_base.h"
  11. u16 ifcvf_set_vq_vector(struct ifcvf_hw *hw, u16 qid, int vector)
  12. {
  13. struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
  14. vp_iowrite16(qid, &cfg->queue_select);
  15. vp_iowrite16(vector, &cfg->queue_msix_vector);
  16. return vp_ioread16(&cfg->queue_msix_vector);
  17. }
  18. u16 ifcvf_set_config_vector(struct ifcvf_hw *hw, int vector)
  19. {
  20. struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
  21. vp_iowrite16(vector, &cfg->msix_config);
  22. return vp_ioread16(&cfg->msix_config);
  23. }
  24. static void __iomem *get_cap_addr(struct ifcvf_hw *hw,
  25. struct virtio_pci_cap *cap)
  26. {
  27. u32 length, offset;
  28. u8 bar;
  29. length = le32_to_cpu(cap->length);
  30. offset = le32_to_cpu(cap->offset);
  31. bar = cap->bar;
  32. if (bar >= IFCVF_PCI_MAX_RESOURCE) {
  33. IFCVF_DBG(hw->pdev,
  34. "Invalid bar number %u to get capabilities\n", bar);
  35. return NULL;
  36. }
  37. if (offset + length > pci_resource_len(hw->pdev, bar)) {
  38. IFCVF_DBG(hw->pdev,
  39. "offset(%u) + len(%u) overflows bar%u's capability\n",
  40. offset, length, bar);
  41. return NULL;
  42. }
  43. return hw->base[bar] + offset;
  44. }
  45. static int ifcvf_read_config_range(struct pci_dev *dev,
  46. uint32_t *val, int size, int where)
  47. {
  48. int ret, i;
  49. for (i = 0; i < size; i += 4) {
  50. ret = pci_read_config_dword(dev, where + i, val + i / 4);
  51. if (ret < 0)
  52. return ret;
  53. }
  54. return 0;
  55. }
  56. u16 ifcvf_get_vq_size(struct ifcvf_hw *hw, u16 qid)
  57. {
  58. u16 queue_size;
  59. if (qid >= hw->nr_vring)
  60. return 0;
  61. vp_iowrite16(qid, &hw->common_cfg->queue_select);
  62. queue_size = vp_ioread16(&hw->common_cfg->queue_size);
  63. return queue_size;
  64. }
  65. u16 ifcvf_get_max_vq_size(struct ifcvf_hw *hw)
  66. {
  67. u16 queue_size, max_size, qid;
  68. max_size = ifcvf_get_vq_size(hw, 0);
  69. for (qid = 1; qid < hw->nr_vring; qid++) {
  70. queue_size = ifcvf_get_vq_size(hw, qid);
  71. /* 0 means the queue is unavailable */
  72. if (!queue_size)
  73. continue;
  74. max_size = max(queue_size, max_size);
  75. }
  76. return max_size;
  77. }
  78. int ifcvf_init_hw(struct ifcvf_hw *hw, struct pci_dev *pdev)
  79. {
  80. struct virtio_pci_cap cap;
  81. u16 notify_off;
  82. int ret;
  83. u8 pos;
  84. u32 i;
  85. ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
  86. if (ret) {
  87. IFCVF_ERR(pdev, "Failed to read PCI capability list\n");
  88. return -EIO;
  89. }
  90. hw->pdev = pdev;
  91. while (pos) {
  92. ret = ifcvf_read_config_range(pdev, (u32 *)&cap,
  93. sizeof(cap), pos);
  94. if (ret < 0) {
  95. IFCVF_ERR(pdev,
  96. "Failed to get PCI capability at %x\n", pos);
  97. break;
  98. }
  99. if (cap.cap_vndr != PCI_CAP_ID_VNDR)
  100. goto next;
  101. switch (cap.cfg_type) {
  102. case VIRTIO_PCI_CAP_COMMON_CFG:
  103. hw->common_cfg = get_cap_addr(hw, &cap);
  104. IFCVF_DBG(pdev, "hw->common_cfg = %p\n",
  105. hw->common_cfg);
  106. break;
  107. case VIRTIO_PCI_CAP_NOTIFY_CFG:
  108. pci_read_config_dword(pdev, pos + sizeof(cap),
  109. &hw->notify_off_multiplier);
  110. hw->notify_bar = cap.bar;
  111. hw->notify_base = get_cap_addr(hw, &cap);
  112. hw->notify_base_pa = pci_resource_start(pdev, cap.bar) +
  113. le32_to_cpu(cap.offset);
  114. IFCVF_DBG(pdev, "hw->notify_base = %p\n",
  115. hw->notify_base);
  116. break;
  117. case VIRTIO_PCI_CAP_ISR_CFG:
  118. hw->isr = get_cap_addr(hw, &cap);
  119. IFCVF_DBG(pdev, "hw->isr = %p\n", hw->isr);
  120. break;
  121. case VIRTIO_PCI_CAP_DEVICE_CFG:
  122. hw->dev_cfg = get_cap_addr(hw, &cap);
  123. hw->cap_dev_config_size = le32_to_cpu(cap.length);
  124. IFCVF_DBG(pdev, "hw->dev_cfg = %p\n", hw->dev_cfg);
  125. break;
  126. }
  127. next:
  128. pos = cap.cap_next;
  129. }
  130. if (hw->common_cfg == NULL || hw->notify_base == NULL ||
  131. hw->isr == NULL || hw->dev_cfg == NULL) {
  132. IFCVF_ERR(pdev, "Incomplete PCI capabilities\n");
  133. return -EIO;
  134. }
  135. hw->nr_vring = vp_ioread16(&hw->common_cfg->num_queues);
  136. hw->vring = kzalloc(sizeof(struct vring_info) * hw->nr_vring, GFP_KERNEL);
  137. if (!hw->vring)
  138. return -ENOMEM;
  139. for (i = 0; i < hw->nr_vring; i++) {
  140. vp_iowrite16(i, &hw->common_cfg->queue_select);
  141. notify_off = vp_ioread16(&hw->common_cfg->queue_notify_off);
  142. hw->vring[i].notify_addr = hw->notify_base +
  143. notify_off * hw->notify_off_multiplier;
  144. hw->vring[i].notify_pa = hw->notify_base_pa +
  145. notify_off * hw->notify_off_multiplier;
  146. hw->vring[i].irq = -EINVAL;
  147. }
  148. hw->lm_cfg = hw->base[IFCVF_LM_BAR];
  149. IFCVF_DBG(pdev,
  150. "PCI capability mapping: common cfg: %p, notify base: %p\n, isr cfg: %p, device cfg: %p, multiplier: %u\n",
  151. hw->common_cfg, hw->notify_base, hw->isr,
  152. hw->dev_cfg, hw->notify_off_multiplier);
  153. hw->vqs_reused_irq = -EINVAL;
  154. hw->config_irq = -EINVAL;
  155. return 0;
  156. }
  157. u8 ifcvf_get_status(struct ifcvf_hw *hw)
  158. {
  159. return vp_ioread8(&hw->common_cfg->device_status);
  160. }
  161. void ifcvf_set_status(struct ifcvf_hw *hw, u8 status)
  162. {
  163. vp_iowrite8(status, &hw->common_cfg->device_status);
  164. }
  165. void ifcvf_reset(struct ifcvf_hw *hw)
  166. {
  167. ifcvf_set_status(hw, 0);
  168. while (ifcvf_get_status(hw))
  169. msleep(1);
  170. }
  171. u64 ifcvf_get_hw_features(struct ifcvf_hw *hw)
  172. {
  173. struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
  174. u32 features_lo, features_hi;
  175. u64 features;
  176. vp_iowrite32(0, &cfg->device_feature_select);
  177. features_lo = vp_ioread32(&cfg->device_feature);
  178. vp_iowrite32(1, &cfg->device_feature_select);
  179. features_hi = vp_ioread32(&cfg->device_feature);
  180. features = ((u64)features_hi << 32) | features_lo;
  181. return features;
  182. }
  183. /* return provisioned vDPA dev features */
  184. u64 ifcvf_get_dev_features(struct ifcvf_hw *hw)
  185. {
  186. return hw->dev_features;
  187. }
  188. u64 ifcvf_get_driver_features(struct ifcvf_hw *hw)
  189. {
  190. struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
  191. u32 features_lo, features_hi;
  192. u64 features;
  193. vp_iowrite32(0, &cfg->device_feature_select);
  194. features_lo = vp_ioread32(&cfg->guest_feature);
  195. vp_iowrite32(1, &cfg->device_feature_select);
  196. features_hi = vp_ioread32(&cfg->guest_feature);
  197. features = ((u64)features_hi << 32) | features_lo;
  198. return features;
  199. }
  200. int ifcvf_verify_min_features(struct ifcvf_hw *hw, u64 features)
  201. {
  202. if (!(features & BIT_ULL(VIRTIO_F_ACCESS_PLATFORM)) && features) {
  203. IFCVF_ERR(hw->pdev, "VIRTIO_F_ACCESS_PLATFORM is not negotiated\n");
  204. return -EINVAL;
  205. }
  206. return 0;
  207. }
  208. u32 ifcvf_get_config_size(struct ifcvf_hw *hw)
  209. {
  210. u32 net_config_size = sizeof(struct virtio_net_config);
  211. u32 blk_config_size = sizeof(struct virtio_blk_config);
  212. u32 cap_size = hw->cap_dev_config_size;
  213. u32 config_size;
  214. /* If the onboard device config space size is greater than
  215. * the size of struct virtio_net/blk_config, only the spec
  216. * implementing contents size is returned, this is very
  217. * unlikely, defensive programming.
  218. */
  219. switch (hw->dev_type) {
  220. case VIRTIO_ID_NET:
  221. config_size = min(cap_size, net_config_size);
  222. break;
  223. case VIRTIO_ID_BLOCK:
  224. config_size = min(cap_size, blk_config_size);
  225. break;
  226. default:
  227. config_size = 0;
  228. IFCVF_ERR(hw->pdev, "VIRTIO ID %u not supported\n", hw->dev_type);
  229. }
  230. return config_size;
  231. }
  232. void ifcvf_read_dev_config(struct ifcvf_hw *hw, u64 offset,
  233. void *dst, int length)
  234. {
  235. u8 old_gen, new_gen, *p;
  236. int i;
  237. WARN_ON(offset + length > hw->config_size);
  238. do {
  239. old_gen = vp_ioread8(&hw->common_cfg->config_generation);
  240. p = dst;
  241. for (i = 0; i < length; i++)
  242. *p++ = vp_ioread8(hw->dev_cfg + offset + i);
  243. new_gen = vp_ioread8(&hw->common_cfg->config_generation);
  244. } while (old_gen != new_gen);
  245. }
  246. void ifcvf_write_dev_config(struct ifcvf_hw *hw, u64 offset,
  247. const void *src, int length)
  248. {
  249. const u8 *p;
  250. int i;
  251. p = src;
  252. WARN_ON(offset + length > hw->config_size);
  253. for (i = 0; i < length; i++)
  254. vp_iowrite8(*p++, hw->dev_cfg + offset + i);
  255. }
  256. void ifcvf_set_driver_features(struct ifcvf_hw *hw, u64 features)
  257. {
  258. struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
  259. vp_iowrite32(0, &cfg->guest_feature_select);
  260. vp_iowrite32((u32)features, &cfg->guest_feature);
  261. vp_iowrite32(1, &cfg->guest_feature_select);
  262. vp_iowrite32(features >> 32, &cfg->guest_feature);
  263. }
  264. u16 ifcvf_get_vq_state(struct ifcvf_hw *hw, u16 qid)
  265. {
  266. struct ifcvf_lm_cfg __iomem *lm_cfg = hw->lm_cfg;
  267. u16 last_avail_idx;
  268. last_avail_idx = vp_ioread16(&lm_cfg->vq_state_region + qid * 2);
  269. return last_avail_idx;
  270. }
  271. int ifcvf_set_vq_state(struct ifcvf_hw *hw, u16 qid, u16 num)
  272. {
  273. struct ifcvf_lm_cfg __iomem *lm_cfg = hw->lm_cfg;
  274. vp_iowrite16(num, &lm_cfg->vq_state_region + qid * 2);
  275. return 0;
  276. }
  277. void ifcvf_set_vq_num(struct ifcvf_hw *hw, u16 qid, u32 num)
  278. {
  279. struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
  280. vp_iowrite16(qid, &cfg->queue_select);
  281. vp_iowrite16(num, &cfg->queue_size);
  282. }
  283. int ifcvf_set_vq_address(struct ifcvf_hw *hw, u16 qid, u64 desc_area,
  284. u64 driver_area, u64 device_area)
  285. {
  286. struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
  287. vp_iowrite16(qid, &cfg->queue_select);
  288. vp_iowrite64_twopart(desc_area, &cfg->queue_desc_lo,
  289. &cfg->queue_desc_hi);
  290. vp_iowrite64_twopart(driver_area, &cfg->queue_avail_lo,
  291. &cfg->queue_avail_hi);
  292. vp_iowrite64_twopart(device_area, &cfg->queue_used_lo,
  293. &cfg->queue_used_hi);
  294. return 0;
  295. }
  296. bool ifcvf_get_vq_ready(struct ifcvf_hw *hw, u16 qid)
  297. {
  298. struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
  299. u16 queue_enable;
  300. vp_iowrite16(qid, &cfg->queue_select);
  301. queue_enable = vp_ioread16(&cfg->queue_enable);
  302. return (bool)queue_enable;
  303. }
  304. void ifcvf_set_vq_ready(struct ifcvf_hw *hw, u16 qid, bool ready)
  305. {
  306. struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
  307. vp_iowrite16(qid, &cfg->queue_select);
  308. vp_iowrite16(ready, &cfg->queue_enable);
  309. }
  310. static void ifcvf_reset_vring(struct ifcvf_hw *hw)
  311. {
  312. u16 qid;
  313. for (qid = 0; qid < hw->nr_vring; qid++) {
  314. hw->vring[qid].cb.callback = NULL;
  315. hw->vring[qid].cb.private = NULL;
  316. ifcvf_set_vq_vector(hw, qid, VIRTIO_MSI_NO_VECTOR);
  317. }
  318. }
  319. static void ifcvf_reset_config_handler(struct ifcvf_hw *hw)
  320. {
  321. hw->config_cb.callback = NULL;
  322. hw->config_cb.private = NULL;
  323. ifcvf_set_config_vector(hw, VIRTIO_MSI_NO_VECTOR);
  324. }
  325. static void ifcvf_synchronize_irq(struct ifcvf_hw *hw)
  326. {
  327. u32 nvectors = hw->num_msix_vectors;
  328. struct pci_dev *pdev = hw->pdev;
  329. int i, irq;
  330. for (i = 0; i < nvectors; i++) {
  331. irq = pci_irq_vector(pdev, i);
  332. if (irq >= 0)
  333. synchronize_irq(irq);
  334. }
  335. }
  336. void ifcvf_stop(struct ifcvf_hw *hw)
  337. {
  338. ifcvf_synchronize_irq(hw);
  339. ifcvf_reset_vring(hw);
  340. ifcvf_reset_config_handler(hw);
  341. }
  342. void ifcvf_notify_queue(struct ifcvf_hw *hw, u16 qid)
  343. {
  344. vp_iowrite16(qid, hw->vring[qid].notify_addr);
  345. }