mediatek.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 MediaTek Inc.
  4. *
  5. * Author:
  6. * Min Guo <min.guo@mediatek.com>
  7. * Yonglong Wu <yonglong.wu@mediatek.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/usb/role.h>
  16. #include <linux/usb/usb_phy_generic.h>
  17. #include "musb_core.h"
  18. #include "musb_dma.h"
  19. #define USB_L1INTS 0x00a0
  20. #define USB_L1INTM 0x00a4
  21. #define MTK_MUSB_TXFUNCADDR 0x0480
  22. /* MediaTek controller toggle enable and status reg */
  23. #define MUSB_RXTOG 0x80
  24. #define MUSB_RXTOGEN 0x82
  25. #define MUSB_TXTOG 0x84
  26. #define MUSB_TXTOGEN 0x86
  27. #define MTK_TOGGLE_EN GENMASK(15, 0)
  28. #define TX_INT_STATUS BIT(0)
  29. #define RX_INT_STATUS BIT(1)
  30. #define USBCOM_INT_STATUS BIT(2)
  31. #define DMA_INT_STATUS BIT(3)
  32. #define DMA_INTR_STATUS_MSK GENMASK(7, 0)
  33. #define DMA_INTR_UNMASK_SET_MSK GENMASK(31, 24)
  34. #define MTK_MUSB_CLKS_NUM 3
  35. struct mtk_glue {
  36. struct device *dev;
  37. struct musb *musb;
  38. struct platform_device *musb_pdev;
  39. struct platform_device *usb_phy;
  40. struct phy *phy;
  41. struct usb_phy *xceiv;
  42. enum phy_mode phy_mode;
  43. struct clk_bulk_data clks[MTK_MUSB_CLKS_NUM];
  44. enum usb_role role;
  45. struct usb_role_switch *role_sw;
  46. };
  47. static int mtk_musb_clks_get(struct mtk_glue *glue)
  48. {
  49. struct device *dev = glue->dev;
  50. glue->clks[0].id = "main";
  51. glue->clks[1].id = "mcu";
  52. glue->clks[2].id = "univpll";
  53. return devm_clk_bulk_get(dev, MTK_MUSB_CLKS_NUM, glue->clks);
  54. }
  55. static int mtk_otg_switch_set(struct mtk_glue *glue, enum usb_role role)
  56. {
  57. struct musb *musb = glue->musb;
  58. u8 devctl = readb(musb->mregs + MUSB_DEVCTL);
  59. enum usb_role new_role;
  60. if (role == glue->role)
  61. return 0;
  62. switch (role) {
  63. case USB_ROLE_HOST:
  64. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  65. glue->phy_mode = PHY_MODE_USB_HOST;
  66. new_role = USB_ROLE_HOST;
  67. if (glue->role == USB_ROLE_NONE)
  68. phy_power_on(glue->phy);
  69. devctl |= MUSB_DEVCTL_SESSION;
  70. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  71. MUSB_HST_MODE(musb);
  72. break;
  73. case USB_ROLE_DEVICE:
  74. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  75. glue->phy_mode = PHY_MODE_USB_DEVICE;
  76. new_role = USB_ROLE_DEVICE;
  77. devctl &= ~MUSB_DEVCTL_SESSION;
  78. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  79. if (glue->role == USB_ROLE_NONE)
  80. phy_power_on(glue->phy);
  81. MUSB_DEV_MODE(musb);
  82. break;
  83. case USB_ROLE_NONE:
  84. glue->phy_mode = PHY_MODE_USB_OTG;
  85. new_role = USB_ROLE_NONE;
  86. devctl &= ~MUSB_DEVCTL_SESSION;
  87. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  88. if (glue->role != USB_ROLE_NONE)
  89. phy_power_off(glue->phy);
  90. break;
  91. default:
  92. dev_err(glue->dev, "Invalid State\n");
  93. return -EINVAL;
  94. }
  95. glue->role = new_role;
  96. phy_set_mode(glue->phy, glue->phy_mode);
  97. return 0;
  98. }
  99. static int musb_usb_role_sx_set(struct usb_role_switch *sw, enum usb_role role)
  100. {
  101. return mtk_otg_switch_set(usb_role_switch_get_drvdata(sw), role);
  102. }
  103. static enum usb_role musb_usb_role_sx_get(struct usb_role_switch *sw)
  104. {
  105. struct mtk_glue *glue = usb_role_switch_get_drvdata(sw);
  106. return glue->role;
  107. }
  108. static int mtk_otg_switch_init(struct mtk_glue *glue)
  109. {
  110. struct usb_role_switch_desc role_sx_desc = { 0 };
  111. role_sx_desc.set = musb_usb_role_sx_set;
  112. role_sx_desc.get = musb_usb_role_sx_get;
  113. role_sx_desc.allow_userspace_control = true;
  114. role_sx_desc.fwnode = dev_fwnode(glue->dev);
  115. role_sx_desc.driver_data = glue;
  116. glue->role_sw = usb_role_switch_register(glue->dev, &role_sx_desc);
  117. return PTR_ERR_OR_ZERO(glue->role_sw);
  118. }
  119. static void mtk_otg_switch_exit(struct mtk_glue *glue)
  120. {
  121. return usb_role_switch_unregister(glue->role_sw);
  122. }
  123. static irqreturn_t generic_interrupt(int irq, void *__hci)
  124. {
  125. unsigned long flags;
  126. irqreturn_t retval = IRQ_NONE;
  127. struct musb *musb = __hci;
  128. spin_lock_irqsave(&musb->lock, flags);
  129. musb->int_usb = musb_clearb(musb->mregs, MUSB_INTRUSB);
  130. musb->int_rx = musb_clearw(musb->mregs, MUSB_INTRRX);
  131. musb->int_tx = musb_clearw(musb->mregs, MUSB_INTRTX);
  132. if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
  133. /* ep0 FADDR must be 0 when (re)entering peripheral mode */
  134. musb_ep_select(musb->mregs, 0);
  135. musb_writeb(musb->mregs, MUSB_FADDR, 0);
  136. }
  137. if (musb->int_usb || musb->int_tx || musb->int_rx)
  138. retval = musb_interrupt(musb);
  139. spin_unlock_irqrestore(&musb->lock, flags);
  140. return retval;
  141. }
  142. static irqreturn_t mtk_musb_interrupt(int irq, void *dev_id)
  143. {
  144. irqreturn_t retval = IRQ_NONE;
  145. struct musb *musb = (struct musb *)dev_id;
  146. u32 l1_ints;
  147. l1_ints = musb_readl(musb->mregs, USB_L1INTS) &
  148. musb_readl(musb->mregs, USB_L1INTM);
  149. if (l1_ints & (TX_INT_STATUS | RX_INT_STATUS | USBCOM_INT_STATUS))
  150. retval = generic_interrupt(irq, musb);
  151. #if defined(CONFIG_USB_INVENTRA_DMA)
  152. if (l1_ints & DMA_INT_STATUS)
  153. retval = dma_controller_irq(irq, musb->dma_controller);
  154. #endif
  155. return retval;
  156. }
  157. static u32 mtk_musb_busctl_offset(u8 epnum, u16 offset)
  158. {
  159. return MTK_MUSB_TXFUNCADDR + offset + 8 * epnum;
  160. }
  161. static u8 mtk_musb_clearb(void __iomem *addr, unsigned int offset)
  162. {
  163. u8 data;
  164. /* W1C */
  165. data = musb_readb(addr, offset);
  166. musb_writeb(addr, offset, data);
  167. return data;
  168. }
  169. static u16 mtk_musb_clearw(void __iomem *addr, unsigned int offset)
  170. {
  171. u16 data;
  172. /* W1C */
  173. data = musb_readw(addr, offset);
  174. musb_writew(addr, offset, data);
  175. return data;
  176. }
  177. static int mtk_musb_set_mode(struct musb *musb, u8 mode)
  178. {
  179. struct device *dev = musb->controller;
  180. struct mtk_glue *glue = dev_get_drvdata(dev->parent);
  181. enum phy_mode new_mode;
  182. enum usb_role new_role;
  183. switch (mode) {
  184. case MUSB_HOST:
  185. new_mode = PHY_MODE_USB_HOST;
  186. new_role = USB_ROLE_HOST;
  187. break;
  188. case MUSB_PERIPHERAL:
  189. new_mode = PHY_MODE_USB_DEVICE;
  190. new_role = USB_ROLE_DEVICE;
  191. break;
  192. case MUSB_OTG:
  193. new_mode = PHY_MODE_USB_OTG;
  194. new_role = USB_ROLE_NONE;
  195. break;
  196. default:
  197. dev_err(glue->dev, "Invalid mode request\n");
  198. return -EINVAL;
  199. }
  200. if (glue->phy_mode == new_mode)
  201. return 0;
  202. if (musb->port_mode != MUSB_OTG) {
  203. dev_err(glue->dev, "Does not support changing modes\n");
  204. return -EINVAL;
  205. }
  206. mtk_otg_switch_set(glue, new_role);
  207. return 0;
  208. }
  209. static int mtk_musb_init(struct musb *musb)
  210. {
  211. struct device *dev = musb->controller;
  212. struct mtk_glue *glue = dev_get_drvdata(dev->parent);
  213. int ret;
  214. glue->musb = musb;
  215. musb->phy = glue->phy;
  216. musb->xceiv = glue->xceiv;
  217. musb->is_host = false;
  218. musb->isr = mtk_musb_interrupt;
  219. /* Set TX/RX toggle enable */
  220. musb_writew(musb->mregs, MUSB_TXTOGEN, MTK_TOGGLE_EN);
  221. musb_writew(musb->mregs, MUSB_RXTOGEN, MTK_TOGGLE_EN);
  222. if (musb->port_mode == MUSB_OTG) {
  223. ret = mtk_otg_switch_init(glue);
  224. if (ret)
  225. return ret;
  226. }
  227. ret = phy_init(glue->phy);
  228. if (ret)
  229. goto err_phy_init;
  230. ret = phy_power_on(glue->phy);
  231. if (ret)
  232. goto err_phy_power_on;
  233. phy_set_mode(glue->phy, glue->phy_mode);
  234. #if defined(CONFIG_USB_INVENTRA_DMA)
  235. musb_writel(musb->mregs, MUSB_HSDMA_INTR,
  236. DMA_INTR_STATUS_MSK | DMA_INTR_UNMASK_SET_MSK);
  237. #endif
  238. musb_writel(musb->mregs, USB_L1INTM, TX_INT_STATUS | RX_INT_STATUS |
  239. USBCOM_INT_STATUS | DMA_INT_STATUS);
  240. return 0;
  241. err_phy_power_on:
  242. phy_exit(glue->phy);
  243. err_phy_init:
  244. if (musb->port_mode == MUSB_OTG)
  245. mtk_otg_switch_exit(glue);
  246. return ret;
  247. }
  248. static u16 mtk_musb_get_toggle(struct musb_qh *qh, int is_out)
  249. {
  250. struct musb *musb = qh->hw_ep->musb;
  251. u8 epnum = qh->hw_ep->epnum;
  252. u16 toggle;
  253. toggle = musb_readw(musb->mregs, is_out ? MUSB_TXTOG : MUSB_RXTOG);
  254. return toggle & (1 << epnum);
  255. }
  256. static u16 mtk_musb_set_toggle(struct musb_qh *qh, int is_out, struct urb *urb)
  257. {
  258. struct musb *musb = qh->hw_ep->musb;
  259. u8 epnum = qh->hw_ep->epnum;
  260. u16 value, toggle;
  261. toggle = usb_gettoggle(urb->dev, qh->epnum, is_out);
  262. if (is_out) {
  263. value = musb_readw(musb->mregs, MUSB_TXTOG);
  264. value |= toggle << epnum;
  265. musb_writew(musb->mregs, MUSB_TXTOG, value);
  266. } else {
  267. value = musb_readw(musb->mregs, MUSB_RXTOG);
  268. value |= toggle << epnum;
  269. musb_writew(musb->mregs, MUSB_RXTOG, value);
  270. }
  271. return 0;
  272. }
  273. static int mtk_musb_exit(struct musb *musb)
  274. {
  275. struct device *dev = musb->controller;
  276. struct mtk_glue *glue = dev_get_drvdata(dev->parent);
  277. mtk_otg_switch_exit(glue);
  278. phy_power_off(glue->phy);
  279. phy_exit(glue->phy);
  280. clk_bulk_disable_unprepare(MTK_MUSB_CLKS_NUM, glue->clks);
  281. pm_runtime_put_sync(dev);
  282. pm_runtime_disable(dev);
  283. return 0;
  284. }
  285. static const struct musb_platform_ops mtk_musb_ops = {
  286. .quirks = MUSB_DMA_INVENTRA,
  287. .init = mtk_musb_init,
  288. .get_toggle = mtk_musb_get_toggle,
  289. .set_toggle = mtk_musb_set_toggle,
  290. .exit = mtk_musb_exit,
  291. #ifdef CONFIG_USB_INVENTRA_DMA
  292. .dma_init = musbhs_dma_controller_create_noirq,
  293. .dma_exit = musbhs_dma_controller_destroy,
  294. #endif
  295. .clearb = mtk_musb_clearb,
  296. .clearw = mtk_musb_clearw,
  297. .busctl_offset = mtk_musb_busctl_offset,
  298. .set_mode = mtk_musb_set_mode,
  299. };
  300. #define MTK_MUSB_MAX_EP_NUM 8
  301. #define MTK_MUSB_RAM_BITS 11
  302. static const struct musb_fifo_cfg mtk_musb_mode_cfg[] = {
  303. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  304. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  305. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  306. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  307. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  308. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  309. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
  310. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
  311. { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
  312. { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
  313. { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 1024, },
  314. { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 1024, },
  315. { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
  316. { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 64, },
  317. };
  318. static const struct musb_hdrc_config mtk_musb_hdrc_config = {
  319. .fifo_cfg = mtk_musb_mode_cfg,
  320. .fifo_cfg_size = ARRAY_SIZE(mtk_musb_mode_cfg),
  321. .multipoint = true,
  322. .dyn_fifo = true,
  323. .num_eps = MTK_MUSB_MAX_EP_NUM,
  324. .ram_bits = MTK_MUSB_RAM_BITS,
  325. };
  326. static const struct platform_device_info mtk_dev_info = {
  327. .name = "musb-hdrc",
  328. .id = PLATFORM_DEVID_AUTO,
  329. .dma_mask = DMA_BIT_MASK(32),
  330. };
  331. static int mtk_musb_probe(struct platform_device *pdev)
  332. {
  333. struct musb_hdrc_platform_data *pdata;
  334. struct mtk_glue *glue;
  335. struct platform_device_info pinfo;
  336. struct device *dev = &pdev->dev;
  337. struct device_node *np = dev->of_node;
  338. int ret;
  339. glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
  340. if (!glue)
  341. return -ENOMEM;
  342. glue->dev = dev;
  343. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  344. if (!pdata)
  345. return -ENOMEM;
  346. ret = of_platform_populate(np, NULL, NULL, dev);
  347. if (ret)
  348. return dev_err_probe(dev, ret,
  349. "failed to create child devices at %p\n", np);
  350. ret = mtk_musb_clks_get(glue);
  351. if (ret)
  352. return ret;
  353. pdata->config = &mtk_musb_hdrc_config;
  354. pdata->platform_ops = &mtk_musb_ops;
  355. pdata->mode = usb_get_dr_mode(dev);
  356. if (IS_ENABLED(CONFIG_USB_MUSB_HOST))
  357. pdata->mode = USB_DR_MODE_HOST;
  358. else if (IS_ENABLED(CONFIG_USB_MUSB_GADGET))
  359. pdata->mode = USB_DR_MODE_PERIPHERAL;
  360. switch (pdata->mode) {
  361. case USB_DR_MODE_HOST:
  362. glue->phy_mode = PHY_MODE_USB_HOST;
  363. glue->role = USB_ROLE_HOST;
  364. break;
  365. case USB_DR_MODE_PERIPHERAL:
  366. glue->phy_mode = PHY_MODE_USB_DEVICE;
  367. glue->role = USB_ROLE_DEVICE;
  368. break;
  369. case USB_DR_MODE_OTG:
  370. glue->phy_mode = PHY_MODE_USB_OTG;
  371. glue->role = USB_ROLE_NONE;
  372. break;
  373. default:
  374. return dev_err_probe(&pdev->dev, -EINVAL,
  375. "Error 'dr_mode' property\n");
  376. }
  377. glue->phy = devm_of_phy_get_by_index(dev, np, 0);
  378. if (IS_ERR(glue->phy))
  379. return dev_err_probe(dev, PTR_ERR(glue->phy),
  380. "fail to getting phy\n");
  381. glue->usb_phy = usb_phy_generic_register();
  382. if (IS_ERR(glue->usb_phy))
  383. return dev_err_probe(dev, PTR_ERR(glue->usb_phy),
  384. "fail to registering usb-phy\n");
  385. glue->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
  386. if (IS_ERR(glue->xceiv)) {
  387. ret = PTR_ERR(glue->xceiv);
  388. dev_err(dev, "fail to getting usb-phy %d\n", ret);
  389. goto err_unregister_usb_phy;
  390. }
  391. platform_set_drvdata(pdev, glue);
  392. pm_runtime_enable(dev);
  393. pm_runtime_get_sync(dev);
  394. ret = clk_bulk_prepare_enable(MTK_MUSB_CLKS_NUM, glue->clks);
  395. if (ret)
  396. goto err_enable_clk;
  397. pinfo = mtk_dev_info;
  398. pinfo.parent = dev;
  399. pinfo.res = pdev->resource;
  400. pinfo.num_res = pdev->num_resources;
  401. pinfo.data = pdata;
  402. pinfo.size_data = sizeof(*pdata);
  403. pinfo.fwnode = of_fwnode_handle(np);
  404. pinfo.of_node_reused = true;
  405. glue->musb_pdev = platform_device_register_full(&pinfo);
  406. if (IS_ERR(glue->musb_pdev)) {
  407. ret = PTR_ERR(glue->musb_pdev);
  408. dev_err(dev, "failed to register musb device: %d\n", ret);
  409. goto err_device_register;
  410. }
  411. return 0;
  412. err_device_register:
  413. clk_bulk_disable_unprepare(MTK_MUSB_CLKS_NUM, glue->clks);
  414. err_enable_clk:
  415. pm_runtime_put_sync(dev);
  416. pm_runtime_disable(dev);
  417. err_unregister_usb_phy:
  418. usb_phy_generic_unregister(glue->usb_phy);
  419. return ret;
  420. }
  421. static void mtk_musb_remove(struct platform_device *pdev)
  422. {
  423. struct mtk_glue *glue = platform_get_drvdata(pdev);
  424. struct platform_device *usb_phy = glue->usb_phy;
  425. platform_device_unregister(glue->musb_pdev);
  426. usb_phy_generic_unregister(usb_phy);
  427. }
  428. #ifdef CONFIG_OF
  429. static const struct of_device_id mtk_musb_match[] = {
  430. {.compatible = "mediatek,mtk-musb",},
  431. {},
  432. };
  433. MODULE_DEVICE_TABLE(of, mtk_musb_match);
  434. #endif
  435. static struct platform_driver mtk_musb_driver = {
  436. .probe = mtk_musb_probe,
  437. .remove = mtk_musb_remove,
  438. .driver = {
  439. .name = "musb-mtk",
  440. .of_match_table = of_match_ptr(mtk_musb_match),
  441. },
  442. };
  443. module_platform_driver(mtk_musb_driver);
  444. MODULE_DESCRIPTION("MediaTek MUSB Glue Layer");
  445. MODULE_AUTHOR("Min Guo <min.guo@mediatek.com>");
  446. MODULE_LICENSE("GPL v2");