8250_rt288x.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * RT288x/Au1xxx driver
  4. */
  5. #include <linux/module.h>
  6. #include <linux/io.h>
  7. #include <linux/init.h>
  8. #include <linux/console.h>
  9. #include <linux/serial.h>
  10. #include <linux/serial_8250.h>
  11. #include "8250.h"
  12. #define RT288X_DL 0x28
  13. /* Au1x00/RT288x UART hardware has a weird register layout */
  14. static const u8 au_io_in_map[7] = {
  15. [UART_RX] = 0,
  16. [UART_IER] = 2,
  17. [UART_IIR] = 3,
  18. [UART_LCR] = 5,
  19. [UART_MCR] = 6,
  20. [UART_LSR] = 7,
  21. [UART_MSR] = 8,
  22. };
  23. static const u8 au_io_out_map[5] = {
  24. [UART_TX] = 1,
  25. [UART_IER] = 2,
  26. [UART_FCR] = 4,
  27. [UART_LCR] = 5,
  28. [UART_MCR] = 6,
  29. };
  30. static u32 au_serial_in(struct uart_port *p, unsigned int offset)
  31. {
  32. if (offset >= ARRAY_SIZE(au_io_in_map))
  33. return UINT_MAX;
  34. offset = au_io_in_map[offset];
  35. return __raw_readl(p->membase + (offset << p->regshift));
  36. }
  37. static void au_serial_out(struct uart_port *p, unsigned int offset, u32 value)
  38. {
  39. if (offset >= ARRAY_SIZE(au_io_out_map))
  40. return;
  41. offset = au_io_out_map[offset];
  42. __raw_writel(value, p->membase + (offset << p->regshift));
  43. }
  44. /* Au1x00 haven't got a standard divisor latch */
  45. static u32 au_serial_dl_read(struct uart_8250_port *up)
  46. {
  47. return __raw_readl(up->port.membase + RT288X_DL);
  48. }
  49. static void au_serial_dl_write(struct uart_8250_port *up, u32 value)
  50. {
  51. __raw_writel(value, up->port.membase + RT288X_DL);
  52. }
  53. int au_platform_setup(struct plat_serial8250_port *p)
  54. {
  55. p->iotype = UPIO_AU;
  56. p->serial_in = au_serial_in;
  57. p->serial_out = au_serial_out;
  58. p->dl_read = au_serial_dl_read;
  59. p->dl_write = au_serial_dl_write;
  60. p->mapsize = 0x1000;
  61. p->bugs |= UART_BUG_NOMSR;
  62. return 0;
  63. }
  64. EXPORT_SYMBOL_GPL(au_platform_setup);
  65. int rt288x_setup(struct uart_port *p)
  66. {
  67. struct uart_8250_port *up = up_to_u8250p(p);
  68. p->iotype = UPIO_AU;
  69. p->serial_in = au_serial_in;
  70. p->serial_out = au_serial_out;
  71. up->dl_read = au_serial_dl_read;
  72. up->dl_write = au_serial_dl_write;
  73. p->mapsize = 0x100;
  74. up->bugs |= UART_BUG_NOMSR;
  75. return 0;
  76. }
  77. EXPORT_SYMBOL_GPL(rt288x_setup);
  78. #ifdef CONFIG_SERIAL_8250_CONSOLE
  79. static void au_putc(struct uart_port *port, unsigned char c)
  80. {
  81. unsigned int status;
  82. au_serial_out(port, UART_TX, c);
  83. for (;;) {
  84. status = au_serial_in(port, UART_LSR);
  85. if (uart_lsr_tx_empty(status))
  86. break;
  87. cpu_relax();
  88. }
  89. }
  90. static void au_early_serial8250_write(struct console *console,
  91. const char *s, unsigned int count)
  92. {
  93. struct earlycon_device *device = console->data;
  94. struct uart_port *port = &device->port;
  95. uart_console_write(port, s, count, au_putc);
  96. }
  97. static int __init early_au_setup(struct earlycon_device *dev, const char *opt)
  98. {
  99. rt288x_setup(&dev->port);
  100. dev->con->write = au_early_serial8250_write;
  101. return 0;
  102. }
  103. OF_EARLYCON_DECLARE(palmchip, "ralink,rt2880-uart", early_au_setup);
  104. #endif
  105. MODULE_DESCRIPTION("RT288x/Au1xxx UART driver");
  106. MODULE_LICENSE("GPL");