8250_ni.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NI 16550 UART Driver
  4. *
  5. * The National Instruments (NI) 16550 is a UART that is compatible with the
  6. * TL16C550C and OX16C950B register interfaces, but has additional functions
  7. * for RS-485 transceiver control. This driver implements support for the
  8. * additional functionality on top of the standard serial8250 core.
  9. *
  10. * Copyright 2012-2023 National Instruments Corporation
  11. */
  12. #include <linux/bitfield.h>
  13. #include <linux/bits.h>
  14. #include <linux/clk.h>
  15. #include <linux/device.h>
  16. #include <linux/io.h>
  17. #include <linux/init.h>
  18. #include <linux/mod_devicetable.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/property.h>
  22. #include <linux/serial_core.h>
  23. #include <linux/types.h>
  24. #include "8250.h"
  25. /* Extra bits in UART_ACR */
  26. #define NI16550_ACR_AUTO_DTR_EN BIT(4)
  27. /* TFS - TX FIFO Size */
  28. #define NI16550_TFS_OFFSET 0x0C
  29. /* RFS - RX FIFO Size */
  30. #define NI16550_RFS_OFFSET 0x0D
  31. /* PMR - Port Mode Register */
  32. #define NI16550_PMR_OFFSET 0x0E
  33. /* PMR[1:0] - Port Capabilities */
  34. #define NI16550_PMR_CAP_MASK GENMASK(1, 0)
  35. #define NI16550_PMR_NOT_IMPL FIELD_PREP(NI16550_PMR_CAP_MASK, 0) /* not implemented */
  36. #define NI16550_PMR_CAP_RS232 FIELD_PREP(NI16550_PMR_CAP_MASK, 1) /* RS-232 capable */
  37. #define NI16550_PMR_CAP_RS485 FIELD_PREP(NI16550_PMR_CAP_MASK, 2) /* RS-485 capable */
  38. #define NI16550_PMR_CAP_DUAL FIELD_PREP(NI16550_PMR_CAP_MASK, 3) /* dual-port */
  39. /* PMR[4] - Interface Mode */
  40. #define NI16550_PMR_MODE_MASK GENMASK(4, 4)
  41. #define NI16550_PMR_MODE_RS232 FIELD_PREP(NI16550_PMR_MODE_MASK, 0) /* currently 232 */
  42. #define NI16550_PMR_MODE_RS485 FIELD_PREP(NI16550_PMR_MODE_MASK, 1) /* currently 485 */
  43. /* PCR - Port Control Register */
  44. /*
  45. * Wire Mode | Tx enabled? | Rx enabled?
  46. * ---------------|----------------------|--------------------------
  47. * PCR_RS422 | Always | Always
  48. * PCR_ECHO_RS485 | When DTR asserted | Always
  49. * PCR_DTR_RS485 | When DTR asserted | Disabled when TX enabled
  50. * PCR_AUTO_RS485 | When data in TX FIFO | Disabled when TX enabled
  51. */
  52. #define NI16550_PCR_OFFSET 0x0F
  53. #define NI16550_PCR_WIRE_MODE_MASK GENMASK(1, 0)
  54. #define NI16550_PCR_RS422 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 0)
  55. #define NI16550_PCR_ECHO_RS485 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 1)
  56. #define NI16550_PCR_DTR_RS485 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 2)
  57. #define NI16550_PCR_AUTO_RS485 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 3)
  58. #define NI16550_PCR_TXVR_ENABLE_BIT BIT(3)
  59. #define NI16550_PCR_RS485_TERMINATION_BIT BIT(6)
  60. /* flags for ni16550_device_info */
  61. #define NI_HAS_PMR BIT(0)
  62. struct ni16550_device_info {
  63. u32 uartclk;
  64. u8 prescaler;
  65. u8 flags;
  66. };
  67. struct ni16550_data {
  68. int line;
  69. struct clk *clk;
  70. };
  71. static int ni16550_enable_transceivers(struct uart_port *port)
  72. {
  73. u8 pcr;
  74. pcr = port->serial_in(port, NI16550_PCR_OFFSET);
  75. pcr |= NI16550_PCR_TXVR_ENABLE_BIT;
  76. dev_dbg(port->dev, "enable transceivers: write pcr: 0x%02x\n", pcr);
  77. port->serial_out(port, NI16550_PCR_OFFSET, pcr);
  78. return 0;
  79. }
  80. static int ni16550_disable_transceivers(struct uart_port *port)
  81. {
  82. u8 pcr;
  83. pcr = serial_port_in(port, NI16550_PCR_OFFSET);
  84. pcr &= ~NI16550_PCR_TXVR_ENABLE_BIT;
  85. dev_dbg(port->dev, "disable transceivers: write pcr: 0x%02x\n", pcr);
  86. serial_port_out(port, NI16550_PCR_OFFSET, pcr);
  87. return 0;
  88. }
  89. static int ni16550_rs485_config(struct uart_port *port,
  90. struct ktermios *termios,
  91. struct serial_rs485 *rs485)
  92. {
  93. struct uart_8250_port *up = container_of(port, struct uart_8250_port, port);
  94. u8 pcr;
  95. pcr = serial_port_in(port, NI16550_PCR_OFFSET);
  96. pcr &= ~NI16550_PCR_WIRE_MODE_MASK;
  97. if ((rs485->flags & SER_RS485_MODE_RS422) ||
  98. !(rs485->flags & SER_RS485_ENABLED)) {
  99. /* RS-422 */
  100. pcr |= NI16550_PCR_RS422;
  101. up->acr &= ~NI16550_ACR_AUTO_DTR_EN;
  102. } else {
  103. /* RS-485 2-wire Auto */
  104. pcr |= NI16550_PCR_AUTO_RS485;
  105. up->acr |= NI16550_ACR_AUTO_DTR_EN;
  106. }
  107. dev_dbg(port->dev, "config rs485: write pcr: 0x%02x, acr: %02x\n", pcr, up->acr);
  108. serial_port_out(port, NI16550_PCR_OFFSET, pcr);
  109. serial_icr_write(up, UART_ACR, up->acr);
  110. return 0;
  111. }
  112. static bool is_pmr_rs232_mode(struct uart_8250_port *up)
  113. {
  114. u8 pmr = serial_in(up, NI16550_PMR_OFFSET);
  115. u8 pmr_mode = pmr & NI16550_PMR_MODE_MASK;
  116. u8 pmr_cap = pmr & NI16550_PMR_CAP_MASK;
  117. /*
  118. * If the PMR is not implemented, then by default NI UARTs are
  119. * connected to RS-485 transceivers
  120. */
  121. if (pmr_cap == NI16550_PMR_NOT_IMPL)
  122. return false;
  123. if (pmr_cap == NI16550_PMR_CAP_DUAL)
  124. /*
  125. * If the port is dual-mode capable, then read the mode bit
  126. * to know the current mode
  127. */
  128. return pmr_mode == NI16550_PMR_MODE_RS232;
  129. /*
  130. * If it is not dual-mode capable, then decide based on the
  131. * capability
  132. */
  133. return pmr_cap == NI16550_PMR_CAP_RS232;
  134. }
  135. static void ni16550_config_prescaler(struct uart_8250_port *up,
  136. u8 prescaler)
  137. {
  138. /*
  139. * Page in the Enhanced Mode Registers
  140. * Sets EFR[4] for Enhanced Mode.
  141. */
  142. u8 lcr_value;
  143. u8 efr_value;
  144. lcr_value = serial_in(up, UART_LCR);
  145. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  146. efr_value = serial_in(up, UART_EFR);
  147. efr_value |= UART_EFR_ECB;
  148. serial_out(up, UART_EFR, efr_value);
  149. /* Page out the Enhanced Mode Registers */
  150. serial_out(up, UART_LCR, lcr_value);
  151. /* Set prescaler to CPR register. */
  152. serial_out(up, UART_SCR, UART_CPR);
  153. serial_out(up, UART_ICR, prescaler);
  154. }
  155. static const struct serial_rs485 ni16550_rs485_supported = {
  156. .flags = SER_RS485_ENABLED | SER_RS485_MODE_RS422 | SER_RS485_RTS_ON_SEND |
  157. SER_RS485_RTS_AFTER_SEND,
  158. /*
  159. * delay_rts_* and RX_DURING_TX are not supported.
  160. *
  161. * RTS_{ON,AFTER}_SEND are supported, but ignored; the transceiver
  162. * is connected in only one way and we don't need userspace to tell
  163. * us, but want to retain compatibility with applications that do.
  164. */
  165. };
  166. static void ni16550_rs485_setup(struct uart_port *port)
  167. {
  168. port->rs485_config = ni16550_rs485_config;
  169. port->rs485_supported = ni16550_rs485_supported;
  170. /*
  171. * The hardware comes up by default in 2-wire auto mode and we
  172. * set the flags to represent that
  173. */
  174. port->rs485.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
  175. }
  176. static int ni16550_port_startup(struct uart_port *port)
  177. {
  178. int ret;
  179. ret = serial8250_do_startup(port);
  180. if (ret)
  181. return ret;
  182. return ni16550_enable_transceivers(port);
  183. }
  184. static void ni16550_port_shutdown(struct uart_port *port)
  185. {
  186. ni16550_disable_transceivers(port);
  187. serial8250_do_shutdown(port);
  188. }
  189. static int ni16550_get_regs(struct platform_device *pdev,
  190. struct uart_port *port)
  191. {
  192. struct resource *regs;
  193. regs = platform_get_mem_or_io(pdev, 0);
  194. if (!regs)
  195. return dev_err_probe(&pdev->dev, -EINVAL, "no registers defined\n");
  196. switch (resource_type(regs)) {
  197. case IORESOURCE_IO:
  198. port->iotype = UPIO_PORT;
  199. port->iobase = regs->start;
  200. return 0;
  201. case IORESOURCE_MEM:
  202. port->iotype = UPIO_MEM;
  203. port->mapbase = regs->start;
  204. port->mapsize = resource_size(regs);
  205. port->flags |= UPF_IOREMAP;
  206. return 0;
  207. default:
  208. return -EINVAL;
  209. }
  210. }
  211. /*
  212. * Very old implementations don't have the TFS or RFS registers
  213. * defined, so we may read all-0s or all-1s. For such devices,
  214. * assume a FIFO size of 128.
  215. */
  216. static u8 ni16550_read_fifo_size(struct uart_8250_port *uart, int reg)
  217. {
  218. u8 value = serial_in(uart, reg);
  219. if (value == 0x00 || value == 0xFF)
  220. return 128;
  221. return value;
  222. }
  223. static void ni16550_set_mctrl(struct uart_port *port, unsigned int mctrl)
  224. {
  225. struct uart_8250_port *up = up_to_u8250p(port);
  226. up->mcr |= UART_MCR_CLKSEL;
  227. serial8250_do_set_mctrl(port, mctrl);
  228. }
  229. static int ni16550_probe(struct platform_device *pdev)
  230. {
  231. struct uart_8250_port *uart __free(kfree) = NULL;
  232. const struct ni16550_device_info *info;
  233. struct device *dev = &pdev->dev;
  234. unsigned int txfifosz, rxfifosz;
  235. struct ni16550_data *data;
  236. unsigned int prescaler;
  237. const char *portmode;
  238. bool rs232_property;
  239. int ret;
  240. uart = kzalloc_obj(*uart);
  241. if (!uart)
  242. return -ENOMEM;
  243. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  244. if (!data)
  245. return -ENOMEM;
  246. spin_lock_init(&uart->port.lock);
  247. ret = ni16550_get_regs(pdev, &uart->port);
  248. if (ret < 0)
  249. return ret;
  250. /* early setup so that serial_in()/serial_out() work */
  251. serial8250_set_defaults(uart);
  252. info = device_get_match_data(dev);
  253. uart->port.dev = dev;
  254. uart->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_FIXED_TYPE;
  255. uart->port.startup = ni16550_port_startup;
  256. uart->port.shutdown = ni16550_port_shutdown;
  257. /*
  258. * Hardware instantiation of FIFO sizes are held in registers.
  259. */
  260. txfifosz = ni16550_read_fifo_size(uart, NI16550_TFS_OFFSET);
  261. rxfifosz = ni16550_read_fifo_size(uart, NI16550_RFS_OFFSET);
  262. dev_dbg(dev, "NI 16550 has TX FIFO size %u, RX FIFO size %u\n",
  263. txfifosz, rxfifosz);
  264. uart->port.type = PORT_16550A;
  265. uart->port.fifosize = txfifosz;
  266. uart->tx_loadsz = txfifosz;
  267. uart->fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
  268. uart->capabilities = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR;
  269. /*
  270. * Declaration of the base clock frequency can come from one of:
  271. * - static declaration in this driver (for older ACPI IDs)
  272. * - a "clock-frequency" ACPI
  273. */
  274. uart->port.uartclk = info->uartclk;
  275. ret = uart_read_port_properties(&uart->port);
  276. if (ret)
  277. return ret;
  278. if (!uart->port.uartclk) {
  279. data->clk = devm_clk_get_enabled(dev, NULL);
  280. if (!IS_ERR(data->clk))
  281. uart->port.uartclk = clk_get_rate(data->clk);
  282. }
  283. if (!uart->port.uartclk)
  284. return dev_err_probe(dev, -ENODEV, "unable to determine clock frequency!\n");
  285. prescaler = info->prescaler;
  286. device_property_read_u32(dev, "clock-prescaler", &prescaler);
  287. if (prescaler) {
  288. uart->port.set_mctrl = ni16550_set_mctrl;
  289. ni16550_config_prescaler(uart, (u8)prescaler);
  290. }
  291. /*
  292. * The determination of whether or not this is an RS-485 or RS-232 port
  293. * can come from the PMR (if present), otherwise we're solely an RS-485
  294. * port.
  295. *
  296. * This is a device-specific property, and there are old devices in the
  297. * field using "transceiver" as an ACPI property, so we have to check
  298. * for that as well.
  299. */
  300. if (!device_property_read_string(dev, "transceiver", &portmode)) {
  301. rs232_property = strncmp(portmode, "RS-232", 6) == 0;
  302. dev_dbg(dev, "port is in %s mode (via device property)\n",
  303. rs232_property ? "RS-232" : "RS-485");
  304. } else if (info->flags & NI_HAS_PMR) {
  305. rs232_property = is_pmr_rs232_mode(uart);
  306. dev_dbg(dev, "port is in %s mode (via PMR)\n",
  307. rs232_property ? "RS-232" : "RS-485");
  308. } else {
  309. rs232_property = 0;
  310. dev_dbg(dev, "port is fixed as RS-485\n");
  311. }
  312. if (!rs232_property) {
  313. /*
  314. * Neither the 'transceiver' property nor the PMR indicate
  315. * that this is an RS-232 port, so it must be an RS-485 one.
  316. */
  317. ni16550_rs485_setup(&uart->port);
  318. }
  319. ret = serial8250_register_8250_port(uart);
  320. if (ret < 0)
  321. return ret;
  322. data->line = ret;
  323. platform_set_drvdata(pdev, data);
  324. return 0;
  325. }
  326. static void ni16550_remove(struct platform_device *pdev)
  327. {
  328. struct ni16550_data *data = platform_get_drvdata(pdev);
  329. serial8250_unregister_port(data->line);
  330. }
  331. /* NI 16550 RS-485 Interface */
  332. static const struct ni16550_device_info nic7750 = {
  333. .uartclk = 33333333,
  334. };
  335. /* NI CVS-145x RS-485 Interface */
  336. static const struct ni16550_device_info nic7772 = {
  337. .uartclk = 1843200,
  338. .flags = NI_HAS_PMR,
  339. };
  340. /* NI cRIO-904x RS-485 Interface */
  341. static const struct ni16550_device_info nic792b = {
  342. /* Sets UART clock rate to 22.222 MHz with 1.125 prescale */
  343. .uartclk = 22222222,
  344. .prescaler = 0x09,
  345. };
  346. /* NI sbRIO 96x8 RS-232/485 Interfaces */
  347. static const struct ni16550_device_info nic7a69 = {
  348. /* Set UART clock rate to 29.629 MHz with 1.125 prescale */
  349. .uartclk = 29629629,
  350. .prescaler = 0x09,
  351. };
  352. static const struct acpi_device_id ni16550_acpi_match[] = {
  353. { "NIC7750", (kernel_ulong_t)&nic7750 },
  354. { "NIC7772", (kernel_ulong_t)&nic7772 },
  355. { "NIC792B", (kernel_ulong_t)&nic792b },
  356. { "NIC7A69", (kernel_ulong_t)&nic7a69 },
  357. { }
  358. };
  359. MODULE_DEVICE_TABLE(acpi, ni16550_acpi_match);
  360. static struct platform_driver ni16550_driver = {
  361. .driver = {
  362. .name = "ni16550",
  363. .acpi_match_table = ni16550_acpi_match,
  364. },
  365. .probe = ni16550_probe,
  366. .remove = ni16550_remove,
  367. };
  368. module_platform_driver(ni16550_driver);
  369. MODULE_AUTHOR("Emerson Electric Co.");
  370. MODULE_DESCRIPTION("NI 16550 Driver");
  371. MODULE_LICENSE("GPL");