moxa.c 54 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*****************************************************************************/
  3. /*
  4. * moxa.c -- MOXA Intellio family multiport serial driver.
  5. *
  6. * Copyright (C) 1999-2000 Moxa Technologies (support@moxa.com).
  7. * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
  8. *
  9. * This code is loosely based on the Linux serial driver, written by
  10. * Linus Torvalds, Theodore T'so and others.
  11. */
  12. /*
  13. * MOXA Intellio Series Driver
  14. * for : LINUX
  15. * date : 1999/1/7
  16. * version : 5.1
  17. */
  18. #include <linux/module.h>
  19. #include <linux/types.h>
  20. #include <linux/mm.h>
  21. #include <linux/ioport.h>
  22. #include <linux/errno.h>
  23. #include <linux/firmware.h>
  24. #include <linux/signal.h>
  25. #include <linux/sched.h>
  26. #include <linux/timer.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/tty.h>
  29. #include <linux/tty_flip.h>
  30. #include <linux/major.h>
  31. #include <linux/string.h>
  32. #include <linux/fcntl.h>
  33. #include <linux/ptrace.h>
  34. #include <linux/serial.h>
  35. #include <linux/tty_driver.h>
  36. #include <linux/delay.h>
  37. #include <linux/pci.h>
  38. #include <linux/init.h>
  39. #include <linux/bitops.h>
  40. #include <linux/slab.h>
  41. #include <linux/ratelimit.h>
  42. #include <asm/io.h>
  43. /*
  44. * System Configuration
  45. */
  46. #define Magic_code 0x404
  47. /*
  48. * for C218 BIOS initialization
  49. */
  50. #define C218_ConfBase 0x800
  51. #define C218_status (C218_ConfBase + 0) /* BIOS running status */
  52. #define C218_diag (C218_ConfBase + 2) /* diagnostic status */
  53. #define C218_key (C218_ConfBase + 4) /* WORD (0x218 for C218) */
  54. #define C218DLoad_len (C218_ConfBase + 6) /* WORD */
  55. #define C218check_sum (C218_ConfBase + 8) /* BYTE */
  56. #define C218chksum_ok (C218_ConfBase + 0x0a) /* BYTE (1:ok) */
  57. #define C218_TestRx (C218_ConfBase + 0x10) /* 8 bytes for 8 ports */
  58. #define C218_TestTx (C218_ConfBase + 0x18) /* 8 bytes for 8 ports */
  59. #define C218_RXerr (C218_ConfBase + 0x20) /* 8 bytes for 8 ports */
  60. #define C218_ErrFlag (C218_ConfBase + 0x28) /* 8 bytes for 8 ports */
  61. #define C218_LoadBuf 0x0F00
  62. #define C218_KeyCode 0x218
  63. #define CP204J_KeyCode 0x204
  64. /*
  65. * for C320 BIOS initialization
  66. */
  67. #define C320_ConfBase 0x800
  68. #define C320_LoadBuf 0x0f00
  69. #define STS_init 0x05 /* for C320_status */
  70. #define C320_status C320_ConfBase + 0 /* BIOS running status */
  71. #define C320_diag C320_ConfBase + 2 /* diagnostic status */
  72. #define C320_key C320_ConfBase + 4 /* WORD (0320H for C320) */
  73. #define C320DLoad_len C320_ConfBase + 6 /* WORD */
  74. #define C320check_sum C320_ConfBase + 8 /* WORD */
  75. #define C320chksum_ok C320_ConfBase + 0x0a /* WORD (1:ok) */
  76. #define C320bapi_len C320_ConfBase + 0x0c /* WORD */
  77. #define C320UART_no C320_ConfBase + 0x0e /* WORD */
  78. #define C320_KeyCode 0x320
  79. #define FixPage_addr 0x0000 /* starting addr of static page */
  80. #define DynPage_addr 0x2000 /* starting addr of dynamic page */
  81. #define C218_start 0x3000 /* starting addr of C218 BIOS prg */
  82. #define Control_reg 0x1ff0 /* select page and reset control */
  83. #define HW_reset 0x80
  84. /*
  85. * Function Codes
  86. */
  87. #define FC_CardReset 0x80
  88. #define FC_ChannelReset 1 /* C320 firmware not supported */
  89. #define FC_EnableCH 2
  90. #define FC_DisableCH 3
  91. #define FC_SetParam 4
  92. #define FC_SetMode 5
  93. #define FC_SetRate 6
  94. #define FC_LineControl 7
  95. #define FC_LineStatus 8
  96. #define FC_XmitControl 9
  97. #define FC_FlushQueue 10
  98. #define FC_SendBreak 11
  99. #define FC_StopBreak 12
  100. #define FC_LoopbackON 13
  101. #define FC_LoopbackOFF 14
  102. #define FC_ClrIrqTable 15
  103. #define FC_SendXon 16
  104. #define FC_SetTermIrq 17 /* C320 firmware not supported */
  105. #define FC_SetCntIrq 18 /* C320 firmware not supported */
  106. #define FC_SetBreakIrq 19
  107. #define FC_SetLineIrq 20
  108. #define FC_SetFlowCtl 21
  109. #define FC_GenIrq 22
  110. #define FC_InCD180 23
  111. #define FC_OutCD180 24
  112. #define FC_InUARTreg 23
  113. #define FC_OutUARTreg 24
  114. #define FC_SetXonXoff 25
  115. #define FC_OutCD180CCR 26
  116. #define FC_ExtIQueue 27
  117. #define FC_ExtOQueue 28
  118. #define FC_ClrLineIrq 29
  119. #define FC_HWFlowCtl 30
  120. #define FC_GetClockRate 35
  121. #define FC_SetBaud 36
  122. #define FC_SetDataMode 41
  123. #define FC_GetCCSR 43
  124. #define FC_GetDataError 45
  125. #define FC_RxControl 50
  126. #define FC_ImmSend 51
  127. #define FC_SetXonState 52
  128. #define FC_SetXoffState 53
  129. #define FC_SetRxFIFOTrig 54
  130. #define FC_SetTxFIFOCnt 55
  131. #define FC_UnixRate 56
  132. #define FC_UnixResetTimer 57
  133. #define RxFIFOTrig1 0
  134. #define RxFIFOTrig4 1
  135. #define RxFIFOTrig8 2
  136. #define RxFIFOTrig14 3
  137. /*
  138. * Dual-Ported RAM
  139. */
  140. #define DRAM_global 0
  141. #define INT_data (DRAM_global + 0)
  142. #define Config_base (DRAM_global + 0x108)
  143. #define IRQindex (INT_data + 0)
  144. #define IRQpending (INT_data + 4)
  145. #define IRQtable (INT_data + 8)
  146. /*
  147. * Interrupt Status
  148. */
  149. #define IntrRx 0x01 /* receiver data O.K. */
  150. #define IntrTx 0x02 /* transmit buffer empty */
  151. #define IntrFunc 0x04 /* function complete */
  152. #define IntrBreak 0x08 /* received break */
  153. #define IntrLine 0x10 /* line status change
  154. for transmitter */
  155. #define IntrIntr 0x20 /* received INTR code */
  156. #define IntrQuit 0x40 /* received QUIT code */
  157. #define IntrEOF 0x80 /* received EOF code */
  158. #define IntrRxTrigger 0x100 /* rx data count reach trigger value */
  159. #define IntrTxTrigger 0x200 /* tx data count below trigger value */
  160. #define Magic_no (Config_base + 0)
  161. #define Card_model_no (Config_base + 2)
  162. #define Total_ports (Config_base + 4)
  163. #define Module_cnt (Config_base + 8)
  164. #define Module_no (Config_base + 10)
  165. #define Timer_10ms (Config_base + 14)
  166. #define Disable_IRQ (Config_base + 20)
  167. #define TMS320_PORT1 (Config_base + 22)
  168. #define TMS320_PORT2 (Config_base + 24)
  169. #define TMS320_CLOCK (Config_base + 26)
  170. /*
  171. * DATA BUFFER in DRAM
  172. */
  173. #define Extern_table 0x400 /* Base address of the external table
  174. (24 words * 64) total 3K bytes
  175. (24 words * 128) total 6K bytes */
  176. #define Extern_size 0x60 /* 96 bytes */
  177. #define RXrptr 0x00 /* read pointer for RX buffer */
  178. #define RXwptr 0x02 /* write pointer for RX buffer */
  179. #define TXrptr 0x04 /* read pointer for TX buffer */
  180. #define TXwptr 0x06 /* write pointer for TX buffer */
  181. #define HostStat 0x08 /* IRQ flag and general flag */
  182. #define FlagStat 0x0A
  183. #define FlowControl 0x0C /* B7 B6 B5 B4 B3 B2 B1 B0 */
  184. /* x x x x | | | | */
  185. /* | | | + CTS flow */
  186. /* | | +--- RTS flow */
  187. /* | +------ TX Xon/Xoff */
  188. /* +--------- RX Xon/Xoff */
  189. #define Break_cnt 0x0E /* received break count */
  190. #define CD180TXirq 0x10 /* if non-0: enable TX irq */
  191. #define RX_mask 0x12
  192. #define TX_mask 0x14
  193. #define Ofs_rxb 0x16
  194. #define Ofs_txb 0x18
  195. #define Page_rxb 0x1A
  196. #define Page_txb 0x1C
  197. #define EndPage_rxb 0x1E
  198. #define EndPage_txb 0x20
  199. #define Data_error 0x22
  200. #define RxTrigger 0x28
  201. #define TxTrigger 0x2a
  202. #define rRXwptr 0x34
  203. #define Low_water 0x36
  204. #define FuncCode 0x40
  205. #define FuncArg 0x42
  206. #define FuncArg1 0x44
  207. #define C218rx_size 0x2000 /* 8K bytes */
  208. #define C218tx_size 0x8000 /* 32K bytes */
  209. #define C218rx_mask (C218rx_size - 1)
  210. #define C218tx_mask (C218tx_size - 1)
  211. #define C320p8rx_size 0x2000
  212. #define C320p8tx_size 0x8000
  213. #define C320p8rx_mask (C320p8rx_size - 1)
  214. #define C320p8tx_mask (C320p8tx_size - 1)
  215. #define C320p16rx_size 0x2000
  216. #define C320p16tx_size 0x4000
  217. #define C320p16rx_mask (C320p16rx_size - 1)
  218. #define C320p16tx_mask (C320p16tx_size - 1)
  219. #define C320p24rx_size 0x2000
  220. #define C320p24tx_size 0x2000
  221. #define C320p24rx_mask (C320p24rx_size - 1)
  222. #define C320p24tx_mask (C320p24tx_size - 1)
  223. #define C320p32rx_size 0x1000
  224. #define C320p32tx_size 0x1000
  225. #define C320p32rx_mask (C320p32rx_size - 1)
  226. #define C320p32tx_mask (C320p32tx_size - 1)
  227. #define Page_size 0x2000U
  228. #define Page_mask (Page_size - 1)
  229. #define C218rx_spage 3
  230. #define C218tx_spage 4
  231. #define C218rx_pageno 1
  232. #define C218tx_pageno 4
  233. #define C218buf_pageno 5
  234. #define C320p8rx_spage 3
  235. #define C320p8tx_spage 4
  236. #define C320p8rx_pgno 1
  237. #define C320p8tx_pgno 4
  238. #define C320p8buf_pgno 5
  239. #define C320p16rx_spage 3
  240. #define C320p16tx_spage 4
  241. #define C320p16rx_pgno 1
  242. #define C320p16tx_pgno 2
  243. #define C320p16buf_pgno 3
  244. #define C320p24rx_spage 3
  245. #define C320p24tx_spage 4
  246. #define C320p24rx_pgno 1
  247. #define C320p24tx_pgno 1
  248. #define C320p24buf_pgno 2
  249. #define C320p32rx_spage 3
  250. #define C320p32tx_ofs C320p32rx_size
  251. #define C320p32tx_spage 3
  252. #define C320p32buf_pgno 1
  253. /*
  254. * Host Status
  255. */
  256. #define WakeupRx 0x01
  257. #define WakeupTx 0x02
  258. #define WakeupBreak 0x08
  259. #define WakeupLine 0x10
  260. #define WakeupIntr 0x20
  261. #define WakeupQuit 0x40
  262. #define WakeupEOF 0x80 /* used in VTIME control */
  263. #define WakeupRxTrigger 0x100
  264. #define WakeupTxTrigger 0x200
  265. /*
  266. * Flag status
  267. */
  268. #define Rx_over 0x01
  269. #define Xoff_state 0x02
  270. #define Tx_flowOff 0x04
  271. #define Tx_enable 0x08
  272. #define CTS_state 0x10
  273. #define DSR_state 0x20
  274. #define DCD_state 0x80
  275. /*
  276. * FlowControl
  277. */
  278. #define CTS_FlowCtl 1
  279. #define RTS_FlowCtl 2
  280. #define Tx_FlowCtl 4
  281. #define Rx_FlowCtl 8
  282. #define IXM_IXANY 0x10
  283. #define LowWater 128
  284. #define DTR_ON 1
  285. #define RTS_ON 2
  286. #define CTS_ON 1
  287. #define DSR_ON 2
  288. #define DCD_ON 8
  289. /* mode definition */
  290. #define MX_CS8 0x03
  291. #define MX_CS7 0x02
  292. #define MX_CS6 0x01
  293. #define MX_CS5 0x00
  294. #define MX_STOP1 0x00
  295. #define MX_STOP15 0x04
  296. #define MX_STOP2 0x08
  297. #define MX_PARNONE 0x00
  298. #define MX_PAREVEN 0x40
  299. #define MX_PARODD 0xC0
  300. #define MX_PARMARK 0xA0
  301. #define MX_PARSPACE 0x20
  302. #define MOXA_FW_HDRLEN 32
  303. #define MOXAMAJOR 172
  304. #define MAX_BOARDS 4 /* Don't change this value */
  305. #define MAX_PORTS_PER_BOARD 32 /* Don't change this value */
  306. #define MAX_PORTS (MAX_BOARDS * MAX_PORTS_PER_BOARD)
  307. #define MOXA_IS_320(brd) ((brd)->boardType == MOXA_BOARD_C320_PCI)
  308. enum {
  309. MOXA_BOARD_C218_PCI = 1,
  310. MOXA_BOARD_C320_PCI,
  311. MOXA_BOARD_CP204J,
  312. };
  313. static char *moxa_brdname[] =
  314. {
  315. "C218 Turbo PCI series",
  316. "C320 Turbo PCI series",
  317. "CP-204J series",
  318. };
  319. static const struct pci_device_id moxa_pcibrds[] = {
  320. { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C218),
  321. .driver_data = MOXA_BOARD_C218_PCI },
  322. { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C320),
  323. .driver_data = MOXA_BOARD_C320_PCI },
  324. { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP204J),
  325. .driver_data = MOXA_BOARD_CP204J },
  326. { 0 }
  327. };
  328. MODULE_DEVICE_TABLE(pci, moxa_pcibrds);
  329. struct moxa_port;
  330. static struct moxa_board_conf {
  331. int boardType;
  332. int numPorts;
  333. unsigned int ready;
  334. struct moxa_port *ports;
  335. void __iomem *basemem;
  336. void __iomem *intNdx;
  337. void __iomem *intPend;
  338. void __iomem *intTable;
  339. } moxa_boards[MAX_BOARDS];
  340. struct moxa_port {
  341. struct tty_port port;
  342. struct moxa_board_conf *board;
  343. void __iomem *tableAddr;
  344. int type;
  345. int cflag;
  346. unsigned long statusflags;
  347. u8 DCDState; /* Protected by the port lock */
  348. u8 lineCtrl;
  349. u8 lowChkFlag;
  350. };
  351. /* statusflags */
  352. #define TXSTOPPED 1
  353. #define LOWWAIT 2
  354. #define EMPTYWAIT 3
  355. #define WAKEUP_CHARS 256
  356. static int ttymajor = MOXAMAJOR;
  357. static unsigned int moxaFuncTout = HZ / 2;
  358. static unsigned int moxaLowWaterChk;
  359. static DEFINE_MUTEX(moxa_openlock);
  360. static DEFINE_SPINLOCK(moxa_lock);
  361. MODULE_AUTHOR("William Chen");
  362. MODULE_DESCRIPTION("MOXA Intellio Family Multiport Board Device Driver");
  363. MODULE_LICENSE("GPL");
  364. MODULE_FIRMWARE("c218tunx.cod");
  365. MODULE_FIRMWARE("cp204unx.cod");
  366. MODULE_FIRMWARE("c320tunx.cod");
  367. module_param(ttymajor, int, 0);
  368. /*
  369. * static functions:
  370. */
  371. static int moxa_open(struct tty_struct *, struct file *);
  372. static void moxa_close(struct tty_struct *, struct file *);
  373. static ssize_t moxa_write(struct tty_struct *, const u8 *, size_t);
  374. static unsigned int moxa_write_room(struct tty_struct *);
  375. static void moxa_flush_buffer(struct tty_struct *);
  376. static unsigned int moxa_chars_in_buffer(struct tty_struct *);
  377. static void moxa_set_termios(struct tty_struct *, const struct ktermios *);
  378. static void moxa_stop(struct tty_struct *);
  379. static void moxa_start(struct tty_struct *);
  380. static void moxa_hangup(struct tty_struct *);
  381. static int moxa_tiocmget(struct tty_struct *tty);
  382. static int moxa_tiocmset(struct tty_struct *tty,
  383. unsigned int set, unsigned int clear);
  384. static void moxa_poll(struct timer_list *);
  385. static void moxa_set_tty_param(struct tty_struct *, const struct ktermios *);
  386. static void moxa_shutdown(struct tty_port *);
  387. static bool moxa_carrier_raised(struct tty_port *);
  388. static void moxa_dtr_rts(struct tty_port *, bool);
  389. /*
  390. * moxa board interface functions:
  391. */
  392. static void MoxaPortEnable(struct moxa_port *);
  393. static void MoxaPortDisable(struct moxa_port *);
  394. static int MoxaPortSetTermio(struct moxa_port *, struct ktermios *, speed_t);
  395. static int MoxaPortGetLineOut(struct moxa_port *, bool *, bool *);
  396. static void MoxaPortLineCtrl(struct moxa_port *, bool, bool);
  397. static void MoxaPortFlowCtrl(struct moxa_port *, int, int, int, int, int);
  398. static int MoxaPortLineStatus(struct moxa_port *);
  399. static void MoxaPortFlushData(struct moxa_port *, int);
  400. static ssize_t MoxaPortWriteData(struct tty_struct *, const u8 *, size_t);
  401. static int MoxaPortReadData(struct moxa_port *);
  402. static unsigned int MoxaPortTxQueue(struct moxa_port *);
  403. static int MoxaPortRxQueue(struct moxa_port *);
  404. static unsigned int MoxaPortTxFree(struct moxa_port *);
  405. static void MoxaPortTxDisable(struct moxa_port *);
  406. static void MoxaPortTxEnable(struct moxa_port *);
  407. static int moxa_get_serial_info(struct tty_struct *, struct serial_struct *);
  408. static int moxa_set_serial_info(struct tty_struct *, struct serial_struct *);
  409. static void MoxaSetFifo(struct moxa_port *port, int enable);
  410. /*
  411. * I/O functions
  412. */
  413. static DEFINE_SPINLOCK(moxafunc_lock);
  414. static void moxa_wait_finish(void __iomem *ofsAddr)
  415. {
  416. unsigned long end = jiffies + moxaFuncTout;
  417. while (readw(ofsAddr + FuncCode) != 0)
  418. if (time_after(jiffies, end))
  419. return;
  420. if (readw(ofsAddr + FuncCode) != 0)
  421. printk_ratelimited(KERN_WARNING "moxa function expired\n");
  422. }
  423. static void moxafunc(void __iomem *ofsAddr, u16 cmd, u16 arg)
  424. {
  425. guard(spinlock_irqsave)(&moxafunc_lock);
  426. writew(arg, ofsAddr + FuncArg);
  427. writew(cmd, ofsAddr + FuncCode);
  428. moxa_wait_finish(ofsAddr);
  429. }
  430. static int moxafuncret(void __iomem *ofsAddr, u16 cmd, u16 arg)
  431. {
  432. guard(spinlock_irqsave)(&moxafunc_lock);
  433. writew(arg, ofsAddr + FuncArg);
  434. writew(cmd, ofsAddr + FuncCode);
  435. moxa_wait_finish(ofsAddr);
  436. return readw(ofsAddr + FuncArg);
  437. }
  438. static void moxa_low_water_check(void __iomem *ofsAddr)
  439. {
  440. u16 rptr, wptr, mask, len;
  441. if (readb(ofsAddr + FlagStat) & Xoff_state) {
  442. rptr = readw(ofsAddr + RXrptr);
  443. wptr = readw(ofsAddr + RXwptr);
  444. mask = readw(ofsAddr + RX_mask);
  445. len = (wptr - rptr) & mask;
  446. if (len <= Low_water)
  447. moxafunc(ofsAddr, FC_SendXon, 0);
  448. }
  449. }
  450. /*
  451. * TTY operations
  452. */
  453. static int moxa_break_ctl(struct tty_struct *tty, int state)
  454. {
  455. struct moxa_port *port = tty->driver_data;
  456. moxafunc(port->tableAddr, state ? FC_SendBreak : FC_StopBreak,
  457. Magic_code);
  458. return 0;
  459. }
  460. static const struct tty_operations moxa_ops = {
  461. .open = moxa_open,
  462. .close = moxa_close,
  463. .write = moxa_write,
  464. .write_room = moxa_write_room,
  465. .flush_buffer = moxa_flush_buffer,
  466. .chars_in_buffer = moxa_chars_in_buffer,
  467. .set_termios = moxa_set_termios,
  468. .stop = moxa_stop,
  469. .start = moxa_start,
  470. .hangup = moxa_hangup,
  471. .break_ctl = moxa_break_ctl,
  472. .tiocmget = moxa_tiocmget,
  473. .tiocmset = moxa_tiocmset,
  474. .set_serial = moxa_set_serial_info,
  475. .get_serial = moxa_get_serial_info,
  476. };
  477. static const struct tty_port_operations moxa_port_ops = {
  478. .carrier_raised = moxa_carrier_raised,
  479. .dtr_rts = moxa_dtr_rts,
  480. .shutdown = moxa_shutdown,
  481. };
  482. static struct tty_driver *moxaDriver;
  483. static DEFINE_TIMER(moxaTimer, moxa_poll);
  484. /*
  485. * HW init
  486. */
  487. static int moxa_check_fw_model(struct moxa_board_conf *brd, u8 model)
  488. {
  489. switch (brd->boardType) {
  490. case MOXA_BOARD_C218_PCI:
  491. if (model != 1)
  492. goto err;
  493. break;
  494. case MOXA_BOARD_CP204J:
  495. if (model != 3)
  496. goto err;
  497. break;
  498. default:
  499. if (model != 2)
  500. goto err;
  501. break;
  502. }
  503. return 0;
  504. err:
  505. return -EINVAL;
  506. }
  507. static int moxa_check_fw(const void *ptr)
  508. {
  509. const __le16 *lptr = ptr;
  510. if (*lptr != cpu_to_le16(0x7980))
  511. return -EINVAL;
  512. return 0;
  513. }
  514. static int moxa_load_bios(struct moxa_board_conf *brd, const u8 *buf,
  515. size_t len)
  516. {
  517. void __iomem *baseAddr = brd->basemem;
  518. u16 tmp;
  519. writeb(HW_reset, baseAddr + Control_reg); /* reset */
  520. msleep(10);
  521. memset_io(baseAddr, 0, 4096);
  522. memcpy_toio(baseAddr, buf, len); /* download BIOS */
  523. writeb(0, baseAddr + Control_reg); /* restart */
  524. msleep(2000);
  525. switch (brd->boardType) {
  526. case MOXA_BOARD_C218_PCI:
  527. tmp = readw(baseAddr + C218_key);
  528. if (tmp != C218_KeyCode)
  529. goto err;
  530. break;
  531. case MOXA_BOARD_CP204J:
  532. tmp = readw(baseAddr + C218_key);
  533. if (tmp != CP204J_KeyCode)
  534. goto err;
  535. break;
  536. default:
  537. tmp = readw(baseAddr + C320_key);
  538. if (tmp != C320_KeyCode)
  539. goto err;
  540. tmp = readw(baseAddr + C320_status);
  541. if (tmp != STS_init) {
  542. printk(KERN_ERR "MOXA: bios upload failed -- CPU/Basic "
  543. "module not found\n");
  544. return -EIO;
  545. }
  546. break;
  547. }
  548. return 0;
  549. err:
  550. printk(KERN_ERR "MOXA: bios upload failed -- board not found\n");
  551. return -EIO;
  552. }
  553. static int moxa_load_320b(struct moxa_board_conf *brd, const u8 *ptr,
  554. size_t len)
  555. {
  556. void __iomem *baseAddr = brd->basemem;
  557. if (len < 7168) {
  558. printk(KERN_ERR "MOXA: invalid 320 bios -- too short\n");
  559. return -EINVAL;
  560. }
  561. writew(len - 7168 - 2, baseAddr + C320bapi_len);
  562. writeb(1, baseAddr + Control_reg); /* Select Page 1 */
  563. memcpy_toio(baseAddr + DynPage_addr, ptr, 7168);
  564. writeb(2, baseAddr + Control_reg); /* Select Page 2 */
  565. memcpy_toio(baseAddr + DynPage_addr, ptr + 7168, len - 7168);
  566. return 0;
  567. }
  568. static int moxa_real_load_code(struct moxa_board_conf *brd, const void *ptr,
  569. size_t len)
  570. {
  571. void __iomem *baseAddr = brd->basemem;
  572. const __le16 *uptr = ptr;
  573. size_t wlen, len2, j;
  574. unsigned long key, loadbuf, loadlen, checksum, checksum_ok;
  575. unsigned int i, retry;
  576. u16 usum, keycode;
  577. keycode = (brd->boardType == MOXA_BOARD_CP204J) ? CP204J_KeyCode :
  578. C218_KeyCode;
  579. switch (brd->boardType) {
  580. case MOXA_BOARD_CP204J:
  581. case MOXA_BOARD_C218_PCI:
  582. key = C218_key;
  583. loadbuf = C218_LoadBuf;
  584. loadlen = C218DLoad_len;
  585. checksum = C218check_sum;
  586. checksum_ok = C218chksum_ok;
  587. break;
  588. default:
  589. key = C320_key;
  590. keycode = C320_KeyCode;
  591. loadbuf = C320_LoadBuf;
  592. loadlen = C320DLoad_len;
  593. checksum = C320check_sum;
  594. checksum_ok = C320chksum_ok;
  595. break;
  596. }
  597. usum = 0;
  598. wlen = len >> 1;
  599. for (i = 0; i < wlen; i++)
  600. usum += le16_to_cpu(uptr[i]);
  601. retry = 0;
  602. do {
  603. wlen = len >> 1;
  604. j = 0;
  605. while (wlen) {
  606. len2 = (wlen > 2048) ? 2048 : wlen;
  607. wlen -= len2;
  608. memcpy_toio(baseAddr + loadbuf, ptr + j, len2 << 1);
  609. j += len2 << 1;
  610. writew(len2, baseAddr + loadlen);
  611. writew(0, baseAddr + key);
  612. for (i = 0; i < 100; i++) {
  613. if (readw(baseAddr + key) == keycode)
  614. break;
  615. msleep(10);
  616. }
  617. if (readw(baseAddr + key) != keycode)
  618. return -EIO;
  619. }
  620. writew(0, baseAddr + loadlen);
  621. writew(usum, baseAddr + checksum);
  622. writew(0, baseAddr + key);
  623. for (i = 0; i < 100; i++) {
  624. if (readw(baseAddr + key) == keycode)
  625. break;
  626. msleep(10);
  627. }
  628. retry++;
  629. } while ((readb(baseAddr + checksum_ok) != 1) && (retry < 3));
  630. if (readb(baseAddr + checksum_ok) != 1)
  631. return -EIO;
  632. writew(0, baseAddr + key);
  633. for (i = 0; i < 600; i++) {
  634. if (readw(baseAddr + Magic_no) == Magic_code)
  635. break;
  636. msleep(10);
  637. }
  638. if (readw(baseAddr + Magic_no) != Magic_code)
  639. return -EIO;
  640. if (MOXA_IS_320(brd)) {
  641. writew(0x3800, baseAddr + TMS320_PORT1);
  642. writew(0x3900, baseAddr + TMS320_PORT2);
  643. writew(28499, baseAddr + TMS320_CLOCK);
  644. }
  645. writew(1, baseAddr + Disable_IRQ);
  646. writew(0, baseAddr + Magic_no);
  647. for (i = 0; i < 500; i++) {
  648. if (readw(baseAddr + Magic_no) == Magic_code)
  649. break;
  650. msleep(10);
  651. }
  652. if (readw(baseAddr + Magic_no) != Magic_code)
  653. return -EIO;
  654. if (MOXA_IS_320(brd)) {
  655. j = readw(baseAddr + Module_cnt);
  656. if (j <= 0)
  657. return -EIO;
  658. brd->numPorts = j * 8;
  659. writew(j, baseAddr + Module_no);
  660. writew(0, baseAddr + Magic_no);
  661. for (i = 0; i < 600; i++) {
  662. if (readw(baseAddr + Magic_no) == Magic_code)
  663. break;
  664. msleep(10);
  665. }
  666. if (readw(baseAddr + Magic_no) != Magic_code)
  667. return -EIO;
  668. }
  669. brd->intNdx = baseAddr + IRQindex;
  670. brd->intPend = baseAddr + IRQpending;
  671. brd->intTable = baseAddr + IRQtable;
  672. return 0;
  673. }
  674. static int moxa_load_code(struct moxa_board_conf *brd, const void *ptr,
  675. size_t len)
  676. {
  677. void __iomem *ofsAddr, *baseAddr = brd->basemem;
  678. struct moxa_port *port;
  679. int retval, i;
  680. if (len % 2) {
  681. printk(KERN_ERR "MOXA: bios length is not even\n");
  682. return -EINVAL;
  683. }
  684. retval = moxa_real_load_code(brd, ptr, len); /* may change numPorts */
  685. if (retval)
  686. return retval;
  687. switch (brd->boardType) {
  688. case MOXA_BOARD_C218_PCI:
  689. case MOXA_BOARD_CP204J:
  690. port = brd->ports;
  691. for (i = 0; i < brd->numPorts; i++, port++) {
  692. port->board = brd;
  693. port->DCDState = 0;
  694. port->tableAddr = baseAddr + Extern_table +
  695. Extern_size * i;
  696. ofsAddr = port->tableAddr;
  697. writew(C218rx_mask, ofsAddr + RX_mask);
  698. writew(C218tx_mask, ofsAddr + TX_mask);
  699. writew(C218rx_spage + i * C218buf_pageno, ofsAddr + Page_rxb);
  700. writew(readw(ofsAddr + Page_rxb) + C218rx_pageno, ofsAddr + EndPage_rxb);
  701. writew(C218tx_spage + i * C218buf_pageno, ofsAddr + Page_txb);
  702. writew(readw(ofsAddr + Page_txb) + C218tx_pageno, ofsAddr + EndPage_txb);
  703. }
  704. break;
  705. default:
  706. port = brd->ports;
  707. for (i = 0; i < brd->numPorts; i++, port++) {
  708. port->board = brd;
  709. port->DCDState = 0;
  710. port->tableAddr = baseAddr + Extern_table +
  711. Extern_size * i;
  712. ofsAddr = port->tableAddr;
  713. switch (brd->numPorts) {
  714. case 8:
  715. writew(C320p8rx_mask, ofsAddr + RX_mask);
  716. writew(C320p8tx_mask, ofsAddr + TX_mask);
  717. writew(C320p8rx_spage + i * C320p8buf_pgno, ofsAddr + Page_rxb);
  718. writew(readw(ofsAddr + Page_rxb) + C320p8rx_pgno, ofsAddr + EndPage_rxb);
  719. writew(C320p8tx_spage + i * C320p8buf_pgno, ofsAddr + Page_txb);
  720. writew(readw(ofsAddr + Page_txb) + C320p8tx_pgno, ofsAddr + EndPage_txb);
  721. break;
  722. case 16:
  723. writew(C320p16rx_mask, ofsAddr + RX_mask);
  724. writew(C320p16tx_mask, ofsAddr + TX_mask);
  725. writew(C320p16rx_spage + i * C320p16buf_pgno, ofsAddr + Page_rxb);
  726. writew(readw(ofsAddr + Page_rxb) + C320p16rx_pgno, ofsAddr + EndPage_rxb);
  727. writew(C320p16tx_spage + i * C320p16buf_pgno, ofsAddr + Page_txb);
  728. writew(readw(ofsAddr + Page_txb) + C320p16tx_pgno, ofsAddr + EndPage_txb);
  729. break;
  730. case 24:
  731. writew(C320p24rx_mask, ofsAddr + RX_mask);
  732. writew(C320p24tx_mask, ofsAddr + TX_mask);
  733. writew(C320p24rx_spage + i * C320p24buf_pgno, ofsAddr + Page_rxb);
  734. writew(readw(ofsAddr + Page_rxb) + C320p24rx_pgno, ofsAddr + EndPage_rxb);
  735. writew(C320p24tx_spage + i * C320p24buf_pgno, ofsAddr + Page_txb);
  736. writew(readw(ofsAddr + Page_txb), ofsAddr + EndPage_txb);
  737. break;
  738. case 32:
  739. writew(C320p32rx_mask, ofsAddr + RX_mask);
  740. writew(C320p32tx_mask, ofsAddr + TX_mask);
  741. writew(C320p32tx_ofs, ofsAddr + Ofs_txb);
  742. writew(C320p32rx_spage + i * C320p32buf_pgno, ofsAddr + Page_rxb);
  743. writew(readb(ofsAddr + Page_rxb), ofsAddr + EndPage_rxb);
  744. writew(C320p32tx_spage + i * C320p32buf_pgno, ofsAddr + Page_txb);
  745. writew(readw(ofsAddr + Page_txb), ofsAddr + EndPage_txb);
  746. break;
  747. }
  748. }
  749. break;
  750. }
  751. return 0;
  752. }
  753. static int moxa_load_fw(struct moxa_board_conf *brd, const struct firmware *fw)
  754. {
  755. const void *ptr = fw->data;
  756. char rsn[64];
  757. u16 lens[5];
  758. size_t len;
  759. unsigned int a, lenp, lencnt;
  760. int ret = -EINVAL;
  761. struct {
  762. __le32 magic; /* 0x34303430 */
  763. u8 reserved1[2];
  764. u8 type; /* UNIX = 3 */
  765. u8 model; /* C218T=1, C320T=2, CP204=3 */
  766. u8 reserved2[8];
  767. __le16 len[5];
  768. } const *hdr = ptr;
  769. BUILD_BUG_ON(ARRAY_SIZE(hdr->len) != ARRAY_SIZE(lens));
  770. if (fw->size < MOXA_FW_HDRLEN) {
  771. strcpy(rsn, "too short (even header won't fit)");
  772. goto err;
  773. }
  774. if (hdr->magic != cpu_to_le32(0x30343034)) {
  775. sprintf(rsn, "bad magic: %.8x", le32_to_cpu(hdr->magic));
  776. goto err;
  777. }
  778. if (hdr->type != 3) {
  779. sprintf(rsn, "not for linux, type is %u", hdr->type);
  780. goto err;
  781. }
  782. if (moxa_check_fw_model(brd, hdr->model)) {
  783. sprintf(rsn, "not for this card, model is %u", hdr->model);
  784. goto err;
  785. }
  786. len = MOXA_FW_HDRLEN;
  787. lencnt = hdr->model == 2 ? 5 : 3;
  788. for (a = 0; a < ARRAY_SIZE(lens); a++) {
  789. lens[a] = le16_to_cpu(hdr->len[a]);
  790. if (lens[a] && len + lens[a] <= fw->size &&
  791. moxa_check_fw(&fw->data[len]))
  792. printk(KERN_WARNING "MOXA firmware: unexpected input "
  793. "at offset %u, but going on\n", (u32)len);
  794. if (!lens[a] && a < lencnt) {
  795. sprintf(rsn, "too few entries in fw file");
  796. goto err;
  797. }
  798. len += lens[a];
  799. }
  800. if (len != fw->size) {
  801. sprintf(rsn, "bad length: %u (should be %u)", (u32)fw->size,
  802. (u32)len);
  803. goto err;
  804. }
  805. ptr += MOXA_FW_HDRLEN;
  806. lenp = 0; /* bios */
  807. strcpy(rsn, "read above");
  808. ret = moxa_load_bios(brd, ptr, lens[lenp]);
  809. if (ret)
  810. goto err;
  811. /* we skip the tty section (lens[1]), since we don't need it */
  812. ptr += lens[lenp] + lens[lenp + 1];
  813. lenp += 2; /* comm */
  814. if (hdr->model == 2) {
  815. ret = moxa_load_320b(brd, ptr, lens[lenp]);
  816. if (ret)
  817. goto err;
  818. /* skip another tty */
  819. ptr += lens[lenp] + lens[lenp + 1];
  820. lenp += 2;
  821. }
  822. ret = moxa_load_code(brd, ptr, lens[lenp]);
  823. if (ret)
  824. goto err;
  825. return 0;
  826. err:
  827. printk(KERN_ERR "firmware failed to load, reason: %s\n", rsn);
  828. return ret;
  829. }
  830. static int moxa_init_board(struct moxa_board_conf *brd, struct device *dev)
  831. {
  832. const struct firmware *fw;
  833. const char *file;
  834. struct moxa_port *p;
  835. unsigned int i, first_idx;
  836. int ret;
  837. brd->ports = kcalloc(MAX_PORTS_PER_BOARD, sizeof(*brd->ports),
  838. GFP_KERNEL);
  839. if (brd->ports == NULL) {
  840. printk(KERN_ERR "cannot allocate memory for ports\n");
  841. ret = -ENOMEM;
  842. goto err;
  843. }
  844. for (i = 0, p = brd->ports; i < MAX_PORTS_PER_BOARD; i++, p++) {
  845. tty_port_init(&p->port);
  846. p->port.ops = &moxa_port_ops;
  847. p->type = PORT_16550A;
  848. p->cflag = B9600 | CS8 | CREAD | CLOCAL | HUPCL;
  849. }
  850. switch (brd->boardType) {
  851. case MOXA_BOARD_C218_PCI:
  852. file = "c218tunx.cod";
  853. break;
  854. case MOXA_BOARD_CP204J:
  855. file = "cp204unx.cod";
  856. break;
  857. default:
  858. file = "c320tunx.cod";
  859. break;
  860. }
  861. ret = request_firmware(&fw, file, dev);
  862. if (ret) {
  863. printk(KERN_ERR "MOXA: request_firmware failed. Make sure "
  864. "you've placed '%s' file into your firmware "
  865. "loader directory (e.g. /lib/firmware)\n",
  866. file);
  867. goto err_free;
  868. }
  869. ret = moxa_load_fw(brd, fw);
  870. release_firmware(fw);
  871. if (ret)
  872. goto err_free;
  873. scoped_guard(spinlock_bh, &moxa_lock) {
  874. brd->ready = 1;
  875. if (!timer_pending(&moxaTimer))
  876. mod_timer(&moxaTimer, jiffies + HZ / 50);
  877. }
  878. first_idx = (brd - moxa_boards) * MAX_PORTS_PER_BOARD;
  879. for (i = 0; i < brd->numPorts; i++)
  880. tty_port_register_device(&brd->ports[i].port, moxaDriver,
  881. first_idx + i, dev);
  882. return 0;
  883. err_free:
  884. for (i = 0; i < MAX_PORTS_PER_BOARD; i++)
  885. tty_port_destroy(&brd->ports[i].port);
  886. kfree(brd->ports);
  887. err:
  888. return ret;
  889. }
  890. static void moxa_board_deinit(struct moxa_board_conf *brd)
  891. {
  892. unsigned int a, opened, first_idx;
  893. scoped_guard(mutex, &moxa_openlock) {
  894. scoped_guard(spinlock_bh, &moxa_lock)
  895. brd->ready = 0;
  896. /* pci hot-un-plug support */
  897. for (a = 0; a < brd->numPorts; a++)
  898. if (tty_port_initialized(&brd->ports[a].port))
  899. tty_port_tty_hangup(&brd->ports[a].port, false);
  900. for (a = 0; a < MAX_PORTS_PER_BOARD; a++)
  901. tty_port_destroy(&brd->ports[a].port);
  902. while (1) {
  903. opened = 0;
  904. for (a = 0; a < brd->numPorts; a++)
  905. if (tty_port_initialized(&brd->ports[a].port))
  906. opened++;
  907. if (!opened)
  908. break;
  909. mutex_unlock(&moxa_openlock);
  910. msleep(50);
  911. mutex_lock(&moxa_openlock);
  912. }
  913. }
  914. first_idx = (brd - moxa_boards) * MAX_PORTS_PER_BOARD;
  915. for (a = 0; a < brd->numPorts; a++)
  916. tty_unregister_device(moxaDriver, first_idx + a);
  917. iounmap(brd->basemem);
  918. brd->basemem = NULL;
  919. kfree(brd->ports);
  920. }
  921. static int moxa_pci_probe(struct pci_dev *pdev,
  922. const struct pci_device_id *ent)
  923. {
  924. struct moxa_board_conf *board;
  925. unsigned int i;
  926. int board_type = ent->driver_data;
  927. int retval;
  928. retval = pci_enable_device(pdev);
  929. if (retval) {
  930. dev_err(&pdev->dev, "can't enable pci device\n");
  931. goto err;
  932. }
  933. for (i = 0; i < MAX_BOARDS; i++)
  934. if (moxa_boards[i].basemem == NULL)
  935. break;
  936. retval = -ENODEV;
  937. if (i >= MAX_BOARDS) {
  938. dev_warn(&pdev->dev, "more than %u MOXA Intellio family boards "
  939. "found. Board is ignored.\n", MAX_BOARDS);
  940. goto err;
  941. }
  942. board = &moxa_boards[i];
  943. retval = pci_request_region(pdev, 2, "moxa-base");
  944. if (retval) {
  945. dev_err(&pdev->dev, "can't request pci region 2\n");
  946. goto err;
  947. }
  948. board->basemem = ioremap(pci_resource_start(pdev, 2), 0x4000);
  949. if (board->basemem == NULL) {
  950. dev_err(&pdev->dev, "can't remap io space 2\n");
  951. retval = -ENOMEM;
  952. goto err_reg;
  953. }
  954. board->boardType = board_type;
  955. switch (board_type) {
  956. case MOXA_BOARD_C218_PCI:
  957. board->numPorts = 8;
  958. break;
  959. case MOXA_BOARD_CP204J:
  960. board->numPorts = 4;
  961. break;
  962. default:
  963. board->numPorts = 0;
  964. break;
  965. }
  966. retval = moxa_init_board(board, &pdev->dev);
  967. if (retval)
  968. goto err_base;
  969. pci_set_drvdata(pdev, board);
  970. dev_info(&pdev->dev, "board '%s' ready (%u ports, firmware loaded)\n",
  971. moxa_brdname[board_type - 1], board->numPorts);
  972. return 0;
  973. err_base:
  974. iounmap(board->basemem);
  975. board->basemem = NULL;
  976. err_reg:
  977. pci_release_region(pdev, 2);
  978. err:
  979. return retval;
  980. }
  981. static void moxa_pci_remove(struct pci_dev *pdev)
  982. {
  983. struct moxa_board_conf *brd = pci_get_drvdata(pdev);
  984. moxa_board_deinit(brd);
  985. pci_release_region(pdev, 2);
  986. }
  987. static struct pci_driver moxa_pci_driver = {
  988. .name = "moxa",
  989. .id_table = moxa_pcibrds,
  990. .probe = moxa_pci_probe,
  991. .remove = moxa_pci_remove
  992. };
  993. static int __init moxa_init(void)
  994. {
  995. int retval = 0;
  996. moxaDriver = tty_alloc_driver(MAX_PORTS,
  997. TTY_DRIVER_REAL_RAW |
  998. TTY_DRIVER_DYNAMIC_DEV);
  999. if (IS_ERR(moxaDriver))
  1000. return PTR_ERR(moxaDriver);
  1001. moxaDriver->name = "ttyMX";
  1002. moxaDriver->major = ttymajor;
  1003. moxaDriver->minor_start = 0;
  1004. moxaDriver->type = TTY_DRIVER_TYPE_SERIAL;
  1005. moxaDriver->subtype = SERIAL_TYPE_NORMAL;
  1006. moxaDriver->init_termios = tty_std_termios;
  1007. moxaDriver->init_termios.c_cflag = B9600 | CS8 | CREAD | CLOCAL | HUPCL;
  1008. moxaDriver->init_termios.c_ispeed = 9600;
  1009. moxaDriver->init_termios.c_ospeed = 9600;
  1010. tty_set_operations(moxaDriver, &moxa_ops);
  1011. if (tty_register_driver(moxaDriver)) {
  1012. printk(KERN_ERR "can't register MOXA Smartio tty driver!\n");
  1013. tty_driver_kref_put(moxaDriver);
  1014. return -1;
  1015. }
  1016. retval = pci_register_driver(&moxa_pci_driver);
  1017. if (retval)
  1018. printk(KERN_ERR "Can't register MOXA pci driver!\n");
  1019. return retval;
  1020. }
  1021. static void __exit moxa_exit(void)
  1022. {
  1023. pci_unregister_driver(&moxa_pci_driver);
  1024. timer_delete_sync(&moxaTimer);
  1025. tty_unregister_driver(moxaDriver);
  1026. tty_driver_kref_put(moxaDriver);
  1027. }
  1028. module_init(moxa_init);
  1029. module_exit(moxa_exit);
  1030. static void moxa_shutdown(struct tty_port *port)
  1031. {
  1032. struct moxa_port *ch = container_of(port, struct moxa_port, port);
  1033. MoxaPortDisable(ch);
  1034. MoxaPortFlushData(ch, 2);
  1035. }
  1036. static bool moxa_carrier_raised(struct tty_port *port)
  1037. {
  1038. struct moxa_port *ch = container_of(port, struct moxa_port, port);
  1039. guard(spinlock_irq)(&port->lock);
  1040. return ch->DCDState;
  1041. }
  1042. static void moxa_dtr_rts(struct tty_port *port, bool active)
  1043. {
  1044. struct moxa_port *ch = container_of(port, struct moxa_port, port);
  1045. MoxaPortLineCtrl(ch, active, active);
  1046. }
  1047. static int moxa_open(struct tty_struct *tty, struct file *filp)
  1048. {
  1049. struct moxa_board_conf *brd;
  1050. struct moxa_port *ch;
  1051. int port = tty->index;
  1052. scoped_cond_guard(mutex_intr, return -ERESTARTSYS, &moxa_openlock) {
  1053. brd = &moxa_boards[port / MAX_PORTS_PER_BOARD];
  1054. if (!brd->ready)
  1055. return -ENODEV;
  1056. if (port % MAX_PORTS_PER_BOARD >= brd->numPorts)
  1057. return -ENODEV;
  1058. ch = &brd->ports[port % MAX_PORTS_PER_BOARD];
  1059. ch->port.count++;
  1060. tty->driver_data = ch;
  1061. tty_port_tty_set(&ch->port, tty);
  1062. guard(mutex)(&ch->port.mutex);
  1063. if (!tty_port_initialized(&ch->port)) {
  1064. ch->statusflags = 0;
  1065. moxa_set_tty_param(tty, &tty->termios);
  1066. MoxaPortLineCtrl(ch, true, true);
  1067. MoxaPortEnable(ch);
  1068. MoxaSetFifo(ch, ch->type == PORT_16550A);
  1069. tty_port_set_initialized(&ch->port, true);
  1070. }
  1071. }
  1072. return tty_port_block_til_ready(&ch->port, tty, filp);
  1073. }
  1074. static void moxa_close(struct tty_struct *tty, struct file *filp)
  1075. {
  1076. struct moxa_port *ch = tty->driver_data;
  1077. ch->cflag = tty->termios.c_cflag;
  1078. tty_port_close(&ch->port, tty, filp);
  1079. }
  1080. static ssize_t moxa_write(struct tty_struct *tty, const u8 *buf, size_t count)
  1081. {
  1082. struct moxa_port *ch = tty->driver_data;
  1083. int len;
  1084. if (ch == NULL)
  1085. return 0;
  1086. scoped_guard(spinlock_irqsave, &moxa_lock)
  1087. len = MoxaPortWriteData(tty, buf, count);
  1088. set_bit(LOWWAIT, &ch->statusflags);
  1089. return len;
  1090. }
  1091. static unsigned int moxa_write_room(struct tty_struct *tty)
  1092. {
  1093. struct moxa_port *ch;
  1094. if (tty->flow.stopped)
  1095. return 0;
  1096. ch = tty->driver_data;
  1097. if (ch == NULL)
  1098. return 0;
  1099. return MoxaPortTxFree(ch);
  1100. }
  1101. static void moxa_flush_buffer(struct tty_struct *tty)
  1102. {
  1103. struct moxa_port *ch = tty->driver_data;
  1104. if (ch == NULL)
  1105. return;
  1106. MoxaPortFlushData(ch, 1);
  1107. tty_wakeup(tty);
  1108. }
  1109. static unsigned int moxa_chars_in_buffer(struct tty_struct *tty)
  1110. {
  1111. struct moxa_port *ch = tty->driver_data;
  1112. unsigned int chars;
  1113. chars = MoxaPortTxQueue(ch);
  1114. if (chars)
  1115. /*
  1116. * Make it possible to wakeup anything waiting for output
  1117. * in tty_ioctl.c, etc.
  1118. */
  1119. set_bit(EMPTYWAIT, &ch->statusflags);
  1120. return chars;
  1121. }
  1122. static int moxa_tiocmget(struct tty_struct *tty)
  1123. {
  1124. struct moxa_port *ch = tty->driver_data;
  1125. bool dtr_active, rts_active;
  1126. int flag = 0;
  1127. int status;
  1128. MoxaPortGetLineOut(ch, &dtr_active, &rts_active);
  1129. if (dtr_active)
  1130. flag |= TIOCM_DTR;
  1131. if (rts_active)
  1132. flag |= TIOCM_RTS;
  1133. status = MoxaPortLineStatus(ch);
  1134. if (status & 1)
  1135. flag |= TIOCM_CTS;
  1136. if (status & 2)
  1137. flag |= TIOCM_DSR;
  1138. if (status & 4)
  1139. flag |= TIOCM_CD;
  1140. return flag;
  1141. }
  1142. static int moxa_tiocmset(struct tty_struct *tty,
  1143. unsigned int set, unsigned int clear)
  1144. {
  1145. bool dtr_active, rts_active;
  1146. struct moxa_port *ch;
  1147. guard(mutex)(&moxa_openlock);
  1148. ch = tty->driver_data;
  1149. if (!ch)
  1150. return -EINVAL;
  1151. MoxaPortGetLineOut(ch, &dtr_active, &rts_active);
  1152. if (set & TIOCM_RTS)
  1153. rts_active = true;
  1154. if (set & TIOCM_DTR)
  1155. dtr_active = true;
  1156. if (clear & TIOCM_RTS)
  1157. rts_active = false;
  1158. if (clear & TIOCM_DTR)
  1159. dtr_active = false;
  1160. MoxaPortLineCtrl(ch, dtr_active, rts_active);
  1161. return 0;
  1162. }
  1163. static void moxa_set_termios(struct tty_struct *tty,
  1164. const struct ktermios *old_termios)
  1165. {
  1166. struct moxa_port *ch = tty->driver_data;
  1167. if (ch == NULL)
  1168. return;
  1169. moxa_set_tty_param(tty, old_termios);
  1170. if (!(old_termios->c_cflag & CLOCAL) && C_CLOCAL(tty))
  1171. wake_up_interruptible(&ch->port.open_wait);
  1172. }
  1173. static void moxa_stop(struct tty_struct *tty)
  1174. {
  1175. struct moxa_port *ch = tty->driver_data;
  1176. if (ch == NULL)
  1177. return;
  1178. MoxaPortTxDisable(ch);
  1179. set_bit(TXSTOPPED, &ch->statusflags);
  1180. }
  1181. static void moxa_start(struct tty_struct *tty)
  1182. {
  1183. struct moxa_port *ch = tty->driver_data;
  1184. if (ch == NULL)
  1185. return;
  1186. if (!test_bit(TXSTOPPED, &ch->statusflags))
  1187. return;
  1188. MoxaPortTxEnable(ch);
  1189. clear_bit(TXSTOPPED, &ch->statusflags);
  1190. }
  1191. static void moxa_hangup(struct tty_struct *tty)
  1192. {
  1193. struct moxa_port *ch = tty->driver_data;
  1194. tty_port_hangup(&ch->port);
  1195. }
  1196. static void moxa_new_dcdstate(struct moxa_port *p, u8 dcd)
  1197. {
  1198. dcd = !!dcd;
  1199. scoped_guard(spinlock_irqsave, &p->port.lock) {
  1200. if (dcd == p->DCDState)
  1201. return;
  1202. p->DCDState = dcd;
  1203. }
  1204. if (!dcd)
  1205. tty_port_tty_hangup(&p->port, true);
  1206. }
  1207. static int moxa_poll_port(struct moxa_port *p, unsigned int handle,
  1208. u16 __iomem *ip)
  1209. {
  1210. struct tty_struct *tty = tty_port_tty_get(&p->port);
  1211. bool inited = tty_port_initialized(&p->port);
  1212. void __iomem *ofsAddr;
  1213. u16 intr;
  1214. if (tty) {
  1215. if (test_bit(EMPTYWAIT, &p->statusflags) &&
  1216. MoxaPortTxQueue(p) == 0) {
  1217. clear_bit(EMPTYWAIT, &p->statusflags);
  1218. tty_wakeup(tty);
  1219. }
  1220. if (test_bit(LOWWAIT, &p->statusflags) && !tty->flow.stopped &&
  1221. MoxaPortTxQueue(p) <= WAKEUP_CHARS) {
  1222. clear_bit(LOWWAIT, &p->statusflags);
  1223. tty_wakeup(tty);
  1224. }
  1225. if (inited && !tty_throttled(tty) &&
  1226. MoxaPortRxQueue(p) > 0) { /* RX */
  1227. MoxaPortReadData(p);
  1228. tty_flip_buffer_push(&p->port);
  1229. }
  1230. } else {
  1231. clear_bit(EMPTYWAIT, &p->statusflags);
  1232. MoxaPortFlushData(p, 0); /* flush RX */
  1233. }
  1234. if (!handle) /* nothing else to do */
  1235. goto put;
  1236. intr = readw(ip); /* port irq status */
  1237. if (intr == 0)
  1238. goto put;
  1239. writew(0, ip); /* ACK port */
  1240. ofsAddr = p->tableAddr;
  1241. if (intr & IntrTx) /* disable tx intr */
  1242. writew(readw(ofsAddr + HostStat) & ~WakeupTx,
  1243. ofsAddr + HostStat);
  1244. if (!inited)
  1245. goto put;
  1246. if (tty && (intr & IntrBreak) && !I_IGNBRK(tty)) { /* BREAK */
  1247. tty_insert_flip_char(&p->port, 0, TTY_BREAK);
  1248. tty_flip_buffer_push(&p->port);
  1249. }
  1250. if (intr & IntrLine)
  1251. moxa_new_dcdstate(p, readb(ofsAddr + FlagStat) & DCD_state);
  1252. put:
  1253. tty_kref_put(tty);
  1254. return 0;
  1255. }
  1256. static void moxa_poll(struct timer_list *unused)
  1257. {
  1258. struct moxa_board_conf *brd;
  1259. u16 __iomem *ip;
  1260. unsigned int card, port, served = 0;
  1261. guard(spinlock)(&moxa_lock);
  1262. for (card = 0; card < MAX_BOARDS; card++) {
  1263. brd = &moxa_boards[card];
  1264. if (!brd->ready)
  1265. continue;
  1266. served++;
  1267. ip = NULL;
  1268. if (readb(brd->intPend) == 0xff)
  1269. ip = brd->intTable + readb(brd->intNdx);
  1270. for (port = 0; port < brd->numPorts; port++)
  1271. moxa_poll_port(&brd->ports[port], !!ip, ip + port);
  1272. if (ip)
  1273. writeb(0, brd->intPend); /* ACK */
  1274. if (moxaLowWaterChk) {
  1275. struct moxa_port *p = brd->ports;
  1276. for (port = 0; port < brd->numPorts; port++, p++)
  1277. if (p->lowChkFlag) {
  1278. p->lowChkFlag = 0;
  1279. moxa_low_water_check(p->tableAddr);
  1280. }
  1281. }
  1282. }
  1283. moxaLowWaterChk = 0;
  1284. if (served)
  1285. mod_timer(&moxaTimer, jiffies + HZ / 50);
  1286. }
  1287. /******************************************************************************/
  1288. static void moxa_set_tty_param(struct tty_struct *tty,
  1289. const struct ktermios *old_termios)
  1290. {
  1291. register struct ktermios *ts = &tty->termios;
  1292. struct moxa_port *ch = tty->driver_data;
  1293. int rts, cts, txflow, rxflow, xany, baud;
  1294. rts = cts = txflow = rxflow = xany = 0;
  1295. if (ts->c_cflag & CRTSCTS)
  1296. rts = cts = 1;
  1297. if (ts->c_iflag & IXON)
  1298. txflow = 1;
  1299. if (ts->c_iflag & IXOFF)
  1300. rxflow = 1;
  1301. if (ts->c_iflag & IXANY)
  1302. xany = 1;
  1303. MoxaPortFlowCtrl(ch, rts, cts, txflow, rxflow, xany);
  1304. baud = MoxaPortSetTermio(ch, ts, tty_get_baud_rate(tty));
  1305. if (baud == -1)
  1306. baud = tty_termios_baud_rate(old_termios);
  1307. /* Not put the baud rate into the termios data */
  1308. tty_encode_baud_rate(tty, baud, baud);
  1309. }
  1310. /*****************************************************************************
  1311. * Driver level functions: *
  1312. *****************************************************************************/
  1313. static void MoxaPortFlushData(struct moxa_port *port, int mode)
  1314. {
  1315. void __iomem *ofsAddr;
  1316. if (mode < 0 || mode > 2)
  1317. return;
  1318. ofsAddr = port->tableAddr;
  1319. moxafunc(ofsAddr, FC_FlushQueue, mode);
  1320. if (mode != 1) {
  1321. port->lowChkFlag = 0;
  1322. moxa_low_water_check(ofsAddr);
  1323. }
  1324. }
  1325. /*
  1326. * Moxa Port Number Description:
  1327. *
  1328. * MOXA serial driver supports up to 4 MOXA-C218/C320 boards. And,
  1329. * the port number using in MOXA driver functions will be 0 to 31 for
  1330. * first MOXA board, 32 to 63 for second, 64 to 95 for third and 96
  1331. * to 127 for fourth. For example, if you setup three MOXA boards,
  1332. * first board is C218, second board is C320-16 and third board is
  1333. * C320-32. The port number of first board (C218 - 8 ports) is from
  1334. * 0 to 7. The port number of second board (C320 - 16 ports) is form
  1335. * 32 to 47. The port number of third board (C320 - 32 ports) is from
  1336. * 64 to 95. And those port numbers form 8 to 31, 48 to 63 and 96 to
  1337. * 127 will be invalid.
  1338. *
  1339. *
  1340. * Moxa Functions Description:
  1341. *
  1342. * Function 1: Driver initialization routine, this routine must be
  1343. * called when initialized driver.
  1344. * Syntax:
  1345. * void MoxaDriverInit();
  1346. *
  1347. *
  1348. * Function 2: Moxa driver private IOCTL command processing.
  1349. * Syntax:
  1350. * int MoxaDriverIoctl(unsigned int cmd, unsigned long arg, int port);
  1351. *
  1352. * unsigned int cmd : IOCTL command
  1353. * unsigned long arg : IOCTL argument
  1354. * int port : port number (0 - 127)
  1355. *
  1356. * return: 0 (OK)
  1357. * -EINVAL
  1358. * -ENOIOCTLCMD
  1359. *
  1360. *
  1361. * Function 6: Enable this port to start Tx/Rx data.
  1362. * Syntax:
  1363. * void MoxaPortEnable(int port);
  1364. * int port : port number (0 - 127)
  1365. *
  1366. *
  1367. * Function 7: Disable this port
  1368. * Syntax:
  1369. * void MoxaPortDisable(int port);
  1370. * int port : port number (0 - 127)
  1371. *
  1372. *
  1373. * Function 10: Setting baud rate of this port.
  1374. * Syntax:
  1375. * speed_t MoxaPortSetBaud(int port, speed_t baud);
  1376. * int port : port number (0 - 127)
  1377. * long baud : baud rate (50 - 115200)
  1378. *
  1379. * return: 0 : this port is invalid or baud < 50
  1380. * 50 - 115200 : the real baud rate set to the port, if
  1381. * the argument baud is large than maximun
  1382. * available baud rate, the real setting
  1383. * baud rate will be the maximun baud rate.
  1384. *
  1385. *
  1386. * Function 12: Configure the port.
  1387. * Syntax:
  1388. * int MoxaPortSetTermio(int port, struct ktermios *termio, speed_t baud);
  1389. * int port : port number (0 - 127)
  1390. * struct ktermios * termio : termio structure pointer
  1391. * speed_t baud : baud rate
  1392. *
  1393. * return: -1 : this port is invalid or termio == NULL
  1394. * 0 : setting O.K.
  1395. *
  1396. *
  1397. * Function 13: Get the DTR/RTS state of this port.
  1398. * Syntax:
  1399. * int MoxaPortGetLineOut(int port, bool *dtrState, bool *rtsState);
  1400. * int port : port number (0 - 127)
  1401. * bool * dtr_active : pointer to bool to receive the current DTR
  1402. * state. (if NULL, this function will not
  1403. * write to this address)
  1404. * bool * rts_active : pointer to bool to receive the current RTS
  1405. * state. (if NULL, this function will not
  1406. * write to this address)
  1407. *
  1408. * return: -1 : this port is invalid
  1409. * 0 : O.K.
  1410. *
  1411. *
  1412. * Function 14: Setting the DTR/RTS output state of this port.
  1413. * Syntax:
  1414. * void MoxaPortLineCtrl(int port, bool dtrState, bool rtsState);
  1415. * int port : port number (0 - 127)
  1416. * bool dtr_active : DTR output state
  1417. * bool rts_active : RTS output state
  1418. *
  1419. *
  1420. * Function 15: Setting the flow control of this port.
  1421. * Syntax:
  1422. * void MoxaPortFlowCtrl(int port, int rtsFlow, int ctsFlow, int rxFlow,
  1423. * int txFlow,int xany);
  1424. * int port : port number (0 - 127)
  1425. * int rtsFlow : H/W RTS flow control (0: no, 1: yes)
  1426. * int ctsFlow : H/W CTS flow control (0: no, 1: yes)
  1427. * int rxFlow : S/W Rx XON/XOFF flow control (0: no, 1: yes)
  1428. * int txFlow : S/W Tx XON/XOFF flow control (0: no, 1: yes)
  1429. * int xany : S/W XANY flow control (0: no, 1: yes)
  1430. *
  1431. *
  1432. * Function 16: Get ths line status of this port
  1433. * Syntax:
  1434. * int MoxaPortLineStatus(int port);
  1435. * int port : port number (0 - 127)
  1436. *
  1437. * return: Bit 0 - CTS state (0: off, 1: on)
  1438. * Bit 1 - DSR state (0: off, 1: on)
  1439. * Bit 2 - DCD state (0: off, 1: on)
  1440. *
  1441. *
  1442. * Function 19: Flush the Rx/Tx buffer data of this port.
  1443. * Syntax:
  1444. * void MoxaPortFlushData(int port, int mode);
  1445. * int port : port number (0 - 127)
  1446. * int mode
  1447. * 0 : flush the Rx buffer
  1448. * 1 : flush the Tx buffer
  1449. * 2 : flush the Rx and Tx buffer
  1450. *
  1451. *
  1452. * Function 20: Write data.
  1453. * Syntax:
  1454. * ssize_t MoxaPortWriteData(int port, u8 *buffer, size_t length);
  1455. * int port : port number (0 - 127)
  1456. * u8 *buffer : pointer to write data buffer.
  1457. * size_t length : write data length
  1458. *
  1459. * return: 0 - length : real write data length
  1460. *
  1461. *
  1462. * Function 21: Read data.
  1463. * Syntax:
  1464. * int MoxaPortReadData(int port, struct tty_struct *tty);
  1465. * int port : port number (0 - 127)
  1466. * struct tty_struct *tty : tty for data
  1467. *
  1468. * return: 0 - length : real read data length
  1469. *
  1470. *
  1471. * Function 24: Get the Tx buffer current queued data bytes
  1472. * Syntax:
  1473. * int MoxaPortTxQueue(int port);
  1474. * int port : port number (0 - 127)
  1475. *
  1476. * return: .. : Tx buffer current queued data bytes
  1477. *
  1478. *
  1479. * Function 25: Get the Tx buffer current free space
  1480. * Syntax:
  1481. * int MoxaPortTxFree(int port);
  1482. * int port : port number (0 - 127)
  1483. *
  1484. * return: .. : Tx buffer current free space
  1485. *
  1486. *
  1487. * Function 26: Get the Rx buffer current queued data bytes
  1488. * Syntax:
  1489. * int MoxaPortRxQueue(int port);
  1490. * int port : port number (0 - 127)
  1491. *
  1492. * return: .. : Rx buffer current queued data bytes
  1493. *
  1494. *
  1495. * Function 28: Disable port data transmission.
  1496. * Syntax:
  1497. * void MoxaPortTxDisable(int port);
  1498. * int port : port number (0 - 127)
  1499. *
  1500. *
  1501. * Function 29: Enable port data transmission.
  1502. * Syntax:
  1503. * void MoxaPortTxEnable(int port);
  1504. * int port : port number (0 - 127)
  1505. *
  1506. *
  1507. * Function 31: Get the received BREAK signal count and reset it.
  1508. * Syntax:
  1509. * int MoxaPortResetBrkCnt(int port);
  1510. * int port : port number (0 - 127)
  1511. *
  1512. * return: 0 - .. : BREAK signal count
  1513. *
  1514. *
  1515. */
  1516. static void MoxaPortEnable(struct moxa_port *port)
  1517. {
  1518. void __iomem *ofsAddr;
  1519. u16 lowwater = 512;
  1520. ofsAddr = port->tableAddr;
  1521. writew(lowwater, ofsAddr + Low_water);
  1522. if (MOXA_IS_320(port->board))
  1523. moxafunc(ofsAddr, FC_SetBreakIrq, 0);
  1524. else
  1525. writew(readw(ofsAddr + HostStat) | WakeupBreak,
  1526. ofsAddr + HostStat);
  1527. moxafunc(ofsAddr, FC_SetLineIrq, Magic_code);
  1528. moxafunc(ofsAddr, FC_FlushQueue, 2);
  1529. moxafunc(ofsAddr, FC_EnableCH, Magic_code);
  1530. MoxaPortLineStatus(port);
  1531. }
  1532. static void MoxaPortDisable(struct moxa_port *port)
  1533. {
  1534. void __iomem *ofsAddr = port->tableAddr;
  1535. moxafunc(ofsAddr, FC_SetFlowCtl, 0); /* disable flow control */
  1536. moxafunc(ofsAddr, FC_ClrLineIrq, Magic_code);
  1537. writew(0, ofsAddr + HostStat);
  1538. moxafunc(ofsAddr, FC_DisableCH, Magic_code);
  1539. }
  1540. static speed_t MoxaPortSetBaud(struct moxa_port *port, speed_t baud)
  1541. {
  1542. void __iomem *ofsAddr = port->tableAddr;
  1543. unsigned int clock, val;
  1544. speed_t max;
  1545. max = MOXA_IS_320(port->board) ? 460800 : 921600;
  1546. if (baud < 50)
  1547. return 0;
  1548. if (baud > max)
  1549. baud = max;
  1550. clock = 921600;
  1551. val = clock / baud;
  1552. moxafunc(ofsAddr, FC_SetBaud, val);
  1553. baud = clock / val;
  1554. return baud;
  1555. }
  1556. static int MoxaPortSetTermio(struct moxa_port *port, struct ktermios *termio,
  1557. speed_t baud)
  1558. {
  1559. void __iomem *ofsAddr;
  1560. tcflag_t mode = 0;
  1561. ofsAddr = port->tableAddr;
  1562. mode = termio->c_cflag & CSIZE;
  1563. if (mode == CS5)
  1564. mode = MX_CS5;
  1565. else if (mode == CS6)
  1566. mode = MX_CS6;
  1567. else if (mode == CS7)
  1568. mode = MX_CS7;
  1569. else if (mode == CS8)
  1570. mode = MX_CS8;
  1571. if (termio->c_cflag & CSTOPB) {
  1572. if (mode == MX_CS5)
  1573. mode |= MX_STOP15;
  1574. else
  1575. mode |= MX_STOP2;
  1576. } else
  1577. mode |= MX_STOP1;
  1578. if (termio->c_cflag & PARENB) {
  1579. if (termio->c_cflag & PARODD) {
  1580. if (termio->c_cflag & CMSPAR)
  1581. mode |= MX_PARMARK;
  1582. else
  1583. mode |= MX_PARODD;
  1584. } else {
  1585. if (termio->c_cflag & CMSPAR)
  1586. mode |= MX_PARSPACE;
  1587. else
  1588. mode |= MX_PAREVEN;
  1589. }
  1590. } else
  1591. mode |= MX_PARNONE;
  1592. moxafunc(ofsAddr, FC_SetDataMode, (u16)mode);
  1593. if (MOXA_IS_320(port->board) && baud >= 921600)
  1594. return -1;
  1595. baud = MoxaPortSetBaud(port, baud);
  1596. if (termio->c_iflag & (IXON | IXOFF | IXANY)) {
  1597. guard(spinlock_irq)(&moxafunc_lock);
  1598. writeb(termio->c_cc[VSTART], ofsAddr + FuncArg);
  1599. writeb(termio->c_cc[VSTOP], ofsAddr + FuncArg1);
  1600. writeb(FC_SetXonXoff, ofsAddr + FuncCode);
  1601. moxa_wait_finish(ofsAddr);
  1602. }
  1603. return baud;
  1604. }
  1605. static int MoxaPortGetLineOut(struct moxa_port *port, bool *dtr_active,
  1606. bool *rts_active)
  1607. {
  1608. if (dtr_active)
  1609. *dtr_active = port->lineCtrl & DTR_ON;
  1610. if (rts_active)
  1611. *rts_active = port->lineCtrl & RTS_ON;
  1612. return 0;
  1613. }
  1614. static void MoxaPortLineCtrl(struct moxa_port *port, bool dtr_active, bool rts_active)
  1615. {
  1616. u8 mode = 0;
  1617. if (dtr_active)
  1618. mode |= DTR_ON;
  1619. if (rts_active)
  1620. mode |= RTS_ON;
  1621. port->lineCtrl = mode;
  1622. moxafunc(port->tableAddr, FC_LineControl, mode);
  1623. }
  1624. static void MoxaPortFlowCtrl(struct moxa_port *port, int rts, int cts,
  1625. int txflow, int rxflow, int txany)
  1626. {
  1627. int mode = 0;
  1628. if (rts)
  1629. mode |= RTS_FlowCtl;
  1630. if (cts)
  1631. mode |= CTS_FlowCtl;
  1632. if (txflow)
  1633. mode |= Tx_FlowCtl;
  1634. if (rxflow)
  1635. mode |= Rx_FlowCtl;
  1636. if (txany)
  1637. mode |= IXM_IXANY;
  1638. moxafunc(port->tableAddr, FC_SetFlowCtl, mode);
  1639. }
  1640. static int MoxaPortLineStatus(struct moxa_port *port)
  1641. {
  1642. void __iomem *ofsAddr;
  1643. int val;
  1644. ofsAddr = port->tableAddr;
  1645. if (MOXA_IS_320(port->board))
  1646. val = moxafuncret(ofsAddr, FC_LineStatus, 0);
  1647. else
  1648. val = readw(ofsAddr + FlagStat) >> 4;
  1649. val &= 0x0B;
  1650. if (val & 8)
  1651. val |= 4;
  1652. moxa_new_dcdstate(port, val & 8);
  1653. val &= 7;
  1654. return val;
  1655. }
  1656. static ssize_t MoxaPortWriteData(struct tty_struct *tty, const u8 *buffer,
  1657. size_t len)
  1658. {
  1659. struct moxa_port *port = tty->driver_data;
  1660. void __iomem *baseAddr, *ofsAddr, *ofs;
  1661. size_t c, total;
  1662. u16 head, tail, tx_mask, spage, epage;
  1663. u16 pageno, pageofs, bufhead;
  1664. ofsAddr = port->tableAddr;
  1665. baseAddr = port->board->basemem;
  1666. tx_mask = readw(ofsAddr + TX_mask);
  1667. spage = readw(ofsAddr + Page_txb);
  1668. epage = readw(ofsAddr + EndPage_txb);
  1669. tail = readw(ofsAddr + TXwptr);
  1670. head = readw(ofsAddr + TXrptr);
  1671. c = (head > tail) ? (head - tail - 1) : (head - tail + tx_mask);
  1672. if (c > len)
  1673. c = len;
  1674. total = c;
  1675. if (spage == epage) {
  1676. bufhead = readw(ofsAddr + Ofs_txb);
  1677. writew(spage, baseAddr + Control_reg);
  1678. while (c > 0) {
  1679. if (head > tail)
  1680. len = head - tail - 1;
  1681. else
  1682. len = tx_mask + 1 - tail;
  1683. len = (c > len) ? len : c;
  1684. ofs = baseAddr + DynPage_addr + bufhead + tail;
  1685. memcpy_toio(ofs, buffer, len);
  1686. buffer += len;
  1687. tail = (tail + len) & tx_mask;
  1688. c -= len;
  1689. }
  1690. } else {
  1691. pageno = spage + (tail >> 13);
  1692. pageofs = tail & Page_mask;
  1693. while (c > 0) {
  1694. len = Page_size - pageofs;
  1695. if (len > c)
  1696. len = c;
  1697. writeb(pageno, baseAddr + Control_reg);
  1698. ofs = baseAddr + DynPage_addr + pageofs;
  1699. memcpy_toio(ofs, buffer, len);
  1700. buffer += len;
  1701. if (++pageno == epage)
  1702. pageno = spage;
  1703. pageofs = 0;
  1704. c -= len;
  1705. }
  1706. tail = (tail + total) & tx_mask;
  1707. }
  1708. writew(tail, ofsAddr + TXwptr);
  1709. writeb(1, ofsAddr + CD180TXirq); /* start to send */
  1710. return total;
  1711. }
  1712. static int MoxaPortReadData(struct moxa_port *port)
  1713. {
  1714. void __iomem *baseAddr, *ofsAddr, *ofs;
  1715. u8 *dst;
  1716. unsigned int count, len, total;
  1717. u16 tail, rx_mask, spage, epage;
  1718. u16 pageno, pageofs, bufhead, head;
  1719. ofsAddr = port->tableAddr;
  1720. baseAddr = port->board->basemem;
  1721. head = readw(ofsAddr + RXrptr);
  1722. tail = readw(ofsAddr + RXwptr);
  1723. rx_mask = readw(ofsAddr + RX_mask);
  1724. spage = readw(ofsAddr + Page_rxb);
  1725. epage = readw(ofsAddr + EndPage_rxb);
  1726. count = (tail >= head) ? (tail - head) : (tail - head + rx_mask + 1);
  1727. if (count == 0)
  1728. return 0;
  1729. total = count;
  1730. if (spage == epage) {
  1731. bufhead = readw(ofsAddr + Ofs_rxb);
  1732. writew(spage, baseAddr + Control_reg);
  1733. while (count > 0) {
  1734. ofs = baseAddr + DynPage_addr + bufhead + head;
  1735. len = (tail >= head) ? (tail - head) :
  1736. (rx_mask + 1 - head);
  1737. len = tty_prepare_flip_string(&port->port, &dst,
  1738. min(len, count));
  1739. memcpy_fromio(dst, ofs, len);
  1740. head = (head + len) & rx_mask;
  1741. count -= len;
  1742. }
  1743. } else {
  1744. pageno = spage + (head >> 13);
  1745. pageofs = head & Page_mask;
  1746. while (count > 0) {
  1747. writew(pageno, baseAddr + Control_reg);
  1748. ofs = baseAddr + DynPage_addr + pageofs;
  1749. len = tty_prepare_flip_string(&port->port, &dst,
  1750. min(Page_size - pageofs, count));
  1751. memcpy_fromio(dst, ofs, len);
  1752. count -= len;
  1753. pageofs = (pageofs + len) & Page_mask;
  1754. if (pageofs == 0 && ++pageno == epage)
  1755. pageno = spage;
  1756. }
  1757. head = (head + total) & rx_mask;
  1758. }
  1759. writew(head, ofsAddr + RXrptr);
  1760. if (readb(ofsAddr + FlagStat) & Xoff_state) {
  1761. moxaLowWaterChk = 1;
  1762. port->lowChkFlag = 1;
  1763. }
  1764. return total;
  1765. }
  1766. static unsigned int MoxaPortTxQueue(struct moxa_port *port)
  1767. {
  1768. void __iomem *ofsAddr = port->tableAddr;
  1769. u16 rptr, wptr, mask;
  1770. rptr = readw(ofsAddr + TXrptr);
  1771. wptr = readw(ofsAddr + TXwptr);
  1772. mask = readw(ofsAddr + TX_mask);
  1773. return (wptr - rptr) & mask;
  1774. }
  1775. static unsigned int MoxaPortTxFree(struct moxa_port *port)
  1776. {
  1777. void __iomem *ofsAddr = port->tableAddr;
  1778. u16 rptr, wptr, mask;
  1779. rptr = readw(ofsAddr + TXrptr);
  1780. wptr = readw(ofsAddr + TXwptr);
  1781. mask = readw(ofsAddr + TX_mask);
  1782. return mask - ((wptr - rptr) & mask);
  1783. }
  1784. static int MoxaPortRxQueue(struct moxa_port *port)
  1785. {
  1786. void __iomem *ofsAddr = port->tableAddr;
  1787. u16 rptr, wptr, mask;
  1788. rptr = readw(ofsAddr + RXrptr);
  1789. wptr = readw(ofsAddr + RXwptr);
  1790. mask = readw(ofsAddr + RX_mask);
  1791. return (wptr - rptr) & mask;
  1792. }
  1793. static void MoxaPortTxDisable(struct moxa_port *port)
  1794. {
  1795. moxafunc(port->tableAddr, FC_SetXoffState, Magic_code);
  1796. }
  1797. static void MoxaPortTxEnable(struct moxa_port *port)
  1798. {
  1799. moxafunc(port->tableAddr, FC_SetXonState, Magic_code);
  1800. }
  1801. static int moxa_get_serial_info(struct tty_struct *tty,
  1802. struct serial_struct *ss)
  1803. {
  1804. struct moxa_port *info = tty->driver_data;
  1805. if (!info)
  1806. return -ENODEV;
  1807. guard(mutex)(&info->port.mutex);
  1808. ss->type = info->type;
  1809. ss->line = info->port.tty->index;
  1810. ss->flags = info->port.flags;
  1811. ss->baud_base = 921600;
  1812. ss->close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
  1813. return 0;
  1814. }
  1815. static int moxa_set_serial_info(struct tty_struct *tty,
  1816. struct serial_struct *ss)
  1817. {
  1818. struct moxa_port *info = tty->driver_data;
  1819. unsigned int close_delay;
  1820. if (!info)
  1821. return -ENODEV;
  1822. close_delay = msecs_to_jiffies(ss->close_delay * 10);
  1823. guard(mutex)(&info->port.mutex);
  1824. if (!capable(CAP_SYS_ADMIN)) {
  1825. if (close_delay != info->port.close_delay ||
  1826. ss->type != info->type ||
  1827. ((ss->flags & ~ASYNC_USR_MASK) !=
  1828. (info->port.flags & ~ASYNC_USR_MASK))) {
  1829. return -EPERM;
  1830. }
  1831. } else {
  1832. info->port.close_delay = close_delay;
  1833. MoxaSetFifo(info, ss->type == PORT_16550A);
  1834. info->type = ss->type;
  1835. }
  1836. return 0;
  1837. }
  1838. /*****************************************************************************
  1839. * Static local functions: *
  1840. *****************************************************************************/
  1841. static void MoxaSetFifo(struct moxa_port *port, int enable)
  1842. {
  1843. void __iomem *ofsAddr = port->tableAddr;
  1844. if (!enable) {
  1845. moxafunc(ofsAddr, FC_SetRxFIFOTrig, 0);
  1846. moxafunc(ofsAddr, FC_SetTxFIFOCnt, 1);
  1847. } else {
  1848. moxafunc(ofsAddr, FC_SetRxFIFOTrig, 3);
  1849. moxafunc(ofsAddr, FC_SetTxFIFOCnt, 16);
  1850. }
  1851. }