intel_pch_thermal.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* intel_pch_thermal.c - Intel PCH Thermal driver
  3. *
  4. * Copyright (c) 2015, Intel Corporation.
  5. *
  6. * Authors:
  7. * Tushar Dave <tushar.n.dave@intel.com>
  8. */
  9. #include <linux/acpi.h>
  10. #include <linux/delay.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/pci.h>
  14. #include <linux/pm.h>
  15. #include <linux/suspend.h>
  16. #include <linux/thermal.h>
  17. #include <linux/types.h>
  18. #include <linux/units.h>
  19. /* Intel PCH thermal Device IDs */
  20. #define PCH_THERMAL_DID_HSW_1 0x9C24 /* Haswell PCH */
  21. #define PCH_THERMAL_DID_HSW_2 0x8C24 /* Haswell PCH */
  22. #define PCH_THERMAL_DID_WPT 0x9CA4 /* Wildcat Point */
  23. #define PCH_THERMAL_DID_SKL 0x9D31 /* Skylake PCH */
  24. #define PCH_THERMAL_DID_SKL_H 0xA131 /* Skylake PCH 100 series */
  25. #define PCH_THERMAL_DID_CNL 0x9Df9 /* CNL PCH */
  26. #define PCH_THERMAL_DID_CNL_H 0xA379 /* CNL-H PCH */
  27. #define PCH_THERMAL_DID_CNL_LP 0x02F9 /* CNL-LP PCH */
  28. #define PCH_THERMAL_DID_CML_H 0X06F9 /* CML-H PCH */
  29. #define PCH_THERMAL_DID_LWB 0xA1B1 /* Lewisburg PCH */
  30. #define PCH_THERMAL_DID_WBG 0x8D24 /* Wellsburg PCH */
  31. /* Wildcat Point-LP PCH Thermal registers */
  32. #define WPT_TEMP 0x0000 /* Temperature */
  33. #define WPT_TSC 0x04 /* Thermal Sensor Control */
  34. #define WPT_TSS 0x06 /* Thermal Sensor Status */
  35. #define WPT_TSEL 0x08 /* Thermal Sensor Enable and Lock */
  36. #define WPT_TSREL 0x0A /* Thermal Sensor Report Enable and Lock */
  37. #define WPT_TSMIC 0x0C /* Thermal Sensor SMI Control */
  38. #define WPT_CTT 0x0010 /* Catastrophic Trip Point */
  39. #define WPT_TSPM 0x001C /* Thermal Sensor Power Management */
  40. #define WPT_TAHV 0x0014 /* Thermal Alert High Value */
  41. #define WPT_TALV 0x0018 /* Thermal Alert Low Value */
  42. #define WPT_TL 0x00000040 /* Throttle Value */
  43. #define WPT_PHL 0x0060 /* PCH Hot Level */
  44. #define WPT_PHLC 0x62 /* PHL Control */
  45. #define WPT_TAS 0x80 /* Thermal Alert Status */
  46. #define WPT_TSPIEN 0x82 /* PCI Interrupt Event Enables */
  47. #define WPT_TSGPEN 0x84 /* General Purpose Event Enables */
  48. /* Wildcat Point-LP PCH Thermal Register bit definitions */
  49. #define WPT_TEMP_TSR 0x01ff /* Temp TS Reading */
  50. #define WPT_TSC_CPDE 0x01 /* Catastrophic Power-Down Enable */
  51. #define WPT_TSS_TSDSS 0x10 /* Thermal Sensor Dynamic Shutdown Status */
  52. #define WPT_TSS_GPES 0x08 /* GPE status */
  53. #define WPT_TSEL_ETS 0x01 /* Enable TS */
  54. #define WPT_TSEL_PLDB 0x80 /* TSEL Policy Lock-Down Bit */
  55. #define WPT_TL_TOL 0x000001FF /* T0 Level */
  56. #define WPT_TL_T1L 0x1ff00000 /* T1 Level */
  57. #define WPT_TL_TTEN 0x20000000 /* TT Enable */
  58. /* Resolution of 1/2 degree C and an offset of -50C */
  59. #define PCH_TEMP_OFFSET (-50)
  60. #define GET_WPT_TEMP(x) ((x) * MILLIDEGREE_PER_DEGREE / 2 + WPT_TEMP_OFFSET)
  61. #define WPT_TEMP_OFFSET (PCH_TEMP_OFFSET * MILLIDEGREE_PER_DEGREE)
  62. #define GET_PCH_TEMP(x) (((x) / 2) + PCH_TEMP_OFFSET)
  63. #define PCH_MAX_TRIPS 3 /* critical, hot, passive */
  64. /* Amount of time for each cooling delay, 100ms by default for now */
  65. static unsigned int delay_timeout = 100;
  66. module_param(delay_timeout, int, 0644);
  67. MODULE_PARM_DESC(delay_timeout, "amount of time delay for each iteration.");
  68. /* Number of iterations for cooling delay, 600 counts by default for now */
  69. static unsigned int delay_cnt = 600;
  70. module_param(delay_cnt, int, 0644);
  71. MODULE_PARM_DESC(delay_cnt, "total number of iterations for time delay.");
  72. static char driver_name[] = "Intel PCH thermal driver";
  73. struct pch_thermal_device {
  74. void __iomem *hw_base;
  75. struct pci_dev *pdev;
  76. struct thermal_zone_device *tzd;
  77. bool bios_enabled;
  78. };
  79. #ifdef CONFIG_ACPI
  80. /*
  81. * On some platforms, there is a companion ACPI device, which adds
  82. * passive trip temperature using _PSV method. There is no specific
  83. * passive temperature setting in MMIO interface of this PCI device.
  84. */
  85. static int pch_wpt_add_acpi_psv_trip(struct pch_thermal_device *ptd,
  86. struct thermal_trip *trip)
  87. {
  88. struct acpi_device *adev;
  89. int temp;
  90. adev = ACPI_COMPANION(&ptd->pdev->dev);
  91. if (!adev)
  92. return 0;
  93. if (thermal_acpi_passive_trip_temp(adev, &temp) || temp <= 0)
  94. return 0;
  95. trip->type = THERMAL_TRIP_PASSIVE;
  96. trip->temperature = temp;
  97. return 1;
  98. }
  99. #else
  100. static int pch_wpt_add_acpi_psv_trip(struct pch_thermal_device *ptd,
  101. struct thermal_trip *trip)
  102. {
  103. return 0;
  104. }
  105. #endif
  106. static int pch_thermal_get_temp(struct thermal_zone_device *tzd, int *temp)
  107. {
  108. struct pch_thermal_device *ptd = thermal_zone_device_priv(tzd);
  109. *temp = GET_WPT_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP));
  110. return 0;
  111. }
  112. static void pch_critical(struct thermal_zone_device *tzd)
  113. {
  114. dev_dbg(thermal_zone_device(tzd), "%s: critical temperature reached\n",
  115. thermal_zone_device_type(tzd));
  116. }
  117. static const struct thermal_zone_device_ops tzd_ops = {
  118. .get_temp = pch_thermal_get_temp,
  119. .critical = pch_critical,
  120. };
  121. enum pch_board_ids {
  122. PCH_BOARD_HSW = 0,
  123. PCH_BOARD_WPT,
  124. PCH_BOARD_SKL,
  125. PCH_BOARD_CNL,
  126. PCH_BOARD_CML,
  127. PCH_BOARD_LWB,
  128. PCH_BOARD_WBG,
  129. };
  130. static const char *board_names[] = {
  131. [PCH_BOARD_HSW] = "pch_haswell",
  132. [PCH_BOARD_WPT] = "pch_wildcat_point",
  133. [PCH_BOARD_SKL] = "pch_skylake",
  134. [PCH_BOARD_CNL] = "pch_cannonlake",
  135. [PCH_BOARD_CML] = "pch_cometlake",
  136. [PCH_BOARD_LWB] = "pch_lewisburg",
  137. [PCH_BOARD_WBG] = "pch_wellsburg",
  138. };
  139. static int intel_pch_thermal_probe(struct pci_dev *pdev,
  140. const struct pci_device_id *id)
  141. {
  142. struct thermal_trip ptd_trips[PCH_MAX_TRIPS] = { 0 };
  143. enum pch_board_ids board_id = id->driver_data;
  144. struct pch_thermal_device *ptd;
  145. int nr_trips = 0;
  146. u16 trip_temp;
  147. u8 tsel;
  148. int err;
  149. ptd = devm_kzalloc(&pdev->dev, sizeof(*ptd), GFP_KERNEL);
  150. if (!ptd)
  151. return -ENOMEM;
  152. pci_set_drvdata(pdev, ptd);
  153. ptd->pdev = pdev;
  154. err = pci_enable_device(pdev);
  155. if (err) {
  156. dev_err(&pdev->dev, "failed to enable pci device\n");
  157. return err;
  158. }
  159. err = pci_request_regions(pdev, driver_name);
  160. if (err) {
  161. dev_err(&pdev->dev, "failed to request pci region\n");
  162. goto error_disable;
  163. }
  164. ptd->hw_base = pci_ioremap_bar(pdev, 0);
  165. if (!ptd->hw_base) {
  166. err = -ENOMEM;
  167. dev_err(&pdev->dev, "failed to map mem base\n");
  168. goto error_release;
  169. }
  170. /* Check if BIOS has already enabled thermal sensor */
  171. if (WPT_TSEL_ETS & readb(ptd->hw_base + WPT_TSEL)) {
  172. ptd->bios_enabled = true;
  173. goto read_trips;
  174. }
  175. tsel = readb(ptd->hw_base + WPT_TSEL);
  176. /*
  177. * When TSEL's Policy Lock-Down bit is 1, TSEL become RO.
  178. * If so, thermal sensor cannot enable. Bail out.
  179. */
  180. if (tsel & WPT_TSEL_PLDB) {
  181. dev_err(&ptd->pdev->dev, "Sensor can't be enabled\n");
  182. err = -ENODEV;
  183. goto error_cleanup;
  184. }
  185. writeb(tsel|WPT_TSEL_ETS, ptd->hw_base + WPT_TSEL);
  186. if (!(WPT_TSEL_ETS & readb(ptd->hw_base + WPT_TSEL))) {
  187. dev_err(&ptd->pdev->dev, "Sensor can't be enabled\n");
  188. err = -ENODEV;
  189. goto error_cleanup;
  190. }
  191. read_trips:
  192. trip_temp = readw(ptd->hw_base + WPT_CTT);
  193. trip_temp &= 0x1FF;
  194. if (trip_temp) {
  195. ptd_trips[nr_trips].temperature = GET_WPT_TEMP(trip_temp);
  196. ptd_trips[nr_trips++].type = THERMAL_TRIP_CRITICAL;
  197. }
  198. trip_temp = readw(ptd->hw_base + WPT_PHL);
  199. trip_temp &= 0x1FF;
  200. if (trip_temp) {
  201. ptd_trips[nr_trips].temperature = GET_WPT_TEMP(trip_temp);
  202. ptd_trips[nr_trips++].type = THERMAL_TRIP_HOT;
  203. }
  204. nr_trips += pch_wpt_add_acpi_psv_trip(ptd, &ptd_trips[nr_trips]);
  205. ptd->tzd = thermal_zone_device_register_with_trips(board_names[board_id],
  206. ptd_trips, nr_trips,
  207. ptd, &tzd_ops,
  208. NULL, 0, 0);
  209. if (IS_ERR(ptd->tzd)) {
  210. dev_err(&pdev->dev, "Failed to register thermal zone %s\n",
  211. board_names[board_id]);
  212. err = PTR_ERR(ptd->tzd);
  213. goto error_cleanup;
  214. }
  215. err = thermal_zone_device_enable(ptd->tzd);
  216. if (err)
  217. goto err_unregister;
  218. return 0;
  219. err_unregister:
  220. thermal_zone_device_unregister(ptd->tzd);
  221. error_cleanup:
  222. iounmap(ptd->hw_base);
  223. error_release:
  224. pci_release_regions(pdev);
  225. error_disable:
  226. pci_disable_device(pdev);
  227. dev_err(&pdev->dev, "pci device failed to probe\n");
  228. return err;
  229. }
  230. static void intel_pch_thermal_remove(struct pci_dev *pdev)
  231. {
  232. struct pch_thermal_device *ptd = pci_get_drvdata(pdev);
  233. thermal_zone_device_unregister(ptd->tzd);
  234. iounmap(ptd->hw_base);
  235. pci_release_regions(pdev);
  236. pci_disable_device(pdev);
  237. }
  238. static int intel_pch_thermal_suspend_noirq(struct device *device)
  239. {
  240. struct pch_thermal_device *ptd = dev_get_drvdata(device);
  241. u16 pch_thr_temp, pch_cur_temp;
  242. int pch_delay_cnt = 0;
  243. u8 tsel;
  244. /* Shutdown the thermal sensor if it is not enabled by BIOS */
  245. if (!ptd->bios_enabled) {
  246. tsel = readb(ptd->hw_base + WPT_TSEL);
  247. writeb(tsel & 0xFE, ptd->hw_base + WPT_TSEL);
  248. return 0;
  249. }
  250. /* Do not check temperature if it is not s2idle */
  251. if (pm_suspend_via_firmware())
  252. return 0;
  253. /* Get the PCH temperature threshold value */
  254. pch_thr_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TSPM));
  255. /* Get the PCH current temperature value */
  256. pch_cur_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP));
  257. if (pch_cur_temp >= pch_thr_temp)
  258. dev_warn(&ptd->pdev->dev,
  259. "CPU-PCH current temp [%dC] higher than the threshold temp [%dC], S0ix might fail. Start cooling...\n",
  260. pch_cur_temp, pch_thr_temp);
  261. /*
  262. * If current PCH temperature is higher than configured PCH threshold
  263. * value, run some delay loop with sleep to let the current temperature
  264. * go down below the threshold value which helps to allow system enter
  265. * lower power S0ix suspend state. Even after delay loop if PCH current
  266. * temperature stays above threshold, notify the warning message
  267. * which helps to indentify the reason why S0ix entry was rejected.
  268. */
  269. while (pch_delay_cnt < delay_cnt) {
  270. if (pch_cur_temp < pch_thr_temp)
  271. break;
  272. if (pm_wakeup_pending()) {
  273. dev_warn(&ptd->pdev->dev, "Wakeup event detected, abort cooling\n");
  274. return 0;
  275. }
  276. pch_delay_cnt++;
  277. dev_dbg(&ptd->pdev->dev,
  278. "CPU-PCH current temp [%dC] higher than the threshold temp [%dC], sleep %d times for %d ms duration\n",
  279. pch_cur_temp, pch_thr_temp, pch_delay_cnt, delay_timeout);
  280. msleep(delay_timeout);
  281. /* Read the PCH current temperature for next cycle. */
  282. pch_cur_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP));
  283. }
  284. if (pch_cur_temp >= pch_thr_temp)
  285. dev_warn(&ptd->pdev->dev,
  286. "CPU-PCH is hot [%dC] after %d ms delay. S0ix might fail\n",
  287. pch_cur_temp, pch_delay_cnt * delay_timeout);
  288. else {
  289. if (pch_delay_cnt)
  290. dev_info(&ptd->pdev->dev,
  291. "CPU-PCH is cool [%dC] after %d ms delay\n",
  292. pch_cur_temp, pch_delay_cnt * delay_timeout);
  293. else
  294. dev_info(&ptd->pdev->dev,
  295. "CPU-PCH is cool [%dC]\n",
  296. pch_cur_temp);
  297. }
  298. return 0;
  299. }
  300. static int intel_pch_thermal_resume(struct device *device)
  301. {
  302. struct pch_thermal_device *ptd = dev_get_drvdata(device);
  303. u8 tsel;
  304. if (ptd->bios_enabled)
  305. return 0;
  306. tsel = readb(ptd->hw_base + WPT_TSEL);
  307. writeb(tsel | WPT_TSEL_ETS, ptd->hw_base + WPT_TSEL);
  308. return 0;
  309. }
  310. static const struct pci_device_id intel_pch_thermal_id[] = {
  311. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_HSW_1),
  312. .driver_data = PCH_BOARD_HSW, },
  313. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_HSW_2),
  314. .driver_data = PCH_BOARD_HSW, },
  315. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_WPT),
  316. .driver_data = PCH_BOARD_WPT, },
  317. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_SKL),
  318. .driver_data = PCH_BOARD_SKL, },
  319. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_SKL_H),
  320. .driver_data = PCH_BOARD_SKL, },
  321. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CNL),
  322. .driver_data = PCH_BOARD_CNL, },
  323. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CNL_H),
  324. .driver_data = PCH_BOARD_CNL, },
  325. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CNL_LP),
  326. .driver_data = PCH_BOARD_CNL, },
  327. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CML_H),
  328. .driver_data = PCH_BOARD_CML, },
  329. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_LWB),
  330. .driver_data = PCH_BOARD_LWB, },
  331. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_WBG),
  332. .driver_data = PCH_BOARD_WBG, },
  333. { 0, },
  334. };
  335. MODULE_DEVICE_TABLE(pci, intel_pch_thermal_id);
  336. static const struct dev_pm_ops intel_pch_pm_ops = {
  337. .suspend_noirq = intel_pch_thermal_suspend_noirq,
  338. .resume = intel_pch_thermal_resume,
  339. };
  340. static struct pci_driver intel_pch_thermal_driver = {
  341. .name = "intel_pch_thermal",
  342. .id_table = intel_pch_thermal_id,
  343. .probe = intel_pch_thermal_probe,
  344. .remove = intel_pch_thermal_remove,
  345. .driver.pm = &intel_pch_pm_ops,
  346. };
  347. module_pci_driver(intel_pch_thermal_driver);
  348. MODULE_LICENSE("GPL v2");
  349. MODULE_DESCRIPTION("Intel PCH Thermal driver");