intel_bxt_pmic_thermal.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel Broxton PMIC thermal driver
  4. *
  5. * Copyright (C) 2016 Intel Corporation. All rights reserved.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/kernel.h>
  9. #include <linux/slab.h>
  10. #include <linux/delay.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/device.h>
  13. #include <linux/thermal.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/sched.h>
  16. #include <linux/mfd/intel_soc_pmic.h>
  17. #define BXTWC_THRM0IRQ 0x4E04
  18. #define BXTWC_THRM1IRQ 0x4E05
  19. #define BXTWC_THRM2IRQ 0x4E06
  20. #define BXTWC_MTHRM0IRQ 0x4E12
  21. #define BXTWC_MTHRM1IRQ 0x4E13
  22. #define BXTWC_MTHRM2IRQ 0x4E14
  23. #define BXTWC_STHRM0IRQ 0x4F19
  24. #define BXTWC_STHRM1IRQ 0x4F1A
  25. #define BXTWC_STHRM2IRQ 0x4F1B
  26. struct trip_config_map {
  27. u16 irq_reg;
  28. u16 irq_en;
  29. u16 evt_stat;
  30. u8 irq_mask;
  31. u8 irq_en_mask;
  32. u8 evt_mask;
  33. u8 trip_num;
  34. };
  35. struct thermal_irq_map {
  36. char handle[20];
  37. int num_trips;
  38. const struct trip_config_map *trip_config;
  39. };
  40. struct pmic_thermal_data {
  41. const struct thermal_irq_map *maps;
  42. int num_maps;
  43. };
  44. static const struct trip_config_map bxtwc_str0_trip_config[] = {
  45. {
  46. .irq_reg = BXTWC_THRM0IRQ,
  47. .irq_mask = 0x01,
  48. .irq_en = BXTWC_MTHRM0IRQ,
  49. .irq_en_mask = 0x01,
  50. .evt_stat = BXTWC_STHRM0IRQ,
  51. .evt_mask = 0x01,
  52. .trip_num = 0
  53. },
  54. {
  55. .irq_reg = BXTWC_THRM0IRQ,
  56. .irq_mask = 0x10,
  57. .irq_en = BXTWC_MTHRM0IRQ,
  58. .irq_en_mask = 0x10,
  59. .evt_stat = BXTWC_STHRM0IRQ,
  60. .evt_mask = 0x10,
  61. .trip_num = 1
  62. }
  63. };
  64. static const struct trip_config_map bxtwc_str1_trip_config[] = {
  65. {
  66. .irq_reg = BXTWC_THRM0IRQ,
  67. .irq_mask = 0x02,
  68. .irq_en = BXTWC_MTHRM0IRQ,
  69. .irq_en_mask = 0x02,
  70. .evt_stat = BXTWC_STHRM0IRQ,
  71. .evt_mask = 0x02,
  72. .trip_num = 0
  73. },
  74. {
  75. .irq_reg = BXTWC_THRM0IRQ,
  76. .irq_mask = 0x20,
  77. .irq_en = BXTWC_MTHRM0IRQ,
  78. .irq_en_mask = 0x20,
  79. .evt_stat = BXTWC_STHRM0IRQ,
  80. .evt_mask = 0x20,
  81. .trip_num = 1
  82. },
  83. };
  84. static const struct trip_config_map bxtwc_str2_trip_config[] = {
  85. {
  86. .irq_reg = BXTWC_THRM0IRQ,
  87. .irq_mask = 0x04,
  88. .irq_en = BXTWC_MTHRM0IRQ,
  89. .irq_en_mask = 0x04,
  90. .evt_stat = BXTWC_STHRM0IRQ,
  91. .evt_mask = 0x04,
  92. .trip_num = 0
  93. },
  94. {
  95. .irq_reg = BXTWC_THRM0IRQ,
  96. .irq_mask = 0x40,
  97. .irq_en = BXTWC_MTHRM0IRQ,
  98. .irq_en_mask = 0x40,
  99. .evt_stat = BXTWC_STHRM0IRQ,
  100. .evt_mask = 0x40,
  101. .trip_num = 1
  102. },
  103. };
  104. static const struct trip_config_map bxtwc_str3_trip_config[] = {
  105. {
  106. .irq_reg = BXTWC_THRM2IRQ,
  107. .irq_mask = 0x10,
  108. .irq_en = BXTWC_MTHRM2IRQ,
  109. .irq_en_mask = 0x10,
  110. .evt_stat = BXTWC_STHRM2IRQ,
  111. .evt_mask = 0x10,
  112. .trip_num = 0
  113. },
  114. };
  115. static const struct thermal_irq_map bxtwc_thermal_irq_map[] = {
  116. {
  117. .handle = "STR0",
  118. .trip_config = bxtwc_str0_trip_config,
  119. .num_trips = ARRAY_SIZE(bxtwc_str0_trip_config),
  120. },
  121. {
  122. .handle = "STR1",
  123. .trip_config = bxtwc_str1_trip_config,
  124. .num_trips = ARRAY_SIZE(bxtwc_str1_trip_config),
  125. },
  126. {
  127. .handle = "STR2",
  128. .trip_config = bxtwc_str2_trip_config,
  129. .num_trips = ARRAY_SIZE(bxtwc_str2_trip_config),
  130. },
  131. {
  132. .handle = "STR3",
  133. .trip_config = bxtwc_str3_trip_config,
  134. .num_trips = ARRAY_SIZE(bxtwc_str3_trip_config),
  135. },
  136. };
  137. static const struct pmic_thermal_data bxtwc_thermal_data = {
  138. .maps = bxtwc_thermal_irq_map,
  139. .num_maps = ARRAY_SIZE(bxtwc_thermal_irq_map),
  140. };
  141. static irqreturn_t pmic_thermal_irq_handler(int irq, void *data)
  142. {
  143. struct platform_device *pdev = data;
  144. struct thermal_zone_device *tzd;
  145. struct pmic_thermal_data *td;
  146. struct intel_soc_pmic *pmic;
  147. struct regmap *regmap;
  148. u8 reg_val, mask, irq_stat;
  149. u16 reg, evt_stat_reg;
  150. int i, j, ret;
  151. pmic = dev_get_drvdata(pdev->dev.parent);
  152. regmap = pmic->regmap;
  153. td = (struct pmic_thermal_data *)
  154. platform_get_device_id(pdev)->driver_data;
  155. /* Resolve thermal irqs */
  156. for (i = 0; i < td->num_maps; i++) {
  157. for (j = 0; j < td->maps[i].num_trips; j++) {
  158. reg = td->maps[i].trip_config[j].irq_reg;
  159. mask = td->maps[i].trip_config[j].irq_mask;
  160. /*
  161. * Read the irq register to resolve whether the
  162. * interrupt was triggered for this sensor
  163. */
  164. if (regmap_read(regmap, reg, &ret))
  165. return IRQ_HANDLED;
  166. reg_val = (u8)ret;
  167. irq_stat = ((u8)ret & mask);
  168. if (!irq_stat)
  169. continue;
  170. /*
  171. * Read the status register to find out what
  172. * event occurred i.e a high or a low
  173. */
  174. evt_stat_reg = td->maps[i].trip_config[j].evt_stat;
  175. if (regmap_read(regmap, evt_stat_reg, &ret))
  176. return IRQ_HANDLED;
  177. tzd = thermal_zone_get_zone_by_name(td->maps[i].handle);
  178. if (!IS_ERR(tzd))
  179. thermal_zone_device_update(tzd,
  180. THERMAL_EVENT_UNSPECIFIED);
  181. /* Clear the appropriate irq */
  182. regmap_write(regmap, reg, reg_val & mask);
  183. }
  184. }
  185. return IRQ_HANDLED;
  186. }
  187. static int pmic_thermal_probe(struct platform_device *pdev)
  188. {
  189. struct regmap_irq_chip_data *regmap_irq_chip;
  190. struct pmic_thermal_data *thermal_data;
  191. int ret, irq, virq, i, j, pmic_irq_count;
  192. struct intel_soc_pmic *pmic;
  193. struct regmap *regmap;
  194. struct device *dev;
  195. u16 reg;
  196. u8 mask;
  197. dev = &pdev->dev;
  198. pmic = dev_get_drvdata(pdev->dev.parent);
  199. if (!pmic) {
  200. dev_err(dev, "Failed to get struct intel_soc_pmic pointer\n");
  201. return -ENODEV;
  202. }
  203. thermal_data = (struct pmic_thermal_data *)
  204. platform_get_device_id(pdev)->driver_data;
  205. if (!thermal_data) {
  206. dev_err(dev, "No thermal data initialized!!\n");
  207. return -ENODEV;
  208. }
  209. regmap = pmic->regmap;
  210. regmap_irq_chip = pmic->irq_chip_data;
  211. pmic_irq_count = 0;
  212. while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
  213. virq = regmap_irq_get_virq(regmap_irq_chip, irq);
  214. if (virq < 0) {
  215. dev_err(dev, "failed to get virq by irq %d\n", irq);
  216. return virq;
  217. }
  218. ret = devm_request_threaded_irq(&pdev->dev, virq,
  219. NULL, pmic_thermal_irq_handler,
  220. IRQF_ONESHOT, "pmic_thermal", pdev);
  221. if (ret) {
  222. dev_err(dev, "request irq(%d) failed: %d\n", virq, ret);
  223. return ret;
  224. }
  225. pmic_irq_count++;
  226. }
  227. /* Enable thermal interrupts */
  228. for (i = 0; i < thermal_data->num_maps; i++) {
  229. for (j = 0; j < thermal_data->maps[i].num_trips; j++) {
  230. reg = thermal_data->maps[i].trip_config[j].irq_en;
  231. mask = thermal_data->maps[i].trip_config[j].irq_en_mask;
  232. ret = regmap_update_bits(regmap, reg, mask, 0x00);
  233. if (ret)
  234. return ret;
  235. }
  236. }
  237. return 0;
  238. }
  239. static const struct platform_device_id pmic_thermal_id_table[] = {
  240. {
  241. .name = "bxt_wcove_thermal",
  242. .driver_data = (kernel_ulong_t)&bxtwc_thermal_data,
  243. },
  244. {},
  245. };
  246. static struct platform_driver pmic_thermal_driver = {
  247. .probe = pmic_thermal_probe,
  248. .driver = {
  249. .name = "pmic_thermal",
  250. },
  251. .id_table = pmic_thermal_id_table,
  252. };
  253. MODULE_DEVICE_TABLE(platform, pmic_thermal_id_table);
  254. module_platform_driver(pmic_thermal_driver);
  255. MODULE_AUTHOR("Yegnesh S Iyer <yegnesh.s.iyer@intel.com>");
  256. MODULE_DESCRIPTION("Intel Broxton PMIC Thermal Driver");
  257. MODULE_LICENSE("GPL v2");