cadence_master.c 71 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
  2. // Copyright(c) 2015-17 Intel Corporation.
  3. /*
  4. * Cadence SoundWire Master module
  5. * Used by Master driver
  6. */
  7. #include <linux/cleanup.h>
  8. #include <linux/crc8.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/debugfs.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/soundwire/sdw_registers.h>
  18. #include <linux/soundwire/sdw.h>
  19. #include <sound/pcm_params.h>
  20. #include <sound/soc.h>
  21. #include <linux/workqueue.h>
  22. #include "bus.h"
  23. #include "cadence_master.h"
  24. static int interrupt_mask;
  25. module_param_named(cnds_mcp_int_mask, interrupt_mask, int, 0444);
  26. MODULE_PARM_DESC(cdns_mcp_int_mask, "Cadence MCP IntMask");
  27. #define CDNS_MCP_CONFIG 0x0
  28. #define CDNS_MCP_CONFIG_BUS_REL BIT(6)
  29. #define CDNS_IP_MCP_CONFIG 0x0 /* IP offset added at run-time */
  30. #define CDNS_IP_MCP_CONFIG_MCMD_RETRY GENMASK(27, 24)
  31. #define CDNS_IP_MCP_CONFIG_MPREQ_DELAY GENMASK(20, 16)
  32. #define CDNS_IP_MCP_CONFIG_MMASTER BIT(7)
  33. #define CDNS_IP_MCP_CONFIG_SNIFFER BIT(5)
  34. #define CDNS_IP_MCP_CONFIG_CMD BIT(3)
  35. #define CDNS_IP_MCP_CONFIG_OP GENMASK(2, 0)
  36. #define CDNS_IP_MCP_CONFIG_OP_NORMAL 0
  37. #define CDNS_MCP_CONTROL 0x4
  38. #define CDNS_MCP_CONTROL_CMD_RST BIT(7)
  39. #define CDNS_MCP_CONTROL_SOFT_RST BIT(6)
  40. #define CDNS_MCP_CONTROL_HW_RST BIT(4)
  41. #define CDNS_MCP_CONTROL_CLK_STOP_CLR BIT(2)
  42. #define CDNS_IP_MCP_CONTROL 0x4 /* IP offset added at run-time */
  43. #define CDNS_IP_MCP_CONTROL_RST_DELAY GENMASK(10, 8)
  44. #define CDNS_IP_MCP_CONTROL_SW_RST BIT(5)
  45. #define CDNS_IP_MCP_CONTROL_CLK_PAUSE BIT(3)
  46. #define CDNS_IP_MCP_CONTROL_CMD_ACCEPT BIT(1)
  47. #define CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP BIT(0)
  48. #define CDNS_IP_MCP_CMDCTRL 0x8 /* IP offset added at run-time */
  49. #define CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR BIT(2)
  50. #define CDNS_MCP_SSPSTAT 0xC
  51. #define CDNS_MCP_FRAME_SHAPE 0x10
  52. #define CDNS_MCP_FRAME_SHAPE_INIT 0x14
  53. #define CDNS_MCP_FRAME_SHAPE_COL_MASK GENMASK(2, 0)
  54. #define CDNS_MCP_FRAME_SHAPE_ROW_MASK GENMASK(7, 3)
  55. #define CDNS_MCP_CONFIG_UPDATE 0x18
  56. #define CDNS_MCP_CONFIG_UPDATE_BIT BIT(0)
  57. #define CDNS_MCP_PHYCTRL 0x1C
  58. #define CDNS_MCP_SSP_CTRL0 0x20
  59. #define CDNS_MCP_SSP_CTRL1 0x28
  60. #define CDNS_MCP_CLK_CTRL0 0x30
  61. #define CDNS_MCP_CLK_CTRL1 0x38
  62. #define CDNS_MCP_CLK_MCLKD_MASK GENMASK(7, 0)
  63. #define CDNS_MCP_STAT 0x40
  64. #define CDNS_MCP_STAT_ACTIVE_BANK BIT(20)
  65. #define CDNS_MCP_STAT_CLK_STOP BIT(16)
  66. #define CDNS_MCP_INTSTAT 0x44
  67. #define CDNS_MCP_INTMASK 0x48
  68. #define CDNS_MCP_INT_IRQ BIT(31)
  69. #define CDNS_MCP_INT_RESERVED1 GENMASK(30, 17)
  70. #define CDNS_MCP_INT_WAKEUP BIT(16)
  71. #define CDNS_MCP_INT_SLAVE_RSVD BIT(15)
  72. #define CDNS_MCP_INT_SLAVE_ALERT BIT(14)
  73. #define CDNS_MCP_INT_SLAVE_ATTACH BIT(13)
  74. #define CDNS_MCP_INT_SLAVE_NATTACH BIT(12)
  75. #define CDNS_MCP_INT_SLAVE_MASK GENMASK(15, 12)
  76. #define CDNS_MCP_INT_DPINT BIT(11)
  77. #define CDNS_MCP_INT_CTRL_CLASH BIT(10)
  78. #define CDNS_MCP_INT_DATA_CLASH BIT(9)
  79. #define CDNS_MCP_INT_PARITY BIT(8)
  80. #define CDNS_MCP_INT_CMD_ERR BIT(7)
  81. #define CDNS_MCP_INT_RESERVED2 GENMASK(6, 4)
  82. #define CDNS_MCP_INT_RX_NE BIT(3)
  83. #define CDNS_MCP_INT_RX_WL BIT(2)
  84. #define CDNS_MCP_INT_TXE BIT(1)
  85. #define CDNS_MCP_INT_TXF BIT(0)
  86. #define CDNS_MCP_INT_RESERVED (CDNS_MCP_INT_RESERVED1 | CDNS_MCP_INT_RESERVED2)
  87. #define CDNS_MCP_INTSET 0x4C
  88. #define CDNS_MCP_SLAVE_STAT 0x50
  89. #define CDNS_MCP_SLAVE_STAT_MASK GENMASK(1, 0)
  90. #define CDNS_MCP_SLAVE_INTSTAT0 0x54
  91. #define CDNS_MCP_SLAVE_INTSTAT1 0x58
  92. #define CDNS_MCP_SLAVE_INTSTAT_NPRESENT BIT(0)
  93. #define CDNS_MCP_SLAVE_INTSTAT_ATTACHED BIT(1)
  94. #define CDNS_MCP_SLAVE_INTSTAT_ALERT BIT(2)
  95. #define CDNS_MCP_SLAVE_INTSTAT_RESERVED BIT(3)
  96. #define CDNS_MCP_SLAVE_STATUS_BITS GENMASK(3, 0)
  97. #define CDNS_MCP_SLAVE_STATUS_NUM 4
  98. #define CDNS_MCP_SLAVE_INTMASK0 0x5C
  99. #define CDNS_MCP_SLAVE_INTMASK1 0x60
  100. #define CDNS_MCP_SLAVE_INTMASK0_MASK GENMASK(31, 0)
  101. #define CDNS_MCP_SLAVE_INTMASK1_MASK GENMASK(15, 0)
  102. #define CDNS_MCP_PORT_INTSTAT 0x64
  103. #define CDNS_MCP_PDI_STAT 0x6C
  104. #define CDNS_MCP_FIFOLEVEL 0x78
  105. #define CDNS_MCP_FIFOSTAT 0x7C
  106. #define CDNS_MCP_RX_FIFO_AVAIL GENMASK(5, 0)
  107. #define CDNS_IP_MCP_CMD_BASE 0x80 /* IP offset added at run-time */
  108. #define CDNS_IP_MCP_RESP_BASE 0x80 /* IP offset added at run-time */
  109. /* FIFO can hold 8 commands */
  110. #define CDNS_MCP_CMD_LEN 8
  111. #define CDNS_MCP_CMD_WORD_LEN 0x4
  112. #define CDNS_MCP_CMD_SSP_TAG BIT(31)
  113. #define CDNS_MCP_CMD_COMMAND GENMASK(30, 28)
  114. #define CDNS_MCP_CMD_DEV_ADDR GENMASK(27, 24)
  115. #define CDNS_MCP_CMD_REG_ADDR GENMASK(23, 8)
  116. #define CDNS_MCP_CMD_REG_DATA GENMASK(7, 0)
  117. #define CDNS_MCP_CMD_READ 2
  118. #define CDNS_MCP_CMD_WRITE 3
  119. #define CDNS_MCP_RESP_RDATA GENMASK(15, 8)
  120. #define CDNS_MCP_RESP_ACK BIT(0)
  121. #define CDNS_MCP_RESP_NACK BIT(1)
  122. #define CDNS_DP_SIZE 128
  123. #define CDNS_DPN_B0_CONFIG(n) (0x100 + CDNS_DP_SIZE * (n))
  124. #define CDNS_DPN_B0_CH_EN(n) (0x104 + CDNS_DP_SIZE * (n))
  125. #define CDNS_DPN_B0_SAMPLE_CTRL(n) (0x108 + CDNS_DP_SIZE * (n))
  126. #define CDNS_DPN_B0_OFFSET_CTRL(n) (0x10C + CDNS_DP_SIZE * (n))
  127. #define CDNS_DPN_B0_HCTRL(n) (0x110 + CDNS_DP_SIZE * (n))
  128. #define CDNS_DPN_B0_ASYNC_CTRL(n) (0x114 + CDNS_DP_SIZE * (n))
  129. #define CDNS_DPN_B1_CONFIG(n) (0x118 + CDNS_DP_SIZE * (n))
  130. #define CDNS_DPN_B1_CH_EN(n) (0x11C + CDNS_DP_SIZE * (n))
  131. #define CDNS_DPN_B1_SAMPLE_CTRL(n) (0x120 + CDNS_DP_SIZE * (n))
  132. #define CDNS_DPN_B1_OFFSET_CTRL(n) (0x124 + CDNS_DP_SIZE * (n))
  133. #define CDNS_DPN_B1_HCTRL(n) (0x128 + CDNS_DP_SIZE * (n))
  134. #define CDNS_DPN_B1_ASYNC_CTRL(n) (0x12C + CDNS_DP_SIZE * (n))
  135. #define CDNS_DPN_CONFIG_BPM BIT(18)
  136. #define CDNS_DPN_CONFIG_BGC GENMASK(17, 16)
  137. #define CDNS_DPN_CONFIG_WL GENMASK(12, 8)
  138. #define CDNS_DPN_CONFIG_PORT_DAT GENMASK(3, 2)
  139. #define CDNS_DPN_CONFIG_PORT_FLOW GENMASK(1, 0)
  140. #define CDNS_DPN_SAMPLE_CTRL_SI GENMASK(15, 0)
  141. #define CDNS_DPN_OFFSET_CTRL_1 GENMASK(7, 0)
  142. #define CDNS_DPN_OFFSET_CTRL_2 GENMASK(15, 8)
  143. #define CDNS_DPN_HCTRL_HSTOP GENMASK(3, 0)
  144. #define CDNS_DPN_HCTRL_HSTART GENMASK(7, 4)
  145. #define CDNS_DPN_HCTRL_LCTRL GENMASK(10, 8)
  146. #define CDNS_PORTCTRL 0x130
  147. #define CDNS_PORTCTRL_TEST_FAILED BIT(1)
  148. #define CDNS_PORTCTRL_DIRN BIT(7)
  149. #define CDNS_PORTCTRL_BANK_INVERT BIT(8)
  150. #define CDNS_PORTCTRL_BULK_ENABLE BIT(16)
  151. #define CDNS_PORT_OFFSET 0x80
  152. #define CDNS_PDI_CONFIG(n) (0x1100 + (n) * 16)
  153. #define CDNS_PDI_CONFIG_SOFT_RESET BIT(24)
  154. #define CDNS_PDI_CONFIG_CHANNEL GENMASK(15, 8)
  155. #define CDNS_PDI_CONFIG_PORT GENMASK(4, 0)
  156. /* Driver defaults */
  157. #define CDNS_TX_TIMEOUT 500
  158. #define CDNS_SCP_RX_FIFOLEVEL 0x2
  159. /*
  160. * register accessor helpers
  161. */
  162. static inline u32 cdns_readl(struct sdw_cdns *cdns, int offset)
  163. {
  164. return readl(cdns->registers + offset);
  165. }
  166. static inline void cdns_writel(struct sdw_cdns *cdns, int offset, u32 value)
  167. {
  168. writel(value, cdns->registers + offset);
  169. }
  170. static inline u32 cdns_ip_readl(struct sdw_cdns *cdns, int offset)
  171. {
  172. return cdns_readl(cdns, cdns->ip_offset + offset);
  173. }
  174. static inline void cdns_ip_writel(struct sdw_cdns *cdns, int offset, u32 value)
  175. {
  176. return cdns_writel(cdns, cdns->ip_offset + offset, value);
  177. }
  178. static inline void cdns_updatel(struct sdw_cdns *cdns,
  179. int offset, u32 mask, u32 val)
  180. {
  181. u32 tmp;
  182. tmp = cdns_readl(cdns, offset);
  183. tmp = (tmp & ~mask) | val;
  184. cdns_writel(cdns, offset, tmp);
  185. }
  186. static inline void cdns_ip_updatel(struct sdw_cdns *cdns,
  187. int offset, u32 mask, u32 val)
  188. {
  189. cdns_updatel(cdns, cdns->ip_offset + offset, mask, val);
  190. }
  191. static int cdns_set_wait(struct sdw_cdns *cdns, int offset, u32 mask, u32 value)
  192. {
  193. int timeout = 10;
  194. u32 reg_read;
  195. /* Wait for bit to be set */
  196. do {
  197. reg_read = readl(cdns->registers + offset);
  198. if ((reg_read & mask) == value)
  199. return 0;
  200. timeout--;
  201. usleep_range(50, 100);
  202. } while (timeout != 0);
  203. return -ETIMEDOUT;
  204. }
  205. static int cdns_clear_bit(struct sdw_cdns *cdns, int offset, u32 value)
  206. {
  207. writel(value, cdns->registers + offset);
  208. /* Wait for bit to be self cleared */
  209. return cdns_set_wait(cdns, offset, value, 0);
  210. }
  211. /*
  212. * all changes to the MCP_CONFIG, MCP_CONTROL, MCP_CMDCTRL and MCP_PHYCTRL
  213. * need to be confirmed with a write to MCP_CONFIG_UPDATE
  214. */
  215. static int cdns_config_update(struct sdw_cdns *cdns)
  216. {
  217. int ret;
  218. if (sdw_cdns_is_clock_stop(cdns)) {
  219. dev_err(cdns->dev, "Cannot program MCP_CONFIG_UPDATE in ClockStopMode\n");
  220. return -EINVAL;
  221. }
  222. ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE,
  223. CDNS_MCP_CONFIG_UPDATE_BIT);
  224. if (ret < 0)
  225. dev_err(cdns->dev, "Config update timedout\n");
  226. return ret;
  227. }
  228. /**
  229. * sdw_cdns_config_update() - Update configurations
  230. * @cdns: Cadence instance
  231. */
  232. void sdw_cdns_config_update(struct sdw_cdns *cdns)
  233. {
  234. /* commit changes */
  235. cdns_writel(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT);
  236. }
  237. EXPORT_SYMBOL(sdw_cdns_config_update);
  238. /**
  239. * sdw_cdns_config_update_set_wait() - wait until configuration update bit is self-cleared
  240. * @cdns: Cadence instance
  241. */
  242. int sdw_cdns_config_update_set_wait(struct sdw_cdns *cdns)
  243. {
  244. /* the hardware recommendation is to wait at least 300us */
  245. return cdns_set_wait(cdns, CDNS_MCP_CONFIG_UPDATE,
  246. CDNS_MCP_CONFIG_UPDATE_BIT, 0);
  247. }
  248. EXPORT_SYMBOL(sdw_cdns_config_update_set_wait);
  249. /*
  250. * debugfs
  251. */
  252. #ifdef CONFIG_DEBUG_FS
  253. #define RD_BUF (2 * PAGE_SIZE)
  254. static ssize_t cdns_sprintf(struct sdw_cdns *cdns,
  255. char *buf, size_t pos, unsigned int reg)
  256. {
  257. return scnprintf(buf + pos, RD_BUF - pos,
  258. "%4x\t%8x\n", reg, cdns_readl(cdns, reg));
  259. }
  260. static int cdns_reg_show(struct seq_file *s, void *data)
  261. {
  262. struct sdw_cdns *cdns = s->private;
  263. ssize_t ret;
  264. int num_ports;
  265. int i, j;
  266. char *buf __free(kfree) = kzalloc(RD_BUF, GFP_KERNEL);
  267. if (!buf)
  268. return -ENOMEM;
  269. ret = scnprintf(buf, RD_BUF, "Register Value\n");
  270. ret += scnprintf(buf + ret, RD_BUF - ret, "\nMCP Registers\n");
  271. /* 8 MCP registers */
  272. for (i = CDNS_MCP_CONFIG; i <= CDNS_MCP_PHYCTRL; i += sizeof(u32))
  273. ret += cdns_sprintf(cdns, buf, ret, i);
  274. ret += scnprintf(buf + ret, RD_BUF - ret,
  275. "\nStatus & Intr Registers\n");
  276. /* 13 Status & Intr registers (offsets 0x70 and 0x74 not defined) */
  277. for (i = CDNS_MCP_STAT; i <= CDNS_MCP_FIFOSTAT; i += sizeof(u32))
  278. ret += cdns_sprintf(cdns, buf, ret, i);
  279. ret += scnprintf(buf + ret, RD_BUF - ret,
  280. "\nSSP & Clk ctrl Registers\n");
  281. ret += cdns_sprintf(cdns, buf, ret, CDNS_MCP_SSP_CTRL0);
  282. ret += cdns_sprintf(cdns, buf, ret, CDNS_MCP_SSP_CTRL1);
  283. ret += cdns_sprintf(cdns, buf, ret, CDNS_MCP_CLK_CTRL0);
  284. ret += cdns_sprintf(cdns, buf, ret, CDNS_MCP_CLK_CTRL1);
  285. ret += scnprintf(buf + ret, RD_BUF - ret,
  286. "\nDPn B0 Registers\n");
  287. num_ports = cdns->num_ports;
  288. for (i = 0; i < num_ports; i++) {
  289. ret += scnprintf(buf + ret, RD_BUF - ret,
  290. "\nDP-%d\n", i);
  291. for (j = CDNS_DPN_B0_CONFIG(i);
  292. j < CDNS_DPN_B0_ASYNC_CTRL(i); j += sizeof(u32))
  293. ret += cdns_sprintf(cdns, buf, ret, j);
  294. }
  295. ret += scnprintf(buf + ret, RD_BUF - ret,
  296. "\nDPn B1 Registers\n");
  297. for (i = 0; i < num_ports; i++) {
  298. ret += scnprintf(buf + ret, RD_BUF - ret,
  299. "\nDP-%d\n", i);
  300. for (j = CDNS_DPN_B1_CONFIG(i);
  301. j < CDNS_DPN_B1_ASYNC_CTRL(i); j += sizeof(u32))
  302. ret += cdns_sprintf(cdns, buf, ret, j);
  303. }
  304. ret += scnprintf(buf + ret, RD_BUF - ret,
  305. "\nDPn Control Registers\n");
  306. for (i = 0; i < num_ports; i++)
  307. ret += cdns_sprintf(cdns, buf, ret,
  308. CDNS_PORTCTRL + i * CDNS_PORT_OFFSET);
  309. ret += scnprintf(buf + ret, RD_BUF - ret,
  310. "\nPDIn Config Registers\n");
  311. /* number of PDI and ports is interchangeable */
  312. for (i = 0; i < num_ports; i++)
  313. ret += cdns_sprintf(cdns, buf, ret, CDNS_PDI_CONFIG(i));
  314. seq_printf(s, "%s", buf);
  315. return 0;
  316. }
  317. DEFINE_SHOW_ATTRIBUTE(cdns_reg);
  318. static int cdns_hw_reset(void *data, u64 value)
  319. {
  320. struct sdw_cdns *cdns = data;
  321. int ret;
  322. if (value != 1)
  323. return -EINVAL;
  324. /* Userspace changed the hardware state behind the kernel's back */
  325. add_taint(TAINT_USER, LOCKDEP_STILL_OK);
  326. ret = sdw_cdns_exit_reset(cdns);
  327. dev_dbg(cdns->dev, "link hw_reset done: %d\n", ret);
  328. return ret;
  329. }
  330. DEFINE_DEBUGFS_ATTRIBUTE(cdns_hw_reset_fops, NULL, cdns_hw_reset, "%llu\n");
  331. static int cdns_parity_error_injection(void *data, u64 value)
  332. {
  333. struct sdw_cdns *cdns = data;
  334. struct sdw_bus *bus;
  335. int ret;
  336. if (value != 1)
  337. return -EINVAL;
  338. bus = &cdns->bus;
  339. /*
  340. * Resume Master device. If this results in a bus reset, the
  341. * Slave devices will re-attach and be re-enumerated.
  342. */
  343. ret = pm_runtime_resume_and_get(bus->dev);
  344. if (ret < 0 && ret != -EACCES) {
  345. dev_err_ratelimited(cdns->dev,
  346. "pm_runtime_resume_and_get failed in %s, ret %d\n",
  347. __func__, ret);
  348. return ret;
  349. }
  350. /*
  351. * wait long enough for Slave(s) to be in steady state. This
  352. * does not need to be super precise.
  353. */
  354. msleep(200);
  355. /*
  356. * Take the bus lock here to make sure that any bus transactions
  357. * will be queued while we inject a parity error on a dummy read
  358. */
  359. mutex_lock(&bus->bus_lock);
  360. /* program hardware to inject parity error */
  361. cdns_ip_updatel(cdns, CDNS_IP_MCP_CMDCTRL,
  362. CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR,
  363. CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR);
  364. /* commit changes */
  365. ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT);
  366. if (ret < 0)
  367. goto unlock;
  368. /* do a broadcast dummy read to avoid bus clashes */
  369. ret = sdw_bread_no_pm_unlocked(&cdns->bus, 0xf, SDW_SCP_DEVID_0);
  370. dev_info(cdns->dev, "parity error injection, read: %d\n", ret);
  371. /* program hardware to disable parity error */
  372. cdns_ip_updatel(cdns, CDNS_IP_MCP_CMDCTRL,
  373. CDNS_IP_MCP_CMDCTRL_INSERT_PARITY_ERR,
  374. 0);
  375. /* commit changes */
  376. ret = cdns_clear_bit(cdns, CDNS_MCP_CONFIG_UPDATE, CDNS_MCP_CONFIG_UPDATE_BIT);
  377. if (ret < 0)
  378. goto unlock;
  379. /* Userspace changed the hardware state behind the kernel's back */
  380. add_taint(TAINT_USER, LOCKDEP_STILL_OK);
  381. unlock:
  382. /* Continue bus operation with parity error injection disabled */
  383. mutex_unlock(&bus->bus_lock);
  384. /*
  385. * allow Master device to enter pm_runtime suspend. This may
  386. * also result in Slave devices suspending.
  387. */
  388. pm_runtime_mark_last_busy(bus->dev);
  389. pm_runtime_put_autosuspend(bus->dev);
  390. return 0;
  391. }
  392. DEFINE_DEBUGFS_ATTRIBUTE(cdns_parity_error_fops, NULL,
  393. cdns_parity_error_injection, "%llu\n");
  394. static int cdns_set_pdi_loopback_source(void *data, u64 value)
  395. {
  396. struct sdw_cdns *cdns = data;
  397. unsigned int pdi_out_num = cdns->pcm.num_bd + cdns->pcm.num_out;
  398. if (value > pdi_out_num)
  399. return -EINVAL;
  400. /* Userspace changed the hardware state behind the kernel's back */
  401. add_taint(TAINT_USER, LOCKDEP_STILL_OK);
  402. cdns->pdi_loopback_source = value;
  403. return 0;
  404. }
  405. DEFINE_DEBUGFS_ATTRIBUTE(cdns_pdi_loopback_source_fops, NULL, cdns_set_pdi_loopback_source, "%llu\n");
  406. static int cdns_set_pdi_loopback_target(void *data, u64 value)
  407. {
  408. struct sdw_cdns *cdns = data;
  409. unsigned int pdi_in_num = cdns->pcm.num_bd + cdns->pcm.num_in;
  410. if (value > pdi_in_num)
  411. return -EINVAL;
  412. /* Userspace changed the hardware state behind the kernel's back */
  413. add_taint(TAINT_USER, LOCKDEP_STILL_OK);
  414. cdns->pdi_loopback_target = value;
  415. return 0;
  416. }
  417. DEFINE_DEBUGFS_ATTRIBUTE(cdns_pdi_loopback_target_fops, NULL, cdns_set_pdi_loopback_target, "%llu\n");
  418. /**
  419. * sdw_cdns_debugfs_init() - Cadence debugfs init
  420. * @cdns: Cadence instance
  421. * @root: debugfs root
  422. */
  423. void sdw_cdns_debugfs_init(struct sdw_cdns *cdns, struct dentry *root)
  424. {
  425. debugfs_create_file("cdns-registers", 0400, root, cdns, &cdns_reg_fops);
  426. debugfs_create_file("cdns-hw-reset", 0200, root, cdns,
  427. &cdns_hw_reset_fops);
  428. debugfs_create_file("cdns-parity-error-injection", 0200, root, cdns,
  429. &cdns_parity_error_fops);
  430. cdns->pdi_loopback_source = -1;
  431. cdns->pdi_loopback_target = -1;
  432. debugfs_create_file("cdns-pdi-loopback-source", 0200, root, cdns,
  433. &cdns_pdi_loopback_source_fops);
  434. debugfs_create_file("cdns-pdi-loopback-target", 0200, root, cdns,
  435. &cdns_pdi_loopback_target_fops);
  436. }
  437. EXPORT_SYMBOL_GPL(sdw_cdns_debugfs_init);
  438. #endif /* CONFIG_DEBUG_FS */
  439. /*
  440. * IO Calls
  441. */
  442. static enum sdw_command_response
  443. cdns_fill_msg_resp(struct sdw_cdns *cdns,
  444. struct sdw_msg *msg, int count, int offset)
  445. {
  446. int nack = 0, no_ack = 0;
  447. int i;
  448. /* check message response */
  449. for (i = 0; i < count; i++) {
  450. if (!(cdns->response_buf[i] & CDNS_MCP_RESP_ACK)) {
  451. no_ack = 1;
  452. dev_vdbg(cdns->dev, "Msg Ack not received, cmd %d\n", i);
  453. }
  454. if (cdns->response_buf[i] & CDNS_MCP_RESP_NACK) {
  455. nack = 1;
  456. dev_err_ratelimited(cdns->dev, "Msg NACK received, cmd %d\n", i);
  457. }
  458. }
  459. if (nack) {
  460. dev_err_ratelimited(cdns->dev, "Msg NACKed for Slave %d\n", msg->dev_num);
  461. return SDW_CMD_FAIL;
  462. }
  463. if (no_ack) {
  464. dev_dbg_ratelimited(cdns->dev, "Msg ignored for Slave %d\n", msg->dev_num);
  465. return SDW_CMD_IGNORED;
  466. }
  467. if (msg->flags == SDW_MSG_FLAG_READ) {
  468. /* fill response */
  469. for (i = 0; i < count; i++)
  470. msg->buf[i + offset] = FIELD_GET(CDNS_MCP_RESP_RDATA,
  471. cdns->response_buf[i]);
  472. }
  473. return SDW_CMD_OK;
  474. }
  475. static void cdns_read_response(struct sdw_cdns *cdns)
  476. {
  477. u32 num_resp, cmd_base;
  478. int i;
  479. /* RX_FIFO_AVAIL can be 2 entries more than the FIFO size */
  480. BUILD_BUG_ON(ARRAY_SIZE(cdns->response_buf) < CDNS_MCP_CMD_LEN + 2);
  481. num_resp = cdns_readl(cdns, CDNS_MCP_FIFOSTAT);
  482. num_resp &= CDNS_MCP_RX_FIFO_AVAIL;
  483. if (num_resp > ARRAY_SIZE(cdns->response_buf)) {
  484. dev_warn(cdns->dev, "RX AVAIL %d too long\n", num_resp);
  485. num_resp = ARRAY_SIZE(cdns->response_buf);
  486. }
  487. cmd_base = CDNS_IP_MCP_CMD_BASE;
  488. for (i = 0; i < num_resp; i++) {
  489. cdns->response_buf[i] = cdns_ip_readl(cdns, cmd_base);
  490. cmd_base += CDNS_MCP_CMD_WORD_LEN;
  491. }
  492. }
  493. static enum sdw_command_response
  494. _cdns_xfer_msg(struct sdw_cdns *cdns, struct sdw_msg *msg, int cmd,
  495. int offset, int count, bool defer)
  496. {
  497. unsigned long time;
  498. u32 base, i, data;
  499. u16 addr;
  500. /* Program the watermark level for RX FIFO */
  501. if (cdns->msg_count != count) {
  502. cdns_writel(cdns, CDNS_MCP_FIFOLEVEL, count);
  503. cdns->msg_count = count;
  504. }
  505. base = CDNS_IP_MCP_CMD_BASE;
  506. addr = msg->addr + offset;
  507. for (i = 0; i < count; i++) {
  508. data = FIELD_PREP(CDNS_MCP_CMD_DEV_ADDR, msg->dev_num);
  509. data |= FIELD_PREP(CDNS_MCP_CMD_COMMAND, cmd);
  510. data |= FIELD_PREP(CDNS_MCP_CMD_REG_ADDR, addr);
  511. addr++;
  512. if (msg->flags == SDW_MSG_FLAG_WRITE)
  513. data |= msg->buf[i + offset];
  514. data |= FIELD_PREP(CDNS_MCP_CMD_SSP_TAG, msg->ssp_sync);
  515. cdns_ip_writel(cdns, base, data);
  516. base += CDNS_MCP_CMD_WORD_LEN;
  517. }
  518. if (defer)
  519. return SDW_CMD_OK;
  520. /* wait for timeout or response */
  521. time = wait_for_completion_timeout(&cdns->tx_complete,
  522. msecs_to_jiffies(CDNS_TX_TIMEOUT));
  523. if (!time) {
  524. dev_err(cdns->dev, "IO transfer timed out, cmd %d device %d addr %x len %d\n",
  525. cmd, msg->dev_num, msg->addr, msg->len);
  526. msg->len = 0;
  527. /* Drain anything in the RX_FIFO */
  528. cdns_read_response(cdns);
  529. return SDW_CMD_TIMEOUT;
  530. }
  531. return cdns_fill_msg_resp(cdns, msg, count, offset);
  532. }
  533. static enum sdw_command_response
  534. cdns_program_scp_addr(struct sdw_cdns *cdns, struct sdw_msg *msg)
  535. {
  536. int nack = 0, no_ack = 0;
  537. unsigned long time;
  538. u32 data[2], base;
  539. int i;
  540. /* Program the watermark level for RX FIFO */
  541. if (cdns->msg_count != CDNS_SCP_RX_FIFOLEVEL) {
  542. cdns_writel(cdns, CDNS_MCP_FIFOLEVEL, CDNS_SCP_RX_FIFOLEVEL);
  543. cdns->msg_count = CDNS_SCP_RX_FIFOLEVEL;
  544. }
  545. data[0] = FIELD_PREP(CDNS_MCP_CMD_DEV_ADDR, msg->dev_num);
  546. data[0] |= FIELD_PREP(CDNS_MCP_CMD_COMMAND, 0x3);
  547. data[1] = data[0];
  548. data[0] |= FIELD_PREP(CDNS_MCP_CMD_REG_ADDR, SDW_SCP_ADDRPAGE1);
  549. data[1] |= FIELD_PREP(CDNS_MCP_CMD_REG_ADDR, SDW_SCP_ADDRPAGE2);
  550. data[0] |= msg->addr_page1;
  551. data[1] |= msg->addr_page2;
  552. base = CDNS_IP_MCP_CMD_BASE;
  553. cdns_ip_writel(cdns, base, data[0]);
  554. base += CDNS_MCP_CMD_WORD_LEN;
  555. cdns_ip_writel(cdns, base, data[1]);
  556. time = wait_for_completion_timeout(&cdns->tx_complete,
  557. msecs_to_jiffies(CDNS_TX_TIMEOUT));
  558. if (!time) {
  559. dev_err(cdns->dev, "SCP Msg trf timed out\n");
  560. msg->len = 0;
  561. return SDW_CMD_TIMEOUT;
  562. }
  563. /* check response the writes */
  564. for (i = 0; i < 2; i++) {
  565. if (!(cdns->response_buf[i] & CDNS_MCP_RESP_ACK)) {
  566. no_ack = 1;
  567. dev_err(cdns->dev, "Program SCP Ack not received\n");
  568. if (cdns->response_buf[i] & CDNS_MCP_RESP_NACK) {
  569. nack = 1;
  570. dev_err(cdns->dev, "Program SCP NACK received\n");
  571. }
  572. }
  573. }
  574. /* For NACK, NO ack, don't return err if we are in Broadcast mode */
  575. if (nack) {
  576. dev_err_ratelimited(cdns->dev,
  577. "SCP_addrpage NACKed for Slave %d\n", msg->dev_num);
  578. return SDW_CMD_FAIL;
  579. }
  580. if (no_ack) {
  581. dev_dbg_ratelimited(cdns->dev,
  582. "SCP_addrpage ignored for Slave %d\n", msg->dev_num);
  583. return SDW_CMD_IGNORED;
  584. }
  585. return SDW_CMD_OK;
  586. }
  587. static int cdns_prep_msg(struct sdw_cdns *cdns, struct sdw_msg *msg, int *cmd)
  588. {
  589. int ret;
  590. if (msg->page) {
  591. ret = cdns_program_scp_addr(cdns, msg);
  592. if (ret) {
  593. msg->len = 0;
  594. return ret;
  595. }
  596. }
  597. switch (msg->flags) {
  598. case SDW_MSG_FLAG_READ:
  599. *cmd = CDNS_MCP_CMD_READ;
  600. break;
  601. case SDW_MSG_FLAG_WRITE:
  602. *cmd = CDNS_MCP_CMD_WRITE;
  603. break;
  604. default:
  605. dev_err(cdns->dev, "Invalid msg cmd: %d\n", msg->flags);
  606. return -EINVAL;
  607. }
  608. return 0;
  609. }
  610. enum sdw_command_response
  611. cdns_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg)
  612. {
  613. struct sdw_cdns *cdns = bus_to_cdns(bus);
  614. int cmd = 0, ret, i;
  615. ret = cdns_prep_msg(cdns, msg, &cmd);
  616. if (ret)
  617. return SDW_CMD_FAIL_OTHER;
  618. for (i = 0; i < msg->len / CDNS_MCP_CMD_LEN; i++) {
  619. ret = _cdns_xfer_msg(cdns, msg, cmd, i * CDNS_MCP_CMD_LEN,
  620. CDNS_MCP_CMD_LEN, false);
  621. if (ret != SDW_CMD_OK)
  622. return ret;
  623. }
  624. if (!(msg->len % CDNS_MCP_CMD_LEN))
  625. return SDW_CMD_OK;
  626. return _cdns_xfer_msg(cdns, msg, cmd, i * CDNS_MCP_CMD_LEN,
  627. msg->len % CDNS_MCP_CMD_LEN, false);
  628. }
  629. EXPORT_SYMBOL(cdns_xfer_msg);
  630. enum sdw_command_response
  631. cdns_xfer_msg_defer(struct sdw_bus *bus)
  632. {
  633. struct sdw_cdns *cdns = bus_to_cdns(bus);
  634. struct sdw_defer *defer = &bus->defer_msg;
  635. struct sdw_msg *msg = defer->msg;
  636. int cmd = 0, ret;
  637. /* for defer only 1 message is supported */
  638. if (msg->len > 1)
  639. return -ENOTSUPP;
  640. ret = cdns_prep_msg(cdns, msg, &cmd);
  641. if (ret)
  642. return SDW_CMD_FAIL_OTHER;
  643. return _cdns_xfer_msg(cdns, msg, cmd, 0, msg->len, true);
  644. }
  645. EXPORT_SYMBOL(cdns_xfer_msg_defer);
  646. u32 cdns_read_ping_status(struct sdw_bus *bus)
  647. {
  648. struct sdw_cdns *cdns = bus_to_cdns(bus);
  649. return cdns_readl(cdns, CDNS_MCP_SLAVE_STAT);
  650. }
  651. EXPORT_SYMBOL(cdns_read_ping_status);
  652. /*
  653. * IRQ handling
  654. */
  655. static int cdns_update_slave_status(struct sdw_cdns *cdns,
  656. u64 slave_intstat)
  657. {
  658. enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
  659. bool is_slave = false;
  660. u32 mask;
  661. u32 val;
  662. int i, set_status;
  663. memset(status, 0, sizeof(status));
  664. for (i = 0; i <= SDW_MAX_DEVICES; i++) {
  665. mask = (slave_intstat >> (i * CDNS_MCP_SLAVE_STATUS_NUM)) &
  666. CDNS_MCP_SLAVE_STATUS_BITS;
  667. set_status = 0;
  668. if (mask) {
  669. is_slave = true;
  670. if (mask & CDNS_MCP_SLAVE_INTSTAT_RESERVED) {
  671. status[i] = SDW_SLAVE_RESERVED;
  672. set_status++;
  673. }
  674. if (mask & CDNS_MCP_SLAVE_INTSTAT_ATTACHED) {
  675. status[i] = SDW_SLAVE_ATTACHED;
  676. set_status++;
  677. }
  678. if (mask & CDNS_MCP_SLAVE_INTSTAT_ALERT) {
  679. status[i] = SDW_SLAVE_ALERT;
  680. set_status++;
  681. }
  682. if (mask & CDNS_MCP_SLAVE_INTSTAT_NPRESENT) {
  683. status[i] = SDW_SLAVE_UNATTACHED;
  684. set_status++;
  685. }
  686. }
  687. /*
  688. * check that there was a single reported Slave status and when
  689. * there is not use the latest status extracted from PING commands
  690. */
  691. if (set_status != 1) {
  692. val = cdns_readl(cdns, CDNS_MCP_SLAVE_STAT);
  693. val >>= (i * 2);
  694. switch (val & 0x3) {
  695. case 0:
  696. status[i] = SDW_SLAVE_UNATTACHED;
  697. break;
  698. case 1:
  699. status[i] = SDW_SLAVE_ATTACHED;
  700. break;
  701. case 2:
  702. status[i] = SDW_SLAVE_ALERT;
  703. break;
  704. case 3:
  705. default:
  706. status[i] = SDW_SLAVE_RESERVED;
  707. break;
  708. }
  709. }
  710. }
  711. if (is_slave) {
  712. int ret;
  713. mutex_lock(&cdns->status_update_lock);
  714. ret = sdw_handle_slave_status(&cdns->bus, status);
  715. mutex_unlock(&cdns->status_update_lock);
  716. return ret;
  717. }
  718. return 0;
  719. }
  720. /**
  721. * sdw_cdns_irq() - Cadence interrupt handler
  722. * @irq: irq number
  723. * @dev_id: irq context
  724. */
  725. irqreturn_t sdw_cdns_irq(int irq, void *dev_id)
  726. {
  727. struct sdw_cdns *cdns = dev_id;
  728. u32 int_status;
  729. /* Check if the link is up */
  730. if (!cdns->link_up)
  731. return IRQ_NONE;
  732. int_status = cdns_readl(cdns, CDNS_MCP_INTSTAT);
  733. /* check for reserved values read as zero */
  734. if (int_status & CDNS_MCP_INT_RESERVED)
  735. return IRQ_NONE;
  736. if (!(int_status & CDNS_MCP_INT_IRQ))
  737. return IRQ_NONE;
  738. if (int_status & CDNS_MCP_INT_RX_WL) {
  739. struct sdw_bus *bus = &cdns->bus;
  740. struct sdw_defer *defer = &bus->defer_msg;
  741. cdns_read_response(cdns);
  742. if (defer && defer->msg) {
  743. cdns_fill_msg_resp(cdns, defer->msg,
  744. defer->length, 0);
  745. complete(&defer->complete);
  746. } else {
  747. complete(&cdns->tx_complete);
  748. }
  749. }
  750. if (int_status & CDNS_MCP_INT_PARITY) {
  751. /* Parity error detected by Master */
  752. dev_err_ratelimited(cdns->dev, "Parity error\n");
  753. }
  754. if (int_status & CDNS_MCP_INT_CTRL_CLASH) {
  755. /* Slave is driving bit slot during control word */
  756. dev_err_ratelimited(cdns->dev, "Bus clash for control word\n");
  757. }
  758. if (int_status & CDNS_MCP_INT_DATA_CLASH) {
  759. /*
  760. * Multiple slaves trying to drive bit slot, or issue with
  761. * ownership of data bits or Slave gone bonkers
  762. */
  763. dev_err_ratelimited(cdns->dev, "Bus clash for data word\n");
  764. }
  765. if (cdns->bus.params.m_data_mode != SDW_PORT_DATA_MODE_NORMAL &&
  766. int_status & CDNS_MCP_INT_DPINT) {
  767. u32 port_intstat;
  768. /* just log which ports report an error */
  769. port_intstat = cdns_readl(cdns, CDNS_MCP_PORT_INTSTAT);
  770. dev_err_ratelimited(cdns->dev, "DP interrupt: PortIntStat %8x\n",
  771. port_intstat);
  772. /* clear status w/ write1 */
  773. cdns_writel(cdns, CDNS_MCP_PORT_INTSTAT, port_intstat);
  774. }
  775. if (int_status & CDNS_MCP_INT_SLAVE_MASK) {
  776. /* Mask the Slave interrupt and wake thread */
  777. cdns_updatel(cdns, CDNS_MCP_INTMASK,
  778. CDNS_MCP_INT_SLAVE_MASK, 0);
  779. int_status &= ~CDNS_MCP_INT_SLAVE_MASK;
  780. /*
  781. * Deal with possible race condition between interrupt
  782. * handling and disabling interrupts on suspend.
  783. *
  784. * If the master is in the process of disabling
  785. * interrupts, don't schedule a workqueue
  786. */
  787. if (cdns->interrupt_enabled)
  788. schedule_work(&cdns->work);
  789. }
  790. cdns_writel(cdns, CDNS_MCP_INTSTAT, int_status);
  791. return IRQ_HANDLED;
  792. }
  793. EXPORT_SYMBOL(sdw_cdns_irq);
  794. static void cdns_check_attached_status_dwork(struct work_struct *work)
  795. {
  796. struct sdw_cdns *cdns =
  797. container_of(work, struct sdw_cdns, attach_dwork.work);
  798. enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
  799. u32 val;
  800. int ret;
  801. int i;
  802. val = cdns_readl(cdns, CDNS_MCP_SLAVE_STAT);
  803. for (i = 0; i <= SDW_MAX_DEVICES; i++) {
  804. status[i] = val & 0x3;
  805. if (status[i])
  806. dev_dbg(cdns->dev, "Peripheral %d status: %d\n", i, status[i]);
  807. val >>= 2;
  808. }
  809. mutex_lock(&cdns->status_update_lock);
  810. ret = sdw_handle_slave_status(&cdns->bus, status);
  811. mutex_unlock(&cdns->status_update_lock);
  812. if (ret < 0)
  813. dev_err(cdns->dev, "%s: sdw_handle_slave_status failed: %d\n", __func__, ret);
  814. }
  815. /**
  816. * cdns_update_slave_status_work - update slave status in a work since we will need to handle
  817. * other interrupts eg. CDNS_MCP_INT_RX_WL during the update slave
  818. * process.
  819. * @work: cdns worker thread
  820. */
  821. static void cdns_update_slave_status_work(struct work_struct *work)
  822. {
  823. struct sdw_cdns *cdns =
  824. container_of(work, struct sdw_cdns, work);
  825. u32 slave0, slave1;
  826. u64 slave_intstat;
  827. u32 device0_status;
  828. int retry_count = 0;
  829. /*
  830. * Clear main interrupt first so we don't lose any assertions
  831. * that happen during this function.
  832. */
  833. cdns_writel(cdns, CDNS_MCP_INTSTAT, CDNS_MCP_INT_SLAVE_MASK);
  834. slave0 = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT0);
  835. slave1 = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT1);
  836. /*
  837. * Clear the bits before handling so we don't lose any
  838. * bits that re-assert.
  839. */
  840. cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT0, slave0);
  841. cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT1, slave1);
  842. /* combine the two status */
  843. slave_intstat = ((u64)slave1 << 32) | slave0;
  844. dev_dbg_ratelimited(cdns->dev, "Slave status change: 0x%llx\n", slave_intstat);
  845. update_status:
  846. cdns_update_slave_status(cdns, slave_intstat);
  847. /*
  848. * When there is more than one peripheral per link, it's
  849. * possible that a deviceB becomes attached after we deal with
  850. * the attachment of deviceA. Since the hardware does a
  851. * logical AND, the attachment of the second device does not
  852. * change the status seen by the driver.
  853. *
  854. * In that case, clearing the registers above would result in
  855. * the deviceB never being detected - until a change of status
  856. * is observed on the bus.
  857. *
  858. * To avoid this race condition, re-check if any device0 needs
  859. * attention with PING commands. There is no need to check for
  860. * ALERTS since they are not allowed until a non-zero
  861. * device_number is assigned.
  862. *
  863. * Do not clear the INTSTAT0/1. While looping to enumerate devices on
  864. * #0 there could be status changes on other devices - these must
  865. * be kept in the INTSTAT so they can be handled when all #0 devices
  866. * have been handled.
  867. */
  868. device0_status = cdns_readl(cdns, CDNS_MCP_SLAVE_STAT);
  869. device0_status &= 3;
  870. if (device0_status == SDW_SLAVE_ATTACHED) {
  871. if (retry_count++ < SDW_MAX_DEVICES) {
  872. dev_dbg_ratelimited(cdns->dev,
  873. "Device0 detected after clearing status, iteration %d\n",
  874. retry_count);
  875. slave_intstat = CDNS_MCP_SLAVE_INTSTAT_ATTACHED;
  876. goto update_status;
  877. } else {
  878. dev_err_ratelimited(cdns->dev,
  879. "Device0 detected after %d iterations\n",
  880. retry_count);
  881. }
  882. }
  883. /* unmask Slave interrupt now */
  884. cdns_updatel(cdns, CDNS_MCP_INTMASK,
  885. CDNS_MCP_INT_SLAVE_MASK, CDNS_MCP_INT_SLAVE_MASK);
  886. }
  887. /* paranoia check to make sure self-cleared bits are indeed cleared */
  888. void sdw_cdns_check_self_clearing_bits(struct sdw_cdns *cdns, const char *string,
  889. bool initial_delay, int reset_iterations)
  890. {
  891. u32 ip_mcp_control;
  892. u32 mcp_control;
  893. u32 mcp_config_update;
  894. int i;
  895. if (initial_delay)
  896. usleep_range(1000, 1500);
  897. ip_mcp_control = cdns_ip_readl(cdns, CDNS_IP_MCP_CONTROL);
  898. /* the following bits should be cleared immediately */
  899. if (ip_mcp_control & CDNS_IP_MCP_CONTROL_SW_RST)
  900. dev_err(cdns->dev, "%s failed: IP_MCP_CONTROL_SW_RST is not cleared\n", string);
  901. mcp_control = cdns_readl(cdns, CDNS_MCP_CONTROL);
  902. /* the following bits should be cleared immediately */
  903. if (mcp_control & CDNS_MCP_CONTROL_CMD_RST)
  904. dev_err(cdns->dev, "%s failed: MCP_CONTROL_CMD_RST is not cleared\n", string);
  905. if (mcp_control & CDNS_MCP_CONTROL_SOFT_RST)
  906. dev_err(cdns->dev, "%s failed: MCP_CONTROL_SOFT_RST is not cleared\n", string);
  907. if (mcp_control & CDNS_MCP_CONTROL_CLK_STOP_CLR)
  908. dev_err(cdns->dev, "%s failed: MCP_CONTROL_CLK_STOP_CLR is not cleared\n", string);
  909. mcp_config_update = cdns_readl(cdns, CDNS_MCP_CONFIG_UPDATE);
  910. if (mcp_config_update & CDNS_MCP_CONFIG_UPDATE_BIT)
  911. dev_err(cdns->dev, "%s failed: MCP_CONFIG_UPDATE_BIT is not cleared\n", string);
  912. i = 0;
  913. while (mcp_control & CDNS_MCP_CONTROL_HW_RST) {
  914. if (i == reset_iterations) {
  915. dev_err(cdns->dev, "%s failed: MCP_CONTROL_HW_RST is not cleared\n", string);
  916. break;
  917. }
  918. dev_dbg(cdns->dev, "%s: MCP_CONTROL_HW_RST is not cleared at iteration %d\n", string, i);
  919. i++;
  920. usleep_range(1000, 1500);
  921. mcp_control = cdns_readl(cdns, CDNS_MCP_CONTROL);
  922. }
  923. }
  924. EXPORT_SYMBOL(sdw_cdns_check_self_clearing_bits);
  925. /*
  926. * init routines
  927. */
  928. /**
  929. * sdw_cdns_exit_reset() - Program reset parameters and start bus operations
  930. * @cdns: Cadence instance
  931. */
  932. int sdw_cdns_exit_reset(struct sdw_cdns *cdns)
  933. {
  934. /* keep reset delay unchanged to 4096 cycles */
  935. /* use hardware generated reset */
  936. cdns_updatel(cdns, CDNS_MCP_CONTROL,
  937. CDNS_MCP_CONTROL_HW_RST,
  938. CDNS_MCP_CONTROL_HW_RST);
  939. /* commit changes */
  940. return cdns_config_update(cdns);
  941. }
  942. EXPORT_SYMBOL(sdw_cdns_exit_reset);
  943. /**
  944. * cdns_enable_slave_interrupts() - Enable SDW slave interrupts
  945. * @cdns: Cadence instance
  946. * @state: boolean for true/false
  947. */
  948. static void cdns_enable_slave_interrupts(struct sdw_cdns *cdns, bool state)
  949. {
  950. u32 mask;
  951. mask = cdns_readl(cdns, CDNS_MCP_INTMASK);
  952. if (state)
  953. mask |= CDNS_MCP_INT_SLAVE_MASK;
  954. else
  955. mask &= ~CDNS_MCP_INT_SLAVE_MASK;
  956. cdns_writel(cdns, CDNS_MCP_INTMASK, mask);
  957. }
  958. /**
  959. * sdw_cdns_enable_interrupt() - Enable SDW interrupts
  960. * @cdns: Cadence instance
  961. * @state: True if we are trying to enable interrupt.
  962. */
  963. int sdw_cdns_enable_interrupt(struct sdw_cdns *cdns, bool state)
  964. {
  965. u32 slave_intmask0 = 0;
  966. u32 slave_intmask1 = 0;
  967. u32 mask = 0;
  968. if (!state)
  969. goto update_masks;
  970. slave_intmask0 = CDNS_MCP_SLAVE_INTMASK0_MASK;
  971. slave_intmask1 = CDNS_MCP_SLAVE_INTMASK1_MASK;
  972. /* enable detection of all slave state changes */
  973. mask = CDNS_MCP_INT_SLAVE_MASK;
  974. /* enable detection of bus issues */
  975. mask |= CDNS_MCP_INT_CTRL_CLASH | CDNS_MCP_INT_DATA_CLASH |
  976. CDNS_MCP_INT_PARITY;
  977. /* port interrupt limited to test modes for now */
  978. if (cdns->bus.params.m_data_mode != SDW_PORT_DATA_MODE_NORMAL)
  979. mask |= CDNS_MCP_INT_DPINT;
  980. /* enable detection of RX fifo level */
  981. mask |= CDNS_MCP_INT_RX_WL;
  982. /*
  983. * CDNS_MCP_INT_IRQ needs to be set otherwise all previous
  984. * settings are irrelevant
  985. */
  986. mask |= CDNS_MCP_INT_IRQ;
  987. if (interrupt_mask) /* parameter override */
  988. mask = interrupt_mask;
  989. update_masks:
  990. /* clear slave interrupt status before enabling interrupt */
  991. if (state) {
  992. u32 slave_state;
  993. slave_state = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT0);
  994. cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT0, slave_state);
  995. slave_state = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT1);
  996. cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT1, slave_state);
  997. }
  998. cdns->interrupt_enabled = state;
  999. /*
  1000. * Complete any on-going status updates before updating masks,
  1001. * and cancel queued status updates.
  1002. *
  1003. * There could be a race with a new interrupt thrown before
  1004. * the 3 mask updates below are complete, so in the interrupt
  1005. * we use the 'interrupt_enabled' status to prevent new work
  1006. * from being queued.
  1007. */
  1008. if (!state)
  1009. cancel_work_sync(&cdns->work);
  1010. cdns_writel(cdns, CDNS_MCP_SLAVE_INTMASK0, slave_intmask0);
  1011. cdns_writel(cdns, CDNS_MCP_SLAVE_INTMASK1, slave_intmask1);
  1012. cdns_writel(cdns, CDNS_MCP_INTMASK, mask);
  1013. return 0;
  1014. }
  1015. EXPORT_SYMBOL(sdw_cdns_enable_interrupt);
  1016. static int cdns_allocate_pdi(struct sdw_cdns *cdns,
  1017. struct sdw_cdns_pdi **stream,
  1018. u32 num)
  1019. {
  1020. struct sdw_cdns_pdi *pdi;
  1021. int i;
  1022. if (!num)
  1023. return 0;
  1024. pdi = devm_kcalloc(cdns->dev, num, sizeof(*pdi), GFP_KERNEL);
  1025. if (!pdi)
  1026. return -ENOMEM;
  1027. for (i = 0; i < num; i++) {
  1028. pdi[i].num = i;
  1029. }
  1030. *stream = pdi;
  1031. return 0;
  1032. }
  1033. /**
  1034. * sdw_cdns_pdi_init() - PDI initialization routine
  1035. *
  1036. * @cdns: Cadence instance
  1037. * @config: Stream configurations
  1038. */
  1039. int sdw_cdns_pdi_init(struct sdw_cdns *cdns,
  1040. struct sdw_cdns_stream_config config)
  1041. {
  1042. struct sdw_cdns_streams *stream;
  1043. int ret;
  1044. cdns->pcm.num_bd = config.pcm_bd;
  1045. cdns->pcm.num_in = config.pcm_in;
  1046. cdns->pcm.num_out = config.pcm_out;
  1047. /* Allocate PDIs for PCMs */
  1048. stream = &cdns->pcm;
  1049. /* we allocate PDI0 and PDI1 which are used for Bulk */
  1050. ret = cdns_allocate_pdi(cdns, &stream->bd, stream->num_bd);
  1051. if (ret)
  1052. return ret;
  1053. ret = cdns_allocate_pdi(cdns, &stream->in, stream->num_in);
  1054. if (ret)
  1055. return ret;
  1056. ret = cdns_allocate_pdi(cdns, &stream->out, stream->num_out);
  1057. if (ret)
  1058. return ret;
  1059. /* Update total number of PCM PDIs */
  1060. stream->num_pdi = stream->num_bd + stream->num_in + stream->num_out;
  1061. cdns->num_ports = stream->num_pdi;
  1062. return 0;
  1063. }
  1064. EXPORT_SYMBOL(sdw_cdns_pdi_init);
  1065. static u32 cdns_set_initial_frame_shape(int n_rows, int n_cols)
  1066. {
  1067. u32 val;
  1068. int c;
  1069. int r;
  1070. r = sdw_find_row_index(n_rows);
  1071. c = sdw_find_col_index(n_cols);
  1072. val = FIELD_PREP(CDNS_MCP_FRAME_SHAPE_ROW_MASK, r);
  1073. val |= FIELD_PREP(CDNS_MCP_FRAME_SHAPE_COL_MASK, c);
  1074. return val;
  1075. }
  1076. static int cdns_init_clock_ctrl(struct sdw_cdns *cdns)
  1077. {
  1078. struct sdw_bus *bus = &cdns->bus;
  1079. struct sdw_master_prop *prop = &bus->prop;
  1080. u32 val;
  1081. u32 ssp_interval;
  1082. int divider;
  1083. dev_dbg(cdns->dev, "mclk %d max %d row %d col %d\n",
  1084. prop->mclk_freq,
  1085. prop->max_clk_freq,
  1086. prop->default_row,
  1087. prop->default_col);
  1088. if (!prop->default_frame_rate || !prop->default_row) {
  1089. dev_err(cdns->dev, "Default frame_rate %d or row %d is invalid\n",
  1090. prop->default_frame_rate, prop->default_row);
  1091. return -EINVAL;
  1092. }
  1093. /* Set clock divider */
  1094. divider = (prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR /
  1095. bus->params.curr_dr_freq) - 1;
  1096. cdns_updatel(cdns, CDNS_MCP_CLK_CTRL0,
  1097. CDNS_MCP_CLK_MCLKD_MASK, divider);
  1098. cdns_updatel(cdns, CDNS_MCP_CLK_CTRL1,
  1099. CDNS_MCP_CLK_MCLKD_MASK, divider);
  1100. /* Set frame shape base on the actual bus frequency. */
  1101. prop->default_col = bus->params.curr_dr_freq /
  1102. prop->default_frame_rate / prop->default_row;
  1103. /*
  1104. * Frame shape changes after initialization have to be done
  1105. * with the bank switch mechanism
  1106. */
  1107. val = cdns_set_initial_frame_shape(prop->default_row,
  1108. prop->default_col);
  1109. cdns_writel(cdns, CDNS_MCP_FRAME_SHAPE_INIT, val);
  1110. /* Set SSP interval to default value */
  1111. ssp_interval = prop->default_frame_rate / SDW_CADENCE_GSYNC_HZ;
  1112. cdns_writel(cdns, CDNS_MCP_SSP_CTRL0, ssp_interval);
  1113. cdns_writel(cdns, CDNS_MCP_SSP_CTRL1, ssp_interval);
  1114. return 0;
  1115. }
  1116. /**
  1117. * sdw_cdns_soft_reset() - Cadence soft-reset
  1118. * @cdns: Cadence instance
  1119. */
  1120. int sdw_cdns_soft_reset(struct sdw_cdns *cdns)
  1121. {
  1122. int ret;
  1123. cdns_updatel(cdns, CDNS_MCP_CONTROL, CDNS_MCP_CONTROL_SOFT_RST,
  1124. CDNS_MCP_CONTROL_SOFT_RST);
  1125. ret = cdns_config_update(cdns);
  1126. if (ret < 0) {
  1127. dev_err(cdns->dev, "%s: config update failed\n", __func__);
  1128. return ret;
  1129. }
  1130. ret = cdns_set_wait(cdns, CDNS_MCP_CONTROL, CDNS_MCP_CONTROL_SOFT_RST, 0);
  1131. if (ret < 0)
  1132. dev_err(cdns->dev, "%s: Soft Reset timed out\n", __func__);
  1133. return ret;
  1134. }
  1135. EXPORT_SYMBOL(sdw_cdns_soft_reset);
  1136. /**
  1137. * sdw_cdns_init() - Cadence initialization
  1138. * @cdns: Cadence instance
  1139. */
  1140. int sdw_cdns_init(struct sdw_cdns *cdns)
  1141. {
  1142. int ret;
  1143. u32 val;
  1144. ret = cdns_init_clock_ctrl(cdns);
  1145. if (ret)
  1146. return ret;
  1147. sdw_cdns_check_self_clearing_bits(cdns, __func__, false, 0);
  1148. /* reset msg_count to default value of FIFOLEVEL */
  1149. cdns->msg_count = cdns_readl(cdns, CDNS_MCP_FIFOLEVEL);
  1150. /* flush command FIFOs */
  1151. cdns_updatel(cdns, CDNS_MCP_CONTROL, CDNS_MCP_CONTROL_CMD_RST,
  1152. CDNS_MCP_CONTROL_CMD_RST);
  1153. /* Set cmd accept mode */
  1154. cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL, CDNS_IP_MCP_CONTROL_CMD_ACCEPT,
  1155. CDNS_IP_MCP_CONTROL_CMD_ACCEPT);
  1156. /* disable wakeup */
  1157. cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL,
  1158. CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP,
  1159. 0);
  1160. /* Configure mcp config */
  1161. val = cdns_readl(cdns, CDNS_MCP_CONFIG);
  1162. /* Disable auto bus release */
  1163. val &= ~CDNS_MCP_CONFIG_BUS_REL;
  1164. cdns_writel(cdns, CDNS_MCP_CONFIG, val);
  1165. /* Configure IP mcp config */
  1166. val = cdns_ip_readl(cdns, CDNS_IP_MCP_CONFIG);
  1167. /* enable bus operations with clock and data */
  1168. val &= ~CDNS_IP_MCP_CONFIG_OP;
  1169. val |= CDNS_IP_MCP_CONFIG_OP_NORMAL;
  1170. /* Set cmd mode for Tx and Rx cmds */
  1171. val &= ~CDNS_IP_MCP_CONFIG_CMD;
  1172. /* Disable sniffer mode */
  1173. val &= ~CDNS_IP_MCP_CONFIG_SNIFFER;
  1174. if (cdns->bus.multi_link)
  1175. /* Set Multi-master mode to take gsync into account */
  1176. val |= CDNS_IP_MCP_CONFIG_MMASTER;
  1177. /* leave frame delay to hardware default of 0x1F */
  1178. /* leave command retry to hardware default of 0 */
  1179. cdns_ip_writel(cdns, CDNS_IP_MCP_CONFIG, val);
  1180. /* changes will be committed later */
  1181. return 0;
  1182. }
  1183. EXPORT_SYMBOL(sdw_cdns_init);
  1184. int cdns_bus_conf(struct sdw_bus *bus, struct sdw_bus_params *params)
  1185. {
  1186. struct sdw_master_prop *prop = &bus->prop;
  1187. struct sdw_cdns *cdns = bus_to_cdns(bus);
  1188. int mcp_clkctrl_off;
  1189. int divider;
  1190. if (!params->curr_dr_freq) {
  1191. dev_err(cdns->dev, "NULL curr_dr_freq\n");
  1192. return -EINVAL;
  1193. }
  1194. divider = prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR /
  1195. params->curr_dr_freq;
  1196. divider--; /* divider is 1/(N+1) */
  1197. if (params->next_bank)
  1198. mcp_clkctrl_off = CDNS_MCP_CLK_CTRL1;
  1199. else
  1200. mcp_clkctrl_off = CDNS_MCP_CLK_CTRL0;
  1201. cdns_updatel(cdns, mcp_clkctrl_off, CDNS_MCP_CLK_MCLKD_MASK, divider);
  1202. return 0;
  1203. }
  1204. EXPORT_SYMBOL(cdns_bus_conf);
  1205. static int cdns_port_params(struct sdw_bus *bus,
  1206. struct sdw_port_params *p_params, unsigned int bank)
  1207. {
  1208. struct sdw_cdns *cdns = bus_to_cdns(bus);
  1209. int dpn_config_off_source;
  1210. int dpn_config_off_target;
  1211. int target_num = p_params->num;
  1212. int source_num = p_params->num;
  1213. bool override = false;
  1214. int dpn_config;
  1215. if (target_num == cdns->pdi_loopback_target &&
  1216. cdns->pdi_loopback_source != -1) {
  1217. source_num = cdns->pdi_loopback_source;
  1218. override = true;
  1219. }
  1220. if (bank) {
  1221. dpn_config_off_source = CDNS_DPN_B1_CONFIG(source_num);
  1222. dpn_config_off_target = CDNS_DPN_B1_CONFIG(target_num);
  1223. } else {
  1224. dpn_config_off_source = CDNS_DPN_B0_CONFIG(source_num);
  1225. dpn_config_off_target = CDNS_DPN_B0_CONFIG(target_num);
  1226. }
  1227. dpn_config = cdns_readl(cdns, dpn_config_off_source);
  1228. /* use port params if there is no loopback, otherwise use source as is */
  1229. if (!override) {
  1230. u32p_replace_bits(&dpn_config, p_params->bps - 1, CDNS_DPN_CONFIG_WL);
  1231. u32p_replace_bits(&dpn_config, p_params->flow_mode, CDNS_DPN_CONFIG_PORT_FLOW);
  1232. u32p_replace_bits(&dpn_config, p_params->data_mode, CDNS_DPN_CONFIG_PORT_DAT);
  1233. }
  1234. cdns_writel(cdns, dpn_config_off_target, dpn_config);
  1235. return 0;
  1236. }
  1237. static int cdns_transport_params(struct sdw_bus *bus,
  1238. struct sdw_transport_params *t_params,
  1239. enum sdw_reg_bank bank)
  1240. {
  1241. struct sdw_cdns *cdns = bus_to_cdns(bus);
  1242. int dpn_config;
  1243. int dpn_config_off_source;
  1244. int dpn_config_off_target;
  1245. int dpn_hctrl;
  1246. int dpn_hctrl_off_source;
  1247. int dpn_hctrl_off_target;
  1248. int dpn_offsetctrl;
  1249. int dpn_offsetctrl_off_source;
  1250. int dpn_offsetctrl_off_target;
  1251. int dpn_samplectrl;
  1252. int dpn_samplectrl_off_source;
  1253. int dpn_samplectrl_off_target;
  1254. int source_num = t_params->port_num;
  1255. int target_num = t_params->port_num;
  1256. bool override = false;
  1257. if (target_num == cdns->pdi_loopback_target &&
  1258. cdns->pdi_loopback_source != -1) {
  1259. source_num = cdns->pdi_loopback_source;
  1260. override = true;
  1261. }
  1262. /*
  1263. * Note: Only full data port is supported on the Master side for
  1264. * both PCM and PDM ports.
  1265. */
  1266. if (bank) {
  1267. dpn_config_off_source = CDNS_DPN_B1_CONFIG(source_num);
  1268. dpn_hctrl_off_source = CDNS_DPN_B1_HCTRL(source_num);
  1269. dpn_offsetctrl_off_source = CDNS_DPN_B1_OFFSET_CTRL(source_num);
  1270. dpn_samplectrl_off_source = CDNS_DPN_B1_SAMPLE_CTRL(source_num);
  1271. dpn_config_off_target = CDNS_DPN_B1_CONFIG(target_num);
  1272. dpn_hctrl_off_target = CDNS_DPN_B1_HCTRL(target_num);
  1273. dpn_offsetctrl_off_target = CDNS_DPN_B1_OFFSET_CTRL(target_num);
  1274. dpn_samplectrl_off_target = CDNS_DPN_B1_SAMPLE_CTRL(target_num);
  1275. } else {
  1276. dpn_config_off_source = CDNS_DPN_B0_CONFIG(source_num);
  1277. dpn_hctrl_off_source = CDNS_DPN_B0_HCTRL(source_num);
  1278. dpn_offsetctrl_off_source = CDNS_DPN_B0_OFFSET_CTRL(source_num);
  1279. dpn_samplectrl_off_source = CDNS_DPN_B0_SAMPLE_CTRL(source_num);
  1280. dpn_config_off_target = CDNS_DPN_B0_CONFIG(target_num);
  1281. dpn_hctrl_off_target = CDNS_DPN_B0_HCTRL(target_num);
  1282. dpn_offsetctrl_off_target = CDNS_DPN_B0_OFFSET_CTRL(target_num);
  1283. dpn_samplectrl_off_target = CDNS_DPN_B0_SAMPLE_CTRL(target_num);
  1284. }
  1285. dpn_config = cdns_readl(cdns, dpn_config_off_source);
  1286. if (!override) {
  1287. u32p_replace_bits(&dpn_config, t_params->blk_grp_ctrl, CDNS_DPN_CONFIG_BGC);
  1288. u32p_replace_bits(&dpn_config, t_params->blk_pkg_mode, CDNS_DPN_CONFIG_BPM);
  1289. }
  1290. cdns_writel(cdns, dpn_config_off_target, dpn_config);
  1291. if (!override) {
  1292. dpn_offsetctrl = 0;
  1293. u32p_replace_bits(&dpn_offsetctrl, t_params->offset1, CDNS_DPN_OFFSET_CTRL_1);
  1294. u32p_replace_bits(&dpn_offsetctrl, t_params->offset2, CDNS_DPN_OFFSET_CTRL_2);
  1295. } else {
  1296. dpn_offsetctrl = cdns_readl(cdns, dpn_offsetctrl_off_source);
  1297. }
  1298. cdns_writel(cdns, dpn_offsetctrl_off_target, dpn_offsetctrl);
  1299. if (!override) {
  1300. dpn_hctrl = 0;
  1301. u32p_replace_bits(&dpn_hctrl, t_params->hstart, CDNS_DPN_HCTRL_HSTART);
  1302. u32p_replace_bits(&dpn_hctrl, t_params->hstop, CDNS_DPN_HCTRL_HSTOP);
  1303. u32p_replace_bits(&dpn_hctrl, t_params->lane_ctrl, CDNS_DPN_HCTRL_LCTRL);
  1304. } else {
  1305. dpn_hctrl = cdns_readl(cdns, dpn_hctrl_off_source);
  1306. }
  1307. cdns_writel(cdns, dpn_hctrl_off_target, dpn_hctrl);
  1308. if (!override)
  1309. dpn_samplectrl = t_params->sample_interval - 1;
  1310. else
  1311. dpn_samplectrl = cdns_readl(cdns, dpn_samplectrl_off_source);
  1312. cdns_writel(cdns, dpn_samplectrl_off_target, dpn_samplectrl);
  1313. return 0;
  1314. }
  1315. static int cdns_port_enable(struct sdw_bus *bus,
  1316. struct sdw_enable_ch *enable_ch, unsigned int bank)
  1317. {
  1318. struct sdw_cdns *cdns = bus_to_cdns(bus);
  1319. int dpn_chnen_off, ch_mask;
  1320. if (bank)
  1321. dpn_chnen_off = CDNS_DPN_B1_CH_EN(enable_ch->port_num);
  1322. else
  1323. dpn_chnen_off = CDNS_DPN_B0_CH_EN(enable_ch->port_num);
  1324. ch_mask = enable_ch->ch_mask * enable_ch->enable;
  1325. cdns_writel(cdns, dpn_chnen_off, ch_mask);
  1326. return 0;
  1327. }
  1328. static const struct sdw_master_port_ops cdns_port_ops = {
  1329. .dpn_set_port_params = cdns_port_params,
  1330. .dpn_set_port_transport_params = cdns_transport_params,
  1331. .dpn_port_enable_ch = cdns_port_enable,
  1332. };
  1333. /**
  1334. * sdw_cdns_is_clock_stop: Check clock status
  1335. *
  1336. * @cdns: Cadence instance
  1337. */
  1338. bool sdw_cdns_is_clock_stop(struct sdw_cdns *cdns)
  1339. {
  1340. return !!(cdns_readl(cdns, CDNS_MCP_STAT) & CDNS_MCP_STAT_CLK_STOP);
  1341. }
  1342. EXPORT_SYMBOL(sdw_cdns_is_clock_stop);
  1343. /**
  1344. * sdw_cdns_clock_stop: Cadence clock stop configuration routine
  1345. *
  1346. * @cdns: Cadence instance
  1347. * @block_wake: prevent wakes if required by the platform
  1348. */
  1349. int sdw_cdns_clock_stop(struct sdw_cdns *cdns, bool block_wake)
  1350. {
  1351. bool slave_present = false;
  1352. struct sdw_slave *slave;
  1353. int ret;
  1354. sdw_cdns_check_self_clearing_bits(cdns, __func__, false, 0);
  1355. /* Check suspend status */
  1356. if (sdw_cdns_is_clock_stop(cdns)) {
  1357. dev_dbg(cdns->dev, "Clock is already stopped\n");
  1358. return 0;
  1359. }
  1360. /*
  1361. * Before entering clock stop we mask the Slave
  1362. * interrupts. This helps avoid having to deal with e.g. a
  1363. * Slave becoming UNATTACHED while the clock is being stopped
  1364. */
  1365. cdns_enable_slave_interrupts(cdns, false);
  1366. /*
  1367. * For specific platforms, it is required to be able to put
  1368. * master into a state in which it ignores wake-up trials
  1369. * in clock stop state
  1370. */
  1371. if (block_wake)
  1372. cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL,
  1373. CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP,
  1374. CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP);
  1375. list_for_each_entry(slave, &cdns->bus.slaves, node) {
  1376. if (slave->status == SDW_SLAVE_ATTACHED ||
  1377. slave->status == SDW_SLAVE_ALERT) {
  1378. slave_present = true;
  1379. break;
  1380. }
  1381. }
  1382. /* commit changes */
  1383. ret = cdns_config_update(cdns);
  1384. if (ret < 0) {
  1385. dev_err(cdns->dev, "%s: config_update failed\n", __func__);
  1386. return ret;
  1387. }
  1388. /* Prepare slaves for clock stop */
  1389. if (slave_present) {
  1390. ret = sdw_bus_prep_clk_stop(&cdns->bus);
  1391. if (ret < 0 && ret != -ENODATA) {
  1392. dev_err(cdns->dev, "prepare clock stop failed %d\n", ret);
  1393. return ret;
  1394. }
  1395. }
  1396. /*
  1397. * Enter clock stop mode and only report errors if there are
  1398. * Slave devices present (ALERT or ATTACHED)
  1399. */
  1400. ret = sdw_bus_clk_stop(&cdns->bus);
  1401. if (ret < 0 && slave_present && ret != -ENODATA) {
  1402. dev_err(cdns->dev, "bus clock stop failed %d\n", ret);
  1403. return ret;
  1404. }
  1405. ret = cdns_set_wait(cdns, CDNS_MCP_STAT,
  1406. CDNS_MCP_STAT_CLK_STOP,
  1407. CDNS_MCP_STAT_CLK_STOP);
  1408. if (ret < 0)
  1409. dev_err(cdns->dev, "Clock stop failed %d\n", ret);
  1410. return ret;
  1411. }
  1412. EXPORT_SYMBOL(sdw_cdns_clock_stop);
  1413. /**
  1414. * sdw_cdns_clock_restart: Cadence PM clock restart configuration routine
  1415. *
  1416. * @cdns: Cadence instance
  1417. * @bus_reset: context may be lost while in low power modes and the bus
  1418. * may require a Severe Reset and re-enumeration after a wake.
  1419. */
  1420. int sdw_cdns_clock_restart(struct sdw_cdns *cdns, bool bus_reset)
  1421. {
  1422. int ret;
  1423. /* unmask Slave interrupts that were masked when stopping the clock */
  1424. cdns_enable_slave_interrupts(cdns, true);
  1425. ret = cdns_clear_bit(cdns, CDNS_MCP_CONTROL,
  1426. CDNS_MCP_CONTROL_CLK_STOP_CLR);
  1427. if (ret < 0) {
  1428. dev_err(cdns->dev, "Couldn't exit from clock stop\n");
  1429. return ret;
  1430. }
  1431. ret = cdns_set_wait(cdns, CDNS_MCP_STAT, CDNS_MCP_STAT_CLK_STOP, 0);
  1432. if (ret < 0) {
  1433. dev_err(cdns->dev, "clock stop exit failed %d\n", ret);
  1434. return ret;
  1435. }
  1436. cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL,
  1437. CDNS_IP_MCP_CONTROL_BLOCK_WAKEUP, 0);
  1438. cdns_ip_updatel(cdns, CDNS_IP_MCP_CONTROL, CDNS_IP_MCP_CONTROL_CMD_ACCEPT,
  1439. CDNS_IP_MCP_CONTROL_CMD_ACCEPT);
  1440. if (!bus_reset) {
  1441. /* enable bus operations with clock and data */
  1442. cdns_ip_updatel(cdns, CDNS_IP_MCP_CONFIG,
  1443. CDNS_IP_MCP_CONFIG_OP,
  1444. CDNS_IP_MCP_CONFIG_OP_NORMAL);
  1445. ret = cdns_config_update(cdns);
  1446. if (ret < 0) {
  1447. dev_err(cdns->dev, "%s: config_update failed\n", __func__);
  1448. return ret;
  1449. }
  1450. ret = sdw_bus_exit_clk_stop(&cdns->bus);
  1451. if (ret < 0)
  1452. dev_err(cdns->dev, "bus failed to exit clock stop %d\n", ret);
  1453. }
  1454. return ret;
  1455. }
  1456. EXPORT_SYMBOL(sdw_cdns_clock_restart);
  1457. /**
  1458. * sdw_cdns_probe() - Cadence probe routine
  1459. * @cdns: Cadence instance
  1460. */
  1461. int sdw_cdns_probe(struct sdw_cdns *cdns)
  1462. {
  1463. init_completion(&cdns->tx_complete);
  1464. cdns->bus.port_ops = &cdns_port_ops;
  1465. mutex_init(&cdns->status_update_lock);
  1466. INIT_WORK(&cdns->work, cdns_update_slave_status_work);
  1467. INIT_DELAYED_WORK(&cdns->attach_dwork, cdns_check_attached_status_dwork);
  1468. return 0;
  1469. }
  1470. EXPORT_SYMBOL(sdw_cdns_probe);
  1471. int cdns_set_sdw_stream(struct snd_soc_dai *dai,
  1472. void *stream, int direction)
  1473. {
  1474. struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
  1475. struct sdw_cdns_dai_runtime *dai_runtime;
  1476. dai_runtime = cdns->dai_runtime_array[dai->id];
  1477. if (stream) {
  1478. /* first paranoia check */
  1479. if (dai_runtime) {
  1480. dev_err(dai->dev,
  1481. "dai_runtime already allocated for dai %s\n",
  1482. dai->name);
  1483. return -EINVAL;
  1484. }
  1485. /* allocate and set dai_runtime info */
  1486. dai_runtime = kzalloc_obj(*dai_runtime);
  1487. if (!dai_runtime)
  1488. return -ENOMEM;
  1489. dai_runtime->stream_type = SDW_STREAM_PCM;
  1490. dai_runtime->bus = &cdns->bus;
  1491. dai_runtime->link_id = cdns->instance;
  1492. dai_runtime->stream = stream;
  1493. dai_runtime->direction = direction;
  1494. cdns->dai_runtime_array[dai->id] = dai_runtime;
  1495. } else {
  1496. /* second paranoia check */
  1497. if (!dai_runtime) {
  1498. dev_err(dai->dev,
  1499. "dai_runtime not allocated for dai %s\n",
  1500. dai->name);
  1501. return -EINVAL;
  1502. }
  1503. /* for NULL stream we release allocated dai_runtime */
  1504. kfree(dai_runtime);
  1505. cdns->dai_runtime_array[dai->id] = NULL;
  1506. }
  1507. return 0;
  1508. }
  1509. EXPORT_SYMBOL(cdns_set_sdw_stream);
  1510. /**
  1511. * cdns_find_pdi() - Find a free PDI
  1512. *
  1513. * @cdns: Cadence instance
  1514. * @num: Number of PDIs
  1515. * @pdi: PDI instances
  1516. * @dai_id: DAI id
  1517. *
  1518. * Find a PDI for a given PDI array. The PDI num and dai_id are
  1519. * expected to match, return NULL otherwise.
  1520. */
  1521. static struct sdw_cdns_pdi *cdns_find_pdi(struct sdw_cdns *cdns,
  1522. unsigned int num,
  1523. struct sdw_cdns_pdi *pdi,
  1524. int dai_id)
  1525. {
  1526. int i;
  1527. for (i = 0; i < num; i++)
  1528. if (pdi[i].num == dai_id)
  1529. return &pdi[i];
  1530. return NULL;
  1531. }
  1532. /**
  1533. * sdw_cdns_config_stream: Configure a stream
  1534. *
  1535. * @cdns: Cadence instance
  1536. * @ch: Channel count
  1537. * @dir: Data direction
  1538. * @pdi: PDI to be used
  1539. */
  1540. void sdw_cdns_config_stream(struct sdw_cdns *cdns,
  1541. u32 ch, u32 dir, struct sdw_cdns_pdi *pdi)
  1542. {
  1543. u32 offset, val = 0;
  1544. if (dir == SDW_DATA_DIR_RX) {
  1545. val = CDNS_PORTCTRL_DIRN;
  1546. if (cdns->bus.params.m_data_mode != SDW_PORT_DATA_MODE_NORMAL)
  1547. val |= CDNS_PORTCTRL_TEST_FAILED;
  1548. } else if (pdi->num == 0 || pdi->num == 1) {
  1549. val |= CDNS_PORTCTRL_BULK_ENABLE;
  1550. }
  1551. offset = CDNS_PORTCTRL + pdi->num * CDNS_PORT_OFFSET;
  1552. cdns_updatel(cdns, offset,
  1553. CDNS_PORTCTRL_DIRN | CDNS_PORTCTRL_TEST_FAILED |
  1554. CDNS_PORTCTRL_BULK_ENABLE,
  1555. val);
  1556. /* The DataPort0 needs to be mapped to both PDI0 and PDI1 ! */
  1557. if (pdi->num == 1)
  1558. val = 0;
  1559. else
  1560. val = pdi->num;
  1561. val |= CDNS_PDI_CONFIG_SOFT_RESET;
  1562. val |= FIELD_PREP(CDNS_PDI_CONFIG_CHANNEL, (1 << ch) - 1);
  1563. cdns_writel(cdns, CDNS_PDI_CONFIG(pdi->num), val);
  1564. }
  1565. EXPORT_SYMBOL(sdw_cdns_config_stream);
  1566. /**
  1567. * sdw_cdns_alloc_pdi() - Allocate a PDI
  1568. *
  1569. * @cdns: Cadence instance
  1570. * @stream: Stream to be allocated
  1571. * @ch: Channel count
  1572. * @dir: Data direction
  1573. * @dai_id: DAI id
  1574. */
  1575. struct sdw_cdns_pdi *sdw_cdns_alloc_pdi(struct sdw_cdns *cdns,
  1576. struct sdw_cdns_streams *stream,
  1577. u32 ch, u32 dir, int dai_id)
  1578. {
  1579. struct sdw_cdns_pdi *pdi = NULL;
  1580. if (dir == SDW_DATA_DIR_RX)
  1581. pdi = cdns_find_pdi(cdns, stream->num_in, stream->in,
  1582. dai_id);
  1583. else
  1584. pdi = cdns_find_pdi(cdns, stream->num_out, stream->out,
  1585. dai_id);
  1586. /* check if we found a PDI, else find in bi-directional */
  1587. if (!pdi)
  1588. pdi = cdns_find_pdi(cdns, stream->num_bd, stream->bd,
  1589. dai_id);
  1590. if (pdi) {
  1591. pdi->l_ch_num = 0;
  1592. pdi->h_ch_num = ch - 1;
  1593. pdi->dir = dir;
  1594. pdi->ch_count = ch;
  1595. }
  1596. return pdi;
  1597. }
  1598. EXPORT_SYMBOL(sdw_cdns_alloc_pdi);
  1599. /*
  1600. * the MIPI SoundWire CRC8 polynomial is X^8 + X^6 + X^3 + X^2 + 1, MSB first
  1601. * The value is (1)01001101 = 0x4D
  1602. *
  1603. * the table below was generated with
  1604. *
  1605. * u8 crc8_lookup_table[CRC8_TABLE_SIZE];
  1606. * crc8_populate_msb(crc8_lookup_table, SDW_CRC8_POLY);
  1607. *
  1608. */
  1609. #define SDW_CRC8_SEED 0xFF
  1610. #define SDW_CRC8_POLY 0x4D
  1611. static const u8 sdw_crc8_lookup_msb[CRC8_TABLE_SIZE] = {
  1612. 0x00, 0x4d, 0x9a, 0xd7, 0x79, 0x34, 0xe3, 0xae, /* 0 - 7 */
  1613. 0xf2, 0xbf, 0x68, 0x25, 0x8b, 0xc6, 0x11, 0x5c, /* 8 -15 */
  1614. 0xa9, 0xe4, 0x33, 0x7e, 0xd0, 0x9d, 0x4a, 0x07, /* 16 - 23 */
  1615. 0x5b, 0x16, 0xc1, 0x8c, 0x22, 0x6f, 0xb8, 0xf5, /* 24 - 31 */
  1616. 0x1f, 0x52, 0x85, 0xc8, 0x66, 0x2b, 0xfc, 0xb1, /* 32 - 39 */
  1617. 0xed, 0xa0, 0x77, 0x3a, 0x94, 0xd9, 0x0e, 0x43, /* 40 - 47 */
  1618. 0xb6, 0xfb, 0x2c, 0x61, 0xcf, 0x82, 0x55, 0x18, /* 48 - 55 */
  1619. 0x44, 0x09, 0xde, 0x93, 0x3d, 0x70, 0xa7, 0xea, /* 56 - 63 */
  1620. 0x3e, 0x73, 0xa4, 0xe9, 0x47, 0x0a, 0xdd, 0x90, /* 64 - 71 */
  1621. 0xcc, 0x81, 0x56, 0x1b, 0xb5, 0xf8, 0x2f, 0x62, /* 72 - 79 */
  1622. 0x97, 0xda, 0x0d, 0x40, 0xee, 0xa3, 0x74, 0x39, /* 80 - 87 */
  1623. 0x65, 0x28, 0xff, 0xb2, 0x1c, 0x51, 0x86, 0xcb, /* 88 - 95 */
  1624. 0x21, 0x6c, 0xbb, 0xf6, 0x58, 0x15, 0xc2, 0x8f, /* 96 - 103 */
  1625. 0xd3, 0x9e, 0x49, 0x04, 0xaa, 0xe7, 0x30, 0x7d, /* 104 - 111 */
  1626. 0x88, 0xc5, 0x12, 0x5f, 0xf1, 0xbc, 0x6b, 0x26, /* 112 - 119 */
  1627. 0x7a, 0x37, 0xe0, 0xad, 0x03, 0x4e, 0x99, 0xd4, /* 120 - 127 */
  1628. 0x7c, 0x31, 0xe6, 0xab, 0x05, 0x48, 0x9f, 0xd2, /* 128 - 135 */
  1629. 0x8e, 0xc3, 0x14, 0x59, 0xf7, 0xba, 0x6d, 0x20, /* 136 - 143 */
  1630. 0xd5, 0x98, 0x4f, 0x02, 0xac, 0xe1, 0x36, 0x7b, /* 144 - 151 */
  1631. 0x27, 0x6a, 0xbd, 0xf0, 0x5e, 0x13, 0xc4, 0x89, /* 152 - 159 */
  1632. 0x63, 0x2e, 0xf9, 0xb4, 0x1a, 0x57, 0x80, 0xcd, /* 160 - 167 */
  1633. 0x91, 0xdc, 0x0b, 0x46, 0xe8, 0xa5, 0x72, 0x3f, /* 168 - 175 */
  1634. 0xca, 0x87, 0x50, 0x1d, 0xb3, 0xfe, 0x29, 0x64, /* 176 - 183 */
  1635. 0x38, 0x75, 0xa2, 0xef, 0x41, 0x0c, 0xdb, 0x96, /* 184 - 191 */
  1636. 0x42, 0x0f, 0xd8, 0x95, 0x3b, 0x76, 0xa1, 0xec, /* 192 - 199 */
  1637. 0xb0, 0xfd, 0x2a, 0x67, 0xc9, 0x84, 0x53, 0x1e, /* 200 - 207 */
  1638. 0xeb, 0xa6, 0x71, 0x3c, 0x92, 0xdf, 0x08, 0x45, /* 208 - 215 */
  1639. 0x19, 0x54, 0x83, 0xce, 0x60, 0x2d, 0xfa, 0xb7, /* 216 - 223 */
  1640. 0x5d, 0x10, 0xc7, 0x8a, 0x24, 0x69, 0xbe, 0xf3, /* 224 - 231 */
  1641. 0xaf, 0xe2, 0x35, 0x78, 0xd6, 0x9b, 0x4c, 0x01, /* 232 - 239 */
  1642. 0xf4, 0xb9, 0x6e, 0x23, 0x8d, 0xc0, 0x17, 0x5a, /* 240 - 247 */
  1643. 0x06, 0x4b, 0x9c, 0xd1, 0x7f, 0x32, 0xe5, 0xa8 /* 248 - 255 */
  1644. };
  1645. /* BPT/BRA helpers */
  1646. #define SDW_CDNS_BRA_HDR 6 /* defined by MIPI */
  1647. #define SDW_CDNS_BRA_HDR_CRC 1 /* defined by MIPI */
  1648. #define SDW_CDNS_BRA_HDR_CRC_PAD 1 /* Cadence only */
  1649. #define SDW_CDNS_BRA_HDR_RESP 1 /* defined by MIPI */
  1650. #define SDW_CDNS_BRA_HDR_RESP_PAD 1 /* Cadence only */
  1651. #define SDW_CDNS_BRA_DATA_PAD 1 /* Cadence only */
  1652. #define SDW_CDNS_BRA_DATA_CRC 1 /* defined by MIPI */
  1653. #define SDW_CDNS_BRA_DATA_CRC_PAD 1 /* Cadence only */
  1654. #define SDW_CDNS_BRA_FOOTER_RESP 1 /* defined by MIPI */
  1655. #define SDW_CDNS_BRA_FOOTER_RESP_PAD 1 /* Cadence only */
  1656. #define SDW_CDNS_WRITE_PDI1_BUFFER_SIZE \
  1657. ((SDW_CDNS_BRA_HDR_RESP + SDW_CDNS_BRA_HDR_RESP_PAD + \
  1658. SDW_CDNS_BRA_FOOTER_RESP + SDW_CDNS_BRA_FOOTER_RESP_PAD) * 2)
  1659. #define SDW_CDNS_READ_PDI0_BUFFER_SIZE \
  1660. ((SDW_CDNS_BRA_HDR + SDW_CDNS_BRA_HDR_CRC + SDW_CDNS_BRA_HDR_CRC_PAD) * 2)
  1661. static unsigned int sdw_cdns_bra_actual_data_size(unsigned int allocated_bytes_per_frame)
  1662. {
  1663. unsigned int total;
  1664. if (allocated_bytes_per_frame < (SDW_CDNS_BRA_HDR + SDW_CDNS_BRA_HDR_CRC +
  1665. SDW_CDNS_BRA_HDR_RESP + SDW_CDNS_BRA_DATA_CRC +
  1666. SDW_CDNS_BRA_FOOTER_RESP))
  1667. return 0;
  1668. total = allocated_bytes_per_frame - SDW_CDNS_BRA_HDR - SDW_CDNS_BRA_HDR_CRC -
  1669. SDW_CDNS_BRA_HDR_RESP - SDW_CDNS_BRA_DATA_CRC - SDW_CDNS_BRA_FOOTER_RESP;
  1670. return total;
  1671. }
  1672. static unsigned int sdw_cdns_write_pdi0_buffer_size(unsigned int actual_data_size)
  1673. {
  1674. unsigned int total;
  1675. total = SDW_CDNS_BRA_HDR + SDW_CDNS_BRA_HDR_CRC + SDW_CDNS_BRA_HDR_CRC_PAD;
  1676. total += actual_data_size;
  1677. if (actual_data_size & 1)
  1678. total += SDW_CDNS_BRA_DATA_PAD;
  1679. total += SDW_CDNS_BRA_DATA_CRC + SDW_CDNS_BRA_DATA_CRC_PAD;
  1680. return total * 2;
  1681. }
  1682. static unsigned int sdw_cdns_read_pdi1_buffer_size(unsigned int actual_data_size)
  1683. {
  1684. unsigned int total;
  1685. total = SDW_CDNS_BRA_HDR_RESP + SDW_CDNS_BRA_HDR_RESP_PAD;
  1686. total += actual_data_size;
  1687. if (actual_data_size & 1)
  1688. total += SDW_CDNS_BRA_DATA_PAD;
  1689. total += SDW_CDNS_BRA_HDR_CRC + SDW_CDNS_BRA_HDR_CRC_PAD;
  1690. total += SDW_CDNS_BRA_FOOTER_RESP + SDW_CDNS_BRA_FOOTER_RESP_PAD;
  1691. return total * 2;
  1692. }
  1693. int sdw_cdns_bpt_find_bandwidth(int command, /* 0: write, 1: read */
  1694. int row, int col, int frame_rate,
  1695. unsigned int *tx_dma_bandwidth,
  1696. unsigned int *rx_dma_bandwidth)
  1697. {
  1698. unsigned int bpt_bits = row * (col - 1);
  1699. unsigned int bpt_bytes = bpt_bits >> 3;
  1700. unsigned int pdi0_buffer_size;
  1701. unsigned int pdi1_buffer_size;
  1702. unsigned int data_per_frame;
  1703. data_per_frame = sdw_cdns_bra_actual_data_size(bpt_bytes);
  1704. if (!data_per_frame)
  1705. return -EINVAL;
  1706. if (command == 0) {
  1707. pdi0_buffer_size = sdw_cdns_write_pdi0_buffer_size(data_per_frame);
  1708. pdi1_buffer_size = SDW_CDNS_WRITE_PDI1_BUFFER_SIZE;
  1709. } else {
  1710. pdi0_buffer_size = SDW_CDNS_READ_PDI0_BUFFER_SIZE;
  1711. pdi1_buffer_size = sdw_cdns_read_pdi1_buffer_size(data_per_frame);
  1712. }
  1713. *tx_dma_bandwidth = pdi0_buffer_size * 8 * frame_rate;
  1714. *rx_dma_bandwidth = pdi1_buffer_size * 8 * frame_rate;
  1715. return 0;
  1716. }
  1717. EXPORT_SYMBOL(sdw_cdns_bpt_find_bandwidth);
  1718. int sdw_cdns_bpt_find_buffer_sizes(int command, /* 0: write, 1: read */
  1719. int row, int col, unsigned int data_bytes,
  1720. unsigned int requested_bytes_per_frame,
  1721. unsigned int *data_per_frame, unsigned int *pdi0_buffer_size,
  1722. unsigned int *pdi1_buffer_size, unsigned int *num_frames)
  1723. {
  1724. unsigned int bpt_bits = row * (col - 1);
  1725. unsigned int bpt_bytes = bpt_bits >> 3;
  1726. unsigned int actual_bpt_bytes;
  1727. unsigned int pdi0_tx_size;
  1728. unsigned int pdi1_rx_size;
  1729. unsigned int remainder;
  1730. if (!data_bytes)
  1731. return -EINVAL;
  1732. actual_bpt_bytes = sdw_cdns_bra_actual_data_size(bpt_bytes);
  1733. if (!actual_bpt_bytes)
  1734. return -EINVAL;
  1735. /*
  1736. * the caller may want to set the number of bytes per frame,
  1737. * allow when possible
  1738. */
  1739. if (requested_bytes_per_frame < actual_bpt_bytes)
  1740. actual_bpt_bytes = requested_bytes_per_frame;
  1741. *data_per_frame = actual_bpt_bytes;
  1742. if (data_bytes < actual_bpt_bytes)
  1743. actual_bpt_bytes = data_bytes;
  1744. if (command == 0) {
  1745. /*
  1746. * for writes we need to send all the data_bytes per frame,
  1747. * even for the last frame which may only transport fewer bytes
  1748. */
  1749. *num_frames = DIV_ROUND_UP(data_bytes, actual_bpt_bytes);
  1750. pdi0_tx_size = sdw_cdns_write_pdi0_buffer_size(actual_bpt_bytes);
  1751. pdi1_rx_size = SDW_CDNS_WRITE_PDI1_BUFFER_SIZE;
  1752. *pdi0_buffer_size = pdi0_tx_size * *num_frames;
  1753. *pdi1_buffer_size = pdi1_rx_size * *num_frames;
  1754. } else {
  1755. /*
  1756. * for reads we need to retrieve only what is requested in the BPT
  1757. * header, so the last frame needs to be special-cased
  1758. */
  1759. *num_frames = data_bytes / actual_bpt_bytes;
  1760. pdi0_tx_size = SDW_CDNS_READ_PDI0_BUFFER_SIZE;
  1761. pdi1_rx_size = sdw_cdns_read_pdi1_buffer_size(actual_bpt_bytes);
  1762. *pdi0_buffer_size = pdi0_tx_size * *num_frames;
  1763. *pdi1_buffer_size = pdi1_rx_size * *num_frames;
  1764. remainder = data_bytes % actual_bpt_bytes;
  1765. if (remainder) {
  1766. pdi0_tx_size = SDW_CDNS_READ_PDI0_BUFFER_SIZE;
  1767. pdi1_rx_size = sdw_cdns_read_pdi1_buffer_size(remainder);
  1768. *num_frames = *num_frames + 1;
  1769. *pdi0_buffer_size += pdi0_tx_size;
  1770. *pdi1_buffer_size += pdi1_rx_size;
  1771. }
  1772. }
  1773. return 0;
  1774. }
  1775. EXPORT_SYMBOL(sdw_cdns_bpt_find_buffer_sizes);
  1776. static int sdw_cdns_copy_write_data(u8 *data, int data_size, u8 *dma_buffer, int dma_buffer_size)
  1777. {
  1778. /*
  1779. * the implementation copies the data one byte at a time. Experiments with
  1780. * two bytes at a time did not seem to improve the performance
  1781. */
  1782. int i, j;
  1783. /* size check to prevent out of bounds access */
  1784. i = data_size - 1;
  1785. j = (2 * i) - (i & 1);
  1786. if (data_size & 1)
  1787. j++;
  1788. j += 2;
  1789. if (j >= dma_buffer_size)
  1790. return -EINVAL;
  1791. /* copy data */
  1792. for (i = 0; i < data_size; i++) {
  1793. j = (2 * i) - (i & 1);
  1794. dma_buffer[j] = data[i];
  1795. }
  1796. /* add required pad */
  1797. if (data_size & 1)
  1798. dma_buffer[++j] = 0;
  1799. /* skip last two bytes */
  1800. j += 2;
  1801. /* offset and data are off-by-one */
  1802. return j + 1;
  1803. }
  1804. static int sdw_cdns_prepare_write_pd0_buffer(u8 *header, unsigned int header_size,
  1805. u8 *data, unsigned int data_size,
  1806. u8 *dma_buffer, unsigned int dma_buffer_size,
  1807. unsigned int *dma_data_written,
  1808. unsigned int frame_counter)
  1809. {
  1810. int data_written;
  1811. u8 *last_byte;
  1812. u8 crc;
  1813. *dma_data_written = 0;
  1814. data_written = sdw_cdns_copy_write_data(header, header_size, dma_buffer, dma_buffer_size);
  1815. if (data_written < 0)
  1816. return data_written;
  1817. dma_buffer[3] = BIT(7);
  1818. dma_buffer[3] |= frame_counter & GENMASK(3, 0);
  1819. dma_buffer += data_written;
  1820. dma_buffer_size -= data_written;
  1821. *dma_data_written += data_written;
  1822. crc = SDW_CRC8_SEED;
  1823. crc = crc8(sdw_crc8_lookup_msb, header, header_size, crc);
  1824. data_written = sdw_cdns_copy_write_data(&crc, 1, dma_buffer, dma_buffer_size);
  1825. if (data_written < 0)
  1826. return data_written;
  1827. dma_buffer += data_written;
  1828. dma_buffer_size -= data_written;
  1829. *dma_data_written += data_written;
  1830. data_written = sdw_cdns_copy_write_data(data, data_size, dma_buffer, dma_buffer_size);
  1831. if (data_written < 0)
  1832. return data_written;
  1833. dma_buffer += data_written;
  1834. dma_buffer_size -= data_written;
  1835. *dma_data_written += data_written;
  1836. crc = SDW_CRC8_SEED;
  1837. crc = crc8(sdw_crc8_lookup_msb, data, data_size, crc);
  1838. data_written = sdw_cdns_copy_write_data(&crc, 1, dma_buffer, dma_buffer_size);
  1839. if (data_written < 0)
  1840. return data_written;
  1841. dma_buffer += data_written;
  1842. dma_buffer_size -= data_written;
  1843. *dma_data_written += data_written;
  1844. /* tag last byte */
  1845. last_byte = dma_buffer - 1;
  1846. last_byte[0] = BIT(6);
  1847. return 0;
  1848. }
  1849. static int sdw_cdns_prepare_read_pd0_buffer(u8 *header, unsigned int header_size,
  1850. u8 *dma_buffer, unsigned int dma_buffer_size,
  1851. unsigned int *dma_data_written,
  1852. unsigned int frame_counter)
  1853. {
  1854. int data_written;
  1855. u8 *last_byte;
  1856. u8 crc;
  1857. *dma_data_written = 0;
  1858. data_written = sdw_cdns_copy_write_data(header, header_size, dma_buffer, dma_buffer_size);
  1859. if (data_written < 0)
  1860. return data_written;
  1861. dma_buffer[3] = BIT(7);
  1862. dma_buffer[3] |= frame_counter & GENMASK(3, 0);
  1863. dma_buffer += data_written;
  1864. dma_buffer_size -= data_written;
  1865. *dma_data_written += data_written;
  1866. crc = SDW_CRC8_SEED;
  1867. crc = crc8(sdw_crc8_lookup_msb, header, header_size, crc);
  1868. data_written = sdw_cdns_copy_write_data(&crc, 1, dma_buffer, dma_buffer_size);
  1869. if (data_written < 0)
  1870. return data_written;
  1871. dma_buffer += data_written;
  1872. dma_buffer_size -= data_written;
  1873. *dma_data_written += data_written;
  1874. /* tag last byte */
  1875. last_byte = dma_buffer - 1;
  1876. last_byte[0] = BIT(6);
  1877. return 0;
  1878. }
  1879. #define CDNS_BPT_ROLLING_COUNTER_START 1
  1880. int sdw_cdns_prepare_write_dma_buffer(u8 dev_num, struct sdw_bpt_section *sec, int num_sec,
  1881. int data_per_frame, u8 *dma_buffer,
  1882. int dma_buffer_size, int *dma_buffer_total_bytes)
  1883. {
  1884. int total_dma_data_written = 0;
  1885. u8 *p_dma_buffer = dma_buffer;
  1886. u8 header[SDW_CDNS_BRA_HDR];
  1887. unsigned int start_register;
  1888. unsigned int section_size;
  1889. int dma_data_written;
  1890. u8 *p_data;
  1891. u8 counter;
  1892. int ret;
  1893. int i;
  1894. counter = CDNS_BPT_ROLLING_COUNTER_START;
  1895. header[0] = BIT(1); /* write command: BIT(1) set */
  1896. header[0] |= GENMASK(7, 6); /* header is active */
  1897. header[0] |= (dev_num << 2);
  1898. for (i = 0; i < num_sec; i++) {
  1899. start_register = sec[i].addr;
  1900. section_size = sec[i].len;
  1901. p_data = sec[i].buf;
  1902. while (section_size >= data_per_frame) {
  1903. header[1] = data_per_frame;
  1904. header[2] = start_register >> 24 & 0xFF;
  1905. header[3] = start_register >> 16 & 0xFF;
  1906. header[4] = start_register >> 8 & 0xFF;
  1907. header[5] = start_register >> 0 & 0xFF;
  1908. ret = sdw_cdns_prepare_write_pd0_buffer(header, SDW_CDNS_BRA_HDR,
  1909. p_data, data_per_frame,
  1910. p_dma_buffer, dma_buffer_size,
  1911. &dma_data_written, counter);
  1912. if (ret < 0)
  1913. return ret;
  1914. counter++;
  1915. p_data += data_per_frame;
  1916. section_size -= data_per_frame;
  1917. p_dma_buffer += dma_data_written;
  1918. dma_buffer_size -= dma_data_written;
  1919. total_dma_data_written += dma_data_written;
  1920. start_register += data_per_frame;
  1921. }
  1922. if (section_size) {
  1923. header[1] = section_size;
  1924. header[2] = start_register >> 24 & 0xFF;
  1925. header[3] = start_register >> 16 & 0xFF;
  1926. header[4] = start_register >> 8 & 0xFF;
  1927. header[5] = start_register >> 0 & 0xFF;
  1928. ret = sdw_cdns_prepare_write_pd0_buffer(header, SDW_CDNS_BRA_HDR,
  1929. p_data, section_size,
  1930. p_dma_buffer, dma_buffer_size,
  1931. &dma_data_written, counter);
  1932. if (ret < 0)
  1933. return ret;
  1934. counter++;
  1935. p_dma_buffer += dma_data_written;
  1936. dma_buffer_size -= dma_data_written;
  1937. total_dma_data_written += dma_data_written;
  1938. }
  1939. }
  1940. *dma_buffer_total_bytes = total_dma_data_written;
  1941. return 0;
  1942. }
  1943. EXPORT_SYMBOL(sdw_cdns_prepare_write_dma_buffer);
  1944. int sdw_cdns_prepare_read_dma_buffer(u8 dev_num, struct sdw_bpt_section *sec, int num_sec,
  1945. int data_per_frame, u8 *dma_buffer, int dma_buffer_size,
  1946. int *dma_buffer_total_bytes, unsigned int fake_size)
  1947. {
  1948. int total_dma_data_written = 0;
  1949. u8 *p_dma_buffer = dma_buffer;
  1950. u8 header[SDW_CDNS_BRA_HDR];
  1951. unsigned int start_register;
  1952. unsigned int data_size;
  1953. int dma_data_written;
  1954. u8 counter;
  1955. int ret;
  1956. int i;
  1957. counter = CDNS_BPT_ROLLING_COUNTER_START;
  1958. header[0] = 0; /* read command: BIT(1) cleared */
  1959. header[0] |= GENMASK(7, 6); /* header is active */
  1960. header[0] |= (dev_num << 2);
  1961. for (i = 0; i < num_sec; i++) {
  1962. start_register = sec[i].addr;
  1963. data_size = sec[i].len;
  1964. while (data_size >= data_per_frame) {
  1965. header[1] = data_per_frame;
  1966. header[2] = start_register >> 24 & 0xFF;
  1967. header[3] = start_register >> 16 & 0xFF;
  1968. header[4] = start_register >> 8 & 0xFF;
  1969. header[5] = start_register >> 0 & 0xFF;
  1970. ret = sdw_cdns_prepare_read_pd0_buffer(header, SDW_CDNS_BRA_HDR,
  1971. p_dma_buffer, dma_buffer_size,
  1972. &dma_data_written, counter);
  1973. if (ret < 0)
  1974. return ret;
  1975. counter++;
  1976. data_size -= data_per_frame;
  1977. p_dma_buffer += dma_data_written;
  1978. dma_buffer_size -= dma_data_written;
  1979. total_dma_data_written += dma_data_written;
  1980. start_register += data_per_frame;
  1981. }
  1982. if (data_size) {
  1983. header[1] = data_size;
  1984. header[2] = start_register >> 24 & 0xFF;
  1985. header[3] = start_register >> 16 & 0xFF;
  1986. header[4] = start_register >> 8 & 0xFF;
  1987. header[5] = start_register >> 0 & 0xFF;
  1988. ret = sdw_cdns_prepare_read_pd0_buffer(header, SDW_CDNS_BRA_HDR,
  1989. p_dma_buffer, dma_buffer_size,
  1990. &dma_data_written, counter);
  1991. if (ret < 0)
  1992. return ret;
  1993. counter++;
  1994. p_dma_buffer += dma_data_written;
  1995. dma_buffer_size -= dma_data_written;
  1996. total_dma_data_written += dma_data_written;
  1997. }
  1998. }
  1999. /* Add fake frame */
  2000. header[0] &= ~GENMASK(7, 6); /* Set inactive flag in BPT/BRA frame heade */
  2001. while (fake_size >= data_per_frame) {
  2002. header[1] = data_per_frame;
  2003. ret = sdw_cdns_prepare_read_pd0_buffer(header, SDW_CDNS_BRA_HDR, p_dma_buffer,
  2004. dma_buffer_size, &dma_data_written,
  2005. counter);
  2006. if (ret < 0)
  2007. return ret;
  2008. counter++;
  2009. fake_size -= data_per_frame;
  2010. p_dma_buffer += dma_data_written;
  2011. dma_buffer_size -= dma_data_written;
  2012. total_dma_data_written += dma_data_written;
  2013. }
  2014. if (fake_size) {
  2015. header[1] = fake_size;
  2016. ret = sdw_cdns_prepare_read_pd0_buffer(header, SDW_CDNS_BRA_HDR, p_dma_buffer,
  2017. dma_buffer_size, &dma_data_written,
  2018. counter);
  2019. if (ret < 0)
  2020. return ret;
  2021. counter++;
  2022. p_dma_buffer += dma_data_written;
  2023. dma_buffer_size -= dma_data_written;
  2024. total_dma_data_written += dma_data_written;
  2025. }
  2026. *dma_buffer_total_bytes = total_dma_data_written;
  2027. return 0;
  2028. }
  2029. EXPORT_SYMBOL(sdw_cdns_prepare_read_dma_buffer);
  2030. static int check_counter(u32 val, u8 counter)
  2031. {
  2032. u8 frame;
  2033. frame = (val >> 24) & GENMASK(3, 0);
  2034. if (counter != frame)
  2035. return -EIO;
  2036. return 0;
  2037. }
  2038. static int check_response(u32 val)
  2039. {
  2040. u8 response;
  2041. response = (val >> 3) & GENMASK(1, 0);
  2042. if (response == 0) /* Ignored */
  2043. return -ENODATA;
  2044. if (response != 1) /* ACK */
  2045. return -EIO;
  2046. return 0;
  2047. }
  2048. static int check_frame_start(u32 header, u8 counter)
  2049. {
  2050. int ret;
  2051. /* check frame_start marker */
  2052. if (!(header & BIT(31)))
  2053. return -EIO;
  2054. ret = check_counter(header, counter);
  2055. if (ret < 0)
  2056. return ret;
  2057. return check_response(header);
  2058. }
  2059. static int check_frame_end(u32 footer)
  2060. {
  2061. /* check frame_end marker */
  2062. if (!(footer & BIT(30)))
  2063. return -EIO;
  2064. return check_response(footer);
  2065. }
  2066. int sdw_cdns_check_write_response(struct device *dev, u8 *dma_buffer,
  2067. int dma_buffer_size, int num_frames)
  2068. {
  2069. u32 *p_data;
  2070. int counter;
  2071. u32 header;
  2072. u32 footer;
  2073. int ret;
  2074. int i;
  2075. /* paranoia check on buffer size */
  2076. if (dma_buffer_size != num_frames * 8)
  2077. return -EINVAL;
  2078. counter = CDNS_BPT_ROLLING_COUNTER_START;
  2079. p_data = (u32 *)dma_buffer;
  2080. for (i = 0; i < num_frames; i++) {
  2081. header = *p_data++;
  2082. footer = *p_data++;
  2083. ret = check_frame_start(header, counter);
  2084. if (ret < 0) {
  2085. dev_err(dev, "%s: bad frame %d/%d start header %x\n",
  2086. __func__, i + 1, num_frames, header);
  2087. return ret;
  2088. }
  2089. ret = check_frame_end(footer);
  2090. if (ret < 0) {
  2091. dev_err(dev, "%s: bad frame %d/%d end footer %x\n",
  2092. __func__, i + 1, num_frames, footer);
  2093. return ret;
  2094. }
  2095. counter++;
  2096. counter &= GENMASK(3, 0);
  2097. }
  2098. return 0;
  2099. }
  2100. EXPORT_SYMBOL(sdw_cdns_check_write_response);
  2101. static u8 extract_read_data(u32 *data, int num_bytes, u8 *buffer)
  2102. {
  2103. u32 val;
  2104. int i;
  2105. u8 crc;
  2106. u8 b0;
  2107. u8 b1;
  2108. crc = SDW_CRC8_SEED;
  2109. /* process two bytes at a time */
  2110. for (i = 0; i < num_bytes / 2; i++) {
  2111. val = *data++;
  2112. b0 = val & 0xff;
  2113. b1 = (val >> 8) & 0xff;
  2114. *buffer++ = b0;
  2115. crc = crc8(sdw_crc8_lookup_msb, &b0, 1, crc);
  2116. *buffer++ = b1;
  2117. crc = crc8(sdw_crc8_lookup_msb, &b1, 1, crc);
  2118. }
  2119. /* handle remaining byte if it exists */
  2120. if (num_bytes & 1) {
  2121. val = *data;
  2122. b0 = val & 0xff;
  2123. *buffer++ = b0;
  2124. crc = crc8(sdw_crc8_lookup_msb, &b0, 1, crc);
  2125. }
  2126. return crc;
  2127. }
  2128. int sdw_cdns_check_read_response(struct device *dev, u8 *dma_buffer, int dma_buffer_size,
  2129. struct sdw_bpt_section *sec, int num_sec, int num_frames,
  2130. int data_per_frame)
  2131. {
  2132. int total_num_bytes = 0;
  2133. int buffer_size = 0;
  2134. int sec_index;
  2135. u32 *p_data;
  2136. u8 *p_buf;
  2137. int counter;
  2138. u32 header;
  2139. u32 footer;
  2140. u8 expected_crc;
  2141. u8 crc;
  2142. int len;
  2143. int ret;
  2144. int i;
  2145. counter = CDNS_BPT_ROLLING_COUNTER_START;
  2146. p_data = (u32 *)dma_buffer;
  2147. sec_index = 0;
  2148. p_buf = sec[sec_index].buf;
  2149. buffer_size = sec[sec_index].len;
  2150. for (i = 0; i < num_frames; i++) {
  2151. header = *p_data++;
  2152. ret = check_frame_start(header, counter);
  2153. if (ret < 0) {
  2154. dev_err(dev, "%s: bad frame %d/%d start header %x\n",
  2155. __func__, i + 1, num_frames, header);
  2156. return ret;
  2157. }
  2158. len = data_per_frame;
  2159. if (total_num_bytes + data_per_frame > buffer_size)
  2160. len = buffer_size - total_num_bytes;
  2161. crc = extract_read_data(p_data, len, p_buf);
  2162. p_data += (len + 1) / 2;
  2163. expected_crc = *p_data++ & 0xff;
  2164. if (crc != expected_crc) {
  2165. dev_err(dev, "%s: bad frame %d/%d crc %#x expected %#x\n",
  2166. __func__, i + 1, num_frames, crc, expected_crc);
  2167. return -EIO;
  2168. }
  2169. p_buf += len;
  2170. total_num_bytes += len;
  2171. footer = *p_data++;
  2172. ret = check_frame_end(footer);
  2173. if (ret < 0) {
  2174. dev_err(dev, "%s: bad frame %d/%d end footer %x\n",
  2175. __func__, i + 1, num_frames, footer);
  2176. return ret;
  2177. }
  2178. counter++;
  2179. counter &= GENMASK(3, 0);
  2180. if (buffer_size == total_num_bytes && (i + 1) < num_frames) {
  2181. sec_index++;
  2182. if (sec_index >= num_sec) {
  2183. dev_err(dev, "%s: incorrect section index %d i %d\n",
  2184. __func__, sec_index, i);
  2185. return -EINVAL;
  2186. }
  2187. p_buf = sec[sec_index].buf;
  2188. buffer_size = sec[sec_index].len;
  2189. total_num_bytes = 0;
  2190. }
  2191. }
  2192. return 0;
  2193. }
  2194. EXPORT_SYMBOL(sdw_cdns_check_read_response);
  2195. MODULE_LICENSE("Dual BSD/GPL");
  2196. MODULE_DESCRIPTION("Cadence Soundwire Library");