qcom_aoss.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019, Linaro Ltd
  4. */
  5. #include <linux/clk-provider.h>
  6. #include <linux/debugfs.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/mailbox_client.h>
  10. #include <linux/module.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/thermal.h>
  14. #include <linux/slab.h>
  15. #include <linux/string_choices.h>
  16. #include <linux/soc/qcom/qcom_aoss.h>
  17. #define CREATE_TRACE_POINTS
  18. #include "trace-aoss.h"
  19. #define QMP_DESC_MAGIC 0x0
  20. #define QMP_DESC_VERSION 0x4
  21. #define QMP_DESC_FEATURES 0x8
  22. /* AOP-side offsets */
  23. #define QMP_DESC_UCORE_LINK_STATE 0xc
  24. #define QMP_DESC_UCORE_LINK_STATE_ACK 0x10
  25. #define QMP_DESC_UCORE_CH_STATE 0x14
  26. #define QMP_DESC_UCORE_CH_STATE_ACK 0x18
  27. #define QMP_DESC_UCORE_MBOX_SIZE 0x1c
  28. #define QMP_DESC_UCORE_MBOX_OFFSET 0x20
  29. /* Linux-side offsets */
  30. #define QMP_DESC_MCORE_LINK_STATE 0x24
  31. #define QMP_DESC_MCORE_LINK_STATE_ACK 0x28
  32. #define QMP_DESC_MCORE_CH_STATE 0x2c
  33. #define QMP_DESC_MCORE_CH_STATE_ACK 0x30
  34. #define QMP_DESC_MCORE_MBOX_SIZE 0x34
  35. #define QMP_DESC_MCORE_MBOX_OFFSET 0x38
  36. #define QMP_STATE_UP GENMASK(15, 0)
  37. #define QMP_STATE_DOWN GENMASK(31, 16)
  38. #define QMP_MAGIC 0x4d41494c /* mail */
  39. #define QMP_VERSION 1
  40. /* 64 bytes is enough to store the requests and provides padding to 4 bytes */
  41. #define QMP_MSG_LEN 64
  42. #define QMP_NUM_COOLING_RESOURCES 2
  43. #define QMP_DEBUGFS_FILES 4
  44. static bool qmp_cdev_max_state = 1;
  45. struct qmp_cooling_device {
  46. struct thermal_cooling_device *cdev;
  47. struct qmp *qmp;
  48. char *name;
  49. bool state;
  50. };
  51. /**
  52. * struct qmp - driver state for QMP implementation
  53. * @msgram: iomem referencing the message RAM used for communication
  54. * @dev: reference to QMP device
  55. * @mbox_client: mailbox client used to ring the doorbell on transmit
  56. * @mbox_chan: mailbox channel used to ring the doorbell on transmit
  57. * @offset: offset within @msgram where messages should be written
  58. * @size: maximum size of the messages to be transmitted
  59. * @event: wait_queue for synchronization with the IRQ
  60. * @tx_lock: provides synchronization between multiple callers of qmp_send()
  61. * @qdss_clk: QDSS clock hw struct
  62. * @cooling_devs: thermal cooling devices
  63. * @debugfs_root: directory for the developer/tester interface
  64. * @debugfs_files: array of individual debugfs entries under debugfs_root
  65. */
  66. struct qmp {
  67. void __iomem *msgram;
  68. struct device *dev;
  69. struct mbox_client mbox_client;
  70. struct mbox_chan *mbox_chan;
  71. size_t offset;
  72. size_t size;
  73. wait_queue_head_t event;
  74. struct mutex tx_lock;
  75. struct clk_hw qdss_clk;
  76. struct qmp_cooling_device *cooling_devs;
  77. struct dentry *debugfs_root;
  78. struct dentry *debugfs_files[QMP_DEBUGFS_FILES];
  79. };
  80. static void qmp_kick(struct qmp *qmp)
  81. {
  82. mbox_send_message(qmp->mbox_chan, NULL);
  83. mbox_client_txdone(qmp->mbox_chan, 0);
  84. }
  85. static bool qmp_magic_valid(struct qmp *qmp)
  86. {
  87. return readl(qmp->msgram + QMP_DESC_MAGIC) == QMP_MAGIC;
  88. }
  89. static bool qmp_link_acked(struct qmp *qmp)
  90. {
  91. return readl(qmp->msgram + QMP_DESC_MCORE_LINK_STATE_ACK) == QMP_STATE_UP;
  92. }
  93. static bool qmp_mcore_channel_acked(struct qmp *qmp)
  94. {
  95. return readl(qmp->msgram + QMP_DESC_MCORE_CH_STATE_ACK) == QMP_STATE_UP;
  96. }
  97. static bool qmp_ucore_channel_up(struct qmp *qmp)
  98. {
  99. return readl(qmp->msgram + QMP_DESC_UCORE_CH_STATE) == QMP_STATE_UP;
  100. }
  101. static int qmp_open(struct qmp *qmp)
  102. {
  103. int ret;
  104. u32 val;
  105. if (!qmp_magic_valid(qmp)) {
  106. dev_err(qmp->dev, "QMP magic doesn't match\n");
  107. return -EINVAL;
  108. }
  109. val = readl(qmp->msgram + QMP_DESC_VERSION);
  110. if (val != QMP_VERSION) {
  111. dev_err(qmp->dev, "unsupported QMP version %d\n", val);
  112. return -EINVAL;
  113. }
  114. qmp->offset = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_OFFSET);
  115. qmp->size = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_SIZE);
  116. if (!qmp->size) {
  117. dev_err(qmp->dev, "invalid mailbox size\n");
  118. return -EINVAL;
  119. }
  120. /* Ack remote core's link state */
  121. val = readl(qmp->msgram + QMP_DESC_UCORE_LINK_STATE);
  122. writel(val, qmp->msgram + QMP_DESC_UCORE_LINK_STATE_ACK);
  123. /* Set local core's link state to up */
  124. writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
  125. qmp_kick(qmp);
  126. ret = wait_event_timeout(qmp->event, qmp_link_acked(qmp), HZ);
  127. if (!ret) {
  128. dev_err(qmp->dev, "ucore didn't ack link\n");
  129. goto timeout_close_link;
  130. }
  131. writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
  132. qmp_kick(qmp);
  133. ret = wait_event_timeout(qmp->event, qmp_ucore_channel_up(qmp), HZ);
  134. if (!ret) {
  135. dev_err(qmp->dev, "ucore didn't open channel\n");
  136. goto timeout_close_channel;
  137. }
  138. /* Ack remote core's channel state */
  139. writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_UCORE_CH_STATE_ACK);
  140. qmp_kick(qmp);
  141. ret = wait_event_timeout(qmp->event, qmp_mcore_channel_acked(qmp), HZ);
  142. if (!ret) {
  143. dev_err(qmp->dev, "ucore didn't ack channel\n");
  144. goto timeout_close_channel;
  145. }
  146. return 0;
  147. timeout_close_channel:
  148. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
  149. timeout_close_link:
  150. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
  151. qmp_kick(qmp);
  152. return -ETIMEDOUT;
  153. }
  154. static void qmp_close(struct qmp *qmp)
  155. {
  156. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
  157. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
  158. qmp_kick(qmp);
  159. }
  160. static irqreturn_t qmp_intr(int irq, void *data)
  161. {
  162. struct qmp *qmp = data;
  163. wake_up_all(&qmp->event);
  164. return IRQ_HANDLED;
  165. }
  166. static bool qmp_message_empty(struct qmp *qmp)
  167. {
  168. return readl(qmp->msgram + qmp->offset) == 0;
  169. }
  170. /**
  171. * qmp_send() - send a message to the AOSS
  172. * @qmp: qmp context
  173. * @fmt: format string for message to be sent
  174. * @...: arguments for the format string
  175. *
  176. * Transmit message to AOSS and wait for the AOSS to acknowledge the message.
  177. * data must not be longer than the mailbox size. Access is synchronized by
  178. * this implementation.
  179. *
  180. * Return: 0 on success, negative errno on failure
  181. */
  182. int __printf(2, 3) qmp_send(struct qmp *qmp, const char *fmt, ...)
  183. {
  184. char buf[QMP_MSG_LEN];
  185. long time_left;
  186. va_list args;
  187. int len;
  188. int ret;
  189. if (WARN_ON(IS_ERR_OR_NULL(qmp) || !fmt))
  190. return -EINVAL;
  191. memset(buf, 0, sizeof(buf));
  192. va_start(args, fmt);
  193. len = vsnprintf(buf, sizeof(buf), fmt, args);
  194. va_end(args);
  195. if (WARN_ON(len >= sizeof(buf)))
  196. return -EINVAL;
  197. mutex_lock(&qmp->tx_lock);
  198. trace_aoss_send(buf);
  199. /* The message RAM only implements 32-bit accesses */
  200. __iowrite32_copy(qmp->msgram + qmp->offset + sizeof(u32),
  201. buf, sizeof(buf) / sizeof(u32));
  202. writel(sizeof(buf), qmp->msgram + qmp->offset);
  203. /* Read back length to confirm data written in message RAM */
  204. readl(qmp->msgram + qmp->offset);
  205. qmp_kick(qmp);
  206. time_left = wait_event_interruptible_timeout(qmp->event,
  207. qmp_message_empty(qmp), HZ);
  208. if (!time_left) {
  209. dev_err(qmp->dev, "ucore did not ack channel\n");
  210. ret = -ETIMEDOUT;
  211. /* Clear message from buffer */
  212. writel(0, qmp->msgram + qmp->offset);
  213. } else {
  214. ret = 0;
  215. }
  216. trace_aoss_send_done(buf, ret);
  217. mutex_unlock(&qmp->tx_lock);
  218. return ret;
  219. }
  220. EXPORT_SYMBOL_GPL(qmp_send);
  221. static int qmp_qdss_clk_prepare(struct clk_hw *hw)
  222. {
  223. static const char *buf = "{class: clock, res: qdss, val: 1}";
  224. struct qmp *qmp = container_of(hw, struct qmp, qdss_clk);
  225. return qmp_send(qmp, buf);
  226. }
  227. static void qmp_qdss_clk_unprepare(struct clk_hw *hw)
  228. {
  229. static const char *buf = "{class: clock, res: qdss, val: 0}";
  230. struct qmp *qmp = container_of(hw, struct qmp, qdss_clk);
  231. qmp_send(qmp, buf);
  232. }
  233. static const struct clk_ops qmp_qdss_clk_ops = {
  234. .prepare = qmp_qdss_clk_prepare,
  235. .unprepare = qmp_qdss_clk_unprepare,
  236. };
  237. static int qmp_qdss_clk_add(struct qmp *qmp)
  238. {
  239. static const struct clk_init_data qdss_init = {
  240. .ops = &qmp_qdss_clk_ops,
  241. .name = "qdss",
  242. };
  243. int ret;
  244. qmp->qdss_clk.init = &qdss_init;
  245. ret = clk_hw_register(qmp->dev, &qmp->qdss_clk);
  246. if (ret < 0) {
  247. dev_err(qmp->dev, "failed to register qdss clock\n");
  248. return ret;
  249. }
  250. ret = of_clk_add_hw_provider(qmp->dev->of_node, of_clk_hw_simple_get,
  251. &qmp->qdss_clk);
  252. if (ret < 0) {
  253. dev_err(qmp->dev, "unable to register of clk hw provider\n");
  254. clk_hw_unregister(&qmp->qdss_clk);
  255. }
  256. return ret;
  257. }
  258. static void qmp_qdss_clk_remove(struct qmp *qmp)
  259. {
  260. of_clk_del_provider(qmp->dev->of_node);
  261. clk_hw_unregister(&qmp->qdss_clk);
  262. }
  263. static int qmp_cdev_get_max_state(struct thermal_cooling_device *cdev,
  264. unsigned long *state)
  265. {
  266. *state = qmp_cdev_max_state;
  267. return 0;
  268. }
  269. static int qmp_cdev_get_cur_state(struct thermal_cooling_device *cdev,
  270. unsigned long *state)
  271. {
  272. struct qmp_cooling_device *qmp_cdev = cdev->devdata;
  273. *state = qmp_cdev->state;
  274. return 0;
  275. }
  276. static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev,
  277. unsigned long state)
  278. {
  279. struct qmp_cooling_device *qmp_cdev = cdev->devdata;
  280. bool cdev_state;
  281. int ret;
  282. /* Normalize state */
  283. cdev_state = !!state;
  284. if (qmp_cdev->state == state)
  285. return 0;
  286. ret = qmp_send(qmp_cdev->qmp, "{class: volt_flr, event:zero_temp, res:%s, value:%s}",
  287. qmp_cdev->name, str_on_off(cdev_state));
  288. if (!ret)
  289. qmp_cdev->state = cdev_state;
  290. return ret;
  291. }
  292. static const struct thermal_cooling_device_ops qmp_cooling_device_ops = {
  293. .get_max_state = qmp_cdev_get_max_state,
  294. .get_cur_state = qmp_cdev_get_cur_state,
  295. .set_cur_state = qmp_cdev_set_cur_state,
  296. };
  297. static int qmp_cooling_device_add(struct qmp *qmp,
  298. struct qmp_cooling_device *qmp_cdev,
  299. struct device_node *node)
  300. {
  301. char *cdev_name = (char *)node->name;
  302. qmp_cdev->qmp = qmp;
  303. qmp_cdev->state = !qmp_cdev_max_state;
  304. qmp_cdev->name = cdev_name;
  305. qmp_cdev->cdev = devm_thermal_of_cooling_device_register
  306. (qmp->dev, node,
  307. cdev_name,
  308. qmp_cdev, &qmp_cooling_device_ops);
  309. if (IS_ERR(qmp_cdev->cdev))
  310. dev_err(qmp->dev, "unable to register %s cooling device\n",
  311. cdev_name);
  312. return PTR_ERR_OR_ZERO(qmp_cdev->cdev);
  313. }
  314. static int qmp_cooling_devices_register(struct qmp *qmp)
  315. {
  316. struct device_node *np;
  317. int count = 0;
  318. int ret;
  319. np = qmp->dev->of_node;
  320. qmp->cooling_devs = devm_kcalloc(qmp->dev, QMP_NUM_COOLING_RESOURCES,
  321. sizeof(*qmp->cooling_devs),
  322. GFP_KERNEL);
  323. if (!qmp->cooling_devs)
  324. return -ENOMEM;
  325. for_each_available_child_of_node_scoped(np, child) {
  326. if (!of_property_present(child, "#cooling-cells"))
  327. continue;
  328. ret = qmp_cooling_device_add(qmp, &qmp->cooling_devs[count++],
  329. child);
  330. if (ret)
  331. goto unroll;
  332. }
  333. if (!count)
  334. devm_kfree(qmp->dev, qmp->cooling_devs);
  335. return 0;
  336. unroll:
  337. while (--count >= 0)
  338. thermal_cooling_device_unregister
  339. (qmp->cooling_devs[count].cdev);
  340. devm_kfree(qmp->dev, qmp->cooling_devs);
  341. return ret;
  342. }
  343. static void qmp_cooling_devices_remove(struct qmp *qmp)
  344. {
  345. int i;
  346. for (i = 0; i < QMP_NUM_COOLING_RESOURCES; i++)
  347. thermal_cooling_device_unregister(qmp->cooling_devs[i].cdev);
  348. }
  349. /**
  350. * qmp_get() - get a qmp handle from a device
  351. * @dev: client device pointer
  352. *
  353. * Return: handle to qmp device on success, ERR_PTR() on failure
  354. */
  355. struct qmp *qmp_get(struct device *dev)
  356. {
  357. struct platform_device *pdev;
  358. struct device_node *np;
  359. struct qmp *qmp;
  360. if (!dev || !dev->of_node)
  361. return ERR_PTR(-EINVAL);
  362. np = of_parse_phandle(dev->of_node, "qcom,qmp", 0);
  363. if (!np)
  364. return ERR_PTR(-ENODEV);
  365. pdev = of_find_device_by_node(np);
  366. of_node_put(np);
  367. if (!pdev)
  368. return ERR_PTR(-EINVAL);
  369. qmp = platform_get_drvdata(pdev);
  370. if (!qmp) {
  371. put_device(&pdev->dev);
  372. return ERR_PTR(-EPROBE_DEFER);
  373. }
  374. return qmp;
  375. }
  376. EXPORT_SYMBOL_GPL(qmp_get);
  377. /**
  378. * qmp_put() - release a qmp handle
  379. * @qmp: qmp handle obtained from qmp_get()
  380. */
  381. void qmp_put(struct qmp *qmp)
  382. {
  383. /*
  384. * Match get_device() inside of_find_device_by_node() in
  385. * qmp_get()
  386. */
  387. if (!IS_ERR_OR_NULL(qmp))
  388. put_device(qmp->dev);
  389. }
  390. EXPORT_SYMBOL_GPL(qmp_put);
  391. struct qmp_debugfs_entry {
  392. const char *name;
  393. const char *fmt;
  394. bool is_bool;
  395. const char *true_val;
  396. const char *false_val;
  397. };
  398. static const struct qmp_debugfs_entry qmp_debugfs_entries[QMP_DEBUGFS_FILES] = {
  399. { "ddr_frequency_mhz", "{class: ddr, res: fixed, val: %u}", false },
  400. { "prevent_aoss_sleep", "{class: aoss_slp, res: sleep: %s}", true, "enable", "disable" },
  401. { "prevent_cx_collapse", "{class: cx_mol, res: cx, val: %s}", true, "mol", "off" },
  402. { "prevent_ddr_collapse", "{class: ddr_mol, res: ddr, val: %s}", true, "mol", "off" },
  403. };
  404. static ssize_t qmp_debugfs_write(struct file *file, const char __user *user_buf,
  405. size_t count, loff_t *pos)
  406. {
  407. const struct qmp_debugfs_entry *entry = NULL;
  408. struct qmp *qmp = file->private_data;
  409. char buf[QMP_MSG_LEN];
  410. unsigned int uint_val;
  411. const char *str_val;
  412. bool bool_val;
  413. int ret;
  414. int i;
  415. for (i = 0; i < ARRAY_SIZE(qmp->debugfs_files); i++) {
  416. if (qmp->debugfs_files[i] == file->f_path.dentry) {
  417. entry = &qmp_debugfs_entries[i];
  418. break;
  419. }
  420. }
  421. if (WARN_ON(!entry))
  422. return -EFAULT;
  423. if (entry->is_bool) {
  424. ret = kstrtobool_from_user(user_buf, count, &bool_val);
  425. if (ret)
  426. return ret;
  427. str_val = bool_val ? entry->true_val : entry->false_val;
  428. ret = snprintf(buf, sizeof(buf), entry->fmt, str_val);
  429. if (ret >= sizeof(buf))
  430. return -EINVAL;
  431. } else {
  432. ret = kstrtou32_from_user(user_buf, count, 0, &uint_val);
  433. if (ret)
  434. return ret;
  435. ret = snprintf(buf, sizeof(buf), entry->fmt, uint_val);
  436. if (ret >= sizeof(buf))
  437. return -EINVAL;
  438. }
  439. ret = qmp_send(qmp, buf);
  440. if (ret < 0)
  441. return ret;
  442. return count;
  443. }
  444. static const struct file_operations qmp_debugfs_fops = {
  445. .open = simple_open,
  446. .write = qmp_debugfs_write,
  447. };
  448. static void qmp_debugfs_create(struct qmp *qmp)
  449. {
  450. const struct qmp_debugfs_entry *entry;
  451. int i;
  452. qmp->debugfs_root = debugfs_create_dir("qcom_aoss", NULL);
  453. for (i = 0; i < ARRAY_SIZE(qmp->debugfs_files); i++) {
  454. entry = &qmp_debugfs_entries[i];
  455. qmp->debugfs_files[i] = debugfs_create_file(entry->name, 0200,
  456. qmp->debugfs_root,
  457. qmp,
  458. &qmp_debugfs_fops);
  459. }
  460. }
  461. static int qmp_probe(struct platform_device *pdev)
  462. {
  463. struct qmp *qmp;
  464. int irq;
  465. int ret;
  466. qmp = devm_kzalloc(&pdev->dev, sizeof(*qmp), GFP_KERNEL);
  467. if (!qmp)
  468. return -ENOMEM;
  469. qmp->dev = &pdev->dev;
  470. init_waitqueue_head(&qmp->event);
  471. mutex_init(&qmp->tx_lock);
  472. qmp->msgram = devm_platform_ioremap_resource(pdev, 0);
  473. if (IS_ERR(qmp->msgram))
  474. return PTR_ERR(qmp->msgram);
  475. qmp->mbox_client.dev = &pdev->dev;
  476. qmp->mbox_client.knows_txdone = true;
  477. qmp->mbox_chan = mbox_request_channel(&qmp->mbox_client, 0);
  478. if (IS_ERR(qmp->mbox_chan)) {
  479. dev_err(&pdev->dev, "failed to acquire ipc mailbox\n");
  480. return PTR_ERR(qmp->mbox_chan);
  481. }
  482. irq = platform_get_irq(pdev, 0);
  483. ret = devm_request_irq(&pdev->dev, irq, qmp_intr, 0,
  484. "aoss-qmp", qmp);
  485. if (ret < 0) {
  486. dev_err(&pdev->dev, "failed to request interrupt\n");
  487. goto err_free_mbox;
  488. }
  489. ret = qmp_open(qmp);
  490. if (ret < 0)
  491. goto err_free_mbox;
  492. ret = qmp_qdss_clk_add(qmp);
  493. if (ret)
  494. goto err_close_qmp;
  495. ret = qmp_cooling_devices_register(qmp);
  496. if (ret)
  497. dev_err(&pdev->dev, "failed to register aoss cooling devices\n");
  498. platform_set_drvdata(pdev, qmp);
  499. qmp_debugfs_create(qmp);
  500. return 0;
  501. err_close_qmp:
  502. qmp_close(qmp);
  503. err_free_mbox:
  504. mbox_free_channel(qmp->mbox_chan);
  505. return ret;
  506. }
  507. static void qmp_remove(struct platform_device *pdev)
  508. {
  509. struct qmp *qmp = platform_get_drvdata(pdev);
  510. debugfs_remove_recursive(qmp->debugfs_root);
  511. qmp_qdss_clk_remove(qmp);
  512. qmp_cooling_devices_remove(qmp);
  513. qmp_close(qmp);
  514. mbox_free_channel(qmp->mbox_chan);
  515. }
  516. static const struct of_device_id qmp_dt_match[] = {
  517. { .compatible = "qcom,sc7180-aoss-qmp", },
  518. { .compatible = "qcom,sc7280-aoss-qmp", },
  519. { .compatible = "qcom,sdm845-aoss-qmp", },
  520. { .compatible = "qcom,sm8150-aoss-qmp", },
  521. { .compatible = "qcom,sm8250-aoss-qmp", },
  522. { .compatible = "qcom,sm8350-aoss-qmp", },
  523. { .compatible = "qcom,aoss-qmp", },
  524. {}
  525. };
  526. MODULE_DEVICE_TABLE(of, qmp_dt_match);
  527. static struct platform_driver qmp_driver = {
  528. .driver = {
  529. .name = "qcom_aoss_qmp",
  530. .of_match_table = qmp_dt_match,
  531. .suppress_bind_attrs = true,
  532. },
  533. .probe = qmp_probe,
  534. .remove = qmp_remove,
  535. };
  536. module_platform_driver(qmp_driver);
  537. MODULE_DESCRIPTION("Qualcomm AOSS QMP driver");
  538. MODULE_LICENSE("GPL v2");