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mt8365-mmsys.h

mt8365-mmsys.h 2.7 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. 

  3. #ifndef __SOC_MEDIATEK_MT8365_MMSYS_H
    4. 

  4. #define __SOC_MEDIATEK_MT8365_MMSYS_H
    5. 

  5. 

  6. #define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0xf3c
    7. 

  7. #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL	0xf4c
    8. 

  8. #define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN	0xf50
    9. 

  9. #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN	0xf54
    10. 

  10. #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN	0xf60
    11. 

  11. #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0xf64
    12. 

  12. #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN		0xf68
    13. 

  13. #define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL	0xfd0
    14. 

  14. #define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN		0xfd8
    15. 

  15. #define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00	0xfdc
    16. 

  16. 

  17. #define MT8365_DISP_MS_IN_OUT_MASK			GENMASK(3, 0)
    18. 

  18. #define MT8365_RDMA0_SOUT_COLOR0			0x1
    19. 

  19. #define MT8365_DITHER_MOUT_EN_DSI0			BIT(0)
    20. 

  20. #define MT8365_DSI0_SEL_IN_DITHER			0x1
    21. 

  21. #define MT8365_RDMA0_SEL_IN_OVL0			0x0
    22. 

  22. #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0			0x0
    23. 

  23. #define MT8365_DISP_COLOR_SEL_IN_COLOR0			0x0
    24. 

  24. #define MT8365_OVL0_MOUT_PATH0_SEL			BIT(0)
    25. 

  25. #define MT8365_RDMA1_SOUT_DPI0				0x1
    26. 

  26. #define MT8365_DPI0_SEL_IN_RDMA1			0x0
    27. 

  27. #define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK		0x1
    28. 

  28. #define MT8365_DPI0_SEL_IN_RDMA1			0x0
    29. 

  29. 

  30. static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
    31. 

  31. 	MMSYS_ROUTE(OVL0, RDMA0,
    32. 

  32. 		    MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
    33. 

  33. 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL),
    34. 

  34. 	MMSYS_ROUTE(OVL0, RDMA0,
    35. 

  35. 		    MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
    36. 

  36. 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0),
    37. 

  37. 	MMSYS_ROUTE(RDMA0, COLOR0,
    38. 

  38. 		    MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
    39. 

  39. 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0),
    40. 

  40. 	MMSYS_ROUTE(COLOR0, CCORR,
    41. 

  41. 		    MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
    42. 

  42. 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0),
    43. 

  43. 	MMSYS_ROUTE(DITHER0, DSI0,
    44. 

  44. 		    MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
    45. 

  45. 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0),
    46. 

  46. 	MMSYS_ROUTE(DITHER0, DSI0,
    47. 

  47. 		    MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
    48. 

  48. 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER),
    49. 

  49. 	MMSYS_ROUTE(RDMA0, COLOR0,
    50. 

  50. 		    MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
    51. 

  51. 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0),
    52. 

  52. 	MMSYS_ROUTE(RDMA1, DPI0,
    53. 

  53. 		    MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
    54. 

  54. 		    MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
    55. 

  55. 		    MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK),
    56. 

  56. 	MMSYS_ROUTE(RDMA1, DPI0,
    57. 

  57. 		    MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
    58. 

  58. 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1),
    59. 

  59. 	MMSYS_ROUTE(RDMA1, DPI0,
    60. 

  60. 		    MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
    61. 

  61. 		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0),
    62. 

  62. };
    63. 

  63. 

  64. #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
    65.