mv_sas.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Marvell 88SE64xx/88SE94xx main function
  4. *
  5. * Copyright 2007 Red Hat, Inc.
  6. * Copyright 2008 Marvell. <kewei@marvell.com>
  7. * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
  8. */
  9. #include "mv_sas.h"
  10. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  11. {
  12. if (task->lldd_task) {
  13. struct mvs_slot_info *slot;
  14. slot = task->lldd_task;
  15. *tag = slot->slot_tag;
  16. return 1;
  17. }
  18. return 0;
  19. }
  20. static void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  21. {
  22. void *bitmap = mvi->rsvd_tags;
  23. clear_bit(tag, bitmap);
  24. }
  25. static void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  26. {
  27. if (tag >= MVS_RSVD_SLOTS)
  28. return;
  29. mvs_tag_clear(mvi, tag);
  30. }
  31. static void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  32. {
  33. void *bitmap = mvi->rsvd_tags;
  34. set_bit(tag, bitmap);
  35. }
  36. static int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  37. {
  38. unsigned int index, tag;
  39. void *bitmap = mvi->rsvd_tags;
  40. index = find_first_zero_bit(bitmap, MVS_RSVD_SLOTS);
  41. tag = index;
  42. if (tag >= MVS_RSVD_SLOTS)
  43. return -SAS_QUEUE_FULL;
  44. mvs_tag_set(mvi, tag);
  45. *tag_out = tag;
  46. return 0;
  47. }
  48. static struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  49. {
  50. unsigned long i = 0, j = 0, hi = 0;
  51. struct sas_ha_struct *sha = dev->port->ha;
  52. struct mvs_info *mvi = NULL;
  53. struct asd_sas_phy *phy;
  54. while (sha->sas_port[i]) {
  55. if (sha->sas_port[i] == dev->port) {
  56. spin_lock(&sha->sas_port[i]->phy_list_lock);
  57. phy = container_of(sha->sas_port[i]->phy_list.next,
  58. struct asd_sas_phy, port_phy_el);
  59. spin_unlock(&sha->sas_port[i]->phy_list_lock);
  60. j = 0;
  61. while (sha->sas_phy[j]) {
  62. if (sha->sas_phy[j] == phy)
  63. break;
  64. j++;
  65. }
  66. break;
  67. }
  68. i++;
  69. }
  70. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  71. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  72. return mvi;
  73. }
  74. static int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  75. {
  76. unsigned long i = 0, j = 0, n = 0, num = 0;
  77. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  78. struct mvs_info *mvi = mvi_dev->mvi_info;
  79. struct sas_ha_struct *sha = dev->port->ha;
  80. while (sha->sas_port[i]) {
  81. if (sha->sas_port[i] == dev->port) {
  82. struct asd_sas_phy *phy;
  83. spin_lock(&sha->sas_port[i]->phy_list_lock);
  84. list_for_each_entry(phy,
  85. &sha->sas_port[i]->phy_list, port_phy_el) {
  86. j = 0;
  87. while (sha->sas_phy[j]) {
  88. if (sha->sas_phy[j] == phy)
  89. break;
  90. j++;
  91. }
  92. phyno[n] = (j >= mvi->chip->n_phy) ?
  93. (j - mvi->chip->n_phy) : j;
  94. num++;
  95. n++;
  96. }
  97. spin_unlock(&sha->sas_port[i]->phy_list_lock);
  98. break;
  99. }
  100. i++;
  101. }
  102. return num;
  103. }
  104. struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
  105. u8 reg_set)
  106. {
  107. u32 dev_no;
  108. for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
  109. if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
  110. continue;
  111. if (mvi->devices[dev_no].taskfileset == reg_set)
  112. return &mvi->devices[dev_no];
  113. }
  114. return NULL;
  115. }
  116. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  117. struct mvs_device *dev)
  118. {
  119. if (!dev) {
  120. mv_printk("device has been free.\n");
  121. return;
  122. }
  123. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  124. return;
  125. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  126. }
  127. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  128. struct mvs_device *dev)
  129. {
  130. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  131. return 0;
  132. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  133. }
  134. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  135. void *funcdata)
  136. {
  137. int rc = 0, phy_id = sas_phy->id;
  138. u32 tmp, i = 0, hi;
  139. struct sas_ha_struct *sha = sas_phy->ha;
  140. struct mvs_info *mvi = NULL;
  141. while (sha->sas_phy[i]) {
  142. if (sha->sas_phy[i] == sas_phy)
  143. break;
  144. i++;
  145. }
  146. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  147. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  148. switch (func) {
  149. case PHY_FUNC_SET_LINK_RATE:
  150. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  151. break;
  152. case PHY_FUNC_HARD_RESET:
  153. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  154. if (tmp & PHY_RST_HARD)
  155. break;
  156. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
  157. break;
  158. case PHY_FUNC_LINK_RESET:
  159. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  160. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
  161. break;
  162. case PHY_FUNC_DISABLE:
  163. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  164. break;
  165. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  166. default:
  167. rc = -ENOSYS;
  168. }
  169. msleep(200);
  170. return rc;
  171. }
  172. void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
  173. u32 off_hi, u64 sas_addr)
  174. {
  175. u32 lo = (u32)sas_addr;
  176. u32 hi = (u32)(sas_addr>>32);
  177. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  178. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  179. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  180. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  181. }
  182. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i, gfp_t gfp_flags)
  183. {
  184. struct mvs_phy *phy = &mvi->phy[i];
  185. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  186. if (!phy->phy_attached)
  187. return;
  188. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  189. && phy->phy_type & PORT_TYPE_SAS) {
  190. return;
  191. }
  192. sas_notify_phy_event(sas_phy, PHYE_OOB_DONE, gfp_flags);
  193. if (sas_phy->phy) {
  194. struct sas_phy *sphy = sas_phy->phy;
  195. sphy->negotiated_linkrate = sas_phy->linkrate;
  196. sphy->minimum_linkrate = phy->minimum_linkrate;
  197. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  198. sphy->maximum_linkrate = phy->maximum_linkrate;
  199. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  200. }
  201. if (phy->phy_type & PORT_TYPE_SAS) {
  202. struct sas_identify_frame *id;
  203. id = (struct sas_identify_frame *)phy->frame_rcvd;
  204. id->dev_type = phy->identify.device_type;
  205. id->initiator_bits = SAS_PROTOCOL_ALL;
  206. id->target_bits = phy->identify.target_port_protocols;
  207. /* direct attached SAS device */
  208. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  209. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  210. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
  211. }
  212. } else if (phy->phy_type & PORT_TYPE_SATA) {
  213. /*Nothing*/
  214. }
  215. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  216. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  217. sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, gfp_flags);
  218. }
  219. void mvs_scan_start(struct Scsi_Host *shost)
  220. {
  221. int i, j;
  222. unsigned short core_nr;
  223. struct mvs_info *mvi;
  224. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  225. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  226. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  227. for (j = 0; j < core_nr; j++) {
  228. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  229. for (i = 0; i < mvi->chip->n_phy; ++i)
  230. mvs_bytes_dmaed(mvi, i, GFP_KERNEL);
  231. }
  232. mvs_prv->scan_finished = 1;
  233. }
  234. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  235. {
  236. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  237. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  238. if (mvs_prv->scan_finished == 0)
  239. return 0;
  240. sas_drain_work(sha);
  241. return 1;
  242. }
  243. static int mvs_task_prep_smp(struct mvs_info *mvi,
  244. struct mvs_task_exec_info *tei)
  245. {
  246. int elem, rc, i;
  247. struct sas_ha_struct *sha = mvi->sas;
  248. struct sas_task *task = tei->task;
  249. struct mvs_cmd_hdr *hdr = tei->hdr;
  250. struct domain_device *dev = task->dev;
  251. struct asd_sas_port *sas_port = dev->port;
  252. struct sas_phy *sphy = dev->phy;
  253. struct asd_sas_phy *sas_phy = sha->sas_phy[sphy->number];
  254. struct scatterlist *sg_req, *sg_resp;
  255. u32 req_len, resp_len, tag = tei->tag;
  256. void *buf_tmp;
  257. u8 *buf_oaf;
  258. dma_addr_t buf_tmp_dma;
  259. void *buf_prd;
  260. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  261. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  262. /*
  263. * DMA-map SMP request, response buffers
  264. */
  265. sg_req = &task->smp_task.smp_req;
  266. elem = dma_map_sg(mvi->dev, sg_req, 1, DMA_TO_DEVICE);
  267. if (!elem)
  268. return -ENOMEM;
  269. req_len = sg_dma_len(sg_req);
  270. sg_resp = &task->smp_task.smp_resp;
  271. elem = dma_map_sg(mvi->dev, sg_resp, 1, DMA_FROM_DEVICE);
  272. if (!elem) {
  273. rc = -ENOMEM;
  274. goto err_out;
  275. }
  276. resp_len = SB_RFB_MAX;
  277. /* must be in dwords */
  278. if ((req_len & 0x3) || (resp_len & 0x3)) {
  279. rc = -EINVAL;
  280. goto err_out_2;
  281. }
  282. /*
  283. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  284. */
  285. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  286. buf_tmp = slot->buf;
  287. buf_tmp_dma = slot->buf_dma;
  288. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  289. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  290. buf_oaf = buf_tmp;
  291. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  292. buf_tmp += MVS_OAF_SZ;
  293. buf_tmp_dma += MVS_OAF_SZ;
  294. /* region 3: PRD table *********************************** */
  295. buf_prd = buf_tmp;
  296. if (tei->n_elem)
  297. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  298. else
  299. hdr->prd_tbl = 0;
  300. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  301. buf_tmp += i;
  302. buf_tmp_dma += i;
  303. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  304. slot->response = buf_tmp;
  305. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  306. if (mvi->flags & MVF_FLAG_SOC)
  307. hdr->reserved[0] = 0;
  308. /*
  309. * Fill in TX ring and command slot header
  310. */
  311. slot->tx = mvi->tx_prod;
  312. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  313. TXQ_MODE_I | tag |
  314. (MVS_PHY_ID << TXQ_PHY_SHIFT));
  315. hdr->flags |= flags;
  316. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  317. hdr->tags = cpu_to_le32(tag);
  318. hdr->data_len = 0;
  319. /* generate open address frame hdr (first 12 bytes) */
  320. /* initiator, SMP, ftype 1h */
  321. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  322. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  323. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  324. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  325. /* fill in PRD (scatter/gather) table, if any */
  326. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  327. return 0;
  328. err_out_2:
  329. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  330. DMA_FROM_DEVICE);
  331. err_out:
  332. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  333. DMA_TO_DEVICE);
  334. return rc;
  335. }
  336. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  337. {
  338. struct ata_queued_cmd *qc = task->uldd_task;
  339. if (qc) {
  340. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  341. qc->tf.command == ATA_CMD_FPDMA_READ ||
  342. qc->tf.command == ATA_CMD_FPDMA_RECV ||
  343. qc->tf.command == ATA_CMD_FPDMA_SEND ||
  344. qc->tf.command == ATA_CMD_NCQ_NON_DATA) {
  345. *tag = qc->tag;
  346. return 1;
  347. }
  348. }
  349. return 0;
  350. }
  351. static int mvs_task_prep_ata(struct mvs_info *mvi,
  352. struct mvs_task_exec_info *tei)
  353. {
  354. struct sas_task *task = tei->task;
  355. struct domain_device *dev = task->dev;
  356. struct mvs_device *mvi_dev = dev->lldd_dev;
  357. struct mvs_cmd_hdr *hdr = tei->hdr;
  358. struct asd_sas_port *sas_port = dev->port;
  359. struct mvs_slot_info *slot;
  360. void *buf_prd;
  361. u32 tag = tei->tag, hdr_tag;
  362. u32 flags, del_q;
  363. void *buf_tmp;
  364. u8 *buf_cmd, *buf_oaf;
  365. dma_addr_t buf_tmp_dma;
  366. u32 i, req_len, resp_len;
  367. const u32 max_resp_len = SB_RFB_MAX;
  368. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  369. mv_dprintk("Have not enough regiset for dev %d.\n",
  370. mvi_dev->device_id);
  371. return -EBUSY;
  372. }
  373. slot = &mvi->slot_info[tag];
  374. slot->tx = mvi->tx_prod;
  375. del_q = TXQ_MODE_I | tag |
  376. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  377. ((sas_port->phy_mask & TXQ_PHY_MASK) << TXQ_PHY_SHIFT) |
  378. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  379. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  380. if (task->data_dir == DMA_FROM_DEVICE)
  381. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  382. else
  383. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  384. if (task->ata_task.use_ncq)
  385. flags |= MCH_FPDMA;
  386. if (dev->sata_dev.class == ATA_DEV_ATAPI) {
  387. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  388. flags |= MCH_ATAPI;
  389. }
  390. hdr->flags = cpu_to_le32(flags);
  391. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  392. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  393. else
  394. hdr_tag = tag;
  395. hdr->tags = cpu_to_le32(hdr_tag);
  396. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  397. /*
  398. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  399. */
  400. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  401. buf_cmd = buf_tmp = slot->buf;
  402. buf_tmp_dma = slot->buf_dma;
  403. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  404. buf_tmp += MVS_ATA_CMD_SZ;
  405. buf_tmp_dma += MVS_ATA_CMD_SZ;
  406. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  407. /* used for STP. unused for SATA? */
  408. buf_oaf = buf_tmp;
  409. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  410. buf_tmp += MVS_OAF_SZ;
  411. buf_tmp_dma += MVS_OAF_SZ;
  412. /* region 3: PRD table ********************************************* */
  413. buf_prd = buf_tmp;
  414. if (tei->n_elem)
  415. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  416. else
  417. hdr->prd_tbl = 0;
  418. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  419. buf_tmp += i;
  420. buf_tmp_dma += i;
  421. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  422. slot->response = buf_tmp;
  423. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  424. if (mvi->flags & MVF_FLAG_SOC)
  425. hdr->reserved[0] = 0;
  426. req_len = sizeof(struct host_to_dev_fis);
  427. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  428. sizeof(struct mvs_err_info) - i;
  429. /* request, response lengths */
  430. resp_len = min(resp_len, max_resp_len);
  431. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  432. if (likely(!task->ata_task.device_control_reg_update))
  433. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  434. /* fill in command FIS and ATAPI CDB */
  435. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  436. if (dev->sata_dev.class == ATA_DEV_ATAPI)
  437. memcpy(buf_cmd + STP_ATAPI_CMD,
  438. task->ata_task.atapi_packet, 16);
  439. /* generate open address frame hdr (first 12 bytes) */
  440. /* initiator, STP, ftype 1h */
  441. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  442. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  443. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  444. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  445. /* fill in PRD (scatter/gather) table, if any */
  446. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  447. if (task->data_dir == DMA_FROM_DEVICE)
  448. MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
  449. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  450. return 0;
  451. }
  452. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  453. struct mvs_task_exec_info *tei, int is_tmf,
  454. struct sas_tmf_task *tmf)
  455. {
  456. struct sas_task *task = tei->task;
  457. struct mvs_cmd_hdr *hdr = tei->hdr;
  458. struct mvs_port *port = tei->port;
  459. struct domain_device *dev = task->dev;
  460. struct mvs_device *mvi_dev = dev->lldd_dev;
  461. struct asd_sas_port *sas_port = dev->port;
  462. struct mvs_slot_info *slot;
  463. void *buf_prd;
  464. struct ssp_frame_hdr *ssp_hdr;
  465. void *buf_tmp;
  466. u8 *buf_cmd, *buf_oaf;
  467. dma_addr_t buf_tmp_dma;
  468. u32 flags;
  469. u32 resp_len, req_len, i, tag = tei->tag;
  470. const u32 max_resp_len = SB_RFB_MAX;
  471. u32 phy_mask;
  472. slot = &mvi->slot_info[tag];
  473. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  474. sas_port->phy_mask) & TXQ_PHY_MASK;
  475. slot->tx = mvi->tx_prod;
  476. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  477. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  478. (phy_mask << TXQ_PHY_SHIFT));
  479. flags = MCH_RETRY;
  480. if (is_tmf)
  481. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  482. else
  483. flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
  484. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  485. hdr->tags = cpu_to_le32(tag);
  486. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  487. /*
  488. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  489. */
  490. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  491. buf_cmd = buf_tmp = slot->buf;
  492. buf_tmp_dma = slot->buf_dma;
  493. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  494. buf_tmp += MVS_SSP_CMD_SZ;
  495. buf_tmp_dma += MVS_SSP_CMD_SZ;
  496. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  497. buf_oaf = buf_tmp;
  498. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  499. buf_tmp += MVS_OAF_SZ;
  500. buf_tmp_dma += MVS_OAF_SZ;
  501. /* region 3: PRD table ********************************************* */
  502. buf_prd = buf_tmp;
  503. if (tei->n_elem)
  504. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  505. else
  506. hdr->prd_tbl = 0;
  507. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  508. buf_tmp += i;
  509. buf_tmp_dma += i;
  510. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  511. slot->response = buf_tmp;
  512. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  513. if (mvi->flags & MVF_FLAG_SOC)
  514. hdr->reserved[0] = 0;
  515. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  516. sizeof(struct mvs_err_info) - i;
  517. resp_len = min(resp_len, max_resp_len);
  518. req_len = sizeof(struct ssp_frame_hdr) + 28;
  519. /* request, response lengths */
  520. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  521. /* generate open address frame hdr (first 12 bytes) */
  522. /* initiator, SSP, ftype 1h */
  523. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  524. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  525. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  526. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  527. /* fill in SSP frame header (Command Table.SSP frame header) */
  528. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  529. if (is_tmf)
  530. ssp_hdr->frame_type = SSP_TASK;
  531. else
  532. ssp_hdr->frame_type = SSP_COMMAND;
  533. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  534. HASHED_SAS_ADDR_SIZE);
  535. memcpy(ssp_hdr->hashed_src_addr,
  536. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  537. ssp_hdr->tag = cpu_to_be16(tag);
  538. /* fill in IU for TASK and Command Frame */
  539. buf_cmd += sizeof(*ssp_hdr);
  540. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  541. if (ssp_hdr->frame_type != SSP_TASK) {
  542. buf_cmd[9] = task->ssp_task.task_attr;
  543. memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
  544. task->ssp_task.cmd->cmd_len);
  545. } else{
  546. buf_cmd[10] = tmf->tmf;
  547. switch (tmf->tmf) {
  548. case TMF_ABORT_TASK:
  549. case TMF_QUERY_TASK:
  550. buf_cmd[12] =
  551. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  552. buf_cmd[13] =
  553. tmf->tag_of_task_to_be_managed & 0xff;
  554. break;
  555. default:
  556. break;
  557. }
  558. }
  559. /* fill in PRD (scatter/gather) table, if any */
  560. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  561. return 0;
  562. }
  563. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == SAS_PHY_UNUSED)))
  564. static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
  565. struct sas_tmf_task *tmf, int *pass)
  566. {
  567. struct domain_device *dev = task->dev;
  568. struct mvs_device *mvi_dev = dev->lldd_dev;
  569. struct mvs_task_exec_info tei;
  570. struct mvs_slot_info *slot;
  571. u32 tag = 0xdeadbeef, n_elem = 0;
  572. struct request *rq;
  573. int rc = 0;
  574. if (!dev->port) {
  575. struct task_status_struct *tsm = &task->task_status;
  576. tsm->resp = SAS_TASK_UNDELIVERED;
  577. tsm->stat = SAS_PHY_DOWN;
  578. /*
  579. * libsas will use dev->port, should
  580. * not call task_done for sata
  581. */
  582. if (dev->dev_type != SAS_SATA_DEV)
  583. task->task_done(task);
  584. return rc;
  585. }
  586. if (DEV_IS_GONE(mvi_dev)) {
  587. if (mvi_dev)
  588. mv_dprintk("device %d not ready.\n",
  589. mvi_dev->device_id);
  590. else
  591. mv_dprintk("device %016llx not ready.\n",
  592. SAS_ADDR(dev->sas_addr));
  593. rc = SAS_PHY_DOWN;
  594. return rc;
  595. }
  596. tei.port = dev->port->lldd_port;
  597. if (tei.port && !tei.port->port_attached && !tmf) {
  598. if (sas_protocol_ata(task->task_proto)) {
  599. struct task_status_struct *ts = &task->task_status;
  600. mv_dprintk("SATA/STP port %d does not attach"
  601. "device.\n", dev->port->id);
  602. ts->resp = SAS_TASK_COMPLETE;
  603. ts->stat = SAS_PHY_DOWN;
  604. task->task_done(task);
  605. } else {
  606. struct task_status_struct *ts = &task->task_status;
  607. mv_dprintk("SAS port %d does not attach"
  608. "device.\n", dev->port->id);
  609. ts->resp = SAS_TASK_UNDELIVERED;
  610. ts->stat = SAS_PHY_DOWN;
  611. task->task_done(task);
  612. }
  613. return rc;
  614. }
  615. if (!sas_protocol_ata(task->task_proto)) {
  616. if (task->num_scatter) {
  617. n_elem = dma_map_sg(mvi->dev,
  618. task->scatter,
  619. task->num_scatter,
  620. task->data_dir);
  621. if (!n_elem) {
  622. rc = -ENOMEM;
  623. goto prep_out;
  624. }
  625. }
  626. } else {
  627. n_elem = task->num_scatter;
  628. }
  629. rq = sas_task_find_rq(task);
  630. if (rq) {
  631. tag = rq->tag + MVS_RSVD_SLOTS;
  632. } else {
  633. rc = mvs_tag_alloc(mvi, &tag);
  634. if (rc)
  635. goto err_out;
  636. }
  637. slot = &mvi->slot_info[tag];
  638. task->lldd_task = NULL;
  639. slot->n_elem = n_elem;
  640. slot->slot_tag = tag;
  641. slot->buf = dma_pool_zalloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
  642. if (!slot->buf) {
  643. rc = -ENOMEM;
  644. goto err_out_tag;
  645. }
  646. tei.task = task;
  647. tei.hdr = &mvi->slot[tag];
  648. tei.tag = tag;
  649. tei.n_elem = n_elem;
  650. switch (task->task_proto) {
  651. case SAS_PROTOCOL_SMP:
  652. rc = mvs_task_prep_smp(mvi, &tei);
  653. break;
  654. case SAS_PROTOCOL_SSP:
  655. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  656. break;
  657. case SAS_PROTOCOL_SATA:
  658. case SAS_PROTOCOL_STP:
  659. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  660. rc = mvs_task_prep_ata(mvi, &tei);
  661. break;
  662. default:
  663. dev_printk(KERN_ERR, mvi->dev,
  664. "unknown sas_task proto: 0x%x\n",
  665. task->task_proto);
  666. rc = -EINVAL;
  667. break;
  668. }
  669. if (rc) {
  670. mv_dprintk("rc is %x\n", rc);
  671. goto err_out_slot_buf;
  672. }
  673. slot->task = task;
  674. slot->port = tei.port;
  675. task->lldd_task = slot;
  676. list_add_tail(&slot->entry, &tei.port->list);
  677. mvi_dev->running_req++;
  678. ++(*pass);
  679. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  680. return rc;
  681. err_out_slot_buf:
  682. dma_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  683. err_out_tag:
  684. mvs_tag_free(mvi, tag);
  685. err_out:
  686. dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
  687. if (!sas_protocol_ata(task->task_proto))
  688. if (n_elem)
  689. dma_unmap_sg(mvi->dev, task->scatter, task->num_scatter,
  690. task->data_dir);
  691. prep_out:
  692. return rc;
  693. }
  694. int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags)
  695. {
  696. struct mvs_info *mvi = NULL;
  697. u32 rc = 0;
  698. u32 pass = 0;
  699. unsigned long flags = 0;
  700. struct sas_tmf_task *tmf = task->tmf;
  701. int is_tmf = !!task->tmf;
  702. mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
  703. spin_lock_irqsave(&mvi->lock, flags);
  704. rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
  705. if (rc)
  706. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  707. if (likely(pass))
  708. MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
  709. (MVS_CHIP_SLOT_SZ - 1));
  710. spin_unlock_irqrestore(&mvi->lock, flags);
  711. return rc;
  712. }
  713. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  714. {
  715. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  716. mvs_tag_free(mvi, slot_idx);
  717. }
  718. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  719. struct mvs_slot_info *slot, u32 slot_idx)
  720. {
  721. if (!slot)
  722. return;
  723. if (!slot->task)
  724. return;
  725. if (!sas_protocol_ata(task->task_proto))
  726. if (slot->n_elem)
  727. dma_unmap_sg(mvi->dev, task->scatter,
  728. task->num_scatter, task->data_dir);
  729. switch (task->task_proto) {
  730. case SAS_PROTOCOL_SMP:
  731. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  732. DMA_FROM_DEVICE);
  733. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  734. DMA_TO_DEVICE);
  735. break;
  736. case SAS_PROTOCOL_SATA:
  737. case SAS_PROTOCOL_STP:
  738. case SAS_PROTOCOL_SSP:
  739. default:
  740. /* do nothing */
  741. break;
  742. }
  743. if (slot->buf) {
  744. dma_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  745. slot->buf = NULL;
  746. }
  747. list_del_init(&slot->entry);
  748. task->lldd_task = NULL;
  749. slot->task = NULL;
  750. slot->port = NULL;
  751. slot->slot_tag = 0xFFFFFFFF;
  752. mvs_slot_free(mvi, slot_idx);
  753. }
  754. static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
  755. {
  756. struct mvs_phy *phy = &mvi->phy[phy_no];
  757. struct mvs_port *port = phy->port;
  758. int j, no;
  759. for_each_phy(port->wide_port_phymap, j, no) {
  760. if (j & 1) {
  761. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  762. PHYR_WIDE_PORT);
  763. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  764. port->wide_port_phymap);
  765. } else {
  766. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  767. PHYR_WIDE_PORT);
  768. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  769. 0);
  770. }
  771. }
  772. }
  773. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  774. {
  775. u32 tmp;
  776. struct mvs_phy *phy = &mvi->phy[i];
  777. struct mvs_port *port = phy->port;
  778. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  779. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  780. if (!port)
  781. phy->phy_attached = 1;
  782. return tmp;
  783. }
  784. if (port) {
  785. if (phy->phy_type & PORT_TYPE_SAS) {
  786. port->wide_port_phymap &= ~(1U << i);
  787. if (!port->wide_port_phymap)
  788. port->port_attached = 0;
  789. mvs_update_wideport(mvi, i);
  790. } else if (phy->phy_type & PORT_TYPE_SATA)
  791. port->port_attached = 0;
  792. phy->port = NULL;
  793. phy->phy_attached = 0;
  794. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  795. }
  796. return 0;
  797. }
  798. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  799. {
  800. u32 *s = (u32 *) buf;
  801. if (!s)
  802. return NULL;
  803. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  804. s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  805. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  806. s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  807. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  808. s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  809. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  810. s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  811. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  812. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  813. return s;
  814. }
  815. static u32 mvs_is_sig_fis_received(u32 irq_status)
  816. {
  817. return irq_status & PHYEV_SIG_FIS;
  818. }
  819. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  820. {
  821. if (phy->timer.function)
  822. timer_delete(&phy->timer);
  823. phy->timer.function = NULL;
  824. }
  825. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  826. {
  827. struct mvs_phy *phy = &mvi->phy[i];
  828. struct sas_identify_frame *id;
  829. id = (struct sas_identify_frame *)phy->frame_rcvd;
  830. if (get_st) {
  831. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  832. phy->phy_status = mvs_is_phy_ready(mvi, i);
  833. }
  834. if (phy->phy_status) {
  835. int oob_done = 0;
  836. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  837. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  838. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  839. if (phy->phy_type & PORT_TYPE_SATA) {
  840. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  841. if (mvs_is_sig_fis_received(phy->irq_status)) {
  842. mvs_sig_remove_timer(phy);
  843. phy->phy_attached = 1;
  844. phy->att_dev_sas_addr =
  845. i + mvi->id * mvi->chip->n_phy;
  846. if (oob_done)
  847. sas_phy->oob_mode = SATA_OOB_MODE;
  848. phy->frame_rcvd_size =
  849. sizeof(struct dev_to_host_fis);
  850. mvs_get_d2h_reg(mvi, i, id);
  851. } else {
  852. u32 tmp;
  853. dev_printk(KERN_DEBUG, mvi->dev,
  854. "Phy%d : No sig fis\n", i);
  855. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  856. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  857. tmp | PHYEV_SIG_FIS);
  858. phy->phy_attached = 0;
  859. phy->phy_type &= ~PORT_TYPE_SATA;
  860. goto out_done;
  861. }
  862. } else if (phy->phy_type & PORT_TYPE_SAS
  863. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  864. phy->phy_attached = 1;
  865. phy->identify.device_type =
  866. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  867. if (phy->identify.device_type == SAS_END_DEVICE)
  868. phy->identify.target_port_protocols =
  869. SAS_PROTOCOL_SSP;
  870. else if (phy->identify.device_type != SAS_PHY_UNUSED)
  871. phy->identify.target_port_protocols =
  872. SAS_PROTOCOL_SMP;
  873. if (oob_done)
  874. sas_phy->oob_mode = SAS_OOB_MODE;
  875. phy->frame_rcvd_size =
  876. sizeof(struct sas_identify_frame);
  877. }
  878. memcpy(sas_phy->attached_sas_addr,
  879. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  880. if (MVS_CHIP_DISP->phy_work_around)
  881. MVS_CHIP_DISP->phy_work_around(mvi, i);
  882. }
  883. mv_dprintk("phy %d attach dev info is %x\n",
  884. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  885. mv_dprintk("phy %d attach sas addr is %llx\n",
  886. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  887. out_done:
  888. if (get_st)
  889. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  890. }
  891. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  892. {
  893. struct sas_ha_struct *sas_ha = sas_phy->ha;
  894. struct mvs_info *mvi = NULL; int i = 0, hi;
  895. struct mvs_phy *phy = sas_phy->lldd_phy;
  896. struct asd_sas_port *sas_port = sas_phy->port;
  897. struct mvs_port *port;
  898. unsigned long flags = 0;
  899. if (!sas_port)
  900. return;
  901. while (sas_ha->sas_phy[i]) {
  902. if (sas_ha->sas_phy[i] == sas_phy)
  903. break;
  904. i++;
  905. }
  906. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  907. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  908. if (i >= mvi->chip->n_phy)
  909. port = &mvi->port[i - mvi->chip->n_phy];
  910. else
  911. port = &mvi->port[i];
  912. if (lock)
  913. spin_lock_irqsave(&mvi->lock, flags);
  914. port->port_attached = 1;
  915. phy->port = port;
  916. sas_port->lldd_port = port;
  917. if (phy->phy_type & PORT_TYPE_SAS) {
  918. port->wide_port_phymap = sas_port->phy_mask;
  919. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  920. mvs_update_wideport(mvi, sas_phy->id);
  921. /* direct attached SAS device */
  922. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  923. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  924. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
  925. }
  926. }
  927. if (lock)
  928. spin_unlock_irqrestore(&mvi->lock, flags);
  929. }
  930. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  931. {
  932. struct domain_device *dev;
  933. struct mvs_phy *phy = sas_phy->lldd_phy;
  934. struct mvs_info *mvi = phy->mvi;
  935. struct asd_sas_port *port = sas_phy->port;
  936. int phy_no = 0;
  937. while (phy != &mvi->phy[phy_no]) {
  938. phy_no++;
  939. if (phy_no >= MVS_MAX_PHYS)
  940. return;
  941. }
  942. list_for_each_entry(dev, &port->dev_list, dev_list_node)
  943. mvs_do_release_task(phy->mvi, phy_no, dev);
  944. }
  945. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  946. {
  947. mvs_port_notify_formed(sas_phy, 1);
  948. }
  949. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  950. {
  951. mvs_port_notify_deformed(sas_phy, 1);
  952. }
  953. static struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  954. {
  955. u32 dev;
  956. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  957. if (mvi->devices[dev].dev_type == SAS_PHY_UNUSED) {
  958. mvi->devices[dev].device_id = dev;
  959. return &mvi->devices[dev];
  960. }
  961. }
  962. if (dev == MVS_MAX_DEVICES)
  963. mv_printk("max support %d devices, ignore ..\n",
  964. MVS_MAX_DEVICES);
  965. return NULL;
  966. }
  967. static void mvs_free_dev(struct mvs_device *mvi_dev)
  968. {
  969. u32 id = mvi_dev->device_id;
  970. memset(mvi_dev, 0, sizeof(*mvi_dev));
  971. mvi_dev->device_id = id;
  972. mvi_dev->dev_type = SAS_PHY_UNUSED;
  973. mvi_dev->dev_status = MVS_DEV_NORMAL;
  974. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  975. }
  976. static int mvs_dev_found_notify(struct domain_device *dev, int lock)
  977. {
  978. unsigned long flags = 0;
  979. int res = 0;
  980. struct mvs_info *mvi = NULL;
  981. struct domain_device *parent_dev = dev->parent;
  982. struct mvs_device *mvi_device;
  983. mvi = mvs_find_dev_mvi(dev);
  984. if (lock)
  985. spin_lock_irqsave(&mvi->lock, flags);
  986. mvi_device = mvs_alloc_dev(mvi);
  987. if (!mvi_device) {
  988. res = -1;
  989. goto found_out;
  990. }
  991. dev->lldd_dev = mvi_device;
  992. mvi_device->dev_status = MVS_DEV_NORMAL;
  993. mvi_device->dev_type = dev->dev_type;
  994. mvi_device->mvi_info = mvi;
  995. mvi_device->sas_device = dev;
  996. if (dev_parent_is_expander(dev)) {
  997. int phy_id;
  998. phy_id = sas_find_attached_phy_id(&parent_dev->ex_dev, dev);
  999. if (phy_id < 0) {
  1000. mv_printk("Error: no attached dev:%016llx"
  1001. "at ex:%016llx.\n",
  1002. SAS_ADDR(dev->sas_addr),
  1003. SAS_ADDR(parent_dev->sas_addr));
  1004. res = phy_id;
  1005. } else {
  1006. mvi_device->attached_phy = phy_id;
  1007. }
  1008. }
  1009. found_out:
  1010. if (lock)
  1011. spin_unlock_irqrestore(&mvi->lock, flags);
  1012. return res;
  1013. }
  1014. int mvs_dev_found(struct domain_device *dev)
  1015. {
  1016. return mvs_dev_found_notify(dev, 1);
  1017. }
  1018. static void mvs_dev_gone_notify(struct domain_device *dev)
  1019. {
  1020. unsigned long flags = 0;
  1021. struct mvs_device *mvi_dev = dev->lldd_dev;
  1022. struct mvs_info *mvi;
  1023. if (!mvi_dev) {
  1024. mv_dprintk("found dev has gone.\n");
  1025. return;
  1026. }
  1027. mvi = mvi_dev->mvi_info;
  1028. spin_lock_irqsave(&mvi->lock, flags);
  1029. mv_dprintk("found dev[%d:%x] is gone.\n",
  1030. mvi_dev->device_id, mvi_dev->dev_type);
  1031. mvs_release_task(mvi, dev);
  1032. mvs_free_reg_set(mvi, mvi_dev);
  1033. mvs_free_dev(mvi_dev);
  1034. dev->lldd_dev = NULL;
  1035. mvi_dev->sas_device = NULL;
  1036. spin_unlock_irqrestore(&mvi->lock, flags);
  1037. }
  1038. void mvs_dev_gone(struct domain_device *dev)
  1039. {
  1040. mvs_dev_gone_notify(dev);
  1041. }
  1042. /* Standard mandates link reset for ATA (type 0)
  1043. and hard reset for SSP (type 1) , only for RECOVERY */
  1044. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1045. {
  1046. int rc;
  1047. struct sas_phy *phy = sas_get_local_phy(dev);
  1048. int reset_type = (dev->dev_type == SAS_SATA_DEV ||
  1049. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1050. rc = sas_phy_reset(phy, reset_type);
  1051. sas_put_local_phy(phy);
  1052. msleep(2000);
  1053. return rc;
  1054. }
  1055. /* mandatory SAM-3 */
  1056. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1057. {
  1058. unsigned long flags;
  1059. int rc = TMF_RESP_FUNC_FAILED;
  1060. struct mvs_device * mvi_dev = dev->lldd_dev;
  1061. struct mvs_info *mvi = mvi_dev->mvi_info;
  1062. mvi_dev->dev_status = MVS_DEV_EH;
  1063. rc = sas_lu_reset(dev, lun);
  1064. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1065. spin_lock_irqsave(&mvi->lock, flags);
  1066. mvs_release_task(mvi, dev);
  1067. spin_unlock_irqrestore(&mvi->lock, flags);
  1068. }
  1069. /* If failed, fall-through I_T_Nexus reset */
  1070. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1071. mvi_dev->device_id, rc);
  1072. return rc;
  1073. }
  1074. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1075. {
  1076. unsigned long flags;
  1077. int rc = TMF_RESP_FUNC_FAILED;
  1078. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1079. struct mvs_info *mvi = mvi_dev->mvi_info;
  1080. if (mvi_dev->dev_status != MVS_DEV_EH)
  1081. return TMF_RESP_FUNC_COMPLETE;
  1082. else
  1083. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1084. rc = mvs_debug_I_T_nexus_reset(dev);
  1085. mv_printk("%s for device[%x]:rc= %d\n",
  1086. __func__, mvi_dev->device_id, rc);
  1087. spin_lock_irqsave(&mvi->lock, flags);
  1088. mvs_release_task(mvi, dev);
  1089. spin_unlock_irqrestore(&mvi->lock, flags);
  1090. return rc;
  1091. }
  1092. /* optional SAM-3 */
  1093. int mvs_query_task(struct sas_task *task)
  1094. {
  1095. u32 tag;
  1096. int rc = TMF_RESP_FUNC_FAILED;
  1097. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1098. struct domain_device *dev = task->dev;
  1099. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1100. struct mvs_info *mvi = mvi_dev->mvi_info;
  1101. rc = mvs_find_tag(mvi, task, &tag);
  1102. if (rc == 0) {
  1103. rc = TMF_RESP_FUNC_FAILED;
  1104. return rc;
  1105. }
  1106. rc = sas_query_task(task, tag);
  1107. switch (rc) {
  1108. /* The task is still in Lun, release it then */
  1109. case TMF_RESP_FUNC_SUCC:
  1110. /* The task is not in Lun or failed, reset the phy */
  1111. case TMF_RESP_FUNC_FAILED:
  1112. case TMF_RESP_FUNC_COMPLETE:
  1113. break;
  1114. }
  1115. }
  1116. mv_printk("%s:rc= %d\n", __func__, rc);
  1117. return rc;
  1118. }
  1119. /* mandatory SAM-3, still need free task/slot info */
  1120. int mvs_abort_task(struct sas_task *task)
  1121. {
  1122. struct domain_device *dev = task->dev;
  1123. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1124. struct mvs_info *mvi;
  1125. int rc = TMF_RESP_FUNC_FAILED;
  1126. unsigned long flags;
  1127. u32 tag;
  1128. if (!mvi_dev) {
  1129. mv_printk("Device has removed\n");
  1130. return TMF_RESP_FUNC_FAILED;
  1131. }
  1132. mvi = mvi_dev->mvi_info;
  1133. spin_lock_irqsave(&task->task_state_lock, flags);
  1134. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1135. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1136. rc = TMF_RESP_FUNC_COMPLETE;
  1137. goto out;
  1138. }
  1139. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1140. mvi_dev->dev_status = MVS_DEV_EH;
  1141. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1142. rc = mvs_find_tag(mvi, task, &tag);
  1143. if (rc == 0) {
  1144. mv_printk("No such tag in %s\n", __func__);
  1145. rc = TMF_RESP_FUNC_FAILED;
  1146. return rc;
  1147. }
  1148. rc = sas_abort_task(task, tag);
  1149. /* if successful, clear the task and callback forwards.*/
  1150. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1151. u32 slot_no;
  1152. struct mvs_slot_info *slot;
  1153. if (task->lldd_task) {
  1154. slot = task->lldd_task;
  1155. slot_no = (u32) (slot - mvi->slot_info);
  1156. spin_lock_irqsave(&mvi->lock, flags);
  1157. mvs_slot_complete(mvi, slot_no, 1);
  1158. spin_unlock_irqrestore(&mvi->lock, flags);
  1159. }
  1160. }
  1161. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1162. task->task_proto & SAS_PROTOCOL_STP) {
  1163. if (SAS_SATA_DEV == dev->dev_type) {
  1164. struct mvs_slot_info *slot = task->lldd_task;
  1165. u32 slot_idx = (u32)(slot - mvi->slot_info);
  1166. mv_dprintk("mvs_abort_task() mvi=%p task=%p "
  1167. "slot=%p slot_idx=x%x\n",
  1168. mvi, task, slot, slot_idx);
  1169. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1170. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1171. rc = TMF_RESP_FUNC_COMPLETE;
  1172. goto out;
  1173. }
  1174. }
  1175. out:
  1176. if (rc != TMF_RESP_FUNC_COMPLETE)
  1177. mv_printk("%s:rc= %d\n", __func__, rc);
  1178. return rc;
  1179. }
  1180. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1181. u32 slot_idx, int err)
  1182. {
  1183. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1184. struct task_status_struct *tstat = &task->task_status;
  1185. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1186. int stat = SAM_STAT_GOOD;
  1187. resp->frame_len = sizeof(struct dev_to_host_fis);
  1188. memcpy(&resp->ending_fis[0],
  1189. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1190. sizeof(struct dev_to_host_fis));
  1191. tstat->buf_valid_size = sizeof(*resp);
  1192. if (unlikely(err)) {
  1193. if (unlikely(err & CMD_ISS_STPD))
  1194. stat = SAS_OPEN_REJECT;
  1195. else
  1196. stat = SAS_PROTO_RESPONSE;
  1197. }
  1198. return stat;
  1199. }
  1200. static void mvs_set_sense(u8 *buffer, int len, int d_sense,
  1201. int key, int asc, int ascq)
  1202. {
  1203. memset(buffer, 0, len);
  1204. if (d_sense) {
  1205. /* Descriptor format */
  1206. if (len < 4) {
  1207. mv_printk("Length %d of sense buffer too small to "
  1208. "fit sense %x:%x:%x", len, key, asc, ascq);
  1209. }
  1210. buffer[0] = 0x72; /* Response Code */
  1211. if (len > 1)
  1212. buffer[1] = key; /* Sense Key */
  1213. if (len > 2)
  1214. buffer[2] = asc; /* ASC */
  1215. if (len > 3)
  1216. buffer[3] = ascq; /* ASCQ */
  1217. } else {
  1218. if (len < 14) {
  1219. mv_printk("Length %d of sense buffer too small to "
  1220. "fit sense %x:%x:%x", len, key, asc, ascq);
  1221. }
  1222. buffer[0] = 0x70; /* Response Code */
  1223. if (len > 2)
  1224. buffer[2] = key; /* Sense Key */
  1225. if (len > 7)
  1226. buffer[7] = 0x0a; /* Additional Sense Length */
  1227. if (len > 12)
  1228. buffer[12] = asc; /* ASC */
  1229. if (len > 13)
  1230. buffer[13] = ascq; /* ASCQ */
  1231. }
  1232. return;
  1233. }
  1234. static void mvs_fill_ssp_resp_iu(struct ssp_response_iu *iu,
  1235. u8 key, u8 asc, u8 asc_q)
  1236. {
  1237. iu->datapres = SAS_DATAPRES_SENSE_DATA;
  1238. iu->response_data_len = 0;
  1239. iu->sense_data_len = 17;
  1240. iu->status = 02;
  1241. mvs_set_sense(iu->sense_data, 17, 0,
  1242. key, asc, asc_q);
  1243. }
  1244. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1245. u32 slot_idx)
  1246. {
  1247. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1248. int stat;
  1249. u32 err_dw0 = le32_to_cpu(*(u32 *)slot->response);
  1250. u32 err_dw1 = le32_to_cpu(*((u32 *)slot->response + 1));
  1251. u32 tfs = 0;
  1252. enum mvs_port_type type = PORT_TYPE_SAS;
  1253. if (err_dw0 & CMD_ISS_STPD)
  1254. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1255. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1256. stat = SAM_STAT_CHECK_CONDITION;
  1257. switch (task->task_proto) {
  1258. case SAS_PROTOCOL_SSP:
  1259. {
  1260. stat = SAS_ABORTED_TASK;
  1261. if ((err_dw0 & NO_DEST) || err_dw1 & bit(31)) {
  1262. struct ssp_response_iu *iu = slot->response +
  1263. sizeof(struct mvs_err_info);
  1264. mvs_fill_ssp_resp_iu(iu, NOT_READY, 0x04, 01);
  1265. sas_ssp_task_response(mvi->dev, task, iu);
  1266. stat = SAM_STAT_CHECK_CONDITION;
  1267. }
  1268. if (err_dw1 & bit(31))
  1269. mv_printk("reuse same slot, retry command.\n");
  1270. break;
  1271. }
  1272. case SAS_PROTOCOL_SMP:
  1273. stat = SAM_STAT_CHECK_CONDITION;
  1274. break;
  1275. case SAS_PROTOCOL_SATA:
  1276. case SAS_PROTOCOL_STP:
  1277. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1278. {
  1279. task->ata_task.use_ncq = 0;
  1280. stat = SAS_PROTO_RESPONSE;
  1281. mvs_sata_done(mvi, task, slot_idx, err_dw0);
  1282. }
  1283. break;
  1284. default:
  1285. break;
  1286. }
  1287. return stat;
  1288. }
  1289. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1290. {
  1291. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1292. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1293. struct sas_task *task = slot->task;
  1294. struct mvs_device *mvi_dev = NULL;
  1295. struct task_status_struct *tstat;
  1296. struct domain_device *dev;
  1297. u32 aborted;
  1298. void *to;
  1299. enum exec_status sts;
  1300. if (unlikely(!task || !task->lldd_task || !task->dev))
  1301. return -1;
  1302. tstat = &task->task_status;
  1303. dev = task->dev;
  1304. mvi_dev = dev->lldd_dev;
  1305. spin_lock(&task->task_state_lock);
  1306. task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  1307. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1308. /* race condition*/
  1309. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1310. spin_unlock(&task->task_state_lock);
  1311. memset(tstat, 0, sizeof(*tstat));
  1312. tstat->resp = SAS_TASK_COMPLETE;
  1313. if (unlikely(aborted)) {
  1314. tstat->stat = SAS_ABORTED_TASK;
  1315. if (mvi_dev && mvi_dev->running_req)
  1316. mvi_dev->running_req--;
  1317. if (sas_protocol_ata(task->task_proto))
  1318. mvs_free_reg_set(mvi, mvi_dev);
  1319. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1320. return -1;
  1321. }
  1322. /* when no device attaching, go ahead and complete by error handling*/
  1323. if (unlikely(!mvi_dev || flags)) {
  1324. if (!mvi_dev)
  1325. mv_dprintk("port has not device.\n");
  1326. tstat->stat = SAS_PHY_DOWN;
  1327. goto out;
  1328. }
  1329. /*
  1330. * error info record present; slot->response is 32 bit aligned but may
  1331. * not be 64 bit aligned, so check for zero in two 32 bit reads
  1332. */
  1333. if (unlikely((rx_desc & RXQ_ERR)
  1334. && (*((u32 *)slot->response)
  1335. || *(((u32 *)slot->response) + 1)))) {
  1336. mv_dprintk("port %d slot %d rx_desc %X has error info"
  1337. "%016llX.\n", slot->port->sas_port.id, slot_idx,
  1338. rx_desc, get_unaligned_le64(slot->response));
  1339. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1340. tstat->resp = SAS_TASK_COMPLETE;
  1341. goto out;
  1342. }
  1343. switch (task->task_proto) {
  1344. case SAS_PROTOCOL_SSP:
  1345. /* hw says status == 0, datapres == 0 */
  1346. if (rx_desc & RXQ_GOOD) {
  1347. tstat->stat = SAS_SAM_STAT_GOOD;
  1348. tstat->resp = SAS_TASK_COMPLETE;
  1349. }
  1350. /* response frame present */
  1351. else if (rx_desc & RXQ_RSP) {
  1352. struct ssp_response_iu *iu = slot->response +
  1353. sizeof(struct mvs_err_info);
  1354. sas_ssp_task_response(mvi->dev, task, iu);
  1355. } else
  1356. tstat->stat = SAS_SAM_STAT_CHECK_CONDITION;
  1357. break;
  1358. case SAS_PROTOCOL_SMP: {
  1359. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1360. tstat->stat = SAS_SAM_STAT_GOOD;
  1361. to = kmap_atomic(sg_page(sg_resp));
  1362. memcpy(to + sg_resp->offset,
  1363. slot->response + sizeof(struct mvs_err_info),
  1364. sg_dma_len(sg_resp));
  1365. kunmap_atomic(to);
  1366. break;
  1367. }
  1368. case SAS_PROTOCOL_SATA:
  1369. case SAS_PROTOCOL_STP:
  1370. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1371. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1372. break;
  1373. }
  1374. default:
  1375. tstat->stat = SAS_SAM_STAT_CHECK_CONDITION;
  1376. break;
  1377. }
  1378. if (!slot->port->port_attached) {
  1379. mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
  1380. tstat->stat = SAS_PHY_DOWN;
  1381. }
  1382. out:
  1383. if (mvi_dev && mvi_dev->running_req) {
  1384. mvi_dev->running_req--;
  1385. if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
  1386. mvs_free_reg_set(mvi, mvi_dev);
  1387. }
  1388. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1389. sts = tstat->stat;
  1390. spin_unlock(&mvi->lock);
  1391. if (task->task_done)
  1392. task->task_done(task);
  1393. spin_lock(&mvi->lock);
  1394. return sts;
  1395. }
  1396. void mvs_do_release_task(struct mvs_info *mvi,
  1397. int phy_no, struct domain_device *dev)
  1398. {
  1399. u32 slot_idx;
  1400. struct mvs_phy *phy;
  1401. struct mvs_port *port;
  1402. struct mvs_slot_info *slot, *slot2;
  1403. phy = &mvi->phy[phy_no];
  1404. port = phy->port;
  1405. if (!port)
  1406. return;
  1407. /* clean cmpl queue in case request is already finished */
  1408. mvs_int_rx(mvi, false);
  1409. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1410. struct sas_task *task;
  1411. slot_idx = (u32) (slot - mvi->slot_info);
  1412. task = slot->task;
  1413. if (dev && task->dev != dev)
  1414. continue;
  1415. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1416. slot_idx, slot->slot_tag, task);
  1417. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1418. mvs_slot_complete(mvi, slot_idx, 1);
  1419. }
  1420. }
  1421. void mvs_release_task(struct mvs_info *mvi,
  1422. struct domain_device *dev)
  1423. {
  1424. int i, phyno[WIDE_PORT_MAX_PHY], num;
  1425. num = mvs_find_dev_phyno(dev, phyno);
  1426. for (i = 0; i < num; i++)
  1427. mvs_do_release_task(mvi, phyno[i], dev);
  1428. }
  1429. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1430. {
  1431. phy->phy_attached = 0;
  1432. phy->att_dev_info = 0;
  1433. phy->att_dev_sas_addr = 0;
  1434. }
  1435. static void mvs_work_queue(struct work_struct *work)
  1436. {
  1437. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1438. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1439. struct mvs_info *mvi = mwq->mvi;
  1440. unsigned long flags;
  1441. u32 phy_no = (unsigned long) mwq->data;
  1442. struct mvs_phy *phy = &mvi->phy[phy_no];
  1443. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1444. spin_lock_irqsave(&mvi->lock, flags);
  1445. if (mwq->handler & PHY_PLUG_EVENT) {
  1446. if (phy->phy_event & PHY_PLUG_OUT) {
  1447. u32 tmp;
  1448. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1449. phy->phy_event &= ~PHY_PLUG_OUT;
  1450. if (!(tmp & PHY_READY_MASK)) {
  1451. sas_phy_disconnected(sas_phy);
  1452. mvs_phy_disconnected(phy);
  1453. sas_notify_phy_event(sas_phy,
  1454. PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC);
  1455. mv_dprintk("phy%d Removed Device\n", phy_no);
  1456. } else {
  1457. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1458. mvs_update_phyinfo(mvi, phy_no, 1);
  1459. mvs_bytes_dmaed(mvi, phy_no, GFP_ATOMIC);
  1460. mvs_port_notify_formed(sas_phy, 0);
  1461. mv_dprintk("phy%d Attached Device\n", phy_no);
  1462. }
  1463. }
  1464. } else if (mwq->handler & EXP_BRCT_CHG) {
  1465. phy->phy_event &= ~EXP_BRCT_CHG;
  1466. sas_notify_port_event(sas_phy,
  1467. PORTE_BROADCAST_RCVD, GFP_ATOMIC);
  1468. mv_dprintk("phy%d Got Broadcast Change\n", phy_no);
  1469. }
  1470. list_del(&mwq->entry);
  1471. spin_unlock_irqrestore(&mvi->lock, flags);
  1472. kfree(mwq);
  1473. }
  1474. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1475. {
  1476. struct mvs_wq *mwq;
  1477. int ret = 0;
  1478. mwq = kmalloc_obj(struct mvs_wq, GFP_ATOMIC);
  1479. if (mwq) {
  1480. mwq->mvi = mvi;
  1481. mwq->data = data;
  1482. mwq->handler = handler;
  1483. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1484. list_add_tail(&mwq->entry, &mvi->wq_list);
  1485. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1486. } else
  1487. ret = -ENOMEM;
  1488. return ret;
  1489. }
  1490. static void mvs_sig_time_out(struct timer_list *t)
  1491. {
  1492. struct mvs_phy *phy = timer_container_of(phy, t, timer);
  1493. struct mvs_info *mvi = phy->mvi;
  1494. u8 phy_no;
  1495. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1496. if (&mvi->phy[phy_no] == phy) {
  1497. mv_dprintk("Get signature time out, reset phy %d\n",
  1498. phy_no+mvi->id*mvi->chip->n_phy);
  1499. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
  1500. }
  1501. }
  1502. }
  1503. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1504. {
  1505. u32 tmp;
  1506. struct mvs_phy *phy = &mvi->phy[phy_no];
  1507. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1508. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1509. mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1510. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1511. mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1512. phy->irq_status);
  1513. /*
  1514. * events is port event now ,
  1515. * we need check the interrupt status which belongs to per port.
  1516. */
  1517. if (phy->irq_status & PHYEV_DCDR_ERR) {
  1518. mv_dprintk("phy %d STP decoding error.\n",
  1519. phy_no + mvi->id*mvi->chip->n_phy);
  1520. }
  1521. if (phy->irq_status & PHYEV_POOF) {
  1522. mdelay(500);
  1523. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1524. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1525. int ready;
  1526. mvs_do_release_task(mvi, phy_no, NULL);
  1527. phy->phy_event |= PHY_PLUG_OUT;
  1528. MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
  1529. mvs_handle_event(mvi,
  1530. (void *)(unsigned long)phy_no,
  1531. PHY_PLUG_EVENT);
  1532. ready = mvs_is_phy_ready(mvi, phy_no);
  1533. if (ready || dev_sata) {
  1534. if (MVS_CHIP_DISP->stp_reset)
  1535. MVS_CHIP_DISP->stp_reset(mvi,
  1536. phy_no);
  1537. else
  1538. MVS_CHIP_DISP->phy_reset(mvi,
  1539. phy_no, MVS_SOFT_RESET);
  1540. return;
  1541. }
  1542. }
  1543. }
  1544. if (phy->irq_status & PHYEV_COMWAKE) {
  1545. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1546. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1547. tmp | PHYEV_SIG_FIS);
  1548. if (phy->timer.function == NULL) {
  1549. phy->timer.function = mvs_sig_time_out;
  1550. phy->timer.expires = jiffies + 5*HZ;
  1551. add_timer(&phy->timer);
  1552. }
  1553. }
  1554. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1555. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1556. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1557. if (phy->phy_status) {
  1558. mdelay(10);
  1559. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1560. if (phy->phy_type & PORT_TYPE_SATA) {
  1561. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1562. mvi, phy_no);
  1563. tmp &= ~PHYEV_SIG_FIS;
  1564. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1565. phy_no, tmp);
  1566. }
  1567. mvs_update_phyinfo(mvi, phy_no, 0);
  1568. if (phy->phy_type & PORT_TYPE_SAS) {
  1569. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
  1570. mdelay(10);
  1571. }
  1572. mvs_bytes_dmaed(mvi, phy_no, GFP_ATOMIC);
  1573. /* whether driver is going to handle hot plug */
  1574. if (phy->phy_event & PHY_PLUG_OUT) {
  1575. mvs_port_notify_formed(&phy->sas_phy, 0);
  1576. phy->phy_event &= ~PHY_PLUG_OUT;
  1577. }
  1578. } else {
  1579. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1580. phy_no + mvi->id*mvi->chip->n_phy);
  1581. }
  1582. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1583. mv_dprintk("phy %d broadcast change.\n",
  1584. phy_no + mvi->id*mvi->chip->n_phy);
  1585. mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
  1586. EXP_BRCT_CHG);
  1587. }
  1588. }
  1589. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1590. {
  1591. u32 rx_prod_idx, rx_desc;
  1592. bool attn = false;
  1593. /* the first dword in the RX ring is special: it contains
  1594. * a mirror of the hardware's RX producer index, so that
  1595. * we don't have to stall the CPU reading that register.
  1596. * The actual RX ring is offset by one dword, due to this.
  1597. */
  1598. rx_prod_idx = mvi->rx_cons;
  1599. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1600. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1601. return 0;
  1602. /* The CMPL_Q may come late, read from register and try again
  1603. * note: if coalescing is enabled,
  1604. * it will need to read from register every time for sure
  1605. */
  1606. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1607. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1608. if (mvi->rx_cons == rx_prod_idx)
  1609. return 0;
  1610. while (mvi->rx_cons != rx_prod_idx) {
  1611. /* increment our internal RX consumer pointer */
  1612. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1613. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1614. if (likely(rx_desc & RXQ_DONE))
  1615. mvs_slot_complete(mvi, rx_desc, 0);
  1616. if (rx_desc & RXQ_ATTN) {
  1617. attn = true;
  1618. } else if (rx_desc & RXQ_ERR) {
  1619. if (!(rx_desc & RXQ_DONE))
  1620. mvs_slot_complete(mvi, rx_desc, 0);
  1621. } else if (rx_desc & RXQ_SLOT_RESET) {
  1622. mvs_slot_free(mvi, rx_desc);
  1623. }
  1624. }
  1625. if (attn && self_clear)
  1626. MVS_CHIP_DISP->int_full(mvi);
  1627. return 0;
  1628. }
  1629. int mvs_gpio_write(struct sas_ha_struct *sha, u8 reg_type, u8 reg_index,
  1630. u8 reg_count, u8 *write_data)
  1631. {
  1632. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  1633. struct mvs_info *mvi = mvs_prv->mvi[0];
  1634. if (MVS_CHIP_DISP->gpio_write) {
  1635. return MVS_CHIP_DISP->gpio_write(mvs_prv, reg_type,
  1636. reg_index, reg_count, write_data);
  1637. }
  1638. return -ENOSYS;
  1639. }