hpsa.c 272 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248624962506251625262536254625562566257625862596260626162626263626462656266626762686269627062716272627362746275627662776278627962806281628262836284628562866287628862896290629162926293629462956296629762986299630063016302630363046305630663076308630963106311631263136314631563166317631863196320632163226323632463256326632763286329633063316332633363346335633663376338633963406341634263436344634563466347634863496350635163526353635463556356635763586359636063616362636363646365636663676368636963706371637263736374637563766377637863796380638163826383638463856386638763886389639063916392639363946395639663976398639964006401640264036404640564066407640864096410641164126413641464156416641764186419642064216422642364246425642664276428642964306431643264336434643564366437643864396440644164426443644464456446644764486449645064516452645364546455645664576458645964606461646264636464646564666467646864696470647164726473647464756476647764786479648064816482648364846485648664876488648964906491649264936494649564966497649864996500650165026503650465056506650765086509651065116512651365146515651665176518651965206521652265236524652565266527652865296530653165326533653465356536653765386539654065416542654365446545654665476548654965506551655265536554655565566557655865596560656165626563656465656566656765686569657065716572657365746575657665776578657965806581658265836584658565866587658865896590659165926593659465956596659765986599660066016602660366046605660666076608660966106611661266136614661566166617661866196620662166226623662466256626662766286629663066316632663366346635663666376638663966406641664266436644664566466647664866496650665166526653665466556656665766586659666066616662666366646665666666676668666966706671667266736674667566766677667866796680668166826683668466856686668766886689669066916692669366946695669666976698669967006701670267036704670567066707670867096710671167126713671467156716671767186719672067216722672367246725672667276728672967306731673267336734673567366737673867396740674167426743674467456746674767486749675067516752675367546755675667576758675967606761676267636764676567666767676867696770677167726773677467756776677767786779678067816782678367846785678667876788678967906791679267936794679567966797679867996800680168026803680468056806680768086809681068116812681368146815681668176818681968206821682268236824682568266827682868296830683168326833683468356836683768386839684068416842684368446845684668476848684968506851685268536854685568566857685868596860686168626863686468656866686768686869687068716872687368746875687668776878687968806881688268836884688568866887688868896890689168926893689468956896689768986899690069016902690369046905690669076908690969106911691269136914691569166917691869196920692169226923692469256926692769286929693069316932693369346935693669376938693969406941694269436944694569466947694869496950695169526953695469556956695769586959696069616962696369646965696669676968696969706971697269736974697569766977697869796980698169826983698469856986698769886989699069916992699369946995699669976998699970007001700270037004700570067007700870097010701170127013701470157016701770187019702070217022702370247025702670277028702970307031703270337034703570367037703870397040704170427043704470457046704770487049705070517052705370547055705670577058705970607061706270637064706570667067706870697070707170727073707470757076707770787079708070817082708370847085708670877088708970907091709270937094709570967097709870997100710171027103710471057106710771087109711071117112711371147115711671177118711971207121712271237124712571267127712871297130713171327133713471357136713771387139714071417142714371447145714671477148714971507151715271537154715571567157715871597160716171627163716471657166716771687169717071717172717371747175717671777178717971807181718271837184718571867187718871897190719171927193719471957196719771987199720072017202720372047205720672077208720972107211721272137214721572167217721872197220722172227223722472257226722772287229723072317232723372347235723672377238723972407241724272437244724572467247724872497250725172527253725472557256725772587259726072617262726372647265726672677268726972707271727272737274727572767277727872797280728172827283728472857286728772887289729072917292729372947295729672977298729973007301730273037304730573067307730873097310731173127313731473157316731773187319732073217322732373247325732673277328732973307331733273337334733573367337733873397340734173427343734473457346734773487349735073517352735373547355735673577358735973607361736273637364736573667367736873697370737173727373737473757376737773787379738073817382738373847385738673877388738973907391739273937394739573967397739873997400740174027403740474057406740774087409741074117412741374147415741674177418741974207421742274237424742574267427742874297430743174327433743474357436743774387439744074417442744374447445744674477448744974507451745274537454745574567457745874597460746174627463746474657466746774687469747074717472747374747475747674777478747974807481748274837484748574867487748874897490749174927493749474957496749774987499750075017502750375047505750675077508750975107511751275137514751575167517751875197520752175227523752475257526752775287529753075317532753375347535753675377538753975407541754275437544754575467547754875497550755175527553755475557556755775587559756075617562756375647565756675677568756975707571757275737574757575767577757875797580758175827583758475857586758775887589759075917592759375947595759675977598759976007601760276037604760576067607760876097610761176127613761476157616761776187619762076217622762376247625762676277628762976307631763276337634763576367637763876397640764176427643764476457646764776487649765076517652765376547655765676577658765976607661766276637664766576667667766876697670767176727673767476757676767776787679768076817682768376847685768676877688768976907691769276937694769576967697769876997700770177027703770477057706770777087709771077117712771377147715771677177718771977207721772277237724772577267727772877297730773177327733773477357736773777387739774077417742774377447745774677477748774977507751775277537754775577567757775877597760776177627763776477657766776777687769777077717772777377747775777677777778777977807781778277837784778577867787778877897790779177927793779477957796779777987799780078017802780378047805780678077808780978107811781278137814781578167817781878197820782178227823782478257826782778287829783078317832783378347835783678377838783978407841784278437844784578467847784878497850785178527853785478557856785778587859786078617862786378647865786678677868786978707871787278737874787578767877787878797880788178827883788478857886788778887889789078917892789378947895789678977898789979007901790279037904790579067907790879097910791179127913791479157916791779187919792079217922792379247925792679277928792979307931793279337934793579367937793879397940794179427943794479457946794779487949795079517952795379547955795679577958795979607961796279637964796579667967796879697970797179727973797479757976797779787979798079817982798379847985798679877988798979907991799279937994799579967997799879998000800180028003800480058006800780088009801080118012801380148015801680178018801980208021802280238024802580268027802880298030803180328033803480358036803780388039804080418042804380448045804680478048804980508051805280538054805580568057805880598060806180628063806480658066806780688069807080718072807380748075807680778078807980808081808280838084808580868087808880898090809180928093809480958096809780988099810081018102810381048105810681078108810981108111811281138114811581168117811881198120812181228123812481258126812781288129813081318132813381348135813681378138813981408141814281438144814581468147814881498150815181528153815481558156815781588159816081618162816381648165816681678168816981708171817281738174817581768177817881798180818181828183818481858186818781888189819081918192819381948195819681978198819982008201820282038204820582068207820882098210821182128213821482158216821782188219822082218222822382248225822682278228822982308231823282338234823582368237823882398240824182428243824482458246824782488249825082518252825382548255825682578258825982608261826282638264826582668267826882698270827182728273827482758276827782788279828082818282828382848285828682878288828982908291829282938294829582968297829882998300830183028303830483058306830783088309831083118312831383148315831683178318831983208321832283238324832583268327832883298330833183328333833483358336833783388339834083418342834383448345834683478348834983508351835283538354835583568357835883598360836183628363836483658366836783688369837083718372837383748375837683778378837983808381838283838384838583868387838883898390839183928393839483958396839783988399840084018402840384048405840684078408840984108411841284138414841584168417841884198420842184228423842484258426842784288429843084318432843384348435843684378438843984408441844284438444844584468447844884498450845184528453845484558456845784588459846084618462846384648465846684678468846984708471847284738474847584768477847884798480848184828483848484858486848784888489849084918492849384948495849684978498849985008501850285038504850585068507850885098510851185128513851485158516851785188519852085218522852385248525852685278528852985308531853285338534853585368537853885398540854185428543854485458546854785488549855085518552855385548555855685578558855985608561856285638564856585668567856885698570857185728573857485758576857785788579858085818582858385848585858685878588858985908591859285938594859585968597859885998600860186028603860486058606860786088609861086118612861386148615861686178618861986208621862286238624862586268627862886298630863186328633863486358636863786388639864086418642864386448645864686478648864986508651865286538654865586568657865886598660866186628663866486658666866786688669867086718672867386748675867686778678867986808681868286838684868586868687868886898690869186928693869486958696869786988699870087018702870387048705870687078708870987108711871287138714871587168717871887198720872187228723872487258726872787288729873087318732873387348735873687378738873987408741874287438744874587468747874887498750875187528753875487558756875787588759876087618762876387648765876687678768876987708771877287738774877587768777877887798780878187828783878487858786878787888789879087918792879387948795879687978798879988008801880288038804880588068807880888098810881188128813881488158816881788188819882088218822882388248825882688278828882988308831883288338834883588368837883888398840884188428843884488458846884788488849885088518852885388548855885688578858885988608861886288638864886588668867886888698870887188728873887488758876887788788879888088818882888388848885888688878888888988908891889288938894889588968897889888998900890189028903890489058906890789088909891089118912891389148915891689178918891989208921892289238924892589268927892889298930893189328933893489358936893789388939894089418942894389448945894689478948894989508951895289538954895589568957895889598960896189628963896489658966896789688969897089718972897389748975897689778978897989808981898289838984898589868987898889898990899189928993899489958996899789988999900090019002900390049005900690079008900990109011901290139014901590169017901890199020902190229023902490259026902790289029903090319032903390349035903690379038903990409041904290439044904590469047904890499050905190529053905490559056905790589059906090619062906390649065906690679068906990709071907290739074907590769077907890799080908190829083908490859086908790889089909090919092909390949095909690979098909991009101910291039104910591069107910891099110911191129113911491159116911791189119912091219122912391249125912691279128912991309131913291339134913591369137913891399140914191429143914491459146914791489149915091519152915391549155915691579158915991609161916291639164916591669167916891699170917191729173917491759176917791789179918091819182918391849185918691879188918991909191919291939194919591969197919891999200920192029203920492059206920792089209921092119212921392149215921692179218921992209221922292239224922592269227922892299230923192329233923492359236923792389239924092419242924392449245924692479248924992509251925292539254925592569257925892599260926192629263926492659266926792689269927092719272927392749275927692779278927992809281928292839284928592869287928892899290929192929293929492959296929792989299930093019302930393049305930693079308930993109311931293139314931593169317931893199320932193229323932493259326932793289329933093319332933393349335933693379338933993409341934293439344934593469347934893499350935193529353935493559356935793589359936093619362936393649365936693679368936993709371937293739374937593769377937893799380938193829383938493859386938793889389939093919392939393949395939693979398939994009401940294039404940594069407940894099410941194129413941494159416941794189419942094219422942394249425942694279428942994309431943294339434943594369437943894399440944194429443944494459446944794489449945094519452945394549455945694579458945994609461946294639464946594669467946894699470947194729473947494759476947794789479948094819482948394849485948694879488948994909491949294939494949594969497949894999500950195029503950495059506950795089509951095119512951395149515951695179518951995209521952295239524952595269527952895299530953195329533953495359536953795389539954095419542954395449545954695479548954995509551955295539554955595569557955895599560956195629563956495659566956795689569957095719572957395749575957695779578957995809581958295839584958595869587958895899590959195929593959495959596959795989599960096019602960396049605960696079608960996109611961296139614961596169617961896199620962196229623962496259626962796289629963096319632963396349635963696379638963996409641964296439644964596469647964896499650965196529653965496559656965796589659966096619662966396649665966696679668966996709671967296739674967596769677967896799680968196829683968496859686968796889689969096919692969396949695969696979698969997009701970297039704970597069707970897099710971197129713971497159716971797189719972097219722972397249725972697279728972997309731973297339734973597369737973897399740974197429743974497459746974797489749975097519752975397549755975697579758975997609761976297639764976597669767976897699770977197729773977497759776977797789779978097819782978397849785978697879788978997909791979297939794979597969797979897999800980198029803980498059806980798089809981098119812981398149815981698179818981998209821982298239824982598269827982898299830983198329833983498359836983798389839984098419842984398449845984698479848984998509851985298539854985598569857985898599860986198629863986498659866986798689869987098719872987398749875987698779878987998809881988298839884988598869887988898899890989198929893989498959896989798989899990099019902990399049905990699079908990999109911991299139914991599169917991899199920992199229923992499259926992799289929993099319932993399349935993699379938993999409941994299439944994599469947994899499950995199529953995499559956995799589959996099619962996399649965996699679968996999709971997299739974997599769977997899799980998199829983998499859986998799889989999099919992999399949995999699979998999910000100011000210003100041000510006
  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
  4. * Copyright 2016 Microsemi Corporation
  5. * Copyright 2014-2015 PMC-Sierra, Inc.
  6. * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  15. * NON INFRINGEMENT. See the GNU General Public License for more details.
  16. *
  17. * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
  18. *
  19. */
  20. #include <linux/module.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/types.h>
  23. #include <linux/pci.h>
  24. #include <linux/kernel.h>
  25. #include <linux/slab.h>
  26. #include <linux/delay.h>
  27. #include <linux/fs.h>
  28. #include <linux/timer.h>
  29. #include <linux/init.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/compat.h>
  32. #include <linux/blktrace_api.h>
  33. #include <linux/uaccess.h>
  34. #include <linux/io.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/completion.h>
  37. #include <linux/moduleparam.h>
  38. #include <scsi/scsi.h>
  39. #include <scsi/scsi_cmnd.h>
  40. #include <scsi/scsi_device.h>
  41. #include <scsi/scsi_host.h>
  42. #include <scsi/scsi_tcq.h>
  43. #include <scsi/scsi_eh.h>
  44. #include <scsi/scsi_transport_sas.h>
  45. #include <scsi/scsi_dbg.h>
  46. #include <linux/cciss_ioctl.h>
  47. #include <linux/string.h>
  48. #include <linux/bitmap.h>
  49. #include <linux/atomic.h>
  50. #include <linux/jiffies.h>
  51. #include <linux/percpu-defs.h>
  52. #include <linux/percpu.h>
  53. #include <linux/unaligned.h>
  54. #include <asm/div64.h>
  55. #include "hpsa_cmd.h"
  56. #include "hpsa.h"
  57. /*
  58. * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
  59. * with an optional trailing '-' followed by a byte value (0-255).
  60. */
  61. #define HPSA_DRIVER_VERSION "3.4.20-200"
  62. #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
  63. #define HPSA "hpsa"
  64. /* How long to wait for CISS doorbell communication */
  65. #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
  66. #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
  67. #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
  68. #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
  69. #define MAX_IOCTL_CONFIG_WAIT 1000
  70. /*define how many times we will try a command because of bus resets */
  71. #define MAX_CMD_RETRIES 3
  72. /* How long to wait before giving up on a command */
  73. #define HPSA_EH_PTRAID_TIMEOUT (240 * HZ)
  74. /* Embedded module documentation macros - see modules.h */
  75. MODULE_AUTHOR("Hewlett-Packard Company");
  76. MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
  77. HPSA_DRIVER_VERSION);
  78. MODULE_VERSION(HPSA_DRIVER_VERSION);
  79. MODULE_LICENSE("GPL");
  80. MODULE_ALIAS("cciss");
  81. static int hpsa_simple_mode;
  82. module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
  83. MODULE_PARM_DESC(hpsa_simple_mode,
  84. "Use 'simple mode' rather than 'performant mode'");
  85. /* define the PCI info for the cards we can control */
  86. static const struct pci_device_id hpsa_pci_device_id[] = {
  87. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
  88. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
  89. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
  90. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
  91. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
  92. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
  93. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
  94. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
  95. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
  96. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
  97. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
  98. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
  99. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
  100. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
  101. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
  102. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1920},
  103. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
  104. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
  105. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
  106. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
  107. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1925},
  108. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
  109. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
  110. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
  111. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
  112. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
  113. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
  114. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
  115. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
  116. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
  117. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
  118. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
  119. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
  120. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
  121. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
  122. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
  123. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
  124. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
  125. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
  126. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
  127. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
  128. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
  129. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
  130. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
  131. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
  132. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
  133. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
  134. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
  135. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
  136. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
  137. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
  138. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
  139. {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
  140. {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  141. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  142. {PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  143. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  144. {0,}
  145. };
  146. MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
  147. /* board_id = Subsystem Device ID & Vendor ID
  148. * product = Marketing Name for the board
  149. * access = Address of the struct of function pointers
  150. */
  151. static struct board_type products[] = {
  152. {0x40700E11, "Smart Array 5300", &SA5A_access},
  153. {0x40800E11, "Smart Array 5i", &SA5B_access},
  154. {0x40820E11, "Smart Array 532", &SA5B_access},
  155. {0x40830E11, "Smart Array 5312", &SA5B_access},
  156. {0x409A0E11, "Smart Array 641", &SA5A_access},
  157. {0x409B0E11, "Smart Array 642", &SA5A_access},
  158. {0x409C0E11, "Smart Array 6400", &SA5A_access},
  159. {0x409D0E11, "Smart Array 6400 EM", &SA5A_access},
  160. {0x40910E11, "Smart Array 6i", &SA5A_access},
  161. {0x3225103C, "Smart Array P600", &SA5A_access},
  162. {0x3223103C, "Smart Array P800", &SA5A_access},
  163. {0x3234103C, "Smart Array P400", &SA5A_access},
  164. {0x3235103C, "Smart Array P400i", &SA5A_access},
  165. {0x3211103C, "Smart Array E200i", &SA5A_access},
  166. {0x3212103C, "Smart Array E200", &SA5A_access},
  167. {0x3213103C, "Smart Array E200i", &SA5A_access},
  168. {0x3214103C, "Smart Array E200i", &SA5A_access},
  169. {0x3215103C, "Smart Array E200i", &SA5A_access},
  170. {0x3237103C, "Smart Array E500", &SA5A_access},
  171. {0x323D103C, "Smart Array P700m", &SA5A_access},
  172. {0x3241103C, "Smart Array P212", &SA5_access},
  173. {0x3243103C, "Smart Array P410", &SA5_access},
  174. {0x3245103C, "Smart Array P410i", &SA5_access},
  175. {0x3247103C, "Smart Array P411", &SA5_access},
  176. {0x3249103C, "Smart Array P812", &SA5_access},
  177. {0x324A103C, "Smart Array P712m", &SA5_access},
  178. {0x324B103C, "Smart Array P711m", &SA5_access},
  179. {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
  180. {0x3350103C, "Smart Array P222", &SA5_access},
  181. {0x3351103C, "Smart Array P420", &SA5_access},
  182. {0x3352103C, "Smart Array P421", &SA5_access},
  183. {0x3353103C, "Smart Array P822", &SA5_access},
  184. {0x3354103C, "Smart Array P420i", &SA5_access},
  185. {0x3355103C, "Smart Array P220i", &SA5_access},
  186. {0x3356103C, "Smart Array P721m", &SA5_access},
  187. {0x1920103C, "Smart Array P430i", &SA5_access},
  188. {0x1921103C, "Smart Array P830i", &SA5_access},
  189. {0x1922103C, "Smart Array P430", &SA5_access},
  190. {0x1923103C, "Smart Array P431", &SA5_access},
  191. {0x1924103C, "Smart Array P830", &SA5_access},
  192. {0x1925103C, "Smart Array P831", &SA5_access},
  193. {0x1926103C, "Smart Array P731m", &SA5_access},
  194. {0x1928103C, "Smart Array P230i", &SA5_access},
  195. {0x1929103C, "Smart Array P530", &SA5_access},
  196. {0x21BD103C, "Smart Array P244br", &SA5_access},
  197. {0x21BE103C, "Smart Array P741m", &SA5_access},
  198. {0x21BF103C, "Smart HBA H240ar", &SA5_access},
  199. {0x21C0103C, "Smart Array P440ar", &SA5_access},
  200. {0x21C1103C, "Smart Array P840ar", &SA5_access},
  201. {0x21C2103C, "Smart Array P440", &SA5_access},
  202. {0x21C3103C, "Smart Array P441", &SA5_access},
  203. {0x21C4103C, "Smart Array", &SA5_access},
  204. {0x21C5103C, "Smart Array P841", &SA5_access},
  205. {0x21C6103C, "Smart HBA H244br", &SA5_access},
  206. {0x21C7103C, "Smart HBA H240", &SA5_access},
  207. {0x21C8103C, "Smart HBA H241", &SA5_access},
  208. {0x21C9103C, "Smart Array", &SA5_access},
  209. {0x21CA103C, "Smart Array P246br", &SA5_access},
  210. {0x21CB103C, "Smart Array P840", &SA5_access},
  211. {0x21CC103C, "Smart Array", &SA5_access},
  212. {0x21CD103C, "Smart Array", &SA5_access},
  213. {0x21CE103C, "Smart HBA", &SA5_access},
  214. {0x05809005, "SmartHBA-SA", &SA5_access},
  215. {0x05819005, "SmartHBA-SA 8i", &SA5_access},
  216. {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
  217. {0x05839005, "SmartHBA-SA 8e", &SA5_access},
  218. {0x05849005, "SmartHBA-SA 16i", &SA5_access},
  219. {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
  220. {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
  221. {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
  222. {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
  223. {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
  224. {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
  225. {0xFFFF103C, "Unknown Smart Array", &SA5_access},
  226. };
  227. static struct scsi_transport_template *hpsa_sas_transport_template;
  228. static int hpsa_add_sas_host(struct ctlr_info *h);
  229. static void hpsa_delete_sas_host(struct ctlr_info *h);
  230. static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
  231. struct hpsa_scsi_dev_t *device);
  232. static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
  233. static struct hpsa_scsi_dev_t
  234. *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
  235. struct sas_rphy *rphy);
  236. #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
  237. static const struct scsi_cmnd hpsa_cmd_busy;
  238. #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
  239. static const struct scsi_cmnd hpsa_cmd_idle;
  240. static int number_of_controllers;
  241. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
  242. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
  243. static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd,
  244. void __user *arg);
  245. static int hpsa_passthru_ioctl(struct ctlr_info *h,
  246. IOCTL_Command_struct *iocommand);
  247. static int hpsa_big_passthru_ioctl(struct ctlr_info *h,
  248. BIG_IOCTL_Command_struct *ioc);
  249. #ifdef CONFIG_COMPAT
  250. static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd,
  251. void __user *arg);
  252. #endif
  253. static void cmd_free(struct ctlr_info *h, struct CommandList *c);
  254. static struct CommandList *cmd_alloc(struct ctlr_info *h);
  255. static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
  256. static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
  257. struct scsi_cmnd *scmd);
  258. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  259. void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
  260. int cmd_type);
  261. static void hpsa_free_cmd_pool(struct ctlr_info *h);
  262. #define VPD_PAGE (1 << 8)
  263. #define HPSA_SIMPLE_ERROR_BITS 0x03
  264. static enum scsi_qc_status hpsa_scsi_queue_command(struct Scsi_Host *h,
  265. struct scsi_cmnd *cmd);
  266. static void hpsa_scan_start(struct Scsi_Host *);
  267. static int hpsa_scan_finished(struct Scsi_Host *sh,
  268. unsigned long elapsed_time);
  269. static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
  270. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
  271. static int hpsa_sdev_init(struct scsi_device *sdev);
  272. static int hpsa_sdev_configure(struct scsi_device *sdev,
  273. struct queue_limits *lim);
  274. static void hpsa_sdev_destroy(struct scsi_device *sdev);
  275. static void hpsa_update_scsi_devices(struct ctlr_info *h);
  276. static int check_for_unit_attention(struct ctlr_info *h,
  277. struct CommandList *c);
  278. static void check_ioctl_unit_attention(struct ctlr_info *h,
  279. struct CommandList *c);
  280. /* performant mode helper functions */
  281. static void calc_bucket_map(int *bucket, int num_buckets,
  282. int nsgs, int min_blocks, u32 *bucket_map);
  283. static void hpsa_free_performant_mode(struct ctlr_info *h);
  284. static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
  285. static inline u32 next_command(struct ctlr_info *h, u8 q);
  286. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  287. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  288. u64 *cfg_offset);
  289. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  290. unsigned long *memory_bar);
  291. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id,
  292. bool *legacy_board);
  293. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  294. unsigned char lunaddr[],
  295. int reply_queue);
  296. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  297. int wait_for_ready);
  298. static inline void finish_cmd(struct CommandList *c);
  299. static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
  300. #define BOARD_NOT_READY 0
  301. #define BOARD_READY 1
  302. static void hpsa_drain_accel_commands(struct ctlr_info *h);
  303. static void hpsa_flush_cache(struct ctlr_info *h);
  304. static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
  305. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  306. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
  307. static void hpsa_command_resubmit_worker(struct work_struct *work);
  308. static u32 lockup_detected(struct ctlr_info *h);
  309. static int detect_controller_lockup(struct ctlr_info *h);
  310. static void hpsa_disable_rld_caching(struct ctlr_info *h);
  311. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  312. struct ReportExtendedLUNdata *buf, int bufsize);
  313. static bool hpsa_vpd_page_supported(struct ctlr_info *h,
  314. unsigned char scsi3addr[], u8 page);
  315. static int hpsa_luns_changed(struct ctlr_info *h);
  316. static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
  317. struct hpsa_scsi_dev_t *dev,
  318. unsigned char *scsi3addr);
  319. static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
  320. {
  321. unsigned long *priv = shost_priv(sdev->host);
  322. return (struct ctlr_info *) *priv;
  323. }
  324. static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
  325. {
  326. unsigned long *priv = shost_priv(sh);
  327. return (struct ctlr_info *) *priv;
  328. }
  329. static inline bool hpsa_is_cmd_idle(struct CommandList *c)
  330. {
  331. return c->scsi_cmd == SCSI_CMD_IDLE;
  332. }
  333. /* extract sense key, asc, and ascq from sense data. -1 means invalid. */
  334. static void decode_sense_data(const u8 *sense_data, int sense_data_len,
  335. u8 *sense_key, u8 *asc, u8 *ascq)
  336. {
  337. struct scsi_sense_hdr sshdr;
  338. bool rc;
  339. *sense_key = -1;
  340. *asc = -1;
  341. *ascq = -1;
  342. if (sense_data_len < 1)
  343. return;
  344. rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
  345. if (rc) {
  346. *sense_key = sshdr.sense_key;
  347. *asc = sshdr.asc;
  348. *ascq = sshdr.ascq;
  349. }
  350. }
  351. static int check_for_unit_attention(struct ctlr_info *h,
  352. struct CommandList *c)
  353. {
  354. u8 sense_key, asc, ascq;
  355. int sense_len;
  356. if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
  357. sense_len = sizeof(c->err_info->SenseInfo);
  358. else
  359. sense_len = c->err_info->SenseLen;
  360. decode_sense_data(c->err_info->SenseInfo, sense_len,
  361. &sense_key, &asc, &ascq);
  362. if (sense_key != UNIT_ATTENTION || asc == 0xff)
  363. return 0;
  364. switch (asc) {
  365. case STATE_CHANGED:
  366. dev_warn(&h->pdev->dev,
  367. "%s: a state change detected, command retried\n",
  368. h->devname);
  369. break;
  370. case LUN_FAILED:
  371. dev_warn(&h->pdev->dev,
  372. "%s: LUN failure detected\n", h->devname);
  373. break;
  374. case REPORT_LUNS_CHANGED:
  375. dev_warn(&h->pdev->dev,
  376. "%s: report LUN data changed\n", h->devname);
  377. /*
  378. * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
  379. * target (array) devices.
  380. */
  381. break;
  382. case POWER_OR_RESET:
  383. dev_warn(&h->pdev->dev,
  384. "%s: a power on or device reset detected\n",
  385. h->devname);
  386. break;
  387. case UNIT_ATTENTION_CLEARED:
  388. dev_warn(&h->pdev->dev,
  389. "%s: unit attention cleared by another initiator\n",
  390. h->devname);
  391. break;
  392. default:
  393. dev_warn(&h->pdev->dev,
  394. "%s: unknown unit attention detected\n",
  395. h->devname);
  396. break;
  397. }
  398. return 1;
  399. }
  400. static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
  401. {
  402. if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
  403. (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
  404. c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
  405. return 0;
  406. dev_warn(&h->pdev->dev, HPSA "device busy");
  407. return 1;
  408. }
  409. static u32 lockup_detected(struct ctlr_info *h);
  410. static ssize_t host_show_lockup_detected(struct device *dev,
  411. struct device_attribute *attr, char *buf)
  412. {
  413. int ld;
  414. struct ctlr_info *h;
  415. struct Scsi_Host *shost = class_to_shost(dev);
  416. h = shost_to_hba(shost);
  417. ld = lockup_detected(h);
  418. return sprintf(buf, "ld=%d\n", ld);
  419. }
  420. static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
  421. struct device_attribute *attr,
  422. const char *buf, size_t count)
  423. {
  424. int status;
  425. struct ctlr_info *h;
  426. struct Scsi_Host *shost = class_to_shost(dev);
  427. if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
  428. return -EACCES;
  429. if (kstrtoint(buf, 10, &status))
  430. return -EINVAL;
  431. h = shost_to_hba(shost);
  432. h->acciopath_status = !!status;
  433. dev_warn(&h->pdev->dev,
  434. "hpsa: HP SSD Smart Path %s via sysfs update.\n",
  435. h->acciopath_status ? "enabled" : "disabled");
  436. return count;
  437. }
  438. static ssize_t host_store_raid_offload_debug(struct device *dev,
  439. struct device_attribute *attr,
  440. const char *buf, size_t count)
  441. {
  442. int debug_level;
  443. struct ctlr_info *h;
  444. struct Scsi_Host *shost = class_to_shost(dev);
  445. if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
  446. return -EACCES;
  447. if (kstrtoint(buf, 10, &debug_level))
  448. return -EINVAL;
  449. if (debug_level < 0)
  450. debug_level = 0;
  451. h = shost_to_hba(shost);
  452. h->raid_offload_debug = debug_level;
  453. dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
  454. h->raid_offload_debug);
  455. return count;
  456. }
  457. static ssize_t host_store_rescan(struct device *dev,
  458. struct device_attribute *attr,
  459. const char *buf, size_t count)
  460. {
  461. struct ctlr_info *h;
  462. struct Scsi_Host *shost = class_to_shost(dev);
  463. h = shost_to_hba(shost);
  464. hpsa_scan_start(h->scsi_host);
  465. return count;
  466. }
  467. static void hpsa_turn_off_ioaccel_for_device(struct hpsa_scsi_dev_t *device)
  468. {
  469. device->offload_enabled = 0;
  470. device->offload_to_be_enabled = 0;
  471. }
  472. static ssize_t host_show_firmware_revision(struct device *dev,
  473. struct device_attribute *attr, char *buf)
  474. {
  475. struct ctlr_info *h;
  476. struct Scsi_Host *shost = class_to_shost(dev);
  477. unsigned char *fwrev;
  478. h = shost_to_hba(shost);
  479. if (!h->hba_inquiry_data)
  480. return 0;
  481. fwrev = &h->hba_inquiry_data[32];
  482. return snprintf(buf, 20, "%c%c%c%c\n",
  483. fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
  484. }
  485. static ssize_t host_show_commands_outstanding(struct device *dev,
  486. struct device_attribute *attr, char *buf)
  487. {
  488. struct Scsi_Host *shost = class_to_shost(dev);
  489. struct ctlr_info *h = shost_to_hba(shost);
  490. return snprintf(buf, 20, "%d\n",
  491. atomic_read(&h->commands_outstanding));
  492. }
  493. static ssize_t host_show_transport_mode(struct device *dev,
  494. struct device_attribute *attr, char *buf)
  495. {
  496. struct ctlr_info *h;
  497. struct Scsi_Host *shost = class_to_shost(dev);
  498. h = shost_to_hba(shost);
  499. return snprintf(buf, 20, "%s\n",
  500. h->transMethod & CFGTBL_Trans_Performant ?
  501. "performant" : "simple");
  502. }
  503. static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
  504. struct device_attribute *attr, char *buf)
  505. {
  506. struct ctlr_info *h;
  507. struct Scsi_Host *shost = class_to_shost(dev);
  508. h = shost_to_hba(shost);
  509. return snprintf(buf, 30, "HP SSD Smart Path %s\n",
  510. (h->acciopath_status == 1) ? "enabled" : "disabled");
  511. }
  512. /* List of controllers which cannot be hard reset on kexec with reset_devices */
  513. static u32 unresettable_controller[] = {
  514. 0x324a103C, /* Smart Array P712m */
  515. 0x324b103C, /* Smart Array P711m */
  516. 0x3223103C, /* Smart Array P800 */
  517. 0x3234103C, /* Smart Array P400 */
  518. 0x3235103C, /* Smart Array P400i */
  519. 0x3211103C, /* Smart Array E200i */
  520. 0x3212103C, /* Smart Array E200 */
  521. 0x3213103C, /* Smart Array E200i */
  522. 0x3214103C, /* Smart Array E200i */
  523. 0x3215103C, /* Smart Array E200i */
  524. 0x3237103C, /* Smart Array E500 */
  525. 0x323D103C, /* Smart Array P700m */
  526. 0x40800E11, /* Smart Array 5i */
  527. 0x409C0E11, /* Smart Array 6400 */
  528. 0x409D0E11, /* Smart Array 6400 EM */
  529. 0x40700E11, /* Smart Array 5300 */
  530. 0x40820E11, /* Smart Array 532 */
  531. 0x40830E11, /* Smart Array 5312 */
  532. 0x409A0E11, /* Smart Array 641 */
  533. 0x409B0E11, /* Smart Array 642 */
  534. 0x40910E11, /* Smart Array 6i */
  535. };
  536. /* List of controllers which cannot even be soft reset */
  537. static u32 soft_unresettable_controller[] = {
  538. 0x40800E11, /* Smart Array 5i */
  539. 0x40700E11, /* Smart Array 5300 */
  540. 0x40820E11, /* Smart Array 532 */
  541. 0x40830E11, /* Smart Array 5312 */
  542. 0x409A0E11, /* Smart Array 641 */
  543. 0x409B0E11, /* Smart Array 642 */
  544. 0x40910E11, /* Smart Array 6i */
  545. /* Exclude 640x boards. These are two pci devices in one slot
  546. * which share a battery backed cache module. One controls the
  547. * cache, the other accesses the cache through the one that controls
  548. * it. If we reset the one controlling the cache, the other will
  549. * likely not be happy. Just forbid resetting this conjoined mess.
  550. * The 640x isn't really supported by hpsa anyway.
  551. */
  552. 0x409C0E11, /* Smart Array 6400 */
  553. 0x409D0E11, /* Smart Array 6400 EM */
  554. };
  555. static int board_id_in_array(u32 a[], int nelems, u32 board_id)
  556. {
  557. int i;
  558. for (i = 0; i < nelems; i++)
  559. if (a[i] == board_id)
  560. return 1;
  561. return 0;
  562. }
  563. static int ctlr_is_hard_resettable(u32 board_id)
  564. {
  565. return !board_id_in_array(unresettable_controller,
  566. ARRAY_SIZE(unresettable_controller), board_id);
  567. }
  568. static int ctlr_is_soft_resettable(u32 board_id)
  569. {
  570. return !board_id_in_array(soft_unresettable_controller,
  571. ARRAY_SIZE(soft_unresettable_controller), board_id);
  572. }
  573. static int ctlr_is_resettable(u32 board_id)
  574. {
  575. return ctlr_is_hard_resettable(board_id) ||
  576. ctlr_is_soft_resettable(board_id);
  577. }
  578. static ssize_t host_show_resettable(struct device *dev,
  579. struct device_attribute *attr, char *buf)
  580. {
  581. struct ctlr_info *h;
  582. struct Scsi_Host *shost = class_to_shost(dev);
  583. h = shost_to_hba(shost);
  584. return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
  585. }
  586. static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
  587. {
  588. return (scsi3addr[3] & 0xC0) == 0x40;
  589. }
  590. static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
  591. "1(+0)ADM", "UNKNOWN", "PHYS DRV"
  592. };
  593. #define HPSA_RAID_0 0
  594. #define HPSA_RAID_4 1
  595. #define HPSA_RAID_1 2 /* also used for RAID 10 */
  596. #define HPSA_RAID_5 3 /* also used for RAID 50 */
  597. #define HPSA_RAID_51 4
  598. #define HPSA_RAID_6 5 /* also used for RAID 60 */
  599. #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
  600. #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
  601. #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
  602. static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
  603. {
  604. return !device->physical_device;
  605. }
  606. static ssize_t raid_level_show(struct device *dev,
  607. struct device_attribute *attr, char *buf)
  608. {
  609. ssize_t l = 0;
  610. unsigned char rlevel;
  611. struct ctlr_info *h;
  612. struct scsi_device *sdev;
  613. struct hpsa_scsi_dev_t *hdev;
  614. unsigned long flags;
  615. sdev = to_scsi_device(dev);
  616. h = sdev_to_hba(sdev);
  617. spin_lock_irqsave(&h->lock, flags);
  618. hdev = sdev->hostdata;
  619. if (!hdev) {
  620. spin_unlock_irqrestore(&h->lock, flags);
  621. return -ENODEV;
  622. }
  623. /* Is this even a logical drive? */
  624. if (!is_logical_device(hdev)) {
  625. spin_unlock_irqrestore(&h->lock, flags);
  626. l = snprintf(buf, PAGE_SIZE, "N/A\n");
  627. return l;
  628. }
  629. rlevel = hdev->raid_level;
  630. spin_unlock_irqrestore(&h->lock, flags);
  631. if (rlevel > RAID_UNKNOWN)
  632. rlevel = RAID_UNKNOWN;
  633. l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
  634. return l;
  635. }
  636. static ssize_t lunid_show(struct device *dev,
  637. struct device_attribute *attr, char *buf)
  638. {
  639. struct ctlr_info *h;
  640. struct scsi_device *sdev;
  641. struct hpsa_scsi_dev_t *hdev;
  642. unsigned long flags;
  643. unsigned char lunid[8];
  644. sdev = to_scsi_device(dev);
  645. h = sdev_to_hba(sdev);
  646. spin_lock_irqsave(&h->lock, flags);
  647. hdev = sdev->hostdata;
  648. if (!hdev) {
  649. spin_unlock_irqrestore(&h->lock, flags);
  650. return -ENODEV;
  651. }
  652. memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
  653. spin_unlock_irqrestore(&h->lock, flags);
  654. return snprintf(buf, 20, "0x%8phN\n", lunid);
  655. }
  656. static ssize_t unique_id_show(struct device *dev,
  657. struct device_attribute *attr, char *buf)
  658. {
  659. struct ctlr_info *h;
  660. struct scsi_device *sdev;
  661. struct hpsa_scsi_dev_t *hdev;
  662. unsigned long flags;
  663. unsigned char sn[16];
  664. sdev = to_scsi_device(dev);
  665. h = sdev_to_hba(sdev);
  666. spin_lock_irqsave(&h->lock, flags);
  667. hdev = sdev->hostdata;
  668. if (!hdev) {
  669. spin_unlock_irqrestore(&h->lock, flags);
  670. return -ENODEV;
  671. }
  672. memcpy(sn, hdev->device_id, sizeof(sn));
  673. spin_unlock_irqrestore(&h->lock, flags);
  674. return snprintf(buf, 16 * 2 + 2,
  675. "%02X%02X%02X%02X%02X%02X%02X%02X"
  676. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  677. sn[0], sn[1], sn[2], sn[3],
  678. sn[4], sn[5], sn[6], sn[7],
  679. sn[8], sn[9], sn[10], sn[11],
  680. sn[12], sn[13], sn[14], sn[15]);
  681. }
  682. static ssize_t sas_address_show(struct device *dev,
  683. struct device_attribute *attr, char *buf)
  684. {
  685. struct ctlr_info *h;
  686. struct scsi_device *sdev;
  687. struct hpsa_scsi_dev_t *hdev;
  688. unsigned long flags;
  689. u64 sas_address;
  690. sdev = to_scsi_device(dev);
  691. h = sdev_to_hba(sdev);
  692. spin_lock_irqsave(&h->lock, flags);
  693. hdev = sdev->hostdata;
  694. if (!hdev || is_logical_device(hdev) || !hdev->expose_device) {
  695. spin_unlock_irqrestore(&h->lock, flags);
  696. return -ENODEV;
  697. }
  698. sas_address = hdev->sas_address;
  699. spin_unlock_irqrestore(&h->lock, flags);
  700. return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address);
  701. }
  702. static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
  703. struct device_attribute *attr, char *buf)
  704. {
  705. struct ctlr_info *h;
  706. struct scsi_device *sdev;
  707. struct hpsa_scsi_dev_t *hdev;
  708. unsigned long flags;
  709. int offload_enabled;
  710. sdev = to_scsi_device(dev);
  711. h = sdev_to_hba(sdev);
  712. spin_lock_irqsave(&h->lock, flags);
  713. hdev = sdev->hostdata;
  714. if (!hdev) {
  715. spin_unlock_irqrestore(&h->lock, flags);
  716. return -ENODEV;
  717. }
  718. offload_enabled = hdev->offload_enabled;
  719. spin_unlock_irqrestore(&h->lock, flags);
  720. if (hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC)
  721. return snprintf(buf, 20, "%d\n", offload_enabled);
  722. else
  723. return snprintf(buf, 40, "%s\n",
  724. "Not applicable for a controller");
  725. }
  726. #define MAX_PATHS 8
  727. static ssize_t path_info_show(struct device *dev,
  728. struct device_attribute *attr, char *buf)
  729. {
  730. struct ctlr_info *h;
  731. struct scsi_device *sdev;
  732. struct hpsa_scsi_dev_t *hdev;
  733. unsigned long flags;
  734. int i;
  735. int output_len = 0;
  736. u8 box;
  737. u8 bay;
  738. u8 path_map_index = 0;
  739. char *active;
  740. unsigned char phys_connector[2];
  741. sdev = to_scsi_device(dev);
  742. h = sdev_to_hba(sdev);
  743. spin_lock_irqsave(&h->devlock, flags);
  744. hdev = sdev->hostdata;
  745. if (!hdev) {
  746. spin_unlock_irqrestore(&h->devlock, flags);
  747. return -ENODEV;
  748. }
  749. bay = hdev->bay;
  750. for (i = 0; i < MAX_PATHS; i++) {
  751. path_map_index = 1<<i;
  752. if (i == hdev->active_path_index)
  753. active = "Active";
  754. else if (hdev->path_map & path_map_index)
  755. active = "Inactive";
  756. else
  757. continue;
  758. output_len += scnprintf(buf + output_len,
  759. PAGE_SIZE - output_len,
  760. "[%d:%d:%d:%d] %20.20s ",
  761. h->scsi_host->host_no,
  762. hdev->bus, hdev->target, hdev->lun,
  763. scsi_device_type(hdev->devtype));
  764. if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) {
  765. output_len += scnprintf(buf + output_len,
  766. PAGE_SIZE - output_len,
  767. "%s\n", active);
  768. continue;
  769. }
  770. box = hdev->box[i];
  771. memcpy(&phys_connector, &hdev->phys_connector[i],
  772. sizeof(phys_connector));
  773. if (phys_connector[0] < '0')
  774. phys_connector[0] = '0';
  775. if (phys_connector[1] < '0')
  776. phys_connector[1] = '0';
  777. output_len += scnprintf(buf + output_len,
  778. PAGE_SIZE - output_len,
  779. "PORT: %.2s ",
  780. phys_connector);
  781. if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) &&
  782. hdev->expose_device) {
  783. if (box == 0 || box == 0xFF) {
  784. output_len += scnprintf(buf + output_len,
  785. PAGE_SIZE - output_len,
  786. "BAY: %hhu %s\n",
  787. bay, active);
  788. } else {
  789. output_len += scnprintf(buf + output_len,
  790. PAGE_SIZE - output_len,
  791. "BOX: %hhu BAY: %hhu %s\n",
  792. box, bay, active);
  793. }
  794. } else if (box != 0 && box != 0xFF) {
  795. output_len += scnprintf(buf + output_len,
  796. PAGE_SIZE - output_len, "BOX: %hhu %s\n",
  797. box, active);
  798. } else
  799. output_len += scnprintf(buf + output_len,
  800. PAGE_SIZE - output_len, "%s\n", active);
  801. }
  802. spin_unlock_irqrestore(&h->devlock, flags);
  803. return output_len;
  804. }
  805. static ssize_t host_show_ctlr_num(struct device *dev,
  806. struct device_attribute *attr, char *buf)
  807. {
  808. struct ctlr_info *h;
  809. struct Scsi_Host *shost = class_to_shost(dev);
  810. h = shost_to_hba(shost);
  811. return snprintf(buf, 20, "%d\n", h->ctlr);
  812. }
  813. static ssize_t host_show_legacy_board(struct device *dev,
  814. struct device_attribute *attr, char *buf)
  815. {
  816. struct ctlr_info *h;
  817. struct Scsi_Host *shost = class_to_shost(dev);
  818. h = shost_to_hba(shost);
  819. return snprintf(buf, 20, "%d\n", h->legacy_board ? 1 : 0);
  820. }
  821. static DEVICE_ATTR_RO(raid_level);
  822. static DEVICE_ATTR_RO(lunid);
  823. static DEVICE_ATTR_RO(unique_id);
  824. static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
  825. static DEVICE_ATTR_RO(sas_address);
  826. static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
  827. host_show_hp_ssd_smart_path_enabled, NULL);
  828. static DEVICE_ATTR_RO(path_info);
  829. static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
  830. host_show_hp_ssd_smart_path_status,
  831. host_store_hp_ssd_smart_path_status);
  832. static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
  833. host_store_raid_offload_debug);
  834. static DEVICE_ATTR(firmware_revision, S_IRUGO,
  835. host_show_firmware_revision, NULL);
  836. static DEVICE_ATTR(commands_outstanding, S_IRUGO,
  837. host_show_commands_outstanding, NULL);
  838. static DEVICE_ATTR(transport_mode, S_IRUGO,
  839. host_show_transport_mode, NULL);
  840. static DEVICE_ATTR(resettable, S_IRUGO,
  841. host_show_resettable, NULL);
  842. static DEVICE_ATTR(lockup_detected, S_IRUGO,
  843. host_show_lockup_detected, NULL);
  844. static DEVICE_ATTR(ctlr_num, S_IRUGO,
  845. host_show_ctlr_num, NULL);
  846. static DEVICE_ATTR(legacy_board, S_IRUGO,
  847. host_show_legacy_board, NULL);
  848. static struct attribute *hpsa_sdev_attrs[] = {
  849. &dev_attr_raid_level.attr,
  850. &dev_attr_lunid.attr,
  851. &dev_attr_unique_id.attr,
  852. &dev_attr_hp_ssd_smart_path_enabled.attr,
  853. &dev_attr_path_info.attr,
  854. &dev_attr_sas_address.attr,
  855. NULL,
  856. };
  857. ATTRIBUTE_GROUPS(hpsa_sdev);
  858. static struct attribute *hpsa_shost_attrs[] = {
  859. &dev_attr_rescan.attr,
  860. &dev_attr_firmware_revision.attr,
  861. &dev_attr_commands_outstanding.attr,
  862. &dev_attr_transport_mode.attr,
  863. &dev_attr_resettable.attr,
  864. &dev_attr_hp_ssd_smart_path_status.attr,
  865. &dev_attr_raid_offload_debug.attr,
  866. &dev_attr_lockup_detected.attr,
  867. &dev_attr_ctlr_num.attr,
  868. &dev_attr_legacy_board.attr,
  869. NULL,
  870. };
  871. ATTRIBUTE_GROUPS(hpsa_shost);
  872. #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_DRIVER +\
  873. HPSA_MAX_CONCURRENT_PASSTHRUS)
  874. static const struct scsi_host_template hpsa_driver_template = {
  875. .module = THIS_MODULE,
  876. .name = HPSA,
  877. .proc_name = HPSA,
  878. .queuecommand = hpsa_scsi_queue_command,
  879. .scan_start = hpsa_scan_start,
  880. .scan_finished = hpsa_scan_finished,
  881. .change_queue_depth = hpsa_change_queue_depth,
  882. .this_id = -1,
  883. .eh_device_reset_handler = hpsa_eh_device_reset_handler,
  884. .ioctl = hpsa_ioctl,
  885. .sdev_init = hpsa_sdev_init,
  886. .sdev_configure = hpsa_sdev_configure,
  887. .sdev_destroy = hpsa_sdev_destroy,
  888. #ifdef CONFIG_COMPAT
  889. .compat_ioctl = hpsa_compat_ioctl,
  890. #endif
  891. .sdev_groups = hpsa_sdev_groups,
  892. .shost_groups = hpsa_shost_groups,
  893. .max_sectors = 2048,
  894. .no_write_same = 1,
  895. };
  896. static inline u32 next_command(struct ctlr_info *h, u8 q)
  897. {
  898. u32 a;
  899. struct reply_queue_buffer *rq = &h->reply_queue[q];
  900. if (h->transMethod & CFGTBL_Trans_io_accel1)
  901. return h->access.command_completed(h, q);
  902. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  903. return h->access.command_completed(h, q);
  904. if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
  905. a = rq->head[rq->current_entry];
  906. rq->current_entry++;
  907. atomic_dec(&h->commands_outstanding);
  908. } else {
  909. a = FIFO_EMPTY;
  910. }
  911. /* Check for wraparound */
  912. if (rq->current_entry == h->max_commands) {
  913. rq->current_entry = 0;
  914. rq->wraparound ^= 1;
  915. }
  916. return a;
  917. }
  918. /*
  919. * There are some special bits in the bus address of the
  920. * command that we have to set for the controller to know
  921. * how to process the command:
  922. *
  923. * Normal performant mode:
  924. * bit 0: 1 means performant mode, 0 means simple mode.
  925. * bits 1-3 = block fetch table entry
  926. * bits 4-6 = command type (== 0)
  927. *
  928. * ioaccel1 mode:
  929. * bit 0 = "performant mode" bit.
  930. * bits 1-3 = block fetch table entry
  931. * bits 4-6 = command type (== 110)
  932. * (command type is needed because ioaccel1 mode
  933. * commands are submitted through the same register as normal
  934. * mode commands, so this is how the controller knows whether
  935. * the command is normal mode or ioaccel1 mode.)
  936. *
  937. * ioaccel2 mode:
  938. * bit 0 = "performant mode" bit.
  939. * bits 1-4 = block fetch table entry (note extra bit)
  940. * bits 4-6 = not needed, because ioaccel2 mode has
  941. * a separate special register for submitting commands.
  942. */
  943. /*
  944. * set_performant_mode: Modify the tag for cciss performant
  945. * set bit 0 for pull model, bits 3-1 for block fetch
  946. * register number
  947. */
  948. #define DEFAULT_REPLY_QUEUE (-1)
  949. static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
  950. int reply_queue)
  951. {
  952. if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
  953. c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
  954. if (unlikely(!h->msix_vectors))
  955. return;
  956. c->Header.ReplyQueue = reply_queue;
  957. }
  958. }
  959. static void set_ioaccel1_performant_mode(struct ctlr_info *h,
  960. struct CommandList *c,
  961. int reply_queue)
  962. {
  963. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
  964. /*
  965. * Tell the controller to post the reply to the queue for this
  966. * processor. This seems to give the best I/O throughput.
  967. */
  968. cp->ReplyQueue = reply_queue;
  969. /*
  970. * Set the bits in the address sent down to include:
  971. * - performant mode bit (bit 0)
  972. * - pull count (bits 1-3)
  973. * - command type (bits 4-6)
  974. */
  975. c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
  976. IOACCEL1_BUSADDR_CMDTYPE;
  977. }
  978. static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
  979. struct CommandList *c,
  980. int reply_queue)
  981. {
  982. struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
  983. &h->ioaccel2_cmd_pool[c->cmdindex];
  984. /* Tell the controller to post the reply to the queue for this
  985. * processor. This seems to give the best I/O throughput.
  986. */
  987. cp->reply_queue = reply_queue;
  988. /* Set the bits in the address sent down to include:
  989. * - performant mode bit not used in ioaccel mode 2
  990. * - pull count (bits 0-3)
  991. * - command type isn't needed for ioaccel2
  992. */
  993. c->busaddr |= h->ioaccel2_blockFetchTable[0];
  994. }
  995. static void set_ioaccel2_performant_mode(struct ctlr_info *h,
  996. struct CommandList *c,
  997. int reply_queue)
  998. {
  999. struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
  1000. /*
  1001. * Tell the controller to post the reply to the queue for this
  1002. * processor. This seems to give the best I/O throughput.
  1003. */
  1004. cp->reply_queue = reply_queue;
  1005. /*
  1006. * Set the bits in the address sent down to include:
  1007. * - performant mode bit not used in ioaccel mode 2
  1008. * - pull count (bits 0-3)
  1009. * - command type isn't needed for ioaccel2
  1010. */
  1011. c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
  1012. }
  1013. static int is_firmware_flash_cmd(u8 *cdb)
  1014. {
  1015. return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
  1016. }
  1017. /*
  1018. * During firmware flash, the heartbeat register may not update as frequently
  1019. * as it should. So we dial down lockup detection during firmware flash. and
  1020. * dial it back up when firmware flash completes.
  1021. */
  1022. #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
  1023. #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
  1024. #define HPSA_EVENT_MONITOR_INTERVAL (15 * HZ)
  1025. static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
  1026. struct CommandList *c)
  1027. {
  1028. if (!is_firmware_flash_cmd(c->Request.CDB))
  1029. return;
  1030. atomic_inc(&h->firmware_flash_in_progress);
  1031. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
  1032. }
  1033. static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
  1034. struct CommandList *c)
  1035. {
  1036. if (is_firmware_flash_cmd(c->Request.CDB) &&
  1037. atomic_dec_and_test(&h->firmware_flash_in_progress))
  1038. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  1039. }
  1040. static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
  1041. struct CommandList *c, int reply_queue)
  1042. {
  1043. dial_down_lockup_detection_during_fw_flash(h, c);
  1044. atomic_inc(&h->commands_outstanding);
  1045. /*
  1046. * Check to see if the command is being retried.
  1047. */
  1048. if (c->device && !c->retry_pending)
  1049. atomic_inc(&c->device->commands_outstanding);
  1050. reply_queue = h->reply_map[raw_smp_processor_id()];
  1051. switch (c->cmd_type) {
  1052. case CMD_IOACCEL1:
  1053. set_ioaccel1_performant_mode(h, c, reply_queue);
  1054. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  1055. break;
  1056. case CMD_IOACCEL2:
  1057. set_ioaccel2_performant_mode(h, c, reply_queue);
  1058. writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
  1059. break;
  1060. case IOACCEL2_TMF:
  1061. set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
  1062. writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
  1063. break;
  1064. default:
  1065. set_performant_mode(h, c, reply_queue);
  1066. h->access.submit_command(h, c);
  1067. }
  1068. }
  1069. static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
  1070. {
  1071. __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
  1072. }
  1073. static inline int is_hba_lunid(unsigned char scsi3addr[])
  1074. {
  1075. return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
  1076. }
  1077. static inline int is_scsi_rev_5(struct ctlr_info *h)
  1078. {
  1079. if (!h->hba_inquiry_data)
  1080. return 0;
  1081. if ((h->hba_inquiry_data[2] & 0x07) == 5)
  1082. return 1;
  1083. return 0;
  1084. }
  1085. static int hpsa_find_target_lun(struct ctlr_info *h,
  1086. unsigned char scsi3addr[], int bus, int *target, int *lun)
  1087. {
  1088. /* finds an unused bus, target, lun for a new physical device
  1089. * assumes h->devlock is held
  1090. */
  1091. int i, found = 0;
  1092. DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
  1093. bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
  1094. for (i = 0; i < h->ndevices; i++) {
  1095. if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
  1096. __set_bit(h->dev[i]->target, lun_taken);
  1097. }
  1098. i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
  1099. if (i < HPSA_MAX_DEVICES) {
  1100. /* *bus = 1; */
  1101. *target = i;
  1102. *lun = 0;
  1103. found = 1;
  1104. }
  1105. return !found;
  1106. }
  1107. static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
  1108. struct hpsa_scsi_dev_t *dev, char *description)
  1109. {
  1110. #define LABEL_SIZE 25
  1111. char label[LABEL_SIZE];
  1112. if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
  1113. return;
  1114. switch (dev->devtype) {
  1115. case TYPE_RAID:
  1116. snprintf(label, LABEL_SIZE, "controller");
  1117. break;
  1118. case TYPE_ENCLOSURE:
  1119. snprintf(label, LABEL_SIZE, "enclosure");
  1120. break;
  1121. case TYPE_DISK:
  1122. case TYPE_ZBC:
  1123. if (dev->external)
  1124. snprintf(label, LABEL_SIZE, "external");
  1125. else if (!is_logical_dev_addr_mode(dev->scsi3addr))
  1126. snprintf(label, LABEL_SIZE, "%s",
  1127. raid_label[PHYSICAL_DRIVE]);
  1128. else
  1129. snprintf(label, LABEL_SIZE, "RAID-%s",
  1130. dev->raid_level > RAID_UNKNOWN ? "?" :
  1131. raid_label[dev->raid_level]);
  1132. break;
  1133. case TYPE_ROM:
  1134. snprintf(label, LABEL_SIZE, "rom");
  1135. break;
  1136. case TYPE_TAPE:
  1137. snprintf(label, LABEL_SIZE, "tape");
  1138. break;
  1139. case TYPE_MEDIUM_CHANGER:
  1140. snprintf(label, LABEL_SIZE, "changer");
  1141. break;
  1142. default:
  1143. snprintf(label, LABEL_SIZE, "UNKNOWN");
  1144. break;
  1145. }
  1146. dev_printk(level, &h->pdev->dev,
  1147. "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
  1148. h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
  1149. description,
  1150. scsi_device_type(dev->devtype),
  1151. dev->vendor,
  1152. dev->model,
  1153. label,
  1154. dev->offload_config ? '+' : '-',
  1155. dev->offload_to_be_enabled ? '+' : '-',
  1156. dev->expose_device);
  1157. }
  1158. /* Add an entry into h->dev[] array. */
  1159. static int hpsa_scsi_add_entry(struct ctlr_info *h,
  1160. struct hpsa_scsi_dev_t *device,
  1161. struct hpsa_scsi_dev_t *added[], int *nadded)
  1162. {
  1163. /* assumes h->devlock is held */
  1164. int n = h->ndevices;
  1165. int i;
  1166. unsigned char addr1[8], addr2[8];
  1167. struct hpsa_scsi_dev_t *sd;
  1168. if (n >= HPSA_MAX_DEVICES) {
  1169. dev_err(&h->pdev->dev, "too many devices, some will be "
  1170. "inaccessible.\n");
  1171. return -1;
  1172. }
  1173. /* physical devices do not have lun or target assigned until now. */
  1174. if (device->lun != -1)
  1175. /* Logical device, lun is already assigned. */
  1176. goto lun_assigned;
  1177. /* If this device a non-zero lun of a multi-lun device
  1178. * byte 4 of the 8-byte LUN addr will contain the logical
  1179. * unit no, zero otherwise.
  1180. */
  1181. if (device->scsi3addr[4] == 0) {
  1182. /* This is not a non-zero lun of a multi-lun device */
  1183. if (hpsa_find_target_lun(h, device->scsi3addr,
  1184. device->bus, &device->target, &device->lun) != 0)
  1185. return -1;
  1186. goto lun_assigned;
  1187. }
  1188. /* This is a non-zero lun of a multi-lun device.
  1189. * Search through our list and find the device which
  1190. * has the same 8 byte LUN address, excepting byte 4 and 5.
  1191. * Assign the same bus and target for this new LUN.
  1192. * Use the logical unit number from the firmware.
  1193. */
  1194. memcpy(addr1, device->scsi3addr, 8);
  1195. addr1[4] = 0;
  1196. addr1[5] = 0;
  1197. for (i = 0; i < n; i++) {
  1198. sd = h->dev[i];
  1199. memcpy(addr2, sd->scsi3addr, 8);
  1200. addr2[4] = 0;
  1201. addr2[5] = 0;
  1202. /* differ only in byte 4 and 5? */
  1203. if (memcmp(addr1, addr2, 8) == 0) {
  1204. device->bus = sd->bus;
  1205. device->target = sd->target;
  1206. device->lun = device->scsi3addr[4];
  1207. break;
  1208. }
  1209. }
  1210. if (device->lun == -1) {
  1211. dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
  1212. " suspect firmware bug or unsupported hardware "
  1213. "configuration.\n");
  1214. return -1;
  1215. }
  1216. lun_assigned:
  1217. h->dev[n] = device;
  1218. h->ndevices++;
  1219. added[*nadded] = device;
  1220. (*nadded)++;
  1221. hpsa_show_dev_msg(KERN_INFO, h, device,
  1222. device->expose_device ? "added" : "masked");
  1223. return 0;
  1224. }
  1225. /*
  1226. * Called during a scan operation.
  1227. *
  1228. * Update an entry in h->dev[] array.
  1229. */
  1230. static void hpsa_scsi_update_entry(struct ctlr_info *h,
  1231. int entry, struct hpsa_scsi_dev_t *new_entry)
  1232. {
  1233. /* assumes h->devlock is held */
  1234. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1235. /* Raid level changed. */
  1236. h->dev[entry]->raid_level = new_entry->raid_level;
  1237. /*
  1238. * ioacccel_handle may have changed for a dual domain disk
  1239. */
  1240. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1241. /* Raid offload parameters changed. Careful about the ordering. */
  1242. if (new_entry->offload_config && new_entry->offload_to_be_enabled) {
  1243. /*
  1244. * if drive is newly offload_enabled, we want to copy the
  1245. * raid map data first. If previously offload_enabled and
  1246. * offload_config were set, raid map data had better be
  1247. * the same as it was before. If raid map data has changed
  1248. * then it had better be the case that
  1249. * h->dev[entry]->offload_enabled is currently 0.
  1250. */
  1251. h->dev[entry]->raid_map = new_entry->raid_map;
  1252. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1253. }
  1254. if (new_entry->offload_to_be_enabled) {
  1255. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1256. wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
  1257. }
  1258. h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
  1259. h->dev[entry]->offload_config = new_entry->offload_config;
  1260. h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
  1261. h->dev[entry]->queue_depth = new_entry->queue_depth;
  1262. /*
  1263. * We can turn off ioaccel offload now, but need to delay turning
  1264. * ioaccel on until we can update h->dev[entry]->phys_disk[], but we
  1265. * can't do that until all the devices are updated.
  1266. */
  1267. h->dev[entry]->offload_to_be_enabled = new_entry->offload_to_be_enabled;
  1268. /*
  1269. * turn ioaccel off immediately if told to do so.
  1270. */
  1271. if (!new_entry->offload_to_be_enabled)
  1272. h->dev[entry]->offload_enabled = 0;
  1273. hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
  1274. }
  1275. /* Replace an entry from h->dev[] array. */
  1276. static void hpsa_scsi_replace_entry(struct ctlr_info *h,
  1277. int entry, struct hpsa_scsi_dev_t *new_entry,
  1278. struct hpsa_scsi_dev_t *added[], int *nadded,
  1279. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  1280. {
  1281. /* assumes h->devlock is held */
  1282. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1283. removed[*nremoved] = h->dev[entry];
  1284. (*nremoved)++;
  1285. /*
  1286. * New physical devices won't have target/lun assigned yet
  1287. * so we need to preserve the values in the slot we are replacing.
  1288. */
  1289. if (new_entry->target == -1) {
  1290. new_entry->target = h->dev[entry]->target;
  1291. new_entry->lun = h->dev[entry]->lun;
  1292. }
  1293. h->dev[entry] = new_entry;
  1294. added[*nadded] = new_entry;
  1295. (*nadded)++;
  1296. hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
  1297. }
  1298. /* Remove an entry from h->dev[] array. */
  1299. static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
  1300. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  1301. {
  1302. /* assumes h->devlock is held */
  1303. int i;
  1304. struct hpsa_scsi_dev_t *sd;
  1305. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1306. sd = h->dev[entry];
  1307. removed[*nremoved] = h->dev[entry];
  1308. (*nremoved)++;
  1309. for (i = entry; i < h->ndevices-1; i++)
  1310. h->dev[i] = h->dev[i+1];
  1311. h->ndevices--;
  1312. hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
  1313. }
  1314. #define SCSI3ADDR_EQ(a, b) ( \
  1315. (a)[7] == (b)[7] && \
  1316. (a)[6] == (b)[6] && \
  1317. (a)[5] == (b)[5] && \
  1318. (a)[4] == (b)[4] && \
  1319. (a)[3] == (b)[3] && \
  1320. (a)[2] == (b)[2] && \
  1321. (a)[1] == (b)[1] && \
  1322. (a)[0] == (b)[0])
  1323. static void fixup_botched_add(struct ctlr_info *h,
  1324. struct hpsa_scsi_dev_t *added)
  1325. {
  1326. /* called when scsi_add_device fails in order to re-adjust
  1327. * h->dev[] to match the mid layer's view.
  1328. */
  1329. unsigned long flags;
  1330. int i, j;
  1331. spin_lock_irqsave(&h->lock, flags);
  1332. for (i = 0; i < h->ndevices; i++) {
  1333. if (h->dev[i] == added) {
  1334. for (j = i; j < h->ndevices-1; j++)
  1335. h->dev[j] = h->dev[j+1];
  1336. h->ndevices--;
  1337. break;
  1338. }
  1339. }
  1340. spin_unlock_irqrestore(&h->lock, flags);
  1341. kfree(added);
  1342. }
  1343. static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
  1344. struct hpsa_scsi_dev_t *dev2)
  1345. {
  1346. /* we compare everything except lun and target as these
  1347. * are not yet assigned. Compare parts likely
  1348. * to differ first
  1349. */
  1350. if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
  1351. sizeof(dev1->scsi3addr)) != 0)
  1352. return 0;
  1353. if (memcmp(dev1->device_id, dev2->device_id,
  1354. sizeof(dev1->device_id)) != 0)
  1355. return 0;
  1356. if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
  1357. return 0;
  1358. if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
  1359. return 0;
  1360. if (dev1->devtype != dev2->devtype)
  1361. return 0;
  1362. if (dev1->bus != dev2->bus)
  1363. return 0;
  1364. return 1;
  1365. }
  1366. static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
  1367. struct hpsa_scsi_dev_t *dev2)
  1368. {
  1369. /* Device attributes that can change, but don't mean
  1370. * that the device is a different device, nor that the OS
  1371. * needs to be told anything about the change.
  1372. */
  1373. if (dev1->raid_level != dev2->raid_level)
  1374. return 1;
  1375. if (dev1->offload_config != dev2->offload_config)
  1376. return 1;
  1377. if (dev1->offload_to_be_enabled != dev2->offload_to_be_enabled)
  1378. return 1;
  1379. if (!is_logical_dev_addr_mode(dev1->scsi3addr))
  1380. if (dev1->queue_depth != dev2->queue_depth)
  1381. return 1;
  1382. /*
  1383. * This can happen for dual domain devices. An active
  1384. * path change causes the ioaccel handle to change
  1385. *
  1386. * for example note the handle differences between p0 and p1
  1387. * Device WWN ,WWN hash,Handle
  1388. * D016 p0|0x3 [02]P2E:01:01,0x5000C5005FC4DACA,0x9B5616,0x01030003
  1389. * p1 0x5000C5005FC4DAC9,0x6798C0,0x00040004
  1390. */
  1391. if (dev1->ioaccel_handle != dev2->ioaccel_handle)
  1392. return 1;
  1393. return 0;
  1394. }
  1395. /* Find needle in haystack. If exact match found, return DEVICE_SAME,
  1396. * and return needle location in *index. If scsi3addr matches, but not
  1397. * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
  1398. * location in *index.
  1399. * In the case of a minor device attribute change, such as RAID level, just
  1400. * return DEVICE_UPDATED, along with the updated device's location in index.
  1401. * If needle not found, return DEVICE_NOT_FOUND.
  1402. */
  1403. static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
  1404. struct hpsa_scsi_dev_t *haystack[], int haystack_size,
  1405. int *index)
  1406. {
  1407. int i;
  1408. #define DEVICE_NOT_FOUND 0
  1409. #define DEVICE_CHANGED 1
  1410. #define DEVICE_SAME 2
  1411. #define DEVICE_UPDATED 3
  1412. if (needle == NULL)
  1413. return DEVICE_NOT_FOUND;
  1414. for (i = 0; i < haystack_size; i++) {
  1415. if (haystack[i] == NULL) /* previously removed. */
  1416. continue;
  1417. if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
  1418. *index = i;
  1419. if (device_is_the_same(needle, haystack[i])) {
  1420. if (device_updated(needle, haystack[i]))
  1421. return DEVICE_UPDATED;
  1422. return DEVICE_SAME;
  1423. } else {
  1424. /* Keep offline devices offline */
  1425. if (needle->volume_offline)
  1426. return DEVICE_NOT_FOUND;
  1427. return DEVICE_CHANGED;
  1428. }
  1429. }
  1430. }
  1431. *index = -1;
  1432. return DEVICE_NOT_FOUND;
  1433. }
  1434. static void hpsa_monitor_offline_device(struct ctlr_info *h,
  1435. unsigned char scsi3addr[])
  1436. {
  1437. struct offline_device_entry *device;
  1438. unsigned long flags;
  1439. /* Check to see if device is already on the list */
  1440. spin_lock_irqsave(&h->offline_device_lock, flags);
  1441. list_for_each_entry(device, &h->offline_device_list, offline_list) {
  1442. if (memcmp(device->scsi3addr, scsi3addr,
  1443. sizeof(device->scsi3addr)) == 0) {
  1444. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1445. return;
  1446. }
  1447. }
  1448. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1449. /* Device is not on the list, add it. */
  1450. device = kmalloc_obj(*device);
  1451. if (!device)
  1452. return;
  1453. memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
  1454. spin_lock_irqsave(&h->offline_device_lock, flags);
  1455. list_add_tail(&device->offline_list, &h->offline_device_list);
  1456. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1457. }
  1458. /* Print a message explaining various offline volume states */
  1459. static void hpsa_show_volume_status(struct ctlr_info *h,
  1460. struct hpsa_scsi_dev_t *sd)
  1461. {
  1462. if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
  1463. dev_info(&h->pdev->dev,
  1464. "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
  1465. h->scsi_host->host_no,
  1466. sd->bus, sd->target, sd->lun);
  1467. switch (sd->volume_offline) {
  1468. case HPSA_LV_OK:
  1469. break;
  1470. case HPSA_LV_UNDERGOING_ERASE:
  1471. dev_info(&h->pdev->dev,
  1472. "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
  1473. h->scsi_host->host_no,
  1474. sd->bus, sd->target, sd->lun);
  1475. break;
  1476. case HPSA_LV_NOT_AVAILABLE:
  1477. dev_info(&h->pdev->dev,
  1478. "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
  1479. h->scsi_host->host_no,
  1480. sd->bus, sd->target, sd->lun);
  1481. break;
  1482. case HPSA_LV_UNDERGOING_RPI:
  1483. dev_info(&h->pdev->dev,
  1484. "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
  1485. h->scsi_host->host_no,
  1486. sd->bus, sd->target, sd->lun);
  1487. break;
  1488. case HPSA_LV_PENDING_RPI:
  1489. dev_info(&h->pdev->dev,
  1490. "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
  1491. h->scsi_host->host_no,
  1492. sd->bus, sd->target, sd->lun);
  1493. break;
  1494. case HPSA_LV_ENCRYPTED_NO_KEY:
  1495. dev_info(&h->pdev->dev,
  1496. "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
  1497. h->scsi_host->host_no,
  1498. sd->bus, sd->target, sd->lun);
  1499. break;
  1500. case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
  1501. dev_info(&h->pdev->dev,
  1502. "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
  1503. h->scsi_host->host_no,
  1504. sd->bus, sd->target, sd->lun);
  1505. break;
  1506. case HPSA_LV_UNDERGOING_ENCRYPTION:
  1507. dev_info(&h->pdev->dev,
  1508. "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
  1509. h->scsi_host->host_no,
  1510. sd->bus, sd->target, sd->lun);
  1511. break;
  1512. case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
  1513. dev_info(&h->pdev->dev,
  1514. "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
  1515. h->scsi_host->host_no,
  1516. sd->bus, sd->target, sd->lun);
  1517. break;
  1518. case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  1519. dev_info(&h->pdev->dev,
  1520. "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
  1521. h->scsi_host->host_no,
  1522. sd->bus, sd->target, sd->lun);
  1523. break;
  1524. case HPSA_LV_PENDING_ENCRYPTION:
  1525. dev_info(&h->pdev->dev,
  1526. "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
  1527. h->scsi_host->host_no,
  1528. sd->bus, sd->target, sd->lun);
  1529. break;
  1530. case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
  1531. dev_info(&h->pdev->dev,
  1532. "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
  1533. h->scsi_host->host_no,
  1534. sd->bus, sd->target, sd->lun);
  1535. break;
  1536. }
  1537. }
  1538. /*
  1539. * Figure the list of physical drive pointers for a logical drive with
  1540. * raid offload configured.
  1541. */
  1542. static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
  1543. struct hpsa_scsi_dev_t *dev[], int ndevices,
  1544. struct hpsa_scsi_dev_t *logical_drive)
  1545. {
  1546. struct raid_map_data *map = &logical_drive->raid_map;
  1547. struct raid_map_disk_data *dd = &map->data[0];
  1548. int i, j;
  1549. int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
  1550. le16_to_cpu(map->metadata_disks_per_row);
  1551. int nraid_map_entries = le16_to_cpu(map->row_cnt) *
  1552. le16_to_cpu(map->layout_map_count) *
  1553. total_disks_per_row;
  1554. int nphys_disk = le16_to_cpu(map->layout_map_count) *
  1555. total_disks_per_row;
  1556. int qdepth;
  1557. if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
  1558. nraid_map_entries = RAID_MAP_MAX_ENTRIES;
  1559. logical_drive->nphysical_disks = nraid_map_entries;
  1560. qdepth = 0;
  1561. for (i = 0; i < nraid_map_entries; i++) {
  1562. logical_drive->phys_disk[i] = NULL;
  1563. if (!logical_drive->offload_config)
  1564. continue;
  1565. for (j = 0; j < ndevices; j++) {
  1566. if (dev[j] == NULL)
  1567. continue;
  1568. if (dev[j]->devtype != TYPE_DISK &&
  1569. dev[j]->devtype != TYPE_ZBC)
  1570. continue;
  1571. if (is_logical_device(dev[j]))
  1572. continue;
  1573. if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
  1574. continue;
  1575. logical_drive->phys_disk[i] = dev[j];
  1576. if (i < nphys_disk)
  1577. qdepth = min(h->nr_cmds, qdepth +
  1578. logical_drive->phys_disk[i]->queue_depth);
  1579. break;
  1580. }
  1581. /*
  1582. * This can happen if a physical drive is removed and
  1583. * the logical drive is degraded. In that case, the RAID
  1584. * map data will refer to a physical disk which isn't actually
  1585. * present. And in that case offload_enabled should already
  1586. * be 0, but we'll turn it off here just in case
  1587. */
  1588. if (!logical_drive->phys_disk[i]) {
  1589. dev_warn(&h->pdev->dev,
  1590. "%s: [%d:%d:%d:%d] A phys disk component of LV is missing, turning off offload_enabled for LV.\n",
  1591. __func__,
  1592. h->scsi_host->host_no, logical_drive->bus,
  1593. logical_drive->target, logical_drive->lun);
  1594. hpsa_turn_off_ioaccel_for_device(logical_drive);
  1595. logical_drive->queue_depth = 8;
  1596. }
  1597. }
  1598. if (nraid_map_entries)
  1599. /*
  1600. * This is correct for reads, too high for full stripe writes,
  1601. * way too high for partial stripe writes
  1602. */
  1603. logical_drive->queue_depth = qdepth;
  1604. else {
  1605. if (logical_drive->external)
  1606. logical_drive->queue_depth = EXTERNAL_QD;
  1607. else
  1608. logical_drive->queue_depth = h->nr_cmds;
  1609. }
  1610. }
  1611. static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
  1612. struct hpsa_scsi_dev_t *dev[], int ndevices)
  1613. {
  1614. int i;
  1615. for (i = 0; i < ndevices; i++) {
  1616. if (dev[i] == NULL)
  1617. continue;
  1618. if (dev[i]->devtype != TYPE_DISK &&
  1619. dev[i]->devtype != TYPE_ZBC)
  1620. continue;
  1621. if (!is_logical_device(dev[i]))
  1622. continue;
  1623. /*
  1624. * If offload is currently enabled, the RAID map and
  1625. * phys_disk[] assignment *better* not be changing
  1626. * because we would be changing ioaccel phsy_disk[] pointers
  1627. * on a ioaccel volume processing I/O requests.
  1628. *
  1629. * If an ioaccel volume status changed, initially because it was
  1630. * re-configured and thus underwent a transformation, or
  1631. * a drive failed, we would have received a state change
  1632. * request and ioaccel should have been turned off. When the
  1633. * transformation completes, we get another state change
  1634. * request to turn ioaccel back on. In this case, we need
  1635. * to update the ioaccel information.
  1636. *
  1637. * Thus: If it is not currently enabled, but will be after
  1638. * the scan completes, make sure the ioaccel pointers
  1639. * are up to date.
  1640. */
  1641. if (!dev[i]->offload_enabled && dev[i]->offload_to_be_enabled)
  1642. hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
  1643. }
  1644. }
  1645. static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
  1646. {
  1647. int rc = 0;
  1648. if (!h->scsi_host)
  1649. return 1;
  1650. if (is_logical_device(device)) /* RAID */
  1651. rc = scsi_add_device(h->scsi_host, device->bus,
  1652. device->target, device->lun);
  1653. else /* HBA */
  1654. rc = hpsa_add_sas_device(h->sas_host, device);
  1655. return rc;
  1656. }
  1657. static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h,
  1658. struct hpsa_scsi_dev_t *dev)
  1659. {
  1660. int i;
  1661. int count = 0;
  1662. for (i = 0; i < h->nr_cmds; i++) {
  1663. struct CommandList *c = h->cmd_pool + i;
  1664. int refcount = atomic_inc_return(&c->refcount);
  1665. if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev,
  1666. dev->scsi3addr)) {
  1667. unsigned long flags;
  1668. spin_lock_irqsave(&h->lock, flags); /* Implied MB */
  1669. if (!hpsa_is_cmd_idle(c))
  1670. ++count;
  1671. spin_unlock_irqrestore(&h->lock, flags);
  1672. }
  1673. cmd_free(h, c);
  1674. }
  1675. return count;
  1676. }
  1677. #define NUM_WAIT 20
  1678. static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h,
  1679. struct hpsa_scsi_dev_t *device)
  1680. {
  1681. int cmds = 0;
  1682. int waits = 0;
  1683. int num_wait = NUM_WAIT;
  1684. if (device->external)
  1685. num_wait = HPSA_EH_PTRAID_TIMEOUT;
  1686. while (1) {
  1687. cmds = hpsa_find_outstanding_commands_for_dev(h, device);
  1688. if (cmds == 0)
  1689. break;
  1690. if (++waits > num_wait)
  1691. break;
  1692. msleep(1000);
  1693. }
  1694. if (waits > num_wait) {
  1695. dev_warn(&h->pdev->dev,
  1696. "%s: removing device [%d:%d:%d:%d] with %d outstanding commands!\n",
  1697. __func__,
  1698. h->scsi_host->host_no,
  1699. device->bus, device->target, device->lun, cmds);
  1700. }
  1701. }
  1702. static void hpsa_remove_device(struct ctlr_info *h,
  1703. struct hpsa_scsi_dev_t *device)
  1704. {
  1705. struct scsi_device *sdev = NULL;
  1706. if (!h->scsi_host)
  1707. return;
  1708. /*
  1709. * Allow for commands to drain
  1710. */
  1711. device->removed = 1;
  1712. hpsa_wait_for_outstanding_commands_for_dev(h, device);
  1713. if (is_logical_device(device)) { /* RAID */
  1714. sdev = scsi_device_lookup(h->scsi_host, device->bus,
  1715. device->target, device->lun);
  1716. if (sdev) {
  1717. scsi_remove_device(sdev);
  1718. scsi_device_put(sdev);
  1719. } else {
  1720. /*
  1721. * We don't expect to get here. Future commands
  1722. * to this device will get a selection timeout as
  1723. * if the device were gone.
  1724. */
  1725. hpsa_show_dev_msg(KERN_WARNING, h, device,
  1726. "didn't find device for removal.");
  1727. }
  1728. } else { /* HBA */
  1729. hpsa_remove_sas_device(device);
  1730. }
  1731. }
  1732. static void adjust_hpsa_scsi_table(struct ctlr_info *h,
  1733. struct hpsa_scsi_dev_t *sd[], int nsds)
  1734. {
  1735. /* sd contains scsi3 addresses and devtypes, and inquiry
  1736. * data. This function takes what's in sd to be the current
  1737. * reality and updates h->dev[] to reflect that reality.
  1738. */
  1739. int i, entry, device_change, changes = 0;
  1740. struct hpsa_scsi_dev_t *csd;
  1741. unsigned long flags;
  1742. struct hpsa_scsi_dev_t **added, **removed;
  1743. int nadded, nremoved;
  1744. /*
  1745. * A reset can cause a device status to change
  1746. * re-schedule the scan to see what happened.
  1747. */
  1748. spin_lock_irqsave(&h->reset_lock, flags);
  1749. if (h->reset_in_progress) {
  1750. h->drv_req_rescan = 1;
  1751. spin_unlock_irqrestore(&h->reset_lock, flags);
  1752. return;
  1753. }
  1754. spin_unlock_irqrestore(&h->reset_lock, flags);
  1755. added = kzalloc_objs(*added, HPSA_MAX_DEVICES);
  1756. removed = kzalloc_objs(*removed, HPSA_MAX_DEVICES);
  1757. if (!added || !removed) {
  1758. dev_warn(&h->pdev->dev, "out of memory in "
  1759. "adjust_hpsa_scsi_table\n");
  1760. goto free_and_out;
  1761. }
  1762. spin_lock_irqsave(&h->devlock, flags);
  1763. /* find any devices in h->dev[] that are not in
  1764. * sd[] and remove them from h->dev[], and for any
  1765. * devices which have changed, remove the old device
  1766. * info and add the new device info.
  1767. * If minor device attributes change, just update
  1768. * the existing device structure.
  1769. */
  1770. i = 0;
  1771. nremoved = 0;
  1772. nadded = 0;
  1773. while (i < h->ndevices) {
  1774. csd = h->dev[i];
  1775. device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
  1776. if (device_change == DEVICE_NOT_FOUND) {
  1777. changes++;
  1778. hpsa_scsi_remove_entry(h, i, removed, &nremoved);
  1779. continue; /* remove ^^^, hence i not incremented */
  1780. } else if (device_change == DEVICE_CHANGED) {
  1781. changes++;
  1782. hpsa_scsi_replace_entry(h, i, sd[entry],
  1783. added, &nadded, removed, &nremoved);
  1784. /* Set it to NULL to prevent it from being freed
  1785. * at the bottom of hpsa_update_scsi_devices()
  1786. */
  1787. sd[entry] = NULL;
  1788. } else if (device_change == DEVICE_UPDATED) {
  1789. hpsa_scsi_update_entry(h, i, sd[entry]);
  1790. }
  1791. i++;
  1792. }
  1793. /* Now, make sure every device listed in sd[] is also
  1794. * listed in h->dev[], adding them if they aren't found
  1795. */
  1796. for (i = 0; i < nsds; i++) {
  1797. if (!sd[i]) /* if already added above. */
  1798. continue;
  1799. /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
  1800. * as the SCSI mid-layer does not handle such devices well.
  1801. * It relentlessly loops sending TUR at 3Hz, then READ(10)
  1802. * at 160Hz, and prevents the system from coming up.
  1803. */
  1804. if (sd[i]->volume_offline) {
  1805. hpsa_show_volume_status(h, sd[i]);
  1806. hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
  1807. continue;
  1808. }
  1809. device_change = hpsa_scsi_find_entry(sd[i], h->dev,
  1810. h->ndevices, &entry);
  1811. if (device_change == DEVICE_NOT_FOUND) {
  1812. changes++;
  1813. if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
  1814. break;
  1815. sd[i] = NULL; /* prevent from being freed later. */
  1816. } else if (device_change == DEVICE_CHANGED) {
  1817. /* should never happen... */
  1818. changes++;
  1819. dev_warn(&h->pdev->dev,
  1820. "device unexpectedly changed.\n");
  1821. /* but if it does happen, we just ignore that device */
  1822. }
  1823. }
  1824. hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
  1825. /*
  1826. * Now that h->dev[]->phys_disk[] is coherent, we can enable
  1827. * any logical drives that need it enabled.
  1828. *
  1829. * The raid map should be current by now.
  1830. *
  1831. * We are updating the device list used for I/O requests.
  1832. */
  1833. for (i = 0; i < h->ndevices; i++) {
  1834. if (h->dev[i] == NULL)
  1835. continue;
  1836. h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
  1837. }
  1838. spin_unlock_irqrestore(&h->devlock, flags);
  1839. /* Monitor devices which are in one of several NOT READY states to be
  1840. * brought online later. This must be done without holding h->devlock,
  1841. * so don't touch h->dev[]
  1842. */
  1843. for (i = 0; i < nsds; i++) {
  1844. if (!sd[i]) /* if already added above. */
  1845. continue;
  1846. if (sd[i]->volume_offline)
  1847. hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
  1848. }
  1849. /* Don't notify scsi mid layer of any changes the first time through
  1850. * (or if there are no changes) scsi_scan_host will do it later the
  1851. * first time through.
  1852. */
  1853. if (!changes)
  1854. goto free_and_out;
  1855. /* Notify scsi mid layer of any removed devices */
  1856. for (i = 0; i < nremoved; i++) {
  1857. if (removed[i] == NULL)
  1858. continue;
  1859. if (removed[i]->expose_device)
  1860. hpsa_remove_device(h, removed[i]);
  1861. kfree(removed[i]);
  1862. removed[i] = NULL;
  1863. }
  1864. /* Notify scsi mid layer of any added devices */
  1865. for (i = 0; i < nadded; i++) {
  1866. int rc = 0;
  1867. if (added[i] == NULL)
  1868. continue;
  1869. if (!(added[i]->expose_device))
  1870. continue;
  1871. rc = hpsa_add_device(h, added[i]);
  1872. if (!rc)
  1873. continue;
  1874. dev_warn(&h->pdev->dev,
  1875. "addition failed %d, device not added.", rc);
  1876. /* now we have to remove it from h->dev,
  1877. * since it didn't get added to scsi mid layer
  1878. */
  1879. fixup_botched_add(h, added[i]);
  1880. h->drv_req_rescan = 1;
  1881. }
  1882. free_and_out:
  1883. kfree(added);
  1884. kfree(removed);
  1885. }
  1886. /*
  1887. * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
  1888. * Assume's h->devlock is held.
  1889. */
  1890. static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
  1891. int bus, int target, int lun)
  1892. {
  1893. int i;
  1894. struct hpsa_scsi_dev_t *sd;
  1895. for (i = 0; i < h->ndevices; i++) {
  1896. sd = h->dev[i];
  1897. if (sd->bus == bus && sd->target == target && sd->lun == lun)
  1898. return sd;
  1899. }
  1900. return NULL;
  1901. }
  1902. static int hpsa_sdev_init(struct scsi_device *sdev)
  1903. {
  1904. struct hpsa_scsi_dev_t *sd = NULL;
  1905. unsigned long flags;
  1906. struct ctlr_info *h;
  1907. h = sdev_to_hba(sdev);
  1908. spin_lock_irqsave(&h->devlock, flags);
  1909. if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
  1910. struct scsi_target *starget;
  1911. struct sas_rphy *rphy;
  1912. starget = scsi_target(sdev);
  1913. rphy = target_to_rphy(starget);
  1914. sd = hpsa_find_device_by_sas_rphy(h, rphy);
  1915. if (sd) {
  1916. sd->target = sdev_id(sdev);
  1917. sd->lun = sdev->lun;
  1918. }
  1919. }
  1920. if (!sd)
  1921. sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
  1922. sdev_id(sdev), sdev->lun);
  1923. if (sd && sd->expose_device) {
  1924. atomic_set(&sd->ioaccel_cmds_out, 0);
  1925. sdev->hostdata = sd;
  1926. } else
  1927. sdev->hostdata = NULL;
  1928. spin_unlock_irqrestore(&h->devlock, flags);
  1929. return 0;
  1930. }
  1931. /* configure scsi device based on internal per-device structure */
  1932. #define CTLR_TIMEOUT (120 * HZ)
  1933. static int hpsa_sdev_configure(struct scsi_device *sdev,
  1934. struct queue_limits *lim)
  1935. {
  1936. struct hpsa_scsi_dev_t *sd;
  1937. int queue_depth;
  1938. sd = sdev->hostdata;
  1939. sdev->no_uld_attach = !sd || !sd->expose_device;
  1940. if (sd) {
  1941. sd->was_removed = 0;
  1942. queue_depth = sd->queue_depth != 0 ?
  1943. sd->queue_depth : sdev->host->can_queue;
  1944. if (sd->external) {
  1945. queue_depth = EXTERNAL_QD;
  1946. sdev->eh_timeout = HPSA_EH_PTRAID_TIMEOUT;
  1947. blk_queue_rq_timeout(sdev->request_queue,
  1948. HPSA_EH_PTRAID_TIMEOUT);
  1949. }
  1950. if (is_hba_lunid(sd->scsi3addr)) {
  1951. sdev->eh_timeout = CTLR_TIMEOUT;
  1952. blk_queue_rq_timeout(sdev->request_queue, CTLR_TIMEOUT);
  1953. }
  1954. } else {
  1955. queue_depth = sdev->host->can_queue;
  1956. }
  1957. scsi_change_queue_depth(sdev, queue_depth);
  1958. return 0;
  1959. }
  1960. static void hpsa_sdev_destroy(struct scsi_device *sdev)
  1961. {
  1962. struct hpsa_scsi_dev_t *hdev = NULL;
  1963. hdev = sdev->hostdata;
  1964. if (hdev)
  1965. hdev->was_removed = 1;
  1966. }
  1967. static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
  1968. {
  1969. int i;
  1970. if (!h->ioaccel2_cmd_sg_list)
  1971. return;
  1972. for (i = 0; i < h->nr_cmds; i++) {
  1973. kfree(h->ioaccel2_cmd_sg_list[i]);
  1974. h->ioaccel2_cmd_sg_list[i] = NULL;
  1975. }
  1976. kfree(h->ioaccel2_cmd_sg_list);
  1977. h->ioaccel2_cmd_sg_list = NULL;
  1978. }
  1979. static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
  1980. {
  1981. int i;
  1982. if (h->chainsize <= 0)
  1983. return 0;
  1984. h->ioaccel2_cmd_sg_list =
  1985. kzalloc_objs(*h->ioaccel2_cmd_sg_list, h->nr_cmds);
  1986. if (!h->ioaccel2_cmd_sg_list)
  1987. return -ENOMEM;
  1988. for (i = 0; i < h->nr_cmds; i++) {
  1989. h->ioaccel2_cmd_sg_list[i] =
  1990. kmalloc_objs(*h->ioaccel2_cmd_sg_list[i],
  1991. h->maxsgentries);
  1992. if (!h->ioaccel2_cmd_sg_list[i])
  1993. goto clean;
  1994. }
  1995. return 0;
  1996. clean:
  1997. hpsa_free_ioaccel2_sg_chain_blocks(h);
  1998. return -ENOMEM;
  1999. }
  2000. static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
  2001. {
  2002. int i;
  2003. if (!h->cmd_sg_list)
  2004. return;
  2005. for (i = 0; i < h->nr_cmds; i++) {
  2006. kfree(h->cmd_sg_list[i]);
  2007. h->cmd_sg_list[i] = NULL;
  2008. }
  2009. kfree(h->cmd_sg_list);
  2010. h->cmd_sg_list = NULL;
  2011. }
  2012. static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
  2013. {
  2014. int i;
  2015. if (h->chainsize <= 0)
  2016. return 0;
  2017. h->cmd_sg_list = kzalloc_objs(*h->cmd_sg_list, h->nr_cmds);
  2018. if (!h->cmd_sg_list)
  2019. return -ENOMEM;
  2020. for (i = 0; i < h->nr_cmds; i++) {
  2021. h->cmd_sg_list[i] = kmalloc_objs(*h->cmd_sg_list[i],
  2022. h->chainsize);
  2023. if (!h->cmd_sg_list[i])
  2024. goto clean;
  2025. }
  2026. return 0;
  2027. clean:
  2028. hpsa_free_sg_chain_blocks(h);
  2029. return -ENOMEM;
  2030. }
  2031. static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
  2032. struct io_accel2_cmd *cp, struct CommandList *c)
  2033. {
  2034. struct ioaccel2_sg_element *chain_block;
  2035. u64 temp64;
  2036. u32 chain_size;
  2037. chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
  2038. chain_size = le32_to_cpu(cp->sg[0].length);
  2039. temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_size,
  2040. DMA_TO_DEVICE);
  2041. if (dma_mapping_error(&h->pdev->dev, temp64)) {
  2042. /* prevent subsequent unmapping */
  2043. cp->sg->address = 0;
  2044. return -1;
  2045. }
  2046. cp->sg->address = cpu_to_le64(temp64);
  2047. return 0;
  2048. }
  2049. static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
  2050. struct io_accel2_cmd *cp)
  2051. {
  2052. struct ioaccel2_sg_element *chain_sg;
  2053. u64 temp64;
  2054. u32 chain_size;
  2055. chain_sg = cp->sg;
  2056. temp64 = le64_to_cpu(chain_sg->address);
  2057. chain_size = le32_to_cpu(cp->sg[0].length);
  2058. dma_unmap_single(&h->pdev->dev, temp64, chain_size, DMA_TO_DEVICE);
  2059. }
  2060. static int hpsa_map_sg_chain_block(struct ctlr_info *h,
  2061. struct CommandList *c)
  2062. {
  2063. struct SGDescriptor *chain_sg, *chain_block;
  2064. u64 temp64;
  2065. u32 chain_len;
  2066. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  2067. chain_block = h->cmd_sg_list[c->cmdindex];
  2068. chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
  2069. chain_len = sizeof(*chain_sg) *
  2070. (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
  2071. chain_sg->Len = cpu_to_le32(chain_len);
  2072. temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_len,
  2073. DMA_TO_DEVICE);
  2074. if (dma_mapping_error(&h->pdev->dev, temp64)) {
  2075. /* prevent subsequent unmapping */
  2076. chain_sg->Addr = cpu_to_le64(0);
  2077. return -1;
  2078. }
  2079. chain_sg->Addr = cpu_to_le64(temp64);
  2080. return 0;
  2081. }
  2082. static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
  2083. struct CommandList *c)
  2084. {
  2085. struct SGDescriptor *chain_sg;
  2086. if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
  2087. return;
  2088. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  2089. dma_unmap_single(&h->pdev->dev, le64_to_cpu(chain_sg->Addr),
  2090. le32_to_cpu(chain_sg->Len), DMA_TO_DEVICE);
  2091. }
  2092. /* Decode the various types of errors on ioaccel2 path.
  2093. * Return 1 for any error that should generate a RAID path retry.
  2094. * Return 0 for errors that don't require a RAID path retry.
  2095. */
  2096. static int handle_ioaccel_mode2_error(struct ctlr_info *h,
  2097. struct CommandList *c,
  2098. struct scsi_cmnd *cmd,
  2099. struct io_accel2_cmd *c2,
  2100. struct hpsa_scsi_dev_t *dev)
  2101. {
  2102. int data_len;
  2103. int retry = 0;
  2104. u32 ioaccel2_resid = 0;
  2105. switch (c2->error_data.serv_response) {
  2106. case IOACCEL2_SERV_RESPONSE_COMPLETE:
  2107. switch (c2->error_data.status) {
  2108. case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
  2109. if (cmd)
  2110. cmd->result = 0;
  2111. break;
  2112. case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
  2113. cmd->result |= SAM_STAT_CHECK_CONDITION;
  2114. if (c2->error_data.data_present !=
  2115. IOACCEL2_SENSE_DATA_PRESENT) {
  2116. memset(cmd->sense_buffer, 0,
  2117. SCSI_SENSE_BUFFERSIZE);
  2118. break;
  2119. }
  2120. /* copy the sense data */
  2121. data_len = c2->error_data.sense_data_len;
  2122. if (data_len > SCSI_SENSE_BUFFERSIZE)
  2123. data_len = SCSI_SENSE_BUFFERSIZE;
  2124. if (data_len > sizeof(c2->error_data.sense_data_buff))
  2125. data_len =
  2126. sizeof(c2->error_data.sense_data_buff);
  2127. memcpy(cmd->sense_buffer,
  2128. c2->error_data.sense_data_buff, data_len);
  2129. retry = 1;
  2130. break;
  2131. case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
  2132. retry = 1;
  2133. break;
  2134. case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
  2135. retry = 1;
  2136. break;
  2137. case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
  2138. retry = 1;
  2139. break;
  2140. case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
  2141. retry = 1;
  2142. break;
  2143. default:
  2144. retry = 1;
  2145. break;
  2146. }
  2147. break;
  2148. case IOACCEL2_SERV_RESPONSE_FAILURE:
  2149. switch (c2->error_data.status) {
  2150. case IOACCEL2_STATUS_SR_IO_ERROR:
  2151. case IOACCEL2_STATUS_SR_IO_ABORTED:
  2152. case IOACCEL2_STATUS_SR_OVERRUN:
  2153. retry = 1;
  2154. break;
  2155. case IOACCEL2_STATUS_SR_UNDERRUN:
  2156. cmd->result = (DID_OK << 16); /* host byte */
  2157. ioaccel2_resid = get_unaligned_le32(
  2158. &c2->error_data.resid_cnt[0]);
  2159. scsi_set_resid(cmd, ioaccel2_resid);
  2160. break;
  2161. case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
  2162. case IOACCEL2_STATUS_SR_INVALID_DEVICE:
  2163. case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
  2164. /*
  2165. * Did an HBA disk disappear? We will eventually
  2166. * get a state change event from the controller but
  2167. * in the meantime, we need to tell the OS that the
  2168. * HBA disk is no longer there and stop I/O
  2169. * from going down. This allows the potential re-insert
  2170. * of the disk to get the same device node.
  2171. */
  2172. if (dev->physical_device && dev->expose_device) {
  2173. cmd->result = DID_NO_CONNECT << 16;
  2174. dev->removed = 1;
  2175. h->drv_req_rescan = 1;
  2176. dev_warn(&h->pdev->dev,
  2177. "%s: device is gone!\n", __func__);
  2178. } else
  2179. /*
  2180. * Retry by sending down the RAID path.
  2181. * We will get an event from ctlr to
  2182. * trigger rescan regardless.
  2183. */
  2184. retry = 1;
  2185. break;
  2186. default:
  2187. retry = 1;
  2188. }
  2189. break;
  2190. case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
  2191. break;
  2192. case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
  2193. break;
  2194. case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
  2195. retry = 1;
  2196. break;
  2197. case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
  2198. break;
  2199. default:
  2200. retry = 1;
  2201. break;
  2202. }
  2203. if (dev->in_reset)
  2204. retry = 0;
  2205. return retry; /* retry on raid path? */
  2206. }
  2207. static void hpsa_cmd_resolve_events(struct ctlr_info *h,
  2208. struct CommandList *c)
  2209. {
  2210. struct hpsa_scsi_dev_t *dev = c->device;
  2211. /*
  2212. * Reset c->scsi_cmd here so that the reset handler will know
  2213. * this command has completed. Then, check to see if the handler is
  2214. * waiting for this command, and, if so, wake it.
  2215. */
  2216. c->scsi_cmd = SCSI_CMD_IDLE;
  2217. mb(); /* Declare command idle before checking for pending events. */
  2218. if (dev) {
  2219. atomic_dec(&dev->commands_outstanding);
  2220. if (dev->in_reset &&
  2221. atomic_read(&dev->commands_outstanding) <= 0)
  2222. wake_up_all(&h->event_sync_wait_queue);
  2223. }
  2224. }
  2225. static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
  2226. struct CommandList *c)
  2227. {
  2228. hpsa_cmd_resolve_events(h, c);
  2229. cmd_tagged_free(h, c);
  2230. }
  2231. static void hpsa_cmd_free_and_done(struct ctlr_info *h,
  2232. struct CommandList *c, struct scsi_cmnd *cmd)
  2233. {
  2234. hpsa_cmd_resolve_and_free(h, c);
  2235. if (cmd)
  2236. scsi_done(cmd);
  2237. }
  2238. static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
  2239. {
  2240. INIT_WORK(&c->work, hpsa_command_resubmit_worker);
  2241. queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
  2242. }
  2243. static void process_ioaccel2_completion(struct ctlr_info *h,
  2244. struct CommandList *c, struct scsi_cmnd *cmd,
  2245. struct hpsa_scsi_dev_t *dev)
  2246. {
  2247. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  2248. /* check for good status */
  2249. if (likely(c2->error_data.serv_response == 0 &&
  2250. c2->error_data.status == 0)) {
  2251. cmd->result = 0;
  2252. return hpsa_cmd_free_and_done(h, c, cmd);
  2253. }
  2254. /*
  2255. * Any RAID offload error results in retry which will use
  2256. * the normal I/O path so the controller can handle whatever is
  2257. * wrong.
  2258. */
  2259. if (is_logical_device(dev) &&
  2260. c2->error_data.serv_response ==
  2261. IOACCEL2_SERV_RESPONSE_FAILURE) {
  2262. if (c2->error_data.status ==
  2263. IOACCEL2_STATUS_SR_IOACCEL_DISABLED) {
  2264. hpsa_turn_off_ioaccel_for_device(dev);
  2265. }
  2266. if (dev->in_reset) {
  2267. cmd->result = DID_RESET << 16;
  2268. return hpsa_cmd_free_and_done(h, c, cmd);
  2269. }
  2270. return hpsa_retry_cmd(h, c);
  2271. }
  2272. if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev))
  2273. return hpsa_retry_cmd(h, c);
  2274. return hpsa_cmd_free_and_done(h, c, cmd);
  2275. }
  2276. /* Returns 0 on success, < 0 otherwise. */
  2277. static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
  2278. struct CommandList *cp)
  2279. {
  2280. u8 tmf_status = cp->err_info->ScsiStatus;
  2281. switch (tmf_status) {
  2282. case CISS_TMF_COMPLETE:
  2283. /*
  2284. * CISS_TMF_COMPLETE never happens, instead,
  2285. * ei->CommandStatus == 0 for this case.
  2286. */
  2287. case CISS_TMF_SUCCESS:
  2288. return 0;
  2289. case CISS_TMF_INVALID_FRAME:
  2290. case CISS_TMF_NOT_SUPPORTED:
  2291. case CISS_TMF_FAILED:
  2292. case CISS_TMF_WRONG_LUN:
  2293. case CISS_TMF_OVERLAPPED_TAG:
  2294. break;
  2295. default:
  2296. dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
  2297. tmf_status);
  2298. break;
  2299. }
  2300. return -tmf_status;
  2301. }
  2302. static void complete_scsi_command(struct CommandList *cp)
  2303. {
  2304. struct scsi_cmnd *cmd;
  2305. struct ctlr_info *h;
  2306. struct ErrorInfo *ei;
  2307. struct hpsa_scsi_dev_t *dev;
  2308. struct io_accel2_cmd *c2;
  2309. u8 sense_key;
  2310. u8 asc; /* additional sense code */
  2311. u8 ascq; /* additional sense code qualifier */
  2312. unsigned long sense_data_size;
  2313. ei = cp->err_info;
  2314. cmd = cp->scsi_cmd;
  2315. h = cp->h;
  2316. if (!cmd->device) {
  2317. cmd->result = DID_NO_CONNECT << 16;
  2318. return hpsa_cmd_free_and_done(h, cp, cmd);
  2319. }
  2320. dev = cmd->device->hostdata;
  2321. if (!dev) {
  2322. cmd->result = DID_NO_CONNECT << 16;
  2323. return hpsa_cmd_free_and_done(h, cp, cmd);
  2324. }
  2325. c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
  2326. scsi_dma_unmap(cmd); /* undo the DMA mappings */
  2327. if ((cp->cmd_type == CMD_SCSI) &&
  2328. (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
  2329. hpsa_unmap_sg_chain_block(h, cp);
  2330. if ((cp->cmd_type == CMD_IOACCEL2) &&
  2331. (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
  2332. hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
  2333. cmd->result = (DID_OK << 16); /* host byte */
  2334. /* SCSI command has already been cleaned up in SML */
  2335. if (dev->was_removed) {
  2336. hpsa_cmd_resolve_and_free(h, cp);
  2337. return;
  2338. }
  2339. if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) {
  2340. if (dev->physical_device && dev->expose_device &&
  2341. dev->removed) {
  2342. cmd->result = DID_NO_CONNECT << 16;
  2343. return hpsa_cmd_free_and_done(h, cp, cmd);
  2344. }
  2345. if (likely(cp->phys_disk != NULL))
  2346. atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
  2347. }
  2348. /*
  2349. * We check for lockup status here as it may be set for
  2350. * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
  2351. * fail_all_oustanding_cmds()
  2352. */
  2353. if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
  2354. /* DID_NO_CONNECT will prevent a retry */
  2355. cmd->result = DID_NO_CONNECT << 16;
  2356. return hpsa_cmd_free_and_done(h, cp, cmd);
  2357. }
  2358. if (cp->cmd_type == CMD_IOACCEL2)
  2359. return process_ioaccel2_completion(h, cp, cmd, dev);
  2360. scsi_set_resid(cmd, ei->ResidualCnt);
  2361. if (ei->CommandStatus == 0)
  2362. return hpsa_cmd_free_and_done(h, cp, cmd);
  2363. /* For I/O accelerator commands, copy over some fields to the normal
  2364. * CISS header used below for error handling.
  2365. */
  2366. if (cp->cmd_type == CMD_IOACCEL1) {
  2367. struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
  2368. cp->Header.SGList = scsi_sg_count(cmd);
  2369. cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
  2370. cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
  2371. IOACCEL1_IOFLAGS_CDBLEN_MASK;
  2372. cp->Header.tag = c->tag;
  2373. memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
  2374. memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
  2375. /* Any RAID offload error results in retry which will use
  2376. * the normal I/O path so the controller can handle whatever's
  2377. * wrong.
  2378. */
  2379. if (is_logical_device(dev)) {
  2380. if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
  2381. dev->offload_enabled = 0;
  2382. return hpsa_retry_cmd(h, cp);
  2383. }
  2384. }
  2385. /* an error has occurred */
  2386. switch (ei->CommandStatus) {
  2387. case CMD_TARGET_STATUS:
  2388. cmd->result |= ei->ScsiStatus;
  2389. /* copy the sense data */
  2390. sense_data_size = min_t(unsigned long, SCSI_SENSE_BUFFERSIZE,
  2391. sizeof(ei->SenseInfo));
  2392. if (ei->SenseLen < sense_data_size)
  2393. sense_data_size = ei->SenseLen;
  2394. memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
  2395. if (ei->ScsiStatus)
  2396. decode_sense_data(ei->SenseInfo, sense_data_size,
  2397. &sense_key, &asc, &ascq);
  2398. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
  2399. switch (sense_key) {
  2400. case ABORTED_COMMAND:
  2401. cmd->result |= DID_SOFT_ERROR << 16;
  2402. break;
  2403. case UNIT_ATTENTION:
  2404. if (asc == 0x3F && ascq == 0x0E)
  2405. h->drv_req_rescan = 1;
  2406. break;
  2407. case ILLEGAL_REQUEST:
  2408. if (asc == 0x25 && ascq == 0x00) {
  2409. dev->removed = 1;
  2410. cmd->result = DID_NO_CONNECT << 16;
  2411. }
  2412. break;
  2413. }
  2414. break;
  2415. }
  2416. /* Problem was not a check condition
  2417. * Pass it up to the upper layers...
  2418. */
  2419. if (ei->ScsiStatus) {
  2420. dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
  2421. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  2422. "Returning result: 0x%x\n",
  2423. cp, ei->ScsiStatus,
  2424. sense_key, asc, ascq,
  2425. cmd->result);
  2426. } else { /* scsi status is zero??? How??? */
  2427. dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
  2428. "Returning no connection.\n", cp),
  2429. /* Ordinarily, this case should never happen,
  2430. * but there is a bug in some released firmware
  2431. * revisions that allows it to happen if, for
  2432. * example, a 4100 backplane loses power and
  2433. * the tape drive is in it. We assume that
  2434. * it's a fatal error of some kind because we
  2435. * can't show that it wasn't. We will make it
  2436. * look like selection timeout since that is
  2437. * the most common reason for this to occur,
  2438. * and it's severe enough.
  2439. */
  2440. cmd->result = DID_NO_CONNECT << 16;
  2441. }
  2442. break;
  2443. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  2444. break;
  2445. case CMD_DATA_OVERRUN:
  2446. dev_warn(&h->pdev->dev,
  2447. "CDB %16phN data overrun\n", cp->Request.CDB);
  2448. break;
  2449. case CMD_INVALID: {
  2450. /* print_bytes(cp, sizeof(*cp), 1, 0);
  2451. print_cmd(cp); */
  2452. /* We get CMD_INVALID if you address a non-existent device
  2453. * instead of a selection timeout (no response). You will
  2454. * see this if you yank out a drive, then try to access it.
  2455. * This is kind of a shame because it means that any other
  2456. * CMD_INVALID (e.g. driver bug) will get interpreted as a
  2457. * missing target. */
  2458. cmd->result = DID_NO_CONNECT << 16;
  2459. }
  2460. break;
  2461. case CMD_PROTOCOL_ERR:
  2462. cmd->result = DID_ERROR << 16;
  2463. dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
  2464. cp->Request.CDB);
  2465. break;
  2466. case CMD_HARDWARE_ERR:
  2467. cmd->result = DID_ERROR << 16;
  2468. dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
  2469. cp->Request.CDB);
  2470. break;
  2471. case CMD_CONNECTION_LOST:
  2472. cmd->result = DID_ERROR << 16;
  2473. dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
  2474. cp->Request.CDB);
  2475. break;
  2476. case CMD_ABORTED:
  2477. cmd->result = DID_ABORT << 16;
  2478. break;
  2479. case CMD_ABORT_FAILED:
  2480. cmd->result = DID_ERROR << 16;
  2481. dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
  2482. cp->Request.CDB);
  2483. break;
  2484. case CMD_UNSOLICITED_ABORT:
  2485. cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
  2486. dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
  2487. cp->Request.CDB);
  2488. break;
  2489. case CMD_TIMEOUT:
  2490. cmd->result = DID_TIME_OUT << 16;
  2491. dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
  2492. cp->Request.CDB);
  2493. break;
  2494. case CMD_UNABORTABLE:
  2495. cmd->result = DID_ERROR << 16;
  2496. dev_warn(&h->pdev->dev, "Command unabortable\n");
  2497. break;
  2498. case CMD_TMF_STATUS:
  2499. if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
  2500. cmd->result = DID_ERROR << 16;
  2501. break;
  2502. case CMD_IOACCEL_DISABLED:
  2503. /* This only handles the direct pass-through case since RAID
  2504. * offload is handled above. Just attempt a retry.
  2505. */
  2506. cmd->result = DID_SOFT_ERROR << 16;
  2507. dev_warn(&h->pdev->dev,
  2508. "cp %p had HP SSD Smart Path error\n", cp);
  2509. break;
  2510. default:
  2511. cmd->result = DID_ERROR << 16;
  2512. dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
  2513. cp, ei->CommandStatus);
  2514. }
  2515. return hpsa_cmd_free_and_done(h, cp, cmd);
  2516. }
  2517. static void hpsa_pci_unmap(struct pci_dev *pdev, struct CommandList *c,
  2518. int sg_used, enum dma_data_direction data_direction)
  2519. {
  2520. int i;
  2521. for (i = 0; i < sg_used; i++)
  2522. dma_unmap_single(&pdev->dev, le64_to_cpu(c->SG[i].Addr),
  2523. le32_to_cpu(c->SG[i].Len),
  2524. data_direction);
  2525. }
  2526. static int hpsa_map_one(struct pci_dev *pdev,
  2527. struct CommandList *cp,
  2528. unsigned char *buf,
  2529. size_t buflen,
  2530. enum dma_data_direction data_direction)
  2531. {
  2532. u64 addr64;
  2533. if (buflen == 0 || data_direction == DMA_NONE) {
  2534. cp->Header.SGList = 0;
  2535. cp->Header.SGTotal = cpu_to_le16(0);
  2536. return 0;
  2537. }
  2538. addr64 = dma_map_single(&pdev->dev, buf, buflen, data_direction);
  2539. if (dma_mapping_error(&pdev->dev, addr64)) {
  2540. /* Prevent subsequent unmap of something never mapped */
  2541. cp->Header.SGList = 0;
  2542. cp->Header.SGTotal = cpu_to_le16(0);
  2543. return -1;
  2544. }
  2545. cp->SG[0].Addr = cpu_to_le64(addr64);
  2546. cp->SG[0].Len = cpu_to_le32(buflen);
  2547. cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
  2548. cp->Header.SGList = 1; /* no. SGs contig in this cmd */
  2549. cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
  2550. return 0;
  2551. }
  2552. #define NO_TIMEOUT ((unsigned long) -1)
  2553. #define DEFAULT_TIMEOUT 30000 /* milliseconds */
  2554. static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
  2555. struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
  2556. {
  2557. DECLARE_COMPLETION_ONSTACK(wait);
  2558. c->waiting = &wait;
  2559. __enqueue_cmd_and_start_io(h, c, reply_queue);
  2560. if (timeout_msecs == NO_TIMEOUT) {
  2561. /* TODO: get rid of this no-timeout thing */
  2562. wait_for_completion_io(&wait);
  2563. return IO_OK;
  2564. }
  2565. if (!wait_for_completion_io_timeout(&wait,
  2566. msecs_to_jiffies(timeout_msecs))) {
  2567. dev_warn(&h->pdev->dev, "Command timed out.\n");
  2568. return -ETIMEDOUT;
  2569. }
  2570. return IO_OK;
  2571. }
  2572. static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
  2573. int reply_queue, unsigned long timeout_msecs)
  2574. {
  2575. if (unlikely(lockup_detected(h))) {
  2576. c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
  2577. return IO_OK;
  2578. }
  2579. return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
  2580. }
  2581. static u32 lockup_detected(struct ctlr_info *h)
  2582. {
  2583. int cpu;
  2584. u32 rc, *lockup_detected;
  2585. cpu = get_cpu();
  2586. lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
  2587. rc = *lockup_detected;
  2588. put_cpu();
  2589. return rc;
  2590. }
  2591. #define MAX_DRIVER_CMD_RETRIES 25
  2592. static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
  2593. struct CommandList *c, enum dma_data_direction data_direction,
  2594. unsigned long timeout_msecs)
  2595. {
  2596. int backoff_time = 10, retry_count = 0;
  2597. int rc;
  2598. do {
  2599. memset(c->err_info, 0, sizeof(*c->err_info));
  2600. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  2601. timeout_msecs);
  2602. if (rc)
  2603. break;
  2604. retry_count++;
  2605. if (retry_count > 3) {
  2606. msleep(backoff_time);
  2607. if (backoff_time < 1000)
  2608. backoff_time *= 2;
  2609. }
  2610. } while ((check_for_unit_attention(h, c) ||
  2611. check_for_busy(h, c)) &&
  2612. retry_count <= MAX_DRIVER_CMD_RETRIES);
  2613. hpsa_pci_unmap(h->pdev, c, 1, data_direction);
  2614. if (retry_count > MAX_DRIVER_CMD_RETRIES)
  2615. rc = -EIO;
  2616. return rc;
  2617. }
  2618. static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
  2619. struct CommandList *c)
  2620. {
  2621. const u8 *cdb = c->Request.CDB;
  2622. const u8 *lun = c->Header.LUN.LunAddrBytes;
  2623. dev_warn(&h->pdev->dev, "%s: LUN:%8phN CDB:%16phN\n",
  2624. txt, lun, cdb);
  2625. }
  2626. static void hpsa_scsi_interpret_error(struct ctlr_info *h,
  2627. struct CommandList *cp)
  2628. {
  2629. const struct ErrorInfo *ei = cp->err_info;
  2630. struct device *d = &cp->h->pdev->dev;
  2631. u8 sense_key, asc, ascq;
  2632. int sense_len;
  2633. switch (ei->CommandStatus) {
  2634. case CMD_TARGET_STATUS:
  2635. if (ei->SenseLen > sizeof(ei->SenseInfo))
  2636. sense_len = sizeof(ei->SenseInfo);
  2637. else
  2638. sense_len = ei->SenseLen;
  2639. decode_sense_data(ei->SenseInfo, sense_len,
  2640. &sense_key, &asc, &ascq);
  2641. hpsa_print_cmd(h, "SCSI status", cp);
  2642. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
  2643. dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
  2644. sense_key, asc, ascq);
  2645. else
  2646. dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
  2647. if (ei->ScsiStatus == 0)
  2648. dev_warn(d, "SCSI status is abnormally zero. "
  2649. "(probably indicates selection timeout "
  2650. "reported incorrectly due to a known "
  2651. "firmware bug, circa July, 2001.)\n");
  2652. break;
  2653. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  2654. break;
  2655. case CMD_DATA_OVERRUN:
  2656. hpsa_print_cmd(h, "overrun condition", cp);
  2657. break;
  2658. case CMD_INVALID: {
  2659. /* controller unfortunately reports SCSI passthru's
  2660. * to non-existent targets as invalid commands.
  2661. */
  2662. hpsa_print_cmd(h, "invalid command", cp);
  2663. dev_warn(d, "probably means device no longer present\n");
  2664. }
  2665. break;
  2666. case CMD_PROTOCOL_ERR:
  2667. hpsa_print_cmd(h, "protocol error", cp);
  2668. break;
  2669. case CMD_HARDWARE_ERR:
  2670. hpsa_print_cmd(h, "hardware error", cp);
  2671. break;
  2672. case CMD_CONNECTION_LOST:
  2673. hpsa_print_cmd(h, "connection lost", cp);
  2674. break;
  2675. case CMD_ABORTED:
  2676. hpsa_print_cmd(h, "aborted", cp);
  2677. break;
  2678. case CMD_ABORT_FAILED:
  2679. hpsa_print_cmd(h, "abort failed", cp);
  2680. break;
  2681. case CMD_UNSOLICITED_ABORT:
  2682. hpsa_print_cmd(h, "unsolicited abort", cp);
  2683. break;
  2684. case CMD_TIMEOUT:
  2685. hpsa_print_cmd(h, "timed out", cp);
  2686. break;
  2687. case CMD_UNABORTABLE:
  2688. hpsa_print_cmd(h, "unabortable", cp);
  2689. break;
  2690. case CMD_CTLR_LOCKUP:
  2691. hpsa_print_cmd(h, "controller lockup detected", cp);
  2692. break;
  2693. default:
  2694. hpsa_print_cmd(h, "unknown status", cp);
  2695. dev_warn(d, "Unknown command status %x\n",
  2696. ei->CommandStatus);
  2697. }
  2698. }
  2699. static int hpsa_do_receive_diagnostic(struct ctlr_info *h, u8 *scsi3addr,
  2700. u8 page, u8 *buf, size_t bufsize)
  2701. {
  2702. int rc = IO_OK;
  2703. struct CommandList *c;
  2704. struct ErrorInfo *ei;
  2705. c = cmd_alloc(h);
  2706. if (fill_cmd(c, RECEIVE_DIAGNOSTIC, h, buf, bufsize,
  2707. page, scsi3addr, TYPE_CMD)) {
  2708. rc = -1;
  2709. goto out;
  2710. }
  2711. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  2712. NO_TIMEOUT);
  2713. if (rc)
  2714. goto out;
  2715. ei = c->err_info;
  2716. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2717. hpsa_scsi_interpret_error(h, c);
  2718. rc = -1;
  2719. }
  2720. out:
  2721. cmd_free(h, c);
  2722. return rc;
  2723. }
  2724. static u64 hpsa_get_enclosure_logical_identifier(struct ctlr_info *h,
  2725. u8 *scsi3addr)
  2726. {
  2727. u8 *buf;
  2728. u64 sa = 0;
  2729. int rc = 0;
  2730. buf = kzalloc(1024, GFP_KERNEL);
  2731. if (!buf)
  2732. return 0;
  2733. rc = hpsa_do_receive_diagnostic(h, scsi3addr, RECEIVE_DIAGNOSTIC,
  2734. buf, 1024);
  2735. if (rc)
  2736. goto out;
  2737. sa = get_unaligned_be64(buf+12);
  2738. out:
  2739. kfree(buf);
  2740. return sa;
  2741. }
  2742. static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
  2743. u16 page, unsigned char *buf,
  2744. unsigned char bufsize)
  2745. {
  2746. int rc = IO_OK;
  2747. struct CommandList *c;
  2748. struct ErrorInfo *ei;
  2749. c = cmd_alloc(h);
  2750. if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
  2751. page, scsi3addr, TYPE_CMD)) {
  2752. rc = -1;
  2753. goto out;
  2754. }
  2755. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  2756. NO_TIMEOUT);
  2757. if (rc)
  2758. goto out;
  2759. ei = c->err_info;
  2760. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2761. hpsa_scsi_interpret_error(h, c);
  2762. rc = -1;
  2763. }
  2764. out:
  2765. cmd_free(h, c);
  2766. return rc;
  2767. }
  2768. static int hpsa_send_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
  2769. u8 reset_type, int reply_queue)
  2770. {
  2771. int rc = IO_OK;
  2772. struct CommandList *c;
  2773. struct ErrorInfo *ei;
  2774. c = cmd_alloc(h);
  2775. c->device = dev;
  2776. /* fill_cmd can't fail here, no data buffer to map. */
  2777. (void) fill_cmd(c, reset_type, h, NULL, 0, 0, dev->scsi3addr, TYPE_MSG);
  2778. rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
  2779. if (rc) {
  2780. dev_warn(&h->pdev->dev, "Failed to send reset command\n");
  2781. goto out;
  2782. }
  2783. /* no unmap needed here because no data xfer. */
  2784. ei = c->err_info;
  2785. if (ei->CommandStatus != 0) {
  2786. hpsa_scsi_interpret_error(h, c);
  2787. rc = -1;
  2788. }
  2789. out:
  2790. cmd_free(h, c);
  2791. return rc;
  2792. }
  2793. static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
  2794. struct hpsa_scsi_dev_t *dev,
  2795. unsigned char *scsi3addr)
  2796. {
  2797. int i;
  2798. bool match = false;
  2799. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  2800. struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
  2801. if (hpsa_is_cmd_idle(c))
  2802. return false;
  2803. switch (c->cmd_type) {
  2804. case CMD_SCSI:
  2805. case CMD_IOCTL_PEND:
  2806. match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
  2807. sizeof(c->Header.LUN.LunAddrBytes));
  2808. break;
  2809. case CMD_IOACCEL1:
  2810. case CMD_IOACCEL2:
  2811. if (c->phys_disk == dev) {
  2812. /* HBA mode match */
  2813. match = true;
  2814. } else {
  2815. /* Possible RAID mode -- check each phys dev. */
  2816. /* FIXME: Do we need to take out a lock here? If
  2817. * so, we could just call hpsa_get_pdisk_of_ioaccel2()
  2818. * instead. */
  2819. for (i = 0; i < dev->nphysical_disks && !match; i++) {
  2820. /* FIXME: an alternate test might be
  2821. *
  2822. * match = dev->phys_disk[i]->ioaccel_handle
  2823. * == c2->scsi_nexus; */
  2824. match = dev->phys_disk[i] == c->phys_disk;
  2825. }
  2826. }
  2827. break;
  2828. case IOACCEL2_TMF:
  2829. for (i = 0; i < dev->nphysical_disks && !match; i++) {
  2830. match = dev->phys_disk[i]->ioaccel_handle ==
  2831. le32_to_cpu(ac->it_nexus);
  2832. }
  2833. break;
  2834. case 0: /* The command is in the middle of being initialized. */
  2835. match = false;
  2836. break;
  2837. default:
  2838. dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
  2839. c->cmd_type);
  2840. BUG();
  2841. }
  2842. return match;
  2843. }
  2844. static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
  2845. u8 reset_type, int reply_queue)
  2846. {
  2847. int rc = 0;
  2848. /* We can really only handle one reset at a time */
  2849. if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
  2850. dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
  2851. return -EINTR;
  2852. }
  2853. rc = hpsa_send_reset(h, dev, reset_type, reply_queue);
  2854. if (!rc) {
  2855. /* incremented by sending the reset request */
  2856. atomic_dec(&dev->commands_outstanding);
  2857. wait_event(h->event_sync_wait_queue,
  2858. atomic_read(&dev->commands_outstanding) <= 0 ||
  2859. lockup_detected(h));
  2860. }
  2861. if (unlikely(lockup_detected(h))) {
  2862. dev_warn(&h->pdev->dev,
  2863. "Controller lockup detected during reset wait\n");
  2864. rc = -ENODEV;
  2865. }
  2866. if (!rc)
  2867. rc = wait_for_device_to_become_ready(h, dev->scsi3addr, 0);
  2868. mutex_unlock(&h->reset_mutex);
  2869. return rc;
  2870. }
  2871. static void hpsa_get_raid_level(struct ctlr_info *h,
  2872. unsigned char *scsi3addr, unsigned char *raid_level)
  2873. {
  2874. int rc;
  2875. unsigned char *buf;
  2876. *raid_level = RAID_UNKNOWN;
  2877. buf = kzalloc(64, GFP_KERNEL);
  2878. if (!buf)
  2879. return;
  2880. if (!hpsa_vpd_page_supported(h, scsi3addr,
  2881. HPSA_VPD_LV_DEVICE_GEOMETRY))
  2882. goto exit;
  2883. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
  2884. HPSA_VPD_LV_DEVICE_GEOMETRY, buf, 64);
  2885. if (rc == 0)
  2886. *raid_level = buf[8];
  2887. if (*raid_level > RAID_UNKNOWN)
  2888. *raid_level = RAID_UNKNOWN;
  2889. exit:
  2890. kfree(buf);
  2891. return;
  2892. }
  2893. #define HPSA_MAP_DEBUG
  2894. #ifdef HPSA_MAP_DEBUG
  2895. static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
  2896. struct raid_map_data *map_buff)
  2897. {
  2898. struct raid_map_disk_data *dd = &map_buff->data[0];
  2899. int map, row, col;
  2900. u16 map_cnt, row_cnt, disks_per_row;
  2901. if (rc != 0)
  2902. return;
  2903. /* Show details only if debugging has been activated. */
  2904. if (h->raid_offload_debug < 2)
  2905. return;
  2906. dev_info(&h->pdev->dev, "structure_size = %u\n",
  2907. le32_to_cpu(map_buff->structure_size));
  2908. dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
  2909. le32_to_cpu(map_buff->volume_blk_size));
  2910. dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
  2911. le64_to_cpu(map_buff->volume_blk_cnt));
  2912. dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
  2913. map_buff->phys_blk_shift);
  2914. dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
  2915. map_buff->parity_rotation_shift);
  2916. dev_info(&h->pdev->dev, "strip_size = %u\n",
  2917. le16_to_cpu(map_buff->strip_size));
  2918. dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
  2919. le64_to_cpu(map_buff->disk_starting_blk));
  2920. dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
  2921. le64_to_cpu(map_buff->disk_blk_cnt));
  2922. dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
  2923. le16_to_cpu(map_buff->data_disks_per_row));
  2924. dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
  2925. le16_to_cpu(map_buff->metadata_disks_per_row));
  2926. dev_info(&h->pdev->dev, "row_cnt = %u\n",
  2927. le16_to_cpu(map_buff->row_cnt));
  2928. dev_info(&h->pdev->dev, "layout_map_count = %u\n",
  2929. le16_to_cpu(map_buff->layout_map_count));
  2930. dev_info(&h->pdev->dev, "flags = 0x%x\n",
  2931. le16_to_cpu(map_buff->flags));
  2932. dev_info(&h->pdev->dev, "encryption = %s\n",
  2933. le16_to_cpu(map_buff->flags) &
  2934. RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
  2935. dev_info(&h->pdev->dev, "dekindex = %u\n",
  2936. le16_to_cpu(map_buff->dekindex));
  2937. map_cnt = le16_to_cpu(map_buff->layout_map_count);
  2938. for (map = 0; map < map_cnt; map++) {
  2939. dev_info(&h->pdev->dev, "Map%u:\n", map);
  2940. row_cnt = le16_to_cpu(map_buff->row_cnt);
  2941. for (row = 0; row < row_cnt; row++) {
  2942. dev_info(&h->pdev->dev, " Row%u:\n", row);
  2943. disks_per_row =
  2944. le16_to_cpu(map_buff->data_disks_per_row);
  2945. for (col = 0; col < disks_per_row; col++, dd++)
  2946. dev_info(&h->pdev->dev,
  2947. " D%02u: h=0x%04x xor=%u,%u\n",
  2948. col, dd->ioaccel_handle,
  2949. dd->xor_mult[0], dd->xor_mult[1]);
  2950. disks_per_row =
  2951. le16_to_cpu(map_buff->metadata_disks_per_row);
  2952. for (col = 0; col < disks_per_row; col++, dd++)
  2953. dev_info(&h->pdev->dev,
  2954. " M%02u: h=0x%04x xor=%u,%u\n",
  2955. col, dd->ioaccel_handle,
  2956. dd->xor_mult[0], dd->xor_mult[1]);
  2957. }
  2958. }
  2959. }
  2960. #else
  2961. static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
  2962. __attribute__((unused)) int rc,
  2963. __attribute__((unused)) struct raid_map_data *map_buff)
  2964. {
  2965. }
  2966. #endif
  2967. static int hpsa_get_raid_map(struct ctlr_info *h,
  2968. unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
  2969. {
  2970. int rc = 0;
  2971. struct CommandList *c;
  2972. struct ErrorInfo *ei;
  2973. c = cmd_alloc(h);
  2974. if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
  2975. sizeof(this_device->raid_map), 0,
  2976. scsi3addr, TYPE_CMD)) {
  2977. dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
  2978. cmd_free(h, c);
  2979. return -1;
  2980. }
  2981. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  2982. NO_TIMEOUT);
  2983. if (rc)
  2984. goto out;
  2985. ei = c->err_info;
  2986. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2987. hpsa_scsi_interpret_error(h, c);
  2988. rc = -1;
  2989. goto out;
  2990. }
  2991. cmd_free(h, c);
  2992. /* @todo in the future, dynamically allocate RAID map memory */
  2993. if (le32_to_cpu(this_device->raid_map.structure_size) >
  2994. sizeof(this_device->raid_map)) {
  2995. dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
  2996. rc = -1;
  2997. }
  2998. hpsa_debug_map_buff(h, rc, &this_device->raid_map);
  2999. return rc;
  3000. out:
  3001. cmd_free(h, c);
  3002. return rc;
  3003. }
  3004. static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
  3005. unsigned char scsi3addr[], u16 bmic_device_index,
  3006. struct bmic_sense_subsystem_info *buf, size_t bufsize)
  3007. {
  3008. int rc = IO_OK;
  3009. struct CommandList *c;
  3010. struct ErrorInfo *ei;
  3011. c = cmd_alloc(h);
  3012. rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
  3013. 0, RAID_CTLR_LUNID, TYPE_CMD);
  3014. if (rc)
  3015. goto out;
  3016. c->Request.CDB[2] = bmic_device_index & 0xff;
  3017. c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
  3018. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3019. NO_TIMEOUT);
  3020. if (rc)
  3021. goto out;
  3022. ei = c->err_info;
  3023. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3024. hpsa_scsi_interpret_error(h, c);
  3025. rc = -1;
  3026. }
  3027. out:
  3028. cmd_free(h, c);
  3029. return rc;
  3030. }
  3031. static int hpsa_bmic_id_controller(struct ctlr_info *h,
  3032. struct bmic_identify_controller *buf, size_t bufsize)
  3033. {
  3034. int rc = IO_OK;
  3035. struct CommandList *c;
  3036. struct ErrorInfo *ei;
  3037. c = cmd_alloc(h);
  3038. rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
  3039. 0, RAID_CTLR_LUNID, TYPE_CMD);
  3040. if (rc)
  3041. goto out;
  3042. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3043. NO_TIMEOUT);
  3044. if (rc)
  3045. goto out;
  3046. ei = c->err_info;
  3047. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3048. hpsa_scsi_interpret_error(h, c);
  3049. rc = -1;
  3050. }
  3051. out:
  3052. cmd_free(h, c);
  3053. return rc;
  3054. }
  3055. static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
  3056. unsigned char scsi3addr[], u16 bmic_device_index,
  3057. struct bmic_identify_physical_device *buf, size_t bufsize)
  3058. {
  3059. int rc = IO_OK;
  3060. struct CommandList *c;
  3061. struct ErrorInfo *ei;
  3062. c = cmd_alloc(h);
  3063. rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
  3064. 0, RAID_CTLR_LUNID, TYPE_CMD);
  3065. if (rc)
  3066. goto out;
  3067. c->Request.CDB[2] = bmic_device_index & 0xff;
  3068. c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
  3069. hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3070. NO_TIMEOUT);
  3071. ei = c->err_info;
  3072. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3073. hpsa_scsi_interpret_error(h, c);
  3074. rc = -1;
  3075. }
  3076. out:
  3077. cmd_free(h, c);
  3078. return rc;
  3079. }
  3080. /*
  3081. * get enclosure information
  3082. * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number
  3083. * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure
  3084. * Uses id_physical_device to determine the box_index.
  3085. */
  3086. static void hpsa_get_enclosure_info(struct ctlr_info *h,
  3087. unsigned char *scsi3addr,
  3088. struct ReportExtendedLUNdata *rlep, int rle_index,
  3089. struct hpsa_scsi_dev_t *encl_dev)
  3090. {
  3091. int rc = -1;
  3092. struct CommandList *c = NULL;
  3093. struct ErrorInfo *ei = NULL;
  3094. struct bmic_sense_storage_box_params *bssbp = NULL;
  3095. struct bmic_identify_physical_device *id_phys = NULL;
  3096. struct ext_report_lun_entry *rle;
  3097. u16 bmic_device_index = 0;
  3098. if (rle_index < 0 || rle_index >= HPSA_MAX_PHYS_LUN)
  3099. return;
  3100. rle = &rlep->LUN[rle_index];
  3101. encl_dev->eli =
  3102. hpsa_get_enclosure_logical_identifier(h, scsi3addr);
  3103. bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]);
  3104. if (encl_dev->target == -1 || encl_dev->lun == -1) {
  3105. rc = IO_OK;
  3106. goto out;
  3107. }
  3108. if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) {
  3109. rc = IO_OK;
  3110. goto out;
  3111. }
  3112. bssbp = kzalloc_obj(*bssbp);
  3113. if (!bssbp)
  3114. goto out;
  3115. id_phys = kzalloc_obj(*id_phys);
  3116. if (!id_phys)
  3117. goto out;
  3118. rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index,
  3119. id_phys, sizeof(*id_phys));
  3120. if (rc) {
  3121. dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n",
  3122. __func__, encl_dev->external, bmic_device_index);
  3123. goto out;
  3124. }
  3125. c = cmd_alloc(h);
  3126. rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp,
  3127. sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD);
  3128. if (rc)
  3129. goto out;
  3130. if (id_phys->phys_connector[1] == 'E')
  3131. c->Request.CDB[5] = id_phys->box_index;
  3132. else
  3133. c->Request.CDB[5] = 0;
  3134. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3135. NO_TIMEOUT);
  3136. if (rc)
  3137. goto out;
  3138. ei = c->err_info;
  3139. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3140. rc = -1;
  3141. goto out;
  3142. }
  3143. encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port;
  3144. memcpy(&encl_dev->phys_connector[id_phys->active_path_number],
  3145. bssbp->phys_connector, sizeof(bssbp->phys_connector));
  3146. rc = IO_OK;
  3147. out:
  3148. kfree(bssbp);
  3149. kfree(id_phys);
  3150. if (c)
  3151. cmd_free(h, c);
  3152. if (rc != IO_OK)
  3153. hpsa_show_dev_msg(KERN_INFO, h, encl_dev,
  3154. "Error, could not get enclosure information");
  3155. }
  3156. static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
  3157. unsigned char *scsi3addr)
  3158. {
  3159. struct ReportExtendedLUNdata *physdev;
  3160. u32 nphysicals;
  3161. u64 sa = 0;
  3162. int i;
  3163. physdev = kzalloc_obj(*physdev);
  3164. if (!physdev)
  3165. return 0;
  3166. if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
  3167. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  3168. kfree(physdev);
  3169. return 0;
  3170. }
  3171. nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
  3172. for (i = 0; i < nphysicals; i++)
  3173. if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
  3174. sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
  3175. break;
  3176. }
  3177. kfree(physdev);
  3178. return sa;
  3179. }
  3180. static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
  3181. struct hpsa_scsi_dev_t *dev)
  3182. {
  3183. int rc;
  3184. u64 sa = 0;
  3185. if (is_hba_lunid(scsi3addr)) {
  3186. struct bmic_sense_subsystem_info *ssi;
  3187. ssi = kzalloc_obj(*ssi);
  3188. if (!ssi)
  3189. return;
  3190. rc = hpsa_bmic_sense_subsystem_information(h,
  3191. scsi3addr, 0, ssi, sizeof(*ssi));
  3192. if (rc == 0) {
  3193. sa = get_unaligned_be64(ssi->primary_world_wide_id);
  3194. h->sas_address = sa;
  3195. }
  3196. kfree(ssi);
  3197. } else
  3198. sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
  3199. dev->sas_address = sa;
  3200. }
  3201. static void hpsa_ext_ctrl_present(struct ctlr_info *h,
  3202. struct ReportExtendedLUNdata *physdev)
  3203. {
  3204. u32 nphysicals;
  3205. int i;
  3206. if (h->discovery_polling)
  3207. return;
  3208. nphysicals = (get_unaligned_be32(physdev->LUNListLength) / 24) + 1;
  3209. for (i = 0; i < nphysicals; i++) {
  3210. if (physdev->LUN[i].device_type ==
  3211. BMIC_DEVICE_TYPE_CONTROLLER
  3212. && !is_hba_lunid(physdev->LUN[i].lunid)) {
  3213. dev_info(&h->pdev->dev,
  3214. "External controller present, activate discovery polling and disable rld caching\n");
  3215. hpsa_disable_rld_caching(h);
  3216. h->discovery_polling = 1;
  3217. break;
  3218. }
  3219. }
  3220. }
  3221. /* Get a device id from inquiry page 0x83 */
  3222. static bool hpsa_vpd_page_supported(struct ctlr_info *h,
  3223. unsigned char scsi3addr[], u8 page)
  3224. {
  3225. int rc;
  3226. int i;
  3227. int pages;
  3228. unsigned char *buf, bufsize;
  3229. buf = kzalloc(256, GFP_KERNEL);
  3230. if (!buf)
  3231. return false;
  3232. /* Get the size of the page list first */
  3233. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  3234. VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
  3235. buf, HPSA_VPD_HEADER_SZ);
  3236. if (rc != 0)
  3237. goto exit_unsupported;
  3238. pages = buf[3];
  3239. bufsize = min(pages + HPSA_VPD_HEADER_SZ, 255);
  3240. /* Get the whole VPD page list */
  3241. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  3242. VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
  3243. buf, bufsize);
  3244. if (rc != 0)
  3245. goto exit_unsupported;
  3246. pages = buf[3];
  3247. for (i = 1; i <= pages; i++)
  3248. if (buf[3 + i] == page)
  3249. goto exit_supported;
  3250. exit_unsupported:
  3251. kfree(buf);
  3252. return false;
  3253. exit_supported:
  3254. kfree(buf);
  3255. return true;
  3256. }
  3257. /*
  3258. * Called during a scan operation.
  3259. * Sets ioaccel status on the new device list, not the existing device list
  3260. *
  3261. * The device list used during I/O will be updated later in
  3262. * adjust_hpsa_scsi_table.
  3263. */
  3264. static void hpsa_get_ioaccel_status(struct ctlr_info *h,
  3265. unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
  3266. {
  3267. int rc;
  3268. unsigned char *buf;
  3269. u8 ioaccel_status;
  3270. this_device->offload_config = 0;
  3271. this_device->offload_enabled = 0;
  3272. this_device->offload_to_be_enabled = 0;
  3273. buf = kzalloc(64, GFP_KERNEL);
  3274. if (!buf)
  3275. return;
  3276. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
  3277. goto out;
  3278. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  3279. VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
  3280. if (rc != 0)
  3281. goto out;
  3282. #define IOACCEL_STATUS_BYTE 4
  3283. #define OFFLOAD_CONFIGURED_BIT 0x01
  3284. #define OFFLOAD_ENABLED_BIT 0x02
  3285. ioaccel_status = buf[IOACCEL_STATUS_BYTE];
  3286. this_device->offload_config =
  3287. !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
  3288. if (this_device->offload_config) {
  3289. bool offload_enabled =
  3290. !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
  3291. /*
  3292. * Check to see if offload can be enabled.
  3293. */
  3294. if (offload_enabled) {
  3295. rc = hpsa_get_raid_map(h, scsi3addr, this_device);
  3296. if (rc) /* could not load raid_map */
  3297. goto out;
  3298. this_device->offload_to_be_enabled = 1;
  3299. }
  3300. }
  3301. out:
  3302. kfree(buf);
  3303. return;
  3304. }
  3305. /* Get the device id from inquiry page 0x83 */
  3306. static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
  3307. unsigned char *device_id, int index, int buflen)
  3308. {
  3309. int rc;
  3310. unsigned char *buf;
  3311. /* Does controller have VPD for device id? */
  3312. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_DEVICE_ID))
  3313. return 1; /* not supported */
  3314. buf = kzalloc(64, GFP_KERNEL);
  3315. if (!buf)
  3316. return -ENOMEM;
  3317. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
  3318. HPSA_VPD_LV_DEVICE_ID, buf, 64);
  3319. if (rc == 0) {
  3320. if (buflen > 16)
  3321. buflen = 16;
  3322. memcpy(device_id, &buf[8], buflen);
  3323. }
  3324. kfree(buf);
  3325. return rc; /*0 - got id, otherwise, didn't */
  3326. }
  3327. static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
  3328. void *buf, int bufsize,
  3329. int extended_response)
  3330. {
  3331. int rc = IO_OK;
  3332. struct CommandList *c;
  3333. unsigned char scsi3addr[8];
  3334. struct ErrorInfo *ei;
  3335. c = cmd_alloc(h);
  3336. /* address the controller */
  3337. memset(scsi3addr, 0, sizeof(scsi3addr));
  3338. if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
  3339. buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
  3340. rc = -EAGAIN;
  3341. goto out;
  3342. }
  3343. if (extended_response)
  3344. c->Request.CDB[1] = extended_response;
  3345. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3346. NO_TIMEOUT);
  3347. if (rc)
  3348. goto out;
  3349. ei = c->err_info;
  3350. if (ei->CommandStatus != 0 &&
  3351. ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3352. hpsa_scsi_interpret_error(h, c);
  3353. rc = -EIO;
  3354. } else {
  3355. struct ReportLUNdata *rld = buf;
  3356. if (rld->extended_response_flag != extended_response) {
  3357. if (!h->legacy_board) {
  3358. dev_err(&h->pdev->dev,
  3359. "report luns requested format %u, got %u\n",
  3360. extended_response,
  3361. rld->extended_response_flag);
  3362. rc = -EINVAL;
  3363. } else
  3364. rc = -EOPNOTSUPP;
  3365. }
  3366. }
  3367. out:
  3368. cmd_free(h, c);
  3369. return rc;
  3370. }
  3371. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  3372. struct ReportExtendedLUNdata *buf, int bufsize)
  3373. {
  3374. int rc;
  3375. struct ReportLUNdata *lbuf;
  3376. rc = hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
  3377. HPSA_REPORT_PHYS_EXTENDED);
  3378. if (!rc || rc != -EOPNOTSUPP)
  3379. return rc;
  3380. /* REPORT PHYS EXTENDED is not supported */
  3381. lbuf = kzalloc_obj(*lbuf);
  3382. if (!lbuf)
  3383. return -ENOMEM;
  3384. rc = hpsa_scsi_do_report_luns(h, 0, lbuf, sizeof(*lbuf), 0);
  3385. if (!rc) {
  3386. int i;
  3387. u32 nphys;
  3388. /* Copy ReportLUNdata header */
  3389. memcpy(buf, lbuf, 8);
  3390. nphys = be32_to_cpu(*((__be32 *)lbuf->LUNListLength)) / 8;
  3391. for (i = 0; i < nphys; i++)
  3392. memcpy(buf->LUN[i].lunid, lbuf->LUN[i], 8);
  3393. }
  3394. kfree(lbuf);
  3395. return rc;
  3396. }
  3397. static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
  3398. struct ReportLUNdata *buf, int bufsize)
  3399. {
  3400. return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
  3401. }
  3402. static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
  3403. int bus, int target, int lun)
  3404. {
  3405. device->bus = bus;
  3406. device->target = target;
  3407. device->lun = lun;
  3408. }
  3409. /* Use VPD inquiry to get details of volume status */
  3410. static int hpsa_get_volume_status(struct ctlr_info *h,
  3411. unsigned char scsi3addr[])
  3412. {
  3413. int rc;
  3414. int status;
  3415. int size;
  3416. unsigned char *buf;
  3417. buf = kzalloc(64, GFP_KERNEL);
  3418. if (!buf)
  3419. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3420. /* Does controller have VPD for logical volume status? */
  3421. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
  3422. goto exit_failed;
  3423. /* Get the size of the VPD return buffer */
  3424. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
  3425. buf, HPSA_VPD_HEADER_SZ);
  3426. if (rc != 0)
  3427. goto exit_failed;
  3428. size = buf[3];
  3429. /* Now get the whole VPD buffer */
  3430. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
  3431. buf, size + HPSA_VPD_HEADER_SZ);
  3432. if (rc != 0)
  3433. goto exit_failed;
  3434. status = buf[4]; /* status byte */
  3435. kfree(buf);
  3436. return status;
  3437. exit_failed:
  3438. kfree(buf);
  3439. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3440. }
  3441. /* Determine offline status of a volume.
  3442. * Return either:
  3443. * 0 (not offline)
  3444. * 0xff (offline for unknown reasons)
  3445. * # (integer code indicating one of several NOT READY states
  3446. * describing why a volume is to be kept offline)
  3447. */
  3448. static unsigned char hpsa_volume_offline(struct ctlr_info *h,
  3449. unsigned char scsi3addr[])
  3450. {
  3451. struct CommandList *c;
  3452. unsigned char *sense;
  3453. u8 sense_key, asc, ascq;
  3454. int sense_len;
  3455. int rc, ldstat = 0;
  3456. #define ASC_LUN_NOT_READY 0x04
  3457. #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
  3458. #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
  3459. c = cmd_alloc(h);
  3460. (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
  3461. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  3462. NO_TIMEOUT);
  3463. if (rc) {
  3464. cmd_free(h, c);
  3465. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3466. }
  3467. sense = c->err_info->SenseInfo;
  3468. if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
  3469. sense_len = sizeof(c->err_info->SenseInfo);
  3470. else
  3471. sense_len = c->err_info->SenseLen;
  3472. decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
  3473. cmd_free(h, c);
  3474. /* Determine the reason for not ready state */
  3475. ldstat = hpsa_get_volume_status(h, scsi3addr);
  3476. /* Keep volume offline in certain cases: */
  3477. switch (ldstat) {
  3478. case HPSA_LV_FAILED:
  3479. case HPSA_LV_UNDERGOING_ERASE:
  3480. case HPSA_LV_NOT_AVAILABLE:
  3481. case HPSA_LV_UNDERGOING_RPI:
  3482. case HPSA_LV_PENDING_RPI:
  3483. case HPSA_LV_ENCRYPTED_NO_KEY:
  3484. case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
  3485. case HPSA_LV_UNDERGOING_ENCRYPTION:
  3486. case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
  3487. case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  3488. return ldstat;
  3489. case HPSA_VPD_LV_STATUS_UNSUPPORTED:
  3490. /* If VPD status page isn't available,
  3491. * use ASC/ASCQ to determine state
  3492. */
  3493. if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
  3494. (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
  3495. return ldstat;
  3496. break;
  3497. default:
  3498. break;
  3499. }
  3500. return HPSA_LV_OK;
  3501. }
  3502. static int hpsa_update_device_info(struct ctlr_info *h,
  3503. unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
  3504. unsigned char *is_OBDR_device)
  3505. {
  3506. #define OBDR_SIG_OFFSET 43
  3507. #define OBDR_TAPE_SIG "$DR-10"
  3508. #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
  3509. #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
  3510. unsigned char *inq_buff;
  3511. unsigned char *obdr_sig;
  3512. int rc = 0;
  3513. inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
  3514. if (!inq_buff) {
  3515. rc = -ENOMEM;
  3516. goto bail_out;
  3517. }
  3518. /* Do an inquiry to the device to see what it is. */
  3519. if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
  3520. (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
  3521. dev_err(&h->pdev->dev,
  3522. "%s: inquiry failed, device will be skipped.\n",
  3523. __func__);
  3524. rc = HPSA_INQUIRY_FAILED;
  3525. goto bail_out;
  3526. }
  3527. scsi_sanitize_inquiry_string(&inq_buff[8], 8);
  3528. scsi_sanitize_inquiry_string(&inq_buff[16], 16);
  3529. this_device->devtype = (inq_buff[0] & 0x1f);
  3530. memcpy(this_device->scsi3addr, scsi3addr, 8);
  3531. memcpy(this_device->vendor, &inq_buff[8],
  3532. sizeof(this_device->vendor));
  3533. memcpy(this_device->model, &inq_buff[16],
  3534. sizeof(this_device->model));
  3535. this_device->rev = inq_buff[2];
  3536. memset(this_device->device_id, 0,
  3537. sizeof(this_device->device_id));
  3538. if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
  3539. sizeof(this_device->device_id)) < 0) {
  3540. dev_err(&h->pdev->dev,
  3541. "hpsa%d: %s: can't get device id for [%d:%d:%d:%d]\t%s\t%.16s\n",
  3542. h->ctlr, __func__,
  3543. h->scsi_host->host_no,
  3544. this_device->bus, this_device->target,
  3545. this_device->lun,
  3546. scsi_device_type(this_device->devtype),
  3547. this_device->model);
  3548. rc = HPSA_LV_FAILED;
  3549. goto bail_out;
  3550. }
  3551. if ((this_device->devtype == TYPE_DISK ||
  3552. this_device->devtype == TYPE_ZBC) &&
  3553. is_logical_dev_addr_mode(scsi3addr)) {
  3554. unsigned char volume_offline;
  3555. hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
  3556. if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
  3557. hpsa_get_ioaccel_status(h, scsi3addr, this_device);
  3558. volume_offline = hpsa_volume_offline(h, scsi3addr);
  3559. if (volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED &&
  3560. h->legacy_board) {
  3561. /*
  3562. * Legacy boards might not support volume status
  3563. */
  3564. dev_info(&h->pdev->dev,
  3565. "C0:T%d:L%d Volume status not available, assuming online.\n",
  3566. this_device->target, this_device->lun);
  3567. volume_offline = 0;
  3568. }
  3569. this_device->volume_offline = volume_offline;
  3570. if (volume_offline == HPSA_LV_FAILED) {
  3571. rc = HPSA_LV_FAILED;
  3572. dev_err(&h->pdev->dev,
  3573. "%s: LV failed, device will be skipped.\n",
  3574. __func__);
  3575. goto bail_out;
  3576. }
  3577. } else {
  3578. this_device->raid_level = RAID_UNKNOWN;
  3579. this_device->offload_config = 0;
  3580. hpsa_turn_off_ioaccel_for_device(this_device);
  3581. this_device->hba_ioaccel_enabled = 0;
  3582. this_device->volume_offline = 0;
  3583. this_device->queue_depth = h->nr_cmds;
  3584. }
  3585. if (this_device->external)
  3586. this_device->queue_depth = EXTERNAL_QD;
  3587. if (is_OBDR_device) {
  3588. /* See if this is a One-Button-Disaster-Recovery device
  3589. * by looking for "$DR-10" at offset 43 in inquiry data.
  3590. */
  3591. obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
  3592. *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
  3593. strncmp(obdr_sig, OBDR_TAPE_SIG,
  3594. OBDR_SIG_LEN) == 0);
  3595. }
  3596. kfree(inq_buff);
  3597. return 0;
  3598. bail_out:
  3599. kfree(inq_buff);
  3600. return rc;
  3601. }
  3602. /*
  3603. * Helper function to assign bus, target, lun mapping of devices.
  3604. * Logical drive target and lun are assigned at this time, but
  3605. * physical device lun and target assignment are deferred (assigned
  3606. * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
  3607. */
  3608. static void figure_bus_target_lun(struct ctlr_info *h,
  3609. u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
  3610. {
  3611. u32 lunid = get_unaligned_le32(lunaddrbytes);
  3612. if (!is_logical_dev_addr_mode(lunaddrbytes)) {
  3613. /* physical device, target and lun filled in later */
  3614. if (is_hba_lunid(lunaddrbytes)) {
  3615. int bus = HPSA_HBA_BUS;
  3616. if (!device->rev)
  3617. bus = HPSA_LEGACY_HBA_BUS;
  3618. hpsa_set_bus_target_lun(device,
  3619. bus, 0, lunid & 0x3fff);
  3620. } else
  3621. /* defer target, lun assignment for physical devices */
  3622. hpsa_set_bus_target_lun(device,
  3623. HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
  3624. return;
  3625. }
  3626. /* It's a logical device */
  3627. if (device->external) {
  3628. hpsa_set_bus_target_lun(device,
  3629. HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
  3630. lunid & 0x00ff);
  3631. return;
  3632. }
  3633. hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
  3634. 0, lunid & 0x3fff);
  3635. }
  3636. static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
  3637. int i, int nphysicals, int nlocal_logicals)
  3638. {
  3639. /* In report logicals, local logicals are listed first,
  3640. * then any externals.
  3641. */
  3642. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  3643. if (i == raid_ctlr_position)
  3644. return 0;
  3645. if (i < logicals_start)
  3646. return 0;
  3647. /* i is in logicals range, but still within local logicals */
  3648. if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
  3649. return 0;
  3650. return 1; /* it's an external lun */
  3651. }
  3652. /*
  3653. * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
  3654. * logdev. The number of luns in physdev and logdev are returned in
  3655. * *nphysicals and *nlogicals, respectively.
  3656. * Returns 0 on success, -1 otherwise.
  3657. */
  3658. static int hpsa_gather_lun_info(struct ctlr_info *h,
  3659. struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
  3660. struct ReportLUNdata *logdev, u32 *nlogicals)
  3661. {
  3662. if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
  3663. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  3664. return -1;
  3665. }
  3666. *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
  3667. if (*nphysicals > HPSA_MAX_PHYS_LUN) {
  3668. dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
  3669. HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
  3670. *nphysicals = HPSA_MAX_PHYS_LUN;
  3671. }
  3672. if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
  3673. dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
  3674. return -1;
  3675. }
  3676. *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
  3677. /* Reject Logicals in excess of our max capability. */
  3678. if (*nlogicals > HPSA_MAX_LUN) {
  3679. dev_warn(&h->pdev->dev,
  3680. "maximum logical LUNs (%d) exceeded. "
  3681. "%d LUNs ignored.\n", HPSA_MAX_LUN,
  3682. *nlogicals - HPSA_MAX_LUN);
  3683. *nlogicals = HPSA_MAX_LUN;
  3684. }
  3685. if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
  3686. dev_warn(&h->pdev->dev,
  3687. "maximum logical + physical LUNs (%d) exceeded. "
  3688. "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  3689. *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
  3690. *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
  3691. }
  3692. return 0;
  3693. }
  3694. static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
  3695. int i, int nphysicals, int nlogicals,
  3696. struct ReportExtendedLUNdata *physdev_list,
  3697. struct ReportLUNdata *logdev_list)
  3698. {
  3699. /* Helper function, figure out where the LUN ID info is coming from
  3700. * given index i, lists of physical and logical devices, where in
  3701. * the list the raid controller is supposed to appear (first or last)
  3702. */
  3703. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  3704. int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
  3705. if (i == raid_ctlr_position)
  3706. return RAID_CTLR_LUNID;
  3707. if (i < logicals_start)
  3708. return &physdev_list->LUN[i -
  3709. (raid_ctlr_position == 0)].lunid[0];
  3710. if (i < last_device)
  3711. return &logdev_list->LUN[i - nphysicals -
  3712. (raid_ctlr_position == 0)][0];
  3713. BUG();
  3714. return NULL;
  3715. }
  3716. /* get physical drive ioaccel handle and queue depth */
  3717. static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
  3718. struct hpsa_scsi_dev_t *dev,
  3719. struct ReportExtendedLUNdata *rlep, int rle_index,
  3720. struct bmic_identify_physical_device *id_phys)
  3721. {
  3722. int rc;
  3723. struct ext_report_lun_entry *rle;
  3724. if (rle_index < 0 || rle_index >= HPSA_MAX_PHYS_LUN)
  3725. return;
  3726. rle = &rlep->LUN[rle_index];
  3727. dev->ioaccel_handle = rle->ioaccel_handle;
  3728. if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
  3729. dev->hba_ioaccel_enabled = 1;
  3730. memset(id_phys, 0, sizeof(*id_phys));
  3731. rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
  3732. GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
  3733. sizeof(*id_phys));
  3734. if (!rc)
  3735. /* Reserve space for FW operations */
  3736. #define DRIVE_CMDS_RESERVED_FOR_FW 2
  3737. #define DRIVE_QUEUE_DEPTH 7
  3738. dev->queue_depth =
  3739. le16_to_cpu(id_phys->current_queue_depth_limit) -
  3740. DRIVE_CMDS_RESERVED_FOR_FW;
  3741. else
  3742. dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
  3743. }
  3744. static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
  3745. struct ReportExtendedLUNdata *rlep, int rle_index,
  3746. struct bmic_identify_physical_device *id_phys)
  3747. {
  3748. struct ext_report_lun_entry *rle;
  3749. if (rle_index < 0 || rle_index >= HPSA_MAX_PHYS_LUN)
  3750. return;
  3751. rle = &rlep->LUN[rle_index];
  3752. if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
  3753. this_device->hba_ioaccel_enabled = 1;
  3754. memcpy(&this_device->active_path_index,
  3755. &id_phys->active_path_number,
  3756. sizeof(this_device->active_path_index));
  3757. memcpy(&this_device->path_map,
  3758. &id_phys->redundant_path_present_map,
  3759. sizeof(this_device->path_map));
  3760. memcpy(&this_device->box,
  3761. &id_phys->alternate_paths_phys_box_on_port,
  3762. sizeof(this_device->box));
  3763. memcpy(&this_device->phys_connector,
  3764. &id_phys->alternate_paths_phys_connector,
  3765. sizeof(this_device->phys_connector));
  3766. memcpy(&this_device->bay,
  3767. &id_phys->phys_bay_in_box,
  3768. sizeof(this_device->bay));
  3769. }
  3770. /* get number of local logical disks. */
  3771. static int hpsa_set_local_logical_count(struct ctlr_info *h,
  3772. struct bmic_identify_controller *id_ctlr,
  3773. u32 *nlocals)
  3774. {
  3775. int rc;
  3776. if (!id_ctlr) {
  3777. dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
  3778. __func__);
  3779. return -ENOMEM;
  3780. }
  3781. memset(id_ctlr, 0, sizeof(*id_ctlr));
  3782. rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
  3783. if (!rc)
  3784. if (id_ctlr->configured_logical_drive_count < 255)
  3785. *nlocals = id_ctlr->configured_logical_drive_count;
  3786. else
  3787. *nlocals = le16_to_cpu(
  3788. id_ctlr->extended_logical_unit_count);
  3789. else
  3790. *nlocals = -1;
  3791. return rc;
  3792. }
  3793. static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes)
  3794. {
  3795. struct bmic_identify_physical_device *id_phys;
  3796. bool is_spare = false;
  3797. int rc;
  3798. id_phys = kzalloc_obj(*id_phys);
  3799. if (!id_phys)
  3800. return false;
  3801. rc = hpsa_bmic_id_physical_device(h,
  3802. lunaddrbytes,
  3803. GET_BMIC_DRIVE_NUMBER(lunaddrbytes),
  3804. id_phys, sizeof(*id_phys));
  3805. if (rc == 0)
  3806. is_spare = (id_phys->more_flags >> 6) & 0x01;
  3807. kfree(id_phys);
  3808. return is_spare;
  3809. }
  3810. #define RPL_DEV_FLAG_NON_DISK 0x1
  3811. #define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2
  3812. #define RPL_DEV_FLAG_UNCONFIG_DISK 0x4
  3813. #define BMIC_DEVICE_TYPE_ENCLOSURE 6
  3814. static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes,
  3815. struct ext_report_lun_entry *rle)
  3816. {
  3817. u8 device_flags;
  3818. u8 device_type;
  3819. if (!MASKED_DEVICE(lunaddrbytes))
  3820. return false;
  3821. device_flags = rle->device_flags;
  3822. device_type = rle->device_type;
  3823. if (device_flags & RPL_DEV_FLAG_NON_DISK) {
  3824. if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE)
  3825. return false;
  3826. return true;
  3827. }
  3828. if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED))
  3829. return false;
  3830. if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK)
  3831. return false;
  3832. /*
  3833. * Spares may be spun down, we do not want to
  3834. * do an Inquiry to a RAID set spare drive as
  3835. * that would have them spun up, that is a
  3836. * performance hit because I/O to the RAID device
  3837. * stops while the spin up occurs which can take
  3838. * over 50 seconds.
  3839. */
  3840. if (hpsa_is_disk_spare(h, lunaddrbytes))
  3841. return true;
  3842. return false;
  3843. }
  3844. static void hpsa_update_scsi_devices(struct ctlr_info *h)
  3845. {
  3846. /* the idea here is we could get notified
  3847. * that some devices have changed, so we do a report
  3848. * physical luns and report logical luns cmd, and adjust
  3849. * our list of devices accordingly.
  3850. *
  3851. * The scsi3addr's of devices won't change so long as the
  3852. * adapter is not reset. That means we can rescan and
  3853. * tell which devices we already know about, vs. new
  3854. * devices, vs. disappearing devices.
  3855. */
  3856. struct ReportExtendedLUNdata *physdev_list = NULL;
  3857. struct ReportLUNdata *logdev_list = NULL;
  3858. struct bmic_identify_physical_device *id_phys = NULL;
  3859. struct bmic_identify_controller *id_ctlr = NULL;
  3860. u32 nphysicals = 0;
  3861. u32 nlogicals = 0;
  3862. u32 nlocal_logicals = 0;
  3863. u32 ndev_allocated = 0;
  3864. struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
  3865. int ncurrent = 0;
  3866. int i, ndevs_to_allocate;
  3867. int raid_ctlr_position;
  3868. bool physical_device;
  3869. currentsd = kzalloc_objs(*currentsd, HPSA_MAX_DEVICES);
  3870. physdev_list = kzalloc_obj(*physdev_list);
  3871. logdev_list = kzalloc_obj(*logdev_list);
  3872. tmpdevice = kzalloc_obj(*tmpdevice);
  3873. id_phys = kzalloc_obj(*id_phys);
  3874. id_ctlr = kzalloc_obj(*id_ctlr);
  3875. if (!currentsd || !physdev_list || !logdev_list ||
  3876. !tmpdevice || !id_phys || !id_ctlr) {
  3877. dev_err(&h->pdev->dev, "out of memory\n");
  3878. goto out;
  3879. }
  3880. h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
  3881. if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
  3882. logdev_list, &nlogicals)) {
  3883. h->drv_req_rescan = 1;
  3884. goto out;
  3885. }
  3886. /* Set number of local logicals (non PTRAID) */
  3887. if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
  3888. dev_warn(&h->pdev->dev,
  3889. "%s: Can't determine number of local logical devices.\n",
  3890. __func__);
  3891. }
  3892. /* We might see up to the maximum number of logical and physical disks
  3893. * plus external target devices, and a device for the local RAID
  3894. * controller.
  3895. */
  3896. ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
  3897. hpsa_ext_ctrl_present(h, physdev_list);
  3898. /* Allocate the per device structures */
  3899. for (i = 0; i < ndevs_to_allocate; i++) {
  3900. if (i >= HPSA_MAX_DEVICES) {
  3901. dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
  3902. " %d devices ignored.\n", HPSA_MAX_DEVICES,
  3903. ndevs_to_allocate - HPSA_MAX_DEVICES);
  3904. break;
  3905. }
  3906. currentsd[i] = kzalloc_obj(*currentsd[i]);
  3907. if (!currentsd[i]) {
  3908. h->drv_req_rescan = 1;
  3909. goto out;
  3910. }
  3911. ndev_allocated++;
  3912. }
  3913. if (is_scsi_rev_5(h))
  3914. raid_ctlr_position = 0;
  3915. else
  3916. raid_ctlr_position = nphysicals + nlogicals;
  3917. /* adjust our table of devices */
  3918. for (i = 0; i < nphysicals + nlogicals + 1; i++) {
  3919. u8 *lunaddrbytes, is_OBDR = 0;
  3920. int rc = 0;
  3921. int phys_dev_index = i - (raid_ctlr_position == 0);
  3922. bool skip_device = false;
  3923. memset(tmpdevice, 0, sizeof(*tmpdevice));
  3924. physical_device = i < nphysicals + (raid_ctlr_position == 0);
  3925. /* Figure out where the LUN ID info is coming from */
  3926. lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
  3927. i, nphysicals, nlogicals, physdev_list, logdev_list);
  3928. /* Determine if this is a lun from an external target array */
  3929. tmpdevice->external =
  3930. figure_external_status(h, raid_ctlr_position, i,
  3931. nphysicals, nlocal_logicals);
  3932. /*
  3933. * Skip over some devices such as a spare.
  3934. */
  3935. if (phys_dev_index >= 0 && !tmpdevice->external &&
  3936. physical_device) {
  3937. skip_device = hpsa_skip_device(h, lunaddrbytes,
  3938. &physdev_list->LUN[phys_dev_index]);
  3939. if (skip_device)
  3940. continue;
  3941. }
  3942. /* Get device type, vendor, model, device id, raid_map */
  3943. rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
  3944. &is_OBDR);
  3945. if (rc == -ENOMEM) {
  3946. dev_warn(&h->pdev->dev,
  3947. "Out of memory, rescan deferred.\n");
  3948. h->drv_req_rescan = 1;
  3949. goto out;
  3950. }
  3951. if (rc) {
  3952. h->drv_req_rescan = 1;
  3953. continue;
  3954. }
  3955. figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
  3956. this_device = currentsd[ncurrent];
  3957. *this_device = *tmpdevice;
  3958. this_device->physical_device = physical_device;
  3959. /*
  3960. * Expose all devices except for physical devices that
  3961. * are masked.
  3962. */
  3963. if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
  3964. this_device->expose_device = 0;
  3965. else
  3966. this_device->expose_device = 1;
  3967. /*
  3968. * Get the SAS address for physical devices that are exposed.
  3969. */
  3970. if (this_device->physical_device && this_device->expose_device)
  3971. hpsa_get_sas_address(h, lunaddrbytes, this_device);
  3972. switch (this_device->devtype) {
  3973. case TYPE_ROM:
  3974. /* We don't *really* support actual CD-ROM devices,
  3975. * just "One Button Disaster Recovery" tape drive
  3976. * which temporarily pretends to be a CD-ROM drive.
  3977. * So we check that the device is really an OBDR tape
  3978. * device by checking for "$DR-10" in bytes 43-48 of
  3979. * the inquiry data.
  3980. */
  3981. if (is_OBDR)
  3982. ncurrent++;
  3983. break;
  3984. case TYPE_DISK:
  3985. case TYPE_ZBC:
  3986. if (this_device->physical_device) {
  3987. /* The disk is in HBA mode. */
  3988. /* Never use RAID mapper in HBA mode. */
  3989. this_device->offload_enabled = 0;
  3990. hpsa_get_ioaccel_drive_info(h, this_device,
  3991. physdev_list, phys_dev_index, id_phys);
  3992. hpsa_get_path_info(this_device,
  3993. physdev_list, phys_dev_index, id_phys);
  3994. }
  3995. ncurrent++;
  3996. break;
  3997. case TYPE_TAPE:
  3998. case TYPE_MEDIUM_CHANGER:
  3999. ncurrent++;
  4000. break;
  4001. case TYPE_ENCLOSURE:
  4002. if (!this_device->external)
  4003. hpsa_get_enclosure_info(h, lunaddrbytes,
  4004. physdev_list, phys_dev_index,
  4005. this_device);
  4006. ncurrent++;
  4007. break;
  4008. case TYPE_RAID:
  4009. /* Only present the Smartarray HBA as a RAID controller.
  4010. * If it's a RAID controller other than the HBA itself
  4011. * (an external RAID controller, MSA500 or similar)
  4012. * don't present it.
  4013. */
  4014. if (!is_hba_lunid(lunaddrbytes))
  4015. break;
  4016. ncurrent++;
  4017. break;
  4018. default:
  4019. break;
  4020. }
  4021. if (ncurrent >= HPSA_MAX_DEVICES)
  4022. break;
  4023. }
  4024. if (h->sas_host == NULL) {
  4025. int rc = 0;
  4026. rc = hpsa_add_sas_host(h);
  4027. if (rc) {
  4028. dev_warn(&h->pdev->dev,
  4029. "Could not add sas host %d\n", rc);
  4030. goto out;
  4031. }
  4032. }
  4033. adjust_hpsa_scsi_table(h, currentsd, ncurrent);
  4034. out:
  4035. kfree(tmpdevice);
  4036. for (i = 0; i < ndev_allocated; i++)
  4037. kfree(currentsd[i]);
  4038. kfree(currentsd);
  4039. kfree(physdev_list);
  4040. kfree(logdev_list);
  4041. kfree(id_ctlr);
  4042. kfree(id_phys);
  4043. }
  4044. static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
  4045. struct scatterlist *sg)
  4046. {
  4047. u64 addr64 = (u64) sg_dma_address(sg);
  4048. unsigned int len = sg_dma_len(sg);
  4049. desc->Addr = cpu_to_le64(addr64);
  4050. desc->Len = cpu_to_le32(len);
  4051. desc->Ext = 0;
  4052. }
  4053. /*
  4054. * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
  4055. * dma mapping and fills in the scatter gather entries of the
  4056. * hpsa command, cp.
  4057. */
  4058. static int hpsa_scatter_gather(struct ctlr_info *h,
  4059. struct CommandList *cp,
  4060. struct scsi_cmnd *cmd)
  4061. {
  4062. struct scatterlist *sg;
  4063. int use_sg, i, sg_limit, chained;
  4064. struct SGDescriptor *curr_sg;
  4065. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  4066. use_sg = scsi_dma_map(cmd);
  4067. if (use_sg < 0)
  4068. return use_sg;
  4069. if (!use_sg)
  4070. goto sglist_finished;
  4071. /*
  4072. * If the number of entries is greater than the max for a single list,
  4073. * then we have a chained list; we will set up all but one entry in the
  4074. * first list (the last entry is saved for link information);
  4075. * otherwise, we don't have a chained list and we'll set up at each of
  4076. * the entries in the one list.
  4077. */
  4078. curr_sg = cp->SG;
  4079. chained = use_sg > h->max_cmd_sg_entries;
  4080. sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
  4081. scsi_for_each_sg(cmd, sg, sg_limit, i) {
  4082. hpsa_set_sg_descriptor(curr_sg, sg);
  4083. curr_sg++;
  4084. }
  4085. if (chained) {
  4086. /*
  4087. * Continue with the chained list. Set curr_sg to the chained
  4088. * list. Modify the limit to the total count less the entries
  4089. * we've already set up. Resume the scan at the list entry
  4090. * where the previous loop left off.
  4091. */
  4092. curr_sg = h->cmd_sg_list[cp->cmdindex];
  4093. sg_limit = use_sg - sg_limit;
  4094. for_each_sg(sg, sg, sg_limit, i) {
  4095. hpsa_set_sg_descriptor(curr_sg, sg);
  4096. curr_sg++;
  4097. }
  4098. }
  4099. /* Back the pointer up to the last entry and mark it as "last". */
  4100. (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
  4101. if (use_sg + chained > h->maxSG)
  4102. h->maxSG = use_sg + chained;
  4103. if (chained) {
  4104. cp->Header.SGList = h->max_cmd_sg_entries;
  4105. cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
  4106. if (hpsa_map_sg_chain_block(h, cp)) {
  4107. scsi_dma_unmap(cmd);
  4108. return -1;
  4109. }
  4110. return 0;
  4111. }
  4112. sglist_finished:
  4113. cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
  4114. cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
  4115. return 0;
  4116. }
  4117. static inline void warn_zero_length_transfer(struct ctlr_info *h,
  4118. u8 *cdb, int cdb_len,
  4119. const char *func)
  4120. {
  4121. dev_warn(&h->pdev->dev,
  4122. "%s: Blocking zero-length request: CDB:%*phN\n",
  4123. func, cdb_len, cdb);
  4124. }
  4125. #define IO_ACCEL_INELIGIBLE 1
  4126. /* zero-length transfers trigger hardware errors. */
  4127. static bool is_zero_length_transfer(u8 *cdb)
  4128. {
  4129. u32 block_cnt;
  4130. /* Block zero-length transfer sizes on certain commands. */
  4131. switch (cdb[0]) {
  4132. case READ_10:
  4133. case WRITE_10:
  4134. case VERIFY: /* 0x2F */
  4135. case WRITE_VERIFY: /* 0x2E */
  4136. block_cnt = get_unaligned_be16(&cdb[7]);
  4137. break;
  4138. case READ_12:
  4139. case WRITE_12:
  4140. case VERIFY_12: /* 0xAF */
  4141. case WRITE_VERIFY_12: /* 0xAE */
  4142. block_cnt = get_unaligned_be32(&cdb[6]);
  4143. break;
  4144. case READ_16:
  4145. case WRITE_16:
  4146. case VERIFY_16: /* 0x8F */
  4147. block_cnt = get_unaligned_be32(&cdb[10]);
  4148. break;
  4149. default:
  4150. return false;
  4151. }
  4152. return block_cnt == 0;
  4153. }
  4154. static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
  4155. {
  4156. int is_write = 0;
  4157. u32 block;
  4158. u32 block_cnt;
  4159. /* Perform some CDB fixups if needed using 10 byte reads/writes only */
  4160. switch (cdb[0]) {
  4161. case WRITE_6:
  4162. case WRITE_12:
  4163. is_write = 1;
  4164. fallthrough;
  4165. case READ_6:
  4166. case READ_12:
  4167. if (*cdb_len == 6) {
  4168. block = (((cdb[1] & 0x1F) << 16) |
  4169. (cdb[2] << 8) |
  4170. cdb[3]);
  4171. block_cnt = cdb[4];
  4172. if (block_cnt == 0)
  4173. block_cnt = 256;
  4174. } else {
  4175. BUG_ON(*cdb_len != 12);
  4176. block = get_unaligned_be32(&cdb[2]);
  4177. block_cnt = get_unaligned_be32(&cdb[6]);
  4178. }
  4179. if (block_cnt > 0xffff)
  4180. return IO_ACCEL_INELIGIBLE;
  4181. cdb[0] = is_write ? WRITE_10 : READ_10;
  4182. cdb[1] = 0;
  4183. cdb[2] = (u8) (block >> 24);
  4184. cdb[3] = (u8) (block >> 16);
  4185. cdb[4] = (u8) (block >> 8);
  4186. cdb[5] = (u8) (block);
  4187. cdb[6] = 0;
  4188. cdb[7] = (u8) (block_cnt >> 8);
  4189. cdb[8] = (u8) (block_cnt);
  4190. cdb[9] = 0;
  4191. *cdb_len = 10;
  4192. break;
  4193. }
  4194. return 0;
  4195. }
  4196. static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
  4197. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4198. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4199. {
  4200. struct scsi_cmnd *cmd = c->scsi_cmd;
  4201. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
  4202. unsigned int len;
  4203. unsigned int total_len = 0;
  4204. struct scatterlist *sg;
  4205. u64 addr64;
  4206. int use_sg, i;
  4207. struct SGDescriptor *curr_sg;
  4208. u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
  4209. /* TODO: implement chaining support */
  4210. if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
  4211. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4212. return IO_ACCEL_INELIGIBLE;
  4213. }
  4214. BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
  4215. if (is_zero_length_transfer(cdb)) {
  4216. warn_zero_length_transfer(h, cdb, cdb_len, __func__);
  4217. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4218. return IO_ACCEL_INELIGIBLE;
  4219. }
  4220. if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
  4221. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4222. return IO_ACCEL_INELIGIBLE;
  4223. }
  4224. c->cmd_type = CMD_IOACCEL1;
  4225. /* Adjust the DMA address to point to the accelerated command buffer */
  4226. c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
  4227. (c->cmdindex * sizeof(*cp));
  4228. BUG_ON(c->busaddr & 0x0000007F);
  4229. use_sg = scsi_dma_map(cmd);
  4230. if (use_sg < 0) {
  4231. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4232. return use_sg;
  4233. }
  4234. if (use_sg) {
  4235. curr_sg = cp->SG;
  4236. scsi_for_each_sg(cmd, sg, use_sg, i) {
  4237. addr64 = (u64) sg_dma_address(sg);
  4238. len = sg_dma_len(sg);
  4239. total_len += len;
  4240. curr_sg->Addr = cpu_to_le64(addr64);
  4241. curr_sg->Len = cpu_to_le32(len);
  4242. curr_sg->Ext = cpu_to_le32(0);
  4243. curr_sg++;
  4244. }
  4245. (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
  4246. switch (cmd->sc_data_direction) {
  4247. case DMA_TO_DEVICE:
  4248. control |= IOACCEL1_CONTROL_DATA_OUT;
  4249. break;
  4250. case DMA_FROM_DEVICE:
  4251. control |= IOACCEL1_CONTROL_DATA_IN;
  4252. break;
  4253. case DMA_NONE:
  4254. control |= IOACCEL1_CONTROL_NODATAXFER;
  4255. break;
  4256. default:
  4257. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4258. cmd->sc_data_direction);
  4259. BUG();
  4260. break;
  4261. }
  4262. } else {
  4263. control |= IOACCEL1_CONTROL_NODATAXFER;
  4264. }
  4265. c->Header.SGList = use_sg;
  4266. /* Fill out the command structure to submit */
  4267. cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
  4268. cp->transfer_len = cpu_to_le32(total_len);
  4269. cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
  4270. (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
  4271. cp->control = cpu_to_le32(control);
  4272. memcpy(cp->CDB, cdb, cdb_len);
  4273. memcpy(cp->CISS_LUN, scsi3addr, 8);
  4274. /* Tag was already set at init time. */
  4275. enqueue_cmd_and_start_io(h, c);
  4276. return 0;
  4277. }
  4278. /*
  4279. * Queue a command directly to a device behind the controller using the
  4280. * I/O accelerator path.
  4281. */
  4282. static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
  4283. struct CommandList *c)
  4284. {
  4285. struct scsi_cmnd *cmd = c->scsi_cmd;
  4286. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4287. if (!dev)
  4288. return -1;
  4289. c->phys_disk = dev;
  4290. if (dev->in_reset)
  4291. return -1;
  4292. return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
  4293. cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
  4294. }
  4295. /*
  4296. * Set encryption parameters for the ioaccel2 request
  4297. */
  4298. static void set_encrypt_ioaccel2(struct ctlr_info *h,
  4299. struct CommandList *c, struct io_accel2_cmd *cp)
  4300. {
  4301. struct scsi_cmnd *cmd = c->scsi_cmd;
  4302. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4303. struct raid_map_data *map = &dev->raid_map;
  4304. u64 first_block;
  4305. /* Are we doing encryption on this device */
  4306. if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
  4307. return;
  4308. /* Set the data encryption key index. */
  4309. cp->dekindex = map->dekindex;
  4310. /* Set the encryption enable flag, encoded into direction field. */
  4311. cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
  4312. /* Set encryption tweak values based on logical block address
  4313. * If block size is 512, tweak value is LBA.
  4314. * For other block sizes, tweak is (LBA * block size)/ 512)
  4315. */
  4316. switch (cmd->cmnd[0]) {
  4317. /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
  4318. case READ_6:
  4319. case WRITE_6:
  4320. first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
  4321. (cmd->cmnd[2] << 8) |
  4322. cmd->cmnd[3]);
  4323. break;
  4324. case WRITE_10:
  4325. case READ_10:
  4326. /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
  4327. case WRITE_12:
  4328. case READ_12:
  4329. first_block = get_unaligned_be32(&cmd->cmnd[2]);
  4330. break;
  4331. case WRITE_16:
  4332. case READ_16:
  4333. first_block = get_unaligned_be64(&cmd->cmnd[2]);
  4334. break;
  4335. default:
  4336. dev_err(&h->pdev->dev,
  4337. "ERROR: %s: size (0x%x) not supported for encryption\n",
  4338. __func__, cmd->cmnd[0]);
  4339. BUG();
  4340. break;
  4341. }
  4342. if (le32_to_cpu(map->volume_blk_size) != 512)
  4343. first_block = first_block *
  4344. le32_to_cpu(map->volume_blk_size)/512;
  4345. cp->tweak_lower = cpu_to_le32(first_block);
  4346. cp->tweak_upper = cpu_to_le32(first_block >> 32);
  4347. }
  4348. static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
  4349. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4350. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4351. {
  4352. struct scsi_cmnd *cmd = c->scsi_cmd;
  4353. struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
  4354. struct ioaccel2_sg_element *curr_sg;
  4355. int use_sg, i;
  4356. struct scatterlist *sg;
  4357. u64 addr64;
  4358. u32 len;
  4359. u32 total_len = 0;
  4360. if (!cmd->device)
  4361. return -1;
  4362. if (!cmd->device->hostdata)
  4363. return -1;
  4364. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  4365. if (is_zero_length_transfer(cdb)) {
  4366. warn_zero_length_transfer(h, cdb, cdb_len, __func__);
  4367. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4368. return IO_ACCEL_INELIGIBLE;
  4369. }
  4370. if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
  4371. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4372. return IO_ACCEL_INELIGIBLE;
  4373. }
  4374. c->cmd_type = CMD_IOACCEL2;
  4375. /* Adjust the DMA address to point to the accelerated command buffer */
  4376. c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
  4377. (c->cmdindex * sizeof(*cp));
  4378. BUG_ON(c->busaddr & 0x0000007F);
  4379. memset(cp, 0, sizeof(*cp));
  4380. cp->IU_type = IOACCEL2_IU_TYPE;
  4381. use_sg = scsi_dma_map(cmd);
  4382. if (use_sg < 0) {
  4383. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4384. return use_sg;
  4385. }
  4386. if (use_sg) {
  4387. curr_sg = cp->sg;
  4388. if (use_sg > h->ioaccel_maxsg) {
  4389. addr64 = le64_to_cpu(
  4390. h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
  4391. curr_sg->address = cpu_to_le64(addr64);
  4392. curr_sg->length = 0;
  4393. curr_sg->reserved[0] = 0;
  4394. curr_sg->reserved[1] = 0;
  4395. curr_sg->reserved[2] = 0;
  4396. curr_sg->chain_indicator = IOACCEL2_CHAIN;
  4397. curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
  4398. }
  4399. scsi_for_each_sg(cmd, sg, use_sg, i) {
  4400. addr64 = (u64) sg_dma_address(sg);
  4401. len = sg_dma_len(sg);
  4402. total_len += len;
  4403. curr_sg->address = cpu_to_le64(addr64);
  4404. curr_sg->length = cpu_to_le32(len);
  4405. curr_sg->reserved[0] = 0;
  4406. curr_sg->reserved[1] = 0;
  4407. curr_sg->reserved[2] = 0;
  4408. curr_sg->chain_indicator = 0;
  4409. curr_sg++;
  4410. }
  4411. /*
  4412. * Set the last s/g element bit
  4413. */
  4414. (curr_sg - 1)->chain_indicator = IOACCEL2_LAST_SG;
  4415. switch (cmd->sc_data_direction) {
  4416. case DMA_TO_DEVICE:
  4417. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4418. cp->direction |= IOACCEL2_DIR_DATA_OUT;
  4419. break;
  4420. case DMA_FROM_DEVICE:
  4421. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4422. cp->direction |= IOACCEL2_DIR_DATA_IN;
  4423. break;
  4424. case DMA_NONE:
  4425. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4426. cp->direction |= IOACCEL2_DIR_NO_DATA;
  4427. break;
  4428. default:
  4429. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4430. cmd->sc_data_direction);
  4431. BUG();
  4432. break;
  4433. }
  4434. } else {
  4435. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4436. cp->direction |= IOACCEL2_DIR_NO_DATA;
  4437. }
  4438. /* Set encryption parameters, if necessary */
  4439. set_encrypt_ioaccel2(h, c, cp);
  4440. cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
  4441. cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
  4442. memcpy(cp->cdb, cdb, sizeof(cp->cdb));
  4443. cp->data_len = cpu_to_le32(total_len);
  4444. cp->err_ptr = cpu_to_le64(c->busaddr +
  4445. offsetof(struct io_accel2_cmd, error_data));
  4446. cp->err_len = cpu_to_le32(sizeof(cp->error_data));
  4447. /* fill in sg elements */
  4448. if (use_sg > h->ioaccel_maxsg) {
  4449. cp->sg_count = 1;
  4450. cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
  4451. if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
  4452. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4453. scsi_dma_unmap(cmd);
  4454. return -1;
  4455. }
  4456. } else
  4457. cp->sg_count = (u8) use_sg;
  4458. if (phys_disk->in_reset) {
  4459. cmd->result = DID_RESET << 16;
  4460. return -1;
  4461. }
  4462. enqueue_cmd_and_start_io(h, c);
  4463. return 0;
  4464. }
  4465. /*
  4466. * Queue a command to the correct I/O accelerator path.
  4467. */
  4468. static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
  4469. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4470. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4471. {
  4472. if (!c->scsi_cmd->device)
  4473. return -1;
  4474. if (!c->scsi_cmd->device->hostdata)
  4475. return -1;
  4476. if (phys_disk->in_reset)
  4477. return -1;
  4478. /* Try to honor the device's queue depth */
  4479. if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
  4480. phys_disk->queue_depth) {
  4481. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4482. return IO_ACCEL_INELIGIBLE;
  4483. }
  4484. if (h->transMethod & CFGTBL_Trans_io_accel1)
  4485. return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
  4486. cdb, cdb_len, scsi3addr,
  4487. phys_disk);
  4488. else
  4489. return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
  4490. cdb, cdb_len, scsi3addr,
  4491. phys_disk);
  4492. }
  4493. static void raid_map_helper(struct raid_map_data *map,
  4494. int offload_to_mirror, u32 *map_index, u32 *current_group)
  4495. {
  4496. if (offload_to_mirror == 0) {
  4497. /* use physical disk in the first mirrored group. */
  4498. *map_index %= le16_to_cpu(map->data_disks_per_row);
  4499. return;
  4500. }
  4501. do {
  4502. /* determine mirror group that *map_index indicates */
  4503. *current_group = *map_index /
  4504. le16_to_cpu(map->data_disks_per_row);
  4505. if (offload_to_mirror == *current_group)
  4506. continue;
  4507. if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
  4508. /* select map index from next group */
  4509. *map_index += le16_to_cpu(map->data_disks_per_row);
  4510. (*current_group)++;
  4511. } else {
  4512. /* select map index from first group */
  4513. *map_index %= le16_to_cpu(map->data_disks_per_row);
  4514. *current_group = 0;
  4515. }
  4516. } while (offload_to_mirror != *current_group);
  4517. }
  4518. /*
  4519. * Attempt to perform offload RAID mapping for a logical volume I/O.
  4520. */
  4521. static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
  4522. struct CommandList *c)
  4523. {
  4524. struct scsi_cmnd *cmd = c->scsi_cmd;
  4525. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4526. struct raid_map_data *map = &dev->raid_map;
  4527. struct raid_map_disk_data *dd = &map->data[0];
  4528. int is_write = 0;
  4529. u32 map_index;
  4530. u64 first_block, last_block;
  4531. u32 block_cnt;
  4532. u32 blocks_per_row;
  4533. u64 first_row, last_row;
  4534. u32 first_row_offset, last_row_offset;
  4535. u32 first_column, last_column;
  4536. u64 r0_first_row, r0_last_row;
  4537. u32 r5or6_blocks_per_row;
  4538. u64 r5or6_first_row, r5or6_last_row;
  4539. u32 r5or6_first_row_offset, r5or6_last_row_offset;
  4540. u32 r5or6_first_column, r5or6_last_column;
  4541. u32 total_disks_per_row;
  4542. u32 stripesize;
  4543. u32 first_group, last_group, current_group;
  4544. u32 map_row;
  4545. u32 disk_handle;
  4546. u64 disk_block;
  4547. u32 disk_block_cnt;
  4548. u8 cdb[16];
  4549. u8 cdb_len;
  4550. u16 strip_size;
  4551. #if BITS_PER_LONG == 32
  4552. u64 tmpdiv;
  4553. #endif
  4554. int offload_to_mirror;
  4555. if (!dev)
  4556. return -1;
  4557. if (dev->in_reset)
  4558. return -1;
  4559. /* check for valid opcode, get LBA and block count */
  4560. switch (cmd->cmnd[0]) {
  4561. case WRITE_6:
  4562. is_write = 1;
  4563. fallthrough;
  4564. case READ_6:
  4565. first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
  4566. (cmd->cmnd[2] << 8) |
  4567. cmd->cmnd[3]);
  4568. block_cnt = cmd->cmnd[4];
  4569. if (block_cnt == 0)
  4570. block_cnt = 256;
  4571. break;
  4572. case WRITE_10:
  4573. is_write = 1;
  4574. fallthrough;
  4575. case READ_10:
  4576. first_block =
  4577. (((u64) cmd->cmnd[2]) << 24) |
  4578. (((u64) cmd->cmnd[3]) << 16) |
  4579. (((u64) cmd->cmnd[4]) << 8) |
  4580. cmd->cmnd[5];
  4581. block_cnt =
  4582. (((u32) cmd->cmnd[7]) << 8) |
  4583. cmd->cmnd[8];
  4584. break;
  4585. case WRITE_12:
  4586. is_write = 1;
  4587. fallthrough;
  4588. case READ_12:
  4589. first_block =
  4590. (((u64) cmd->cmnd[2]) << 24) |
  4591. (((u64) cmd->cmnd[3]) << 16) |
  4592. (((u64) cmd->cmnd[4]) << 8) |
  4593. cmd->cmnd[5];
  4594. block_cnt =
  4595. (((u32) cmd->cmnd[6]) << 24) |
  4596. (((u32) cmd->cmnd[7]) << 16) |
  4597. (((u32) cmd->cmnd[8]) << 8) |
  4598. cmd->cmnd[9];
  4599. break;
  4600. case WRITE_16:
  4601. is_write = 1;
  4602. fallthrough;
  4603. case READ_16:
  4604. first_block =
  4605. (((u64) cmd->cmnd[2]) << 56) |
  4606. (((u64) cmd->cmnd[3]) << 48) |
  4607. (((u64) cmd->cmnd[4]) << 40) |
  4608. (((u64) cmd->cmnd[5]) << 32) |
  4609. (((u64) cmd->cmnd[6]) << 24) |
  4610. (((u64) cmd->cmnd[7]) << 16) |
  4611. (((u64) cmd->cmnd[8]) << 8) |
  4612. cmd->cmnd[9];
  4613. block_cnt =
  4614. (((u32) cmd->cmnd[10]) << 24) |
  4615. (((u32) cmd->cmnd[11]) << 16) |
  4616. (((u32) cmd->cmnd[12]) << 8) |
  4617. cmd->cmnd[13];
  4618. break;
  4619. default:
  4620. return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
  4621. }
  4622. last_block = first_block + block_cnt - 1;
  4623. /* check for write to non-RAID-0 */
  4624. if (is_write && dev->raid_level != 0)
  4625. return IO_ACCEL_INELIGIBLE;
  4626. /* check for invalid block or wraparound */
  4627. if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
  4628. last_block < first_block)
  4629. return IO_ACCEL_INELIGIBLE;
  4630. /* calculate stripe information for the request */
  4631. blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
  4632. le16_to_cpu(map->strip_size);
  4633. strip_size = le16_to_cpu(map->strip_size);
  4634. #if BITS_PER_LONG == 32
  4635. tmpdiv = first_block;
  4636. (void) do_div(tmpdiv, blocks_per_row);
  4637. first_row = tmpdiv;
  4638. tmpdiv = last_block;
  4639. (void) do_div(tmpdiv, blocks_per_row);
  4640. last_row = tmpdiv;
  4641. first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
  4642. last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
  4643. tmpdiv = first_row_offset;
  4644. (void) do_div(tmpdiv, strip_size);
  4645. first_column = tmpdiv;
  4646. tmpdiv = last_row_offset;
  4647. (void) do_div(tmpdiv, strip_size);
  4648. last_column = tmpdiv;
  4649. #else
  4650. first_row = first_block / blocks_per_row;
  4651. last_row = last_block / blocks_per_row;
  4652. first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
  4653. last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
  4654. first_column = first_row_offset / strip_size;
  4655. last_column = last_row_offset / strip_size;
  4656. #endif
  4657. /* if this isn't a single row/column then give to the controller */
  4658. if ((first_row != last_row) || (first_column != last_column))
  4659. return IO_ACCEL_INELIGIBLE;
  4660. /* proceeding with driver mapping */
  4661. total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
  4662. le16_to_cpu(map->metadata_disks_per_row);
  4663. map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
  4664. le16_to_cpu(map->row_cnt);
  4665. map_index = (map_row * total_disks_per_row) + first_column;
  4666. switch (dev->raid_level) {
  4667. case HPSA_RAID_0:
  4668. break; /* nothing special to do */
  4669. case HPSA_RAID_1:
  4670. /* Handles load balance across RAID 1 members.
  4671. * (2-drive R1 and R10 with even # of drives.)
  4672. * Appropriate for SSDs, not optimal for HDDs
  4673. * Ensure we have the correct raid_map.
  4674. */
  4675. if (le16_to_cpu(map->layout_map_count) != 2) {
  4676. hpsa_turn_off_ioaccel_for_device(dev);
  4677. return IO_ACCEL_INELIGIBLE;
  4678. }
  4679. if (dev->offload_to_mirror)
  4680. map_index += le16_to_cpu(map->data_disks_per_row);
  4681. dev->offload_to_mirror = !dev->offload_to_mirror;
  4682. break;
  4683. case HPSA_RAID_ADM:
  4684. /* Handles N-way mirrors (R1-ADM)
  4685. * and R10 with # of drives divisible by 3.)
  4686. * Ensure we have the correct raid_map.
  4687. */
  4688. if (le16_to_cpu(map->layout_map_count) != 3) {
  4689. hpsa_turn_off_ioaccel_for_device(dev);
  4690. return IO_ACCEL_INELIGIBLE;
  4691. }
  4692. offload_to_mirror = dev->offload_to_mirror;
  4693. raid_map_helper(map, offload_to_mirror,
  4694. &map_index, &current_group);
  4695. /* set mirror group to use next time */
  4696. offload_to_mirror =
  4697. (offload_to_mirror >=
  4698. le16_to_cpu(map->layout_map_count) - 1)
  4699. ? 0 : offload_to_mirror + 1;
  4700. dev->offload_to_mirror = offload_to_mirror;
  4701. /* Avoid direct use of dev->offload_to_mirror within this
  4702. * function since multiple threads might simultaneously
  4703. * increment it beyond the range of dev->layout_map_count -1.
  4704. */
  4705. break;
  4706. case HPSA_RAID_5:
  4707. case HPSA_RAID_6:
  4708. if (le16_to_cpu(map->layout_map_count) <= 1)
  4709. break;
  4710. /* Verify first and last block are in same RAID group */
  4711. r5or6_blocks_per_row =
  4712. le16_to_cpu(map->strip_size) *
  4713. le16_to_cpu(map->data_disks_per_row);
  4714. if (r5or6_blocks_per_row == 0) {
  4715. hpsa_turn_off_ioaccel_for_device(dev);
  4716. return IO_ACCEL_INELIGIBLE;
  4717. }
  4718. stripesize = r5or6_blocks_per_row *
  4719. le16_to_cpu(map->layout_map_count);
  4720. #if BITS_PER_LONG == 32
  4721. tmpdiv = first_block;
  4722. first_group = do_div(tmpdiv, stripesize);
  4723. tmpdiv = first_group;
  4724. (void) do_div(tmpdiv, r5or6_blocks_per_row);
  4725. first_group = tmpdiv;
  4726. tmpdiv = last_block;
  4727. last_group = do_div(tmpdiv, stripesize);
  4728. tmpdiv = last_group;
  4729. (void) do_div(tmpdiv, r5or6_blocks_per_row);
  4730. last_group = tmpdiv;
  4731. #else
  4732. first_group = (first_block % stripesize) / r5or6_blocks_per_row;
  4733. last_group = (last_block % stripesize) / r5or6_blocks_per_row;
  4734. #endif
  4735. if (first_group != last_group)
  4736. return IO_ACCEL_INELIGIBLE;
  4737. /* Verify request is in a single row of RAID 5/6 */
  4738. #if BITS_PER_LONG == 32
  4739. tmpdiv = first_block;
  4740. (void) do_div(tmpdiv, stripesize);
  4741. first_row = r5or6_first_row = r0_first_row = tmpdiv;
  4742. tmpdiv = last_block;
  4743. (void) do_div(tmpdiv, stripesize);
  4744. r5or6_last_row = r0_last_row = tmpdiv;
  4745. #else
  4746. first_row = r5or6_first_row = r0_first_row =
  4747. first_block / stripesize;
  4748. r5or6_last_row = r0_last_row = last_block / stripesize;
  4749. #endif
  4750. if (r5or6_first_row != r5or6_last_row)
  4751. return IO_ACCEL_INELIGIBLE;
  4752. /* Verify request is in a single column */
  4753. #if BITS_PER_LONG == 32
  4754. tmpdiv = first_block;
  4755. first_row_offset = do_div(tmpdiv, stripesize);
  4756. tmpdiv = first_row_offset;
  4757. first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
  4758. r5or6_first_row_offset = first_row_offset;
  4759. tmpdiv = last_block;
  4760. r5or6_last_row_offset = do_div(tmpdiv, stripesize);
  4761. tmpdiv = r5or6_last_row_offset;
  4762. r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
  4763. tmpdiv = r5or6_first_row_offset;
  4764. (void) do_div(tmpdiv, map->strip_size);
  4765. first_column = r5or6_first_column = tmpdiv;
  4766. tmpdiv = r5or6_last_row_offset;
  4767. (void) do_div(tmpdiv, map->strip_size);
  4768. r5or6_last_column = tmpdiv;
  4769. #else
  4770. first_row_offset = r5or6_first_row_offset =
  4771. (u32)((first_block % stripesize) %
  4772. r5or6_blocks_per_row);
  4773. r5or6_last_row_offset =
  4774. (u32)((last_block % stripesize) %
  4775. r5or6_blocks_per_row);
  4776. first_column = r5or6_first_column =
  4777. r5or6_first_row_offset / le16_to_cpu(map->strip_size);
  4778. r5or6_last_column =
  4779. r5or6_last_row_offset / le16_to_cpu(map->strip_size);
  4780. #endif
  4781. if (r5or6_first_column != r5or6_last_column)
  4782. return IO_ACCEL_INELIGIBLE;
  4783. /* Request is eligible */
  4784. map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
  4785. le16_to_cpu(map->row_cnt);
  4786. map_index = (first_group *
  4787. (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
  4788. (map_row * total_disks_per_row) + first_column;
  4789. break;
  4790. default:
  4791. return IO_ACCEL_INELIGIBLE;
  4792. }
  4793. if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
  4794. return IO_ACCEL_INELIGIBLE;
  4795. c->phys_disk = dev->phys_disk[map_index];
  4796. if (!c->phys_disk)
  4797. return IO_ACCEL_INELIGIBLE;
  4798. disk_handle = dd[map_index].ioaccel_handle;
  4799. disk_block = le64_to_cpu(map->disk_starting_blk) +
  4800. first_row * le16_to_cpu(map->strip_size) +
  4801. (first_row_offset - first_column *
  4802. le16_to_cpu(map->strip_size));
  4803. disk_block_cnt = block_cnt;
  4804. /* handle differing logical/physical block sizes */
  4805. if (map->phys_blk_shift) {
  4806. disk_block <<= map->phys_blk_shift;
  4807. disk_block_cnt <<= map->phys_blk_shift;
  4808. }
  4809. BUG_ON(disk_block_cnt > 0xffff);
  4810. /* build the new CDB for the physical disk I/O */
  4811. if (disk_block > 0xffffffff) {
  4812. cdb[0] = is_write ? WRITE_16 : READ_16;
  4813. cdb[1] = 0;
  4814. cdb[2] = (u8) (disk_block >> 56);
  4815. cdb[3] = (u8) (disk_block >> 48);
  4816. cdb[4] = (u8) (disk_block >> 40);
  4817. cdb[5] = (u8) (disk_block >> 32);
  4818. cdb[6] = (u8) (disk_block >> 24);
  4819. cdb[7] = (u8) (disk_block >> 16);
  4820. cdb[8] = (u8) (disk_block >> 8);
  4821. cdb[9] = (u8) (disk_block);
  4822. cdb[10] = (u8) (disk_block_cnt >> 24);
  4823. cdb[11] = (u8) (disk_block_cnt >> 16);
  4824. cdb[12] = (u8) (disk_block_cnt >> 8);
  4825. cdb[13] = (u8) (disk_block_cnt);
  4826. cdb[14] = 0;
  4827. cdb[15] = 0;
  4828. cdb_len = 16;
  4829. } else {
  4830. cdb[0] = is_write ? WRITE_10 : READ_10;
  4831. cdb[1] = 0;
  4832. cdb[2] = (u8) (disk_block >> 24);
  4833. cdb[3] = (u8) (disk_block >> 16);
  4834. cdb[4] = (u8) (disk_block >> 8);
  4835. cdb[5] = (u8) (disk_block);
  4836. cdb[6] = 0;
  4837. cdb[7] = (u8) (disk_block_cnt >> 8);
  4838. cdb[8] = (u8) (disk_block_cnt);
  4839. cdb[9] = 0;
  4840. cdb_len = 10;
  4841. }
  4842. return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
  4843. dev->scsi3addr,
  4844. dev->phys_disk[map_index]);
  4845. }
  4846. /*
  4847. * Submit commands down the "normal" RAID stack path
  4848. * All callers to hpsa_ciss_submit must check lockup_detected
  4849. * beforehand, before (opt.) and after calling cmd_alloc
  4850. */
  4851. static int hpsa_ciss_submit(struct ctlr_info *h,
  4852. struct CommandList *c, struct scsi_cmnd *cmd,
  4853. struct hpsa_scsi_dev_t *dev)
  4854. {
  4855. cmd->host_scribble = (unsigned char *) c;
  4856. c->cmd_type = CMD_SCSI;
  4857. c->scsi_cmd = cmd;
  4858. c->Header.ReplyQueue = 0; /* unused in simple mode */
  4859. memcpy(&c->Header.LUN.LunAddrBytes[0], &dev->scsi3addr[0], 8);
  4860. c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
  4861. /* Fill in the request block... */
  4862. c->Request.Timeout = 0;
  4863. BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
  4864. c->Request.CDBLen = cmd->cmd_len;
  4865. memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
  4866. switch (cmd->sc_data_direction) {
  4867. case DMA_TO_DEVICE:
  4868. c->Request.type_attr_dir =
  4869. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
  4870. break;
  4871. case DMA_FROM_DEVICE:
  4872. c->Request.type_attr_dir =
  4873. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
  4874. break;
  4875. case DMA_NONE:
  4876. c->Request.type_attr_dir =
  4877. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
  4878. break;
  4879. case DMA_BIDIRECTIONAL:
  4880. /* This can happen if a buggy application does a scsi passthru
  4881. * and sets both inlen and outlen to non-zero. ( see
  4882. * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
  4883. */
  4884. c->Request.type_attr_dir =
  4885. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
  4886. /* This is technically wrong, and hpsa controllers should
  4887. * reject it with CMD_INVALID, which is the most correct
  4888. * response, but non-fibre backends appear to let it
  4889. * slide by, and give the same results as if this field
  4890. * were set correctly. Either way is acceptable for
  4891. * our purposes here.
  4892. */
  4893. break;
  4894. default:
  4895. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4896. cmd->sc_data_direction);
  4897. BUG();
  4898. break;
  4899. }
  4900. if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
  4901. hpsa_cmd_resolve_and_free(h, c);
  4902. return SCSI_MLQUEUE_HOST_BUSY;
  4903. }
  4904. if (dev->in_reset) {
  4905. hpsa_cmd_resolve_and_free(h, c);
  4906. return SCSI_MLQUEUE_HOST_BUSY;
  4907. }
  4908. c->device = dev;
  4909. enqueue_cmd_and_start_io(h, c);
  4910. /* the cmd'll come back via intr handler in complete_scsi_command() */
  4911. return 0;
  4912. }
  4913. static void hpsa_cmd_init(struct ctlr_info *h, int index,
  4914. struct CommandList *c)
  4915. {
  4916. dma_addr_t cmd_dma_handle, err_dma_handle;
  4917. /* Zero out all of commandlist except the last field, refcount */
  4918. memset(c, 0, offsetof(struct CommandList, refcount));
  4919. c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
  4920. cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
  4921. c->err_info = h->errinfo_pool + index;
  4922. memset(c->err_info, 0, sizeof(*c->err_info));
  4923. err_dma_handle = h->errinfo_pool_dhandle
  4924. + index * sizeof(*c->err_info);
  4925. c->cmdindex = index;
  4926. c->busaddr = (u32) cmd_dma_handle;
  4927. c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
  4928. c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
  4929. c->h = h;
  4930. c->scsi_cmd = SCSI_CMD_IDLE;
  4931. }
  4932. static void hpsa_preinitialize_commands(struct ctlr_info *h)
  4933. {
  4934. int i;
  4935. for (i = 0; i < h->nr_cmds; i++) {
  4936. struct CommandList *c = h->cmd_pool + i;
  4937. hpsa_cmd_init(h, i, c);
  4938. atomic_set(&c->refcount, 0);
  4939. }
  4940. }
  4941. static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
  4942. struct CommandList *c)
  4943. {
  4944. dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
  4945. BUG_ON(c->cmdindex != index);
  4946. memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
  4947. memset(c->err_info, 0, sizeof(*c->err_info));
  4948. c->busaddr = (u32) cmd_dma_handle;
  4949. }
  4950. static int hpsa_ioaccel_submit(struct ctlr_info *h,
  4951. struct CommandList *c, struct scsi_cmnd *cmd,
  4952. bool retry)
  4953. {
  4954. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4955. int rc = IO_ACCEL_INELIGIBLE;
  4956. if (!dev)
  4957. return SCSI_MLQUEUE_HOST_BUSY;
  4958. if (dev->in_reset)
  4959. return SCSI_MLQUEUE_HOST_BUSY;
  4960. if (hpsa_simple_mode)
  4961. return IO_ACCEL_INELIGIBLE;
  4962. cmd->host_scribble = (unsigned char *) c;
  4963. if (dev->offload_enabled) {
  4964. hpsa_cmd_init(h, c->cmdindex, c); /* Zeroes out all fields */
  4965. c->cmd_type = CMD_SCSI;
  4966. c->scsi_cmd = cmd;
  4967. c->device = dev;
  4968. if (retry) /* Resubmit but do not increment device->commands_outstanding. */
  4969. c->retry_pending = true;
  4970. rc = hpsa_scsi_ioaccel_raid_map(h, c);
  4971. if (rc < 0) /* scsi_dma_map failed. */
  4972. rc = SCSI_MLQUEUE_HOST_BUSY;
  4973. } else if (dev->hba_ioaccel_enabled) {
  4974. hpsa_cmd_init(h, c->cmdindex, c); /* Zeroes out all fields */
  4975. c->cmd_type = CMD_SCSI;
  4976. c->scsi_cmd = cmd;
  4977. c->device = dev;
  4978. if (retry) /* Resubmit but do not increment device->commands_outstanding. */
  4979. c->retry_pending = true;
  4980. rc = hpsa_scsi_ioaccel_direct_map(h, c);
  4981. if (rc < 0) /* scsi_dma_map failed. */
  4982. rc = SCSI_MLQUEUE_HOST_BUSY;
  4983. }
  4984. return rc;
  4985. }
  4986. static void hpsa_command_resubmit_worker(struct work_struct *work)
  4987. {
  4988. struct scsi_cmnd *cmd;
  4989. struct hpsa_scsi_dev_t *dev;
  4990. struct CommandList *c = container_of(work, struct CommandList, work);
  4991. cmd = c->scsi_cmd;
  4992. dev = cmd->device->hostdata;
  4993. if (!dev) {
  4994. cmd->result = DID_NO_CONNECT << 16;
  4995. return hpsa_cmd_free_and_done(c->h, c, cmd);
  4996. }
  4997. if (dev->in_reset) {
  4998. cmd->result = DID_RESET << 16;
  4999. return hpsa_cmd_free_and_done(c->h, c, cmd);
  5000. }
  5001. if (c->cmd_type == CMD_IOACCEL2) {
  5002. struct ctlr_info *h = c->h;
  5003. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  5004. int rc;
  5005. if (c2->error_data.serv_response ==
  5006. IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
  5007. /* Resubmit with the retry_pending flag set. */
  5008. rc = hpsa_ioaccel_submit(h, c, cmd, true);
  5009. if (rc == 0)
  5010. return;
  5011. if (rc == SCSI_MLQUEUE_HOST_BUSY) {
  5012. /*
  5013. * If we get here, it means dma mapping failed.
  5014. * Try again via scsi mid layer, which will
  5015. * then get SCSI_MLQUEUE_HOST_BUSY.
  5016. */
  5017. cmd->result = DID_IMM_RETRY << 16;
  5018. return hpsa_cmd_free_and_done(h, c, cmd);
  5019. }
  5020. /* else, fall thru and resubmit down CISS path */
  5021. }
  5022. }
  5023. hpsa_cmd_partial_init(c->h, c->cmdindex, c);
  5024. /*
  5025. * Here we have not come in though queue_command, so we
  5026. * can set the retry_pending flag to true for a driver initiated
  5027. * retry attempt (I.E. not a SML retry).
  5028. * I.E. We are submitting a driver initiated retry.
  5029. * Note: hpsa_ciss_submit does not zero out the command fields like
  5030. * ioaccel submit does.
  5031. */
  5032. c->retry_pending = true;
  5033. if (hpsa_ciss_submit(c->h, c, cmd, dev)) {
  5034. /*
  5035. * If we get here, it means dma mapping failed. Try
  5036. * again via scsi mid layer, which will then get
  5037. * SCSI_MLQUEUE_HOST_BUSY.
  5038. *
  5039. * hpsa_ciss_submit will have already freed c
  5040. * if it encountered a dma mapping failure.
  5041. */
  5042. cmd->result = DID_IMM_RETRY << 16;
  5043. scsi_done(cmd);
  5044. }
  5045. }
  5046. /* Running in struct Scsi_Host->host_lock less mode */
  5047. static enum scsi_qc_status hpsa_scsi_queue_command(struct Scsi_Host *sh,
  5048. struct scsi_cmnd *cmd)
  5049. {
  5050. struct ctlr_info *h;
  5051. struct hpsa_scsi_dev_t *dev;
  5052. struct CommandList *c;
  5053. int rc = 0;
  5054. /* Get the ptr to our adapter structure out of cmd->host. */
  5055. h = sdev_to_hba(cmd->device);
  5056. BUG_ON(scsi_cmd_to_rq(cmd)->tag < 0);
  5057. dev = cmd->device->hostdata;
  5058. if (!dev) {
  5059. cmd->result = DID_NO_CONNECT << 16;
  5060. scsi_done(cmd);
  5061. return 0;
  5062. }
  5063. if (dev->removed) {
  5064. cmd->result = DID_NO_CONNECT << 16;
  5065. scsi_done(cmd);
  5066. return 0;
  5067. }
  5068. if (unlikely(lockup_detected(h))) {
  5069. cmd->result = DID_NO_CONNECT << 16;
  5070. scsi_done(cmd);
  5071. return 0;
  5072. }
  5073. if (dev->in_reset)
  5074. return SCSI_MLQUEUE_DEVICE_BUSY;
  5075. c = cmd_tagged_alloc(h, cmd);
  5076. if (c == NULL)
  5077. return SCSI_MLQUEUE_DEVICE_BUSY;
  5078. /*
  5079. * This is necessary because the SML doesn't zero out this field during
  5080. * error recovery.
  5081. */
  5082. cmd->result = 0;
  5083. /*
  5084. * Call alternate submit routine for I/O accelerated commands.
  5085. * Retries always go down the normal I/O path.
  5086. * Note: If cmd->retries is non-zero, then this is a SML
  5087. * initiated retry and not a driver initiated retry.
  5088. * This command has been obtained from cmd_tagged_alloc
  5089. * and is therefore a brand-new command.
  5090. */
  5091. if (likely(cmd->retries == 0 &&
  5092. !blk_rq_is_passthrough(scsi_cmd_to_rq(cmd)) &&
  5093. h->acciopath_status)) {
  5094. /* Submit with the retry_pending flag unset. */
  5095. rc = hpsa_ioaccel_submit(h, c, cmd, false);
  5096. if (rc == 0)
  5097. return 0;
  5098. if (rc == SCSI_MLQUEUE_HOST_BUSY) {
  5099. hpsa_cmd_resolve_and_free(h, c);
  5100. return SCSI_MLQUEUE_HOST_BUSY;
  5101. }
  5102. }
  5103. return hpsa_ciss_submit(h, c, cmd, dev);
  5104. }
  5105. static void hpsa_scan_complete(struct ctlr_info *h)
  5106. {
  5107. unsigned long flags;
  5108. spin_lock_irqsave(&h->scan_lock, flags);
  5109. h->scan_finished = 1;
  5110. wake_up(&h->scan_wait_queue);
  5111. spin_unlock_irqrestore(&h->scan_lock, flags);
  5112. }
  5113. static void hpsa_scan_start(struct Scsi_Host *sh)
  5114. {
  5115. struct ctlr_info *h = shost_to_hba(sh);
  5116. unsigned long flags;
  5117. /*
  5118. * Don't let rescans be initiated on a controller known to be locked
  5119. * up. If the controller locks up *during* a rescan, that thread is
  5120. * probably hosed, but at least we can prevent new rescan threads from
  5121. * piling up on a locked up controller.
  5122. */
  5123. if (unlikely(lockup_detected(h)))
  5124. return hpsa_scan_complete(h);
  5125. /*
  5126. * If a scan is already waiting to run, no need to add another
  5127. */
  5128. spin_lock_irqsave(&h->scan_lock, flags);
  5129. if (h->scan_waiting) {
  5130. spin_unlock_irqrestore(&h->scan_lock, flags);
  5131. return;
  5132. }
  5133. spin_unlock_irqrestore(&h->scan_lock, flags);
  5134. /* wait until any scan already in progress is finished. */
  5135. while (1) {
  5136. spin_lock_irqsave(&h->scan_lock, flags);
  5137. if (h->scan_finished)
  5138. break;
  5139. h->scan_waiting = 1;
  5140. spin_unlock_irqrestore(&h->scan_lock, flags);
  5141. wait_event(h->scan_wait_queue, h->scan_finished);
  5142. /* Note: We don't need to worry about a race between this
  5143. * thread and driver unload because the midlayer will
  5144. * have incremented the reference count, so unload won't
  5145. * happen if we're in here.
  5146. */
  5147. }
  5148. h->scan_finished = 0; /* mark scan as in progress */
  5149. h->scan_waiting = 0;
  5150. spin_unlock_irqrestore(&h->scan_lock, flags);
  5151. if (unlikely(lockup_detected(h)))
  5152. return hpsa_scan_complete(h);
  5153. /*
  5154. * Do the scan after a reset completion
  5155. */
  5156. spin_lock_irqsave(&h->reset_lock, flags);
  5157. if (h->reset_in_progress) {
  5158. h->drv_req_rescan = 1;
  5159. spin_unlock_irqrestore(&h->reset_lock, flags);
  5160. hpsa_scan_complete(h);
  5161. return;
  5162. }
  5163. spin_unlock_irqrestore(&h->reset_lock, flags);
  5164. hpsa_update_scsi_devices(h);
  5165. hpsa_scan_complete(h);
  5166. }
  5167. static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
  5168. {
  5169. struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
  5170. if (!logical_drive)
  5171. return -ENODEV;
  5172. if (qdepth < 1)
  5173. qdepth = 1;
  5174. else if (qdepth > logical_drive->queue_depth)
  5175. qdepth = logical_drive->queue_depth;
  5176. return scsi_change_queue_depth(sdev, qdepth);
  5177. }
  5178. static int hpsa_scan_finished(struct Scsi_Host *sh,
  5179. unsigned long elapsed_time)
  5180. {
  5181. struct ctlr_info *h = shost_to_hba(sh);
  5182. unsigned long flags;
  5183. int finished;
  5184. spin_lock_irqsave(&h->scan_lock, flags);
  5185. finished = h->scan_finished;
  5186. spin_unlock_irqrestore(&h->scan_lock, flags);
  5187. return finished;
  5188. }
  5189. static int hpsa_scsi_host_alloc(struct ctlr_info *h)
  5190. {
  5191. struct Scsi_Host *sh;
  5192. sh = scsi_host_alloc(&hpsa_driver_template, sizeof(struct ctlr_info *));
  5193. if (sh == NULL) {
  5194. dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
  5195. return -ENOMEM;
  5196. }
  5197. sh->io_port = 0;
  5198. sh->n_io_port = 0;
  5199. sh->this_id = -1;
  5200. sh->max_channel = 3;
  5201. sh->max_cmd_len = MAX_COMMAND_SIZE;
  5202. sh->max_lun = HPSA_MAX_LUN;
  5203. sh->max_id = HPSA_MAX_LUN;
  5204. sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
  5205. sh->cmd_per_lun = sh->can_queue;
  5206. sh->sg_tablesize = h->maxsgentries;
  5207. sh->transportt = hpsa_sas_transport_template;
  5208. sh->hostdata[0] = (unsigned long) h;
  5209. sh->irq = pci_irq_vector(h->pdev, 0);
  5210. sh->unique_id = sh->irq;
  5211. h->scsi_host = sh;
  5212. return 0;
  5213. }
  5214. static int hpsa_scsi_add_host(struct ctlr_info *h)
  5215. {
  5216. int rv;
  5217. rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
  5218. if (rv) {
  5219. dev_err(&h->pdev->dev, "scsi_add_host failed\n");
  5220. return rv;
  5221. }
  5222. scsi_scan_host(h->scsi_host);
  5223. return 0;
  5224. }
  5225. /*
  5226. * The block layer has already gone to the trouble of picking out a unique,
  5227. * small-integer tag for this request. We use an offset from that value as
  5228. * an index to select our command block. (The offset allows us to reserve the
  5229. * low-numbered entries for our own uses.)
  5230. */
  5231. static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
  5232. {
  5233. int idx = scsi_cmd_to_rq(scmd)->tag;
  5234. if (idx < 0)
  5235. return idx;
  5236. /* Offset to leave space for internal cmds. */
  5237. return idx += HPSA_NRESERVED_CMDS;
  5238. }
  5239. /*
  5240. * Send a TEST_UNIT_READY command to the specified LUN using the specified
  5241. * reply queue; returns zero if the unit is ready, and non-zero otherwise.
  5242. */
  5243. static int hpsa_send_test_unit_ready(struct ctlr_info *h,
  5244. struct CommandList *c, unsigned char lunaddr[],
  5245. int reply_queue)
  5246. {
  5247. int rc;
  5248. /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
  5249. (void) fill_cmd(c, TEST_UNIT_READY, h,
  5250. NULL, 0, 0, lunaddr, TYPE_CMD);
  5251. rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
  5252. if (rc)
  5253. return rc;
  5254. /* no unmap needed here because no data xfer. */
  5255. /* Check if the unit is already ready. */
  5256. if (c->err_info->CommandStatus == CMD_SUCCESS)
  5257. return 0;
  5258. /*
  5259. * The first command sent after reset will receive "unit attention" to
  5260. * indicate that the LUN has been reset...this is actually what we're
  5261. * looking for (but, success is good too).
  5262. */
  5263. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  5264. c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
  5265. (c->err_info->SenseInfo[2] == NO_SENSE ||
  5266. c->err_info->SenseInfo[2] == UNIT_ATTENTION))
  5267. return 0;
  5268. return 1;
  5269. }
  5270. /*
  5271. * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
  5272. * returns zero when the unit is ready, and non-zero when giving up.
  5273. */
  5274. static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
  5275. struct CommandList *c,
  5276. unsigned char lunaddr[], int reply_queue)
  5277. {
  5278. int rc;
  5279. int count = 0;
  5280. int waittime = 1; /* seconds */
  5281. /* Send test unit ready until device ready, or give up. */
  5282. for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
  5283. /*
  5284. * Wait for a bit. do this first, because if we send
  5285. * the TUR right away, the reset will just abort it.
  5286. */
  5287. msleep(1000 * waittime);
  5288. rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
  5289. if (!rc)
  5290. break;
  5291. /* Increase wait time with each try, up to a point. */
  5292. if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
  5293. waittime *= 2;
  5294. dev_warn(&h->pdev->dev,
  5295. "waiting %d secs for device to become ready.\n",
  5296. waittime);
  5297. }
  5298. return rc;
  5299. }
  5300. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  5301. unsigned char lunaddr[],
  5302. int reply_queue)
  5303. {
  5304. int first_queue;
  5305. int last_queue;
  5306. int rq;
  5307. int rc = 0;
  5308. struct CommandList *c;
  5309. c = cmd_alloc(h);
  5310. /*
  5311. * If no specific reply queue was requested, then send the TUR
  5312. * repeatedly, requesting a reply on each reply queue; otherwise execute
  5313. * the loop exactly once using only the specified queue.
  5314. */
  5315. if (reply_queue == DEFAULT_REPLY_QUEUE) {
  5316. first_queue = 0;
  5317. last_queue = h->nreply_queues - 1;
  5318. } else {
  5319. first_queue = reply_queue;
  5320. last_queue = reply_queue;
  5321. }
  5322. for (rq = first_queue; rq <= last_queue; rq++) {
  5323. rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
  5324. if (rc)
  5325. break;
  5326. }
  5327. if (rc)
  5328. dev_warn(&h->pdev->dev, "giving up on device.\n");
  5329. else
  5330. dev_warn(&h->pdev->dev, "device is ready.\n");
  5331. cmd_free(h, c);
  5332. return rc;
  5333. }
  5334. /* Need at least one of these error handlers to keep ../scsi/hosts.c from
  5335. * complaining. Doing a host- or bus-reset can't do anything good here.
  5336. */
  5337. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
  5338. {
  5339. int rc = SUCCESS;
  5340. int i;
  5341. struct ctlr_info *h;
  5342. struct hpsa_scsi_dev_t *dev = NULL;
  5343. u8 reset_type;
  5344. char msg[48];
  5345. unsigned long flags;
  5346. /* find the controller to which the command to be aborted was sent */
  5347. h = sdev_to_hba(scsicmd->device);
  5348. if (h == NULL) /* paranoia */
  5349. return FAILED;
  5350. spin_lock_irqsave(&h->reset_lock, flags);
  5351. h->reset_in_progress = 1;
  5352. spin_unlock_irqrestore(&h->reset_lock, flags);
  5353. if (lockup_detected(h)) {
  5354. rc = FAILED;
  5355. goto return_reset_status;
  5356. }
  5357. dev = scsicmd->device->hostdata;
  5358. if (!dev) {
  5359. dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
  5360. rc = FAILED;
  5361. goto return_reset_status;
  5362. }
  5363. if (dev->devtype == TYPE_ENCLOSURE) {
  5364. rc = SUCCESS;
  5365. goto return_reset_status;
  5366. }
  5367. /* if controller locked up, we can guarantee command won't complete */
  5368. if (lockup_detected(h)) {
  5369. snprintf(msg, sizeof(msg),
  5370. "cmd %d RESET FAILED, lockup detected",
  5371. hpsa_get_cmd_index(scsicmd));
  5372. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5373. rc = FAILED;
  5374. goto return_reset_status;
  5375. }
  5376. /* this reset request might be the result of a lockup; check */
  5377. if (detect_controller_lockup(h)) {
  5378. snprintf(msg, sizeof(msg),
  5379. "cmd %d RESET FAILED, new lockup detected",
  5380. hpsa_get_cmd_index(scsicmd));
  5381. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5382. rc = FAILED;
  5383. goto return_reset_status;
  5384. }
  5385. /* Do not attempt on controller */
  5386. if (is_hba_lunid(dev->scsi3addr)) {
  5387. rc = SUCCESS;
  5388. goto return_reset_status;
  5389. }
  5390. if (is_logical_dev_addr_mode(dev->scsi3addr))
  5391. reset_type = HPSA_DEVICE_RESET_MSG;
  5392. else
  5393. reset_type = HPSA_PHYS_TARGET_RESET;
  5394. sprintf(msg, "resetting %s",
  5395. reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
  5396. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5397. /*
  5398. * wait to see if any commands will complete before sending reset
  5399. */
  5400. dev->in_reset = true; /* block any new cmds from OS for this device */
  5401. for (i = 0; i < 10; i++) {
  5402. if (atomic_read(&dev->commands_outstanding) > 0)
  5403. msleep(1000);
  5404. else
  5405. break;
  5406. }
  5407. /* send a reset to the SCSI LUN which the command was sent to */
  5408. rc = hpsa_do_reset(h, dev, reset_type, DEFAULT_REPLY_QUEUE);
  5409. if (rc == 0)
  5410. rc = SUCCESS;
  5411. else
  5412. rc = FAILED;
  5413. sprintf(msg, "reset %s %s",
  5414. reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
  5415. rc == SUCCESS ? "completed successfully" : "failed");
  5416. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5417. return_reset_status:
  5418. spin_lock_irqsave(&h->reset_lock, flags);
  5419. h->reset_in_progress = 0;
  5420. if (dev)
  5421. dev->in_reset = false;
  5422. spin_unlock_irqrestore(&h->reset_lock, flags);
  5423. return rc;
  5424. }
  5425. /*
  5426. * For operations with an associated SCSI command, a command block is allocated
  5427. * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
  5428. * block request tag as an index into a table of entries. cmd_tagged_free() is
  5429. * the complement, although cmd_free() may be called instead.
  5430. * This function is only called for new requests from queue_command.
  5431. */
  5432. static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
  5433. struct scsi_cmnd *scmd)
  5434. {
  5435. int idx = hpsa_get_cmd_index(scmd);
  5436. struct CommandList *c = h->cmd_pool + idx;
  5437. if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
  5438. dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
  5439. idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
  5440. /* The index value comes from the block layer, so if it's out of
  5441. * bounds, it's probably not our bug.
  5442. */
  5443. BUG();
  5444. }
  5445. if (unlikely(!hpsa_is_cmd_idle(c))) {
  5446. /*
  5447. * We expect that the SCSI layer will hand us a unique tag
  5448. * value. Thus, there should never be a collision here between
  5449. * two requests...because if the selected command isn't idle
  5450. * then someone is going to be very disappointed.
  5451. */
  5452. if (idx != h->last_collision_tag) { /* Print once per tag */
  5453. dev_warn(&h->pdev->dev,
  5454. "%s: tag collision (tag=%d)\n", __func__, idx);
  5455. if (scmd)
  5456. scsi_print_command(scmd);
  5457. h->last_collision_tag = idx;
  5458. }
  5459. return NULL;
  5460. }
  5461. atomic_inc(&c->refcount);
  5462. hpsa_cmd_partial_init(h, idx, c);
  5463. /*
  5464. * This is a new command obtained from queue_command so
  5465. * there have not been any driver initiated retry attempts.
  5466. */
  5467. c->retry_pending = false;
  5468. return c;
  5469. }
  5470. static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
  5471. {
  5472. /*
  5473. * Release our reference to the block. We don't need to do anything
  5474. * else to free it, because it is accessed by index.
  5475. */
  5476. (void)atomic_dec(&c->refcount);
  5477. }
  5478. /*
  5479. * For operations that cannot sleep, a command block is allocated at init,
  5480. * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
  5481. * which ones are free or in use. Lock must be held when calling this.
  5482. * cmd_free() is the complement.
  5483. * This function never gives up and returns NULL. If it hangs,
  5484. * another thread must call cmd_free() to free some tags.
  5485. */
  5486. static struct CommandList *cmd_alloc(struct ctlr_info *h)
  5487. {
  5488. struct CommandList *c;
  5489. int refcount, i;
  5490. int offset = 0;
  5491. /*
  5492. * There is some *extremely* small but non-zero chance that that
  5493. * multiple threads could get in here, and one thread could
  5494. * be scanning through the list of bits looking for a free
  5495. * one, but the free ones are always behind him, and other
  5496. * threads sneak in behind him and eat them before he can
  5497. * get to them, so that while there is always a free one, a
  5498. * very unlucky thread might be starved anyway, never able to
  5499. * beat the other threads. In reality, this happens so
  5500. * infrequently as to be indistinguishable from never.
  5501. *
  5502. * Note that we start allocating commands before the SCSI host structure
  5503. * is initialized. Since the search starts at bit zero, this
  5504. * all works, since we have at least one command structure available;
  5505. * however, it means that the structures with the low indexes have to be
  5506. * reserved for driver-initiated requests, while requests from the block
  5507. * layer will use the higher indexes.
  5508. */
  5509. for (;;) {
  5510. i = find_next_zero_bit(h->cmd_pool_bits,
  5511. HPSA_NRESERVED_CMDS,
  5512. offset);
  5513. if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
  5514. offset = 0;
  5515. continue;
  5516. }
  5517. c = h->cmd_pool + i;
  5518. refcount = atomic_inc_return(&c->refcount);
  5519. if (unlikely(refcount > 1)) {
  5520. cmd_free(h, c); /* already in use */
  5521. offset = (i + 1) % HPSA_NRESERVED_CMDS;
  5522. continue;
  5523. }
  5524. set_bit(i, h->cmd_pool_bits);
  5525. break; /* it's ours now. */
  5526. }
  5527. hpsa_cmd_partial_init(h, i, c);
  5528. c->device = NULL;
  5529. /*
  5530. * cmd_alloc is for "internal" commands and they are never
  5531. * retried.
  5532. */
  5533. c->retry_pending = false;
  5534. return c;
  5535. }
  5536. /*
  5537. * This is the complementary operation to cmd_alloc(). Note, however, in some
  5538. * corner cases it may also be used to free blocks allocated by
  5539. * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
  5540. * the clear-bit is harmless.
  5541. */
  5542. static void cmd_free(struct ctlr_info *h, struct CommandList *c)
  5543. {
  5544. if (atomic_dec_and_test(&c->refcount)) {
  5545. int i;
  5546. i = c - h->cmd_pool;
  5547. clear_bit(i, h->cmd_pool_bits);
  5548. }
  5549. }
  5550. #ifdef CONFIG_COMPAT
  5551. static int hpsa_ioctl32_passthru(struct scsi_device *dev, unsigned int cmd,
  5552. void __user *arg)
  5553. {
  5554. struct ctlr_info *h = sdev_to_hba(dev);
  5555. IOCTL32_Command_struct __user *arg32 = arg;
  5556. IOCTL_Command_struct arg64;
  5557. int err;
  5558. u32 cp;
  5559. if (!arg)
  5560. return -EINVAL;
  5561. memset(&arg64, 0, sizeof(arg64));
  5562. if (copy_from_user(&arg64, arg32, offsetof(IOCTL_Command_struct, buf)))
  5563. return -EFAULT;
  5564. if (get_user(cp, &arg32->buf))
  5565. return -EFAULT;
  5566. arg64.buf = compat_ptr(cp);
  5567. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5568. return -EAGAIN;
  5569. err = hpsa_passthru_ioctl(h, &arg64);
  5570. atomic_inc(&h->passthru_cmds_avail);
  5571. if (err)
  5572. return err;
  5573. if (copy_to_user(&arg32->error_info, &arg64.error_info,
  5574. sizeof(arg32->error_info)))
  5575. return -EFAULT;
  5576. return 0;
  5577. }
  5578. static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
  5579. unsigned int cmd, void __user *arg)
  5580. {
  5581. struct ctlr_info *h = sdev_to_hba(dev);
  5582. BIG_IOCTL32_Command_struct __user *arg32 = arg;
  5583. BIG_IOCTL_Command_struct arg64;
  5584. int err;
  5585. u32 cp;
  5586. if (!arg)
  5587. return -EINVAL;
  5588. memset(&arg64, 0, sizeof(arg64));
  5589. if (copy_from_user(&arg64, arg32,
  5590. offsetof(BIG_IOCTL32_Command_struct, buf)))
  5591. return -EFAULT;
  5592. if (get_user(cp, &arg32->buf))
  5593. return -EFAULT;
  5594. arg64.buf = compat_ptr(cp);
  5595. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5596. return -EAGAIN;
  5597. err = hpsa_big_passthru_ioctl(h, &arg64);
  5598. atomic_inc(&h->passthru_cmds_avail);
  5599. if (err)
  5600. return err;
  5601. if (copy_to_user(&arg32->error_info, &arg64.error_info,
  5602. sizeof(arg32->error_info)))
  5603. return -EFAULT;
  5604. return 0;
  5605. }
  5606. static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd,
  5607. void __user *arg)
  5608. {
  5609. switch (cmd) {
  5610. case CCISS_GETPCIINFO:
  5611. case CCISS_GETINTINFO:
  5612. case CCISS_SETINTINFO:
  5613. case CCISS_GETNODENAME:
  5614. case CCISS_SETNODENAME:
  5615. case CCISS_GETHEARTBEAT:
  5616. case CCISS_GETBUSTYPES:
  5617. case CCISS_GETFIRMVER:
  5618. case CCISS_GETDRIVVER:
  5619. case CCISS_REVALIDVOLS:
  5620. case CCISS_DEREGDISK:
  5621. case CCISS_REGNEWDISK:
  5622. case CCISS_REGNEWD:
  5623. case CCISS_RESCANDISK:
  5624. case CCISS_GETLUNINFO:
  5625. return hpsa_ioctl(dev, cmd, arg);
  5626. case CCISS_PASSTHRU32:
  5627. return hpsa_ioctl32_passthru(dev, cmd, arg);
  5628. case CCISS_BIG_PASSTHRU32:
  5629. return hpsa_ioctl32_big_passthru(dev, cmd, arg);
  5630. default:
  5631. return -ENOIOCTLCMD;
  5632. }
  5633. }
  5634. #endif
  5635. static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
  5636. {
  5637. struct hpsa_pci_info pciinfo;
  5638. if (!argp)
  5639. return -EINVAL;
  5640. pciinfo.domain = pci_domain_nr(h->pdev->bus);
  5641. pciinfo.bus = h->pdev->bus->number;
  5642. pciinfo.dev_fn = h->pdev->devfn;
  5643. pciinfo.board_id = h->board_id;
  5644. if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
  5645. return -EFAULT;
  5646. return 0;
  5647. }
  5648. static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
  5649. {
  5650. DriverVer_type DriverVer;
  5651. unsigned char vmaj, vmin, vsubmin;
  5652. int rc;
  5653. rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
  5654. &vmaj, &vmin, &vsubmin);
  5655. if (rc != 3) {
  5656. dev_info(&h->pdev->dev, "driver version string '%s' "
  5657. "unrecognized.", HPSA_DRIVER_VERSION);
  5658. vmaj = 0;
  5659. vmin = 0;
  5660. vsubmin = 0;
  5661. }
  5662. DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
  5663. if (!argp)
  5664. return -EINVAL;
  5665. if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
  5666. return -EFAULT;
  5667. return 0;
  5668. }
  5669. static int hpsa_passthru_ioctl(struct ctlr_info *h,
  5670. IOCTL_Command_struct *iocommand)
  5671. {
  5672. struct CommandList *c;
  5673. char *buff = NULL;
  5674. u64 temp64;
  5675. int rc = 0;
  5676. if (!capable(CAP_SYS_RAWIO))
  5677. return -EPERM;
  5678. if ((iocommand->buf_size < 1) &&
  5679. (iocommand->Request.Type.Direction != XFER_NONE)) {
  5680. return -EINVAL;
  5681. }
  5682. if (iocommand->buf_size > 0) {
  5683. if (iocommand->Request.Type.Direction & XFER_WRITE) {
  5684. buff = memdup_user(iocommand->buf, iocommand->buf_size);
  5685. if (IS_ERR(buff))
  5686. return PTR_ERR(buff);
  5687. } else {
  5688. buff = kzalloc(iocommand->buf_size, GFP_KERNEL);
  5689. if (!buff)
  5690. return -ENOMEM;
  5691. }
  5692. }
  5693. c = cmd_alloc(h);
  5694. /* Fill in the command type */
  5695. c->cmd_type = CMD_IOCTL_PEND;
  5696. c->scsi_cmd = SCSI_CMD_BUSY;
  5697. /* Fill in Command Header */
  5698. c->Header.ReplyQueue = 0; /* unused in simple mode */
  5699. if (iocommand->buf_size > 0) { /* buffer to fill */
  5700. c->Header.SGList = 1;
  5701. c->Header.SGTotal = cpu_to_le16(1);
  5702. } else { /* no buffers to fill */
  5703. c->Header.SGList = 0;
  5704. c->Header.SGTotal = cpu_to_le16(0);
  5705. }
  5706. memcpy(&c->Header.LUN, &iocommand->LUN_info, sizeof(c->Header.LUN));
  5707. /* Fill in Request block */
  5708. memcpy(&c->Request, &iocommand->Request,
  5709. sizeof(c->Request));
  5710. /* Fill in the scatter gather information */
  5711. if (iocommand->buf_size > 0) {
  5712. temp64 = dma_map_single(&h->pdev->dev, buff,
  5713. iocommand->buf_size, DMA_BIDIRECTIONAL);
  5714. if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
  5715. c->SG[0].Addr = cpu_to_le64(0);
  5716. c->SG[0].Len = cpu_to_le32(0);
  5717. rc = -ENOMEM;
  5718. goto out;
  5719. }
  5720. c->SG[0].Addr = cpu_to_le64(temp64);
  5721. c->SG[0].Len = cpu_to_le32(iocommand->buf_size);
  5722. c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
  5723. }
  5724. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  5725. NO_TIMEOUT);
  5726. if (iocommand->buf_size > 0)
  5727. hpsa_pci_unmap(h->pdev, c, 1, DMA_BIDIRECTIONAL);
  5728. check_ioctl_unit_attention(h, c);
  5729. if (rc) {
  5730. rc = -EIO;
  5731. goto out;
  5732. }
  5733. /* Copy the error information out */
  5734. memcpy(&iocommand->error_info, c->err_info,
  5735. sizeof(iocommand->error_info));
  5736. if ((iocommand->Request.Type.Direction & XFER_READ) &&
  5737. iocommand->buf_size > 0) {
  5738. /* Copy the data out of the buffer we created */
  5739. if (copy_to_user(iocommand->buf, buff, iocommand->buf_size)) {
  5740. rc = -EFAULT;
  5741. goto out;
  5742. }
  5743. }
  5744. out:
  5745. cmd_free(h, c);
  5746. kfree(buff);
  5747. return rc;
  5748. }
  5749. static int hpsa_big_passthru_ioctl(struct ctlr_info *h,
  5750. BIG_IOCTL_Command_struct *ioc)
  5751. {
  5752. struct CommandList *c;
  5753. unsigned char **buff = NULL;
  5754. int *buff_size = NULL;
  5755. u64 temp64;
  5756. BYTE sg_used = 0;
  5757. int status = 0;
  5758. u32 left;
  5759. u32 sz;
  5760. BYTE __user *data_ptr;
  5761. if (!capable(CAP_SYS_RAWIO))
  5762. return -EPERM;
  5763. if ((ioc->buf_size < 1) &&
  5764. (ioc->Request.Type.Direction != XFER_NONE))
  5765. return -EINVAL;
  5766. /* Check kmalloc limits using all SGs */
  5767. if (ioc->malloc_size > MAX_KMALLOC_SIZE)
  5768. return -EINVAL;
  5769. if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD)
  5770. return -EINVAL;
  5771. buff = kcalloc(SG_ENTRIES_IN_CMD, sizeof(char *), GFP_KERNEL);
  5772. if (!buff) {
  5773. status = -ENOMEM;
  5774. goto cleanup1;
  5775. }
  5776. buff_size = kmalloc_objs(int, SG_ENTRIES_IN_CMD);
  5777. if (!buff_size) {
  5778. status = -ENOMEM;
  5779. goto cleanup1;
  5780. }
  5781. left = ioc->buf_size;
  5782. data_ptr = ioc->buf;
  5783. while (left) {
  5784. sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
  5785. buff_size[sg_used] = sz;
  5786. if (ioc->Request.Type.Direction & XFER_WRITE) {
  5787. buff[sg_used] = memdup_user(data_ptr, sz);
  5788. if (IS_ERR(buff[sg_used])) {
  5789. status = PTR_ERR(buff[sg_used]);
  5790. goto cleanup1;
  5791. }
  5792. } else {
  5793. buff[sg_used] = kzalloc(sz, GFP_KERNEL);
  5794. if (!buff[sg_used]) {
  5795. status = -ENOMEM;
  5796. goto cleanup1;
  5797. }
  5798. }
  5799. left -= sz;
  5800. data_ptr += sz;
  5801. sg_used++;
  5802. }
  5803. c = cmd_alloc(h);
  5804. c->cmd_type = CMD_IOCTL_PEND;
  5805. c->scsi_cmd = SCSI_CMD_BUSY;
  5806. c->Header.ReplyQueue = 0;
  5807. c->Header.SGList = (u8) sg_used;
  5808. c->Header.SGTotal = cpu_to_le16(sg_used);
  5809. memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
  5810. memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
  5811. if (ioc->buf_size > 0) {
  5812. int i;
  5813. for (i = 0; i < sg_used; i++) {
  5814. temp64 = dma_map_single(&h->pdev->dev, buff[i],
  5815. buff_size[i], DMA_BIDIRECTIONAL);
  5816. if (dma_mapping_error(&h->pdev->dev,
  5817. (dma_addr_t) temp64)) {
  5818. c->SG[i].Addr = cpu_to_le64(0);
  5819. c->SG[i].Len = cpu_to_le32(0);
  5820. hpsa_pci_unmap(h->pdev, c, i,
  5821. DMA_BIDIRECTIONAL);
  5822. status = -ENOMEM;
  5823. goto cleanup0;
  5824. }
  5825. c->SG[i].Addr = cpu_to_le64(temp64);
  5826. c->SG[i].Len = cpu_to_le32(buff_size[i]);
  5827. c->SG[i].Ext = cpu_to_le32(0);
  5828. }
  5829. c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
  5830. }
  5831. status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  5832. NO_TIMEOUT);
  5833. if (sg_used)
  5834. hpsa_pci_unmap(h->pdev, c, sg_used, DMA_BIDIRECTIONAL);
  5835. check_ioctl_unit_attention(h, c);
  5836. if (status) {
  5837. status = -EIO;
  5838. goto cleanup0;
  5839. }
  5840. /* Copy the error information out */
  5841. memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
  5842. if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
  5843. int i;
  5844. /* Copy the data out of the buffer we created */
  5845. BYTE __user *ptr = ioc->buf;
  5846. for (i = 0; i < sg_used; i++) {
  5847. if (copy_to_user(ptr, buff[i], buff_size[i])) {
  5848. status = -EFAULT;
  5849. goto cleanup0;
  5850. }
  5851. ptr += buff_size[i];
  5852. }
  5853. }
  5854. status = 0;
  5855. cleanup0:
  5856. cmd_free(h, c);
  5857. cleanup1:
  5858. if (buff) {
  5859. int i;
  5860. for (i = 0; i < sg_used; i++)
  5861. kfree(buff[i]);
  5862. kfree(buff);
  5863. }
  5864. kfree(buff_size);
  5865. return status;
  5866. }
  5867. static void check_ioctl_unit_attention(struct ctlr_info *h,
  5868. struct CommandList *c)
  5869. {
  5870. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  5871. c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
  5872. (void) check_for_unit_attention(h, c);
  5873. }
  5874. /*
  5875. * ioctl
  5876. */
  5877. static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd,
  5878. void __user *argp)
  5879. {
  5880. struct ctlr_info *h = sdev_to_hba(dev);
  5881. int rc;
  5882. switch (cmd) {
  5883. case CCISS_DEREGDISK:
  5884. case CCISS_REGNEWDISK:
  5885. case CCISS_REGNEWD:
  5886. hpsa_scan_start(h->scsi_host);
  5887. return 0;
  5888. case CCISS_GETPCIINFO:
  5889. return hpsa_getpciinfo_ioctl(h, argp);
  5890. case CCISS_GETDRIVVER:
  5891. return hpsa_getdrivver_ioctl(h, argp);
  5892. case CCISS_PASSTHRU: {
  5893. IOCTL_Command_struct iocommand;
  5894. if (!argp)
  5895. return -EINVAL;
  5896. if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
  5897. return -EFAULT;
  5898. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5899. return -EAGAIN;
  5900. rc = hpsa_passthru_ioctl(h, &iocommand);
  5901. atomic_inc(&h->passthru_cmds_avail);
  5902. if (!rc && copy_to_user(argp, &iocommand, sizeof(iocommand)))
  5903. rc = -EFAULT;
  5904. return rc;
  5905. }
  5906. case CCISS_BIG_PASSTHRU: {
  5907. BIG_IOCTL_Command_struct ioc;
  5908. if (!argp)
  5909. return -EINVAL;
  5910. if (copy_from_user(&ioc, argp, sizeof(ioc)))
  5911. return -EFAULT;
  5912. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5913. return -EAGAIN;
  5914. rc = hpsa_big_passthru_ioctl(h, &ioc);
  5915. atomic_inc(&h->passthru_cmds_avail);
  5916. if (!rc && copy_to_user(argp, &ioc, sizeof(ioc)))
  5917. rc = -EFAULT;
  5918. return rc;
  5919. }
  5920. default:
  5921. return -ENOTTY;
  5922. }
  5923. }
  5924. static void hpsa_send_host_reset(struct ctlr_info *h, u8 reset_type)
  5925. {
  5926. struct CommandList *c;
  5927. c = cmd_alloc(h);
  5928. /* fill_cmd can't fail here, no data buffer to map */
  5929. (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
  5930. RAID_CTLR_LUNID, TYPE_MSG);
  5931. c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
  5932. c->waiting = NULL;
  5933. enqueue_cmd_and_start_io(h, c);
  5934. /* Don't wait for completion, the reset won't complete. Don't free
  5935. * the command either. This is the last command we will send before
  5936. * re-initializing everything, so it doesn't matter and won't leak.
  5937. */
  5938. return;
  5939. }
  5940. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  5941. void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
  5942. int cmd_type)
  5943. {
  5944. enum dma_data_direction dir = DMA_NONE;
  5945. c->cmd_type = CMD_IOCTL_PEND;
  5946. c->scsi_cmd = SCSI_CMD_BUSY;
  5947. c->Header.ReplyQueue = 0;
  5948. if (buff != NULL && size > 0) {
  5949. c->Header.SGList = 1;
  5950. c->Header.SGTotal = cpu_to_le16(1);
  5951. } else {
  5952. c->Header.SGList = 0;
  5953. c->Header.SGTotal = cpu_to_le16(0);
  5954. }
  5955. memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
  5956. if (cmd_type == TYPE_CMD) {
  5957. switch (cmd) {
  5958. case HPSA_INQUIRY:
  5959. /* are we trying to read a vital product page */
  5960. if (page_code & VPD_PAGE) {
  5961. c->Request.CDB[1] = 0x01;
  5962. c->Request.CDB[2] = (page_code & 0xff);
  5963. }
  5964. c->Request.CDBLen = 6;
  5965. c->Request.type_attr_dir =
  5966. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5967. c->Request.Timeout = 0;
  5968. c->Request.CDB[0] = HPSA_INQUIRY;
  5969. c->Request.CDB[4] = size & 0xFF;
  5970. break;
  5971. case RECEIVE_DIAGNOSTIC:
  5972. c->Request.CDBLen = 6;
  5973. c->Request.type_attr_dir =
  5974. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5975. c->Request.Timeout = 0;
  5976. c->Request.CDB[0] = cmd;
  5977. c->Request.CDB[1] = 1;
  5978. c->Request.CDB[2] = 1;
  5979. c->Request.CDB[3] = (size >> 8) & 0xFF;
  5980. c->Request.CDB[4] = size & 0xFF;
  5981. break;
  5982. case HPSA_REPORT_LOG:
  5983. case HPSA_REPORT_PHYS:
  5984. /* Talking to controller so It's a physical command
  5985. mode = 00 target = 0. Nothing to write.
  5986. */
  5987. c->Request.CDBLen = 12;
  5988. c->Request.type_attr_dir =
  5989. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5990. c->Request.Timeout = 0;
  5991. c->Request.CDB[0] = cmd;
  5992. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  5993. c->Request.CDB[7] = (size >> 16) & 0xFF;
  5994. c->Request.CDB[8] = (size >> 8) & 0xFF;
  5995. c->Request.CDB[9] = size & 0xFF;
  5996. break;
  5997. case BMIC_SENSE_DIAG_OPTIONS:
  5998. c->Request.CDBLen = 16;
  5999. c->Request.type_attr_dir =
  6000. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6001. c->Request.Timeout = 0;
  6002. /* Spec says this should be BMIC_WRITE */
  6003. c->Request.CDB[0] = BMIC_READ;
  6004. c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
  6005. break;
  6006. case BMIC_SET_DIAG_OPTIONS:
  6007. c->Request.CDBLen = 16;
  6008. c->Request.type_attr_dir =
  6009. TYPE_ATTR_DIR(cmd_type,
  6010. ATTR_SIMPLE, XFER_WRITE);
  6011. c->Request.Timeout = 0;
  6012. c->Request.CDB[0] = BMIC_WRITE;
  6013. c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
  6014. break;
  6015. case HPSA_CACHE_FLUSH:
  6016. c->Request.CDBLen = 12;
  6017. c->Request.type_attr_dir =
  6018. TYPE_ATTR_DIR(cmd_type,
  6019. ATTR_SIMPLE, XFER_WRITE);
  6020. c->Request.Timeout = 0;
  6021. c->Request.CDB[0] = BMIC_WRITE;
  6022. c->Request.CDB[6] = BMIC_CACHE_FLUSH;
  6023. c->Request.CDB[7] = (size >> 8) & 0xFF;
  6024. c->Request.CDB[8] = size & 0xFF;
  6025. break;
  6026. case TEST_UNIT_READY:
  6027. c->Request.CDBLen = 6;
  6028. c->Request.type_attr_dir =
  6029. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6030. c->Request.Timeout = 0;
  6031. break;
  6032. case HPSA_GET_RAID_MAP:
  6033. c->Request.CDBLen = 12;
  6034. c->Request.type_attr_dir =
  6035. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6036. c->Request.Timeout = 0;
  6037. c->Request.CDB[0] = HPSA_CISS_READ;
  6038. c->Request.CDB[1] = cmd;
  6039. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  6040. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6041. c->Request.CDB[8] = (size >> 8) & 0xFF;
  6042. c->Request.CDB[9] = size & 0xFF;
  6043. break;
  6044. case BMIC_SENSE_CONTROLLER_PARAMETERS:
  6045. c->Request.CDBLen = 10;
  6046. c->Request.type_attr_dir =
  6047. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6048. c->Request.Timeout = 0;
  6049. c->Request.CDB[0] = BMIC_READ;
  6050. c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
  6051. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6052. c->Request.CDB[8] = (size >> 8) & 0xFF;
  6053. break;
  6054. case BMIC_IDENTIFY_PHYSICAL_DEVICE:
  6055. c->Request.CDBLen = 10;
  6056. c->Request.type_attr_dir =
  6057. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6058. c->Request.Timeout = 0;
  6059. c->Request.CDB[0] = BMIC_READ;
  6060. c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
  6061. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6062. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6063. break;
  6064. case BMIC_SENSE_SUBSYSTEM_INFORMATION:
  6065. c->Request.CDBLen = 10;
  6066. c->Request.type_attr_dir =
  6067. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6068. c->Request.Timeout = 0;
  6069. c->Request.CDB[0] = BMIC_READ;
  6070. c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
  6071. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6072. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6073. break;
  6074. case BMIC_SENSE_STORAGE_BOX_PARAMS:
  6075. c->Request.CDBLen = 10;
  6076. c->Request.type_attr_dir =
  6077. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6078. c->Request.Timeout = 0;
  6079. c->Request.CDB[0] = BMIC_READ;
  6080. c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS;
  6081. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6082. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6083. break;
  6084. case BMIC_IDENTIFY_CONTROLLER:
  6085. c->Request.CDBLen = 10;
  6086. c->Request.type_attr_dir =
  6087. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6088. c->Request.Timeout = 0;
  6089. c->Request.CDB[0] = BMIC_READ;
  6090. c->Request.CDB[1] = 0;
  6091. c->Request.CDB[2] = 0;
  6092. c->Request.CDB[3] = 0;
  6093. c->Request.CDB[4] = 0;
  6094. c->Request.CDB[5] = 0;
  6095. c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
  6096. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6097. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6098. c->Request.CDB[9] = 0;
  6099. break;
  6100. default:
  6101. dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
  6102. BUG();
  6103. }
  6104. } else if (cmd_type == TYPE_MSG) {
  6105. switch (cmd) {
  6106. case HPSA_PHYS_TARGET_RESET:
  6107. c->Request.CDBLen = 16;
  6108. c->Request.type_attr_dir =
  6109. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6110. c->Request.Timeout = 0; /* Don't time out */
  6111. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  6112. c->Request.CDB[0] = HPSA_RESET;
  6113. c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
  6114. /* Physical target reset needs no control bytes 4-7*/
  6115. c->Request.CDB[4] = 0x00;
  6116. c->Request.CDB[5] = 0x00;
  6117. c->Request.CDB[6] = 0x00;
  6118. c->Request.CDB[7] = 0x00;
  6119. break;
  6120. case HPSA_DEVICE_RESET_MSG:
  6121. c->Request.CDBLen = 16;
  6122. c->Request.type_attr_dir =
  6123. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6124. c->Request.Timeout = 0; /* Don't time out */
  6125. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  6126. c->Request.CDB[0] = cmd;
  6127. c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
  6128. /* If bytes 4-7 are zero, it means reset the */
  6129. /* LunID device */
  6130. c->Request.CDB[4] = 0x00;
  6131. c->Request.CDB[5] = 0x00;
  6132. c->Request.CDB[6] = 0x00;
  6133. c->Request.CDB[7] = 0x00;
  6134. break;
  6135. default:
  6136. dev_warn(&h->pdev->dev, "unknown message type %d\n",
  6137. cmd);
  6138. BUG();
  6139. }
  6140. } else {
  6141. dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
  6142. BUG();
  6143. }
  6144. switch (GET_DIR(c->Request.type_attr_dir)) {
  6145. case XFER_READ:
  6146. dir = DMA_FROM_DEVICE;
  6147. break;
  6148. case XFER_WRITE:
  6149. dir = DMA_TO_DEVICE;
  6150. break;
  6151. case XFER_NONE:
  6152. dir = DMA_NONE;
  6153. break;
  6154. default:
  6155. dir = DMA_BIDIRECTIONAL;
  6156. }
  6157. if (hpsa_map_one(h->pdev, c, buff, size, dir))
  6158. return -1;
  6159. return 0;
  6160. }
  6161. /*
  6162. * Map (physical) PCI mem into (virtual) kernel space
  6163. */
  6164. static void __iomem *remap_pci_mem(ulong base, ulong size)
  6165. {
  6166. ulong page_base = ((ulong) base) & PAGE_MASK;
  6167. ulong page_offs = ((ulong) base) - page_base;
  6168. void __iomem *page_remapped = ioremap(page_base,
  6169. page_offs + size);
  6170. return page_remapped ? (page_remapped + page_offs) : NULL;
  6171. }
  6172. static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
  6173. {
  6174. return h->access.command_completed(h, q);
  6175. }
  6176. static inline bool interrupt_pending(struct ctlr_info *h)
  6177. {
  6178. return h->access.intr_pending(h);
  6179. }
  6180. static inline long interrupt_not_for_us(struct ctlr_info *h)
  6181. {
  6182. return (h->access.intr_pending(h) == 0) ||
  6183. (h->interrupts_enabled == 0);
  6184. }
  6185. static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
  6186. u32 raw_tag)
  6187. {
  6188. if (unlikely(tag_index >= h->nr_cmds)) {
  6189. dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
  6190. return 1;
  6191. }
  6192. return 0;
  6193. }
  6194. static inline void finish_cmd(struct CommandList *c)
  6195. {
  6196. dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
  6197. if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
  6198. || c->cmd_type == CMD_IOACCEL2))
  6199. complete_scsi_command(c);
  6200. else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
  6201. complete(c->waiting);
  6202. }
  6203. /* process completion of an indexed ("direct lookup") command */
  6204. static inline void process_indexed_cmd(struct ctlr_info *h,
  6205. u32 raw_tag)
  6206. {
  6207. u32 tag_index;
  6208. struct CommandList *c;
  6209. tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
  6210. if (!bad_tag(h, tag_index, raw_tag)) {
  6211. c = h->cmd_pool + tag_index;
  6212. finish_cmd(c);
  6213. }
  6214. }
  6215. /* Some controllers, like p400, will give us one interrupt
  6216. * after a soft reset, even if we turned interrupts off.
  6217. * Only need to check for this in the hpsa_xxx_discard_completions
  6218. * functions.
  6219. */
  6220. static int ignore_bogus_interrupt(struct ctlr_info *h)
  6221. {
  6222. if (likely(!reset_devices))
  6223. return 0;
  6224. if (likely(h->interrupts_enabled))
  6225. return 0;
  6226. dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
  6227. "(known firmware bug.) Ignoring.\n");
  6228. return 1;
  6229. }
  6230. /*
  6231. * Convert &h->q[x] (passed to interrupt handlers) back to h.
  6232. * Relies on (h-q[x] == x) being true for x such that
  6233. * 0 <= x < MAX_REPLY_QUEUES.
  6234. */
  6235. static struct ctlr_info *queue_to_hba(u8 *queue)
  6236. {
  6237. return container_of((queue - *queue), struct ctlr_info, q[0]);
  6238. }
  6239. static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
  6240. {
  6241. struct ctlr_info *h = queue_to_hba(queue);
  6242. u8 q = *(u8 *) queue;
  6243. u32 raw_tag;
  6244. if (ignore_bogus_interrupt(h))
  6245. return IRQ_NONE;
  6246. if (interrupt_not_for_us(h))
  6247. return IRQ_NONE;
  6248. h->last_intr_timestamp = get_jiffies_64();
  6249. while (interrupt_pending(h)) {
  6250. raw_tag = get_next_completion(h, q);
  6251. while (raw_tag != FIFO_EMPTY)
  6252. raw_tag = next_command(h, q);
  6253. }
  6254. return IRQ_HANDLED;
  6255. }
  6256. static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
  6257. {
  6258. struct ctlr_info *h = queue_to_hba(queue);
  6259. u32 raw_tag;
  6260. u8 q = *(u8 *) queue;
  6261. if (ignore_bogus_interrupt(h))
  6262. return IRQ_NONE;
  6263. h->last_intr_timestamp = get_jiffies_64();
  6264. raw_tag = get_next_completion(h, q);
  6265. while (raw_tag != FIFO_EMPTY)
  6266. raw_tag = next_command(h, q);
  6267. return IRQ_HANDLED;
  6268. }
  6269. static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
  6270. {
  6271. struct ctlr_info *h = queue_to_hba((u8 *) queue);
  6272. u32 raw_tag;
  6273. u8 q = *(u8 *) queue;
  6274. if (interrupt_not_for_us(h))
  6275. return IRQ_NONE;
  6276. h->last_intr_timestamp = get_jiffies_64();
  6277. while (interrupt_pending(h)) {
  6278. raw_tag = get_next_completion(h, q);
  6279. while (raw_tag != FIFO_EMPTY) {
  6280. process_indexed_cmd(h, raw_tag);
  6281. raw_tag = next_command(h, q);
  6282. }
  6283. }
  6284. return IRQ_HANDLED;
  6285. }
  6286. static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
  6287. {
  6288. struct ctlr_info *h = queue_to_hba(queue);
  6289. u32 raw_tag;
  6290. u8 q = *(u8 *) queue;
  6291. h->last_intr_timestamp = get_jiffies_64();
  6292. raw_tag = get_next_completion(h, q);
  6293. while (raw_tag != FIFO_EMPTY) {
  6294. process_indexed_cmd(h, raw_tag);
  6295. raw_tag = next_command(h, q);
  6296. }
  6297. return IRQ_HANDLED;
  6298. }
  6299. /* Send a message CDB to the firmware. Careful, this only works
  6300. * in simple mode, not performant mode due to the tag lookup.
  6301. * We only ever use this immediately after a controller reset.
  6302. */
  6303. static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
  6304. unsigned char type)
  6305. {
  6306. struct Command {
  6307. struct CommandListHeader CommandHeader;
  6308. struct RequestBlock Request;
  6309. struct ErrDescriptor ErrorDescriptor;
  6310. };
  6311. struct Command *cmd;
  6312. static const size_t cmd_sz = sizeof(*cmd) +
  6313. sizeof(cmd->ErrorDescriptor);
  6314. dma_addr_t paddr64;
  6315. __le32 paddr32;
  6316. u32 tag;
  6317. void __iomem *vaddr;
  6318. int i, err;
  6319. vaddr = pci_ioremap_bar(pdev, 0);
  6320. if (vaddr == NULL)
  6321. return -ENOMEM;
  6322. /* The Inbound Post Queue only accepts 32-bit physical addresses for the
  6323. * CCISS commands, so they must be allocated from the lower 4GiB of
  6324. * memory.
  6325. */
  6326. err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
  6327. if (err) {
  6328. iounmap(vaddr);
  6329. return err;
  6330. }
  6331. cmd = dma_alloc_coherent(&pdev->dev, cmd_sz, &paddr64, GFP_KERNEL);
  6332. if (cmd == NULL) {
  6333. iounmap(vaddr);
  6334. return -ENOMEM;
  6335. }
  6336. /* This must fit, because of the 32-bit consistent DMA mask. Also,
  6337. * although there's no guarantee, we assume that the address is at
  6338. * least 4-byte aligned (most likely, it's page-aligned).
  6339. */
  6340. paddr32 = cpu_to_le32(paddr64);
  6341. cmd->CommandHeader.ReplyQueue = 0;
  6342. cmd->CommandHeader.SGList = 0;
  6343. cmd->CommandHeader.SGTotal = cpu_to_le16(0);
  6344. cmd->CommandHeader.tag = cpu_to_le64(paddr64);
  6345. memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
  6346. cmd->Request.CDBLen = 16;
  6347. cmd->Request.type_attr_dir =
  6348. TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
  6349. cmd->Request.Timeout = 0; /* Don't time out */
  6350. cmd->Request.CDB[0] = opcode;
  6351. cmd->Request.CDB[1] = type;
  6352. memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
  6353. cmd->ErrorDescriptor.Addr =
  6354. cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
  6355. cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
  6356. writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
  6357. for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
  6358. tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
  6359. if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
  6360. break;
  6361. msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
  6362. }
  6363. iounmap(vaddr);
  6364. /* we leak the DMA buffer here ... no choice since the controller could
  6365. * still complete the command.
  6366. */
  6367. if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
  6368. dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
  6369. opcode, type);
  6370. return -ETIMEDOUT;
  6371. }
  6372. dma_free_coherent(&pdev->dev, cmd_sz, cmd, paddr64);
  6373. if (tag & HPSA_ERROR_BIT) {
  6374. dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
  6375. opcode, type);
  6376. return -EIO;
  6377. }
  6378. dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
  6379. opcode, type);
  6380. return 0;
  6381. }
  6382. #define hpsa_noop(p) hpsa_message(p, 3, 0)
  6383. static int hpsa_controller_hard_reset(struct pci_dev *pdev,
  6384. void __iomem *vaddr, u32 use_doorbell)
  6385. {
  6386. if (use_doorbell) {
  6387. /* For everything after the P600, the PCI power state method
  6388. * of resetting the controller doesn't work, so we have this
  6389. * other way using the doorbell register.
  6390. */
  6391. dev_info(&pdev->dev, "using doorbell to reset controller\n");
  6392. writel(use_doorbell, vaddr + SA5_DOORBELL);
  6393. /* PMC hardware guys tell us we need a 10 second delay after
  6394. * doorbell reset and before any attempt to talk to the board
  6395. * at all to ensure that this actually works and doesn't fall
  6396. * over in some weird corner cases.
  6397. */
  6398. msleep(10000);
  6399. } else { /* Try to do it the PCI power state way */
  6400. /* Quoting from the Open CISS Specification: "The Power
  6401. * Management Control/Status Register (CSR) controls the power
  6402. * state of the device. The normal operating state is D0,
  6403. * CSR=00h. The software off state is D3, CSR=03h. To reset
  6404. * the controller, place the interface device in D3 then to D0,
  6405. * this causes a secondary PCI reset which will reset the
  6406. * controller." */
  6407. int rc = 0;
  6408. dev_info(&pdev->dev, "using PCI PM to reset controller\n");
  6409. /* enter the D3hot power management state */
  6410. rc = pci_set_power_state(pdev, PCI_D3hot);
  6411. if (rc)
  6412. return rc;
  6413. msleep(500);
  6414. /* enter the D0 power management state */
  6415. rc = pci_set_power_state(pdev, PCI_D0);
  6416. if (rc)
  6417. return rc;
  6418. /*
  6419. * The P600 requires a small delay when changing states.
  6420. * Otherwise we may think the board did not reset and we bail.
  6421. * This for kdump only and is particular to the P600.
  6422. */
  6423. msleep(500);
  6424. }
  6425. return 0;
  6426. }
  6427. static void init_driver_version(char *driver_version, int len)
  6428. {
  6429. strscpy_pad(driver_version, HPSA " " HPSA_DRIVER_VERSION, len);
  6430. }
  6431. static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
  6432. {
  6433. char *driver_version;
  6434. int i, size = sizeof(cfgtable->driver_version);
  6435. driver_version = kmalloc(size, GFP_KERNEL);
  6436. if (!driver_version)
  6437. return -ENOMEM;
  6438. init_driver_version(driver_version, size);
  6439. for (i = 0; i < size; i++)
  6440. writeb(driver_version[i], &cfgtable->driver_version[i]);
  6441. kfree(driver_version);
  6442. return 0;
  6443. }
  6444. static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
  6445. unsigned char *driver_ver)
  6446. {
  6447. int i;
  6448. for (i = 0; i < sizeof(cfgtable->driver_version); i++)
  6449. driver_ver[i] = readb(&cfgtable->driver_version[i]);
  6450. }
  6451. static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
  6452. {
  6453. char *driver_ver, *old_driver_ver;
  6454. int rc, size = sizeof(cfgtable->driver_version);
  6455. old_driver_ver = kmalloc_array(2, size, GFP_KERNEL);
  6456. if (!old_driver_ver)
  6457. return -ENOMEM;
  6458. driver_ver = old_driver_ver + size;
  6459. /* After a reset, the 32 bytes of "driver version" in the cfgtable
  6460. * should have been changed, otherwise we know the reset failed.
  6461. */
  6462. init_driver_version(old_driver_ver, size);
  6463. read_driver_ver_from_cfgtable(cfgtable, driver_ver);
  6464. rc = !memcmp(driver_ver, old_driver_ver, size);
  6465. kfree(old_driver_ver);
  6466. return rc;
  6467. }
  6468. /* This does a hard reset of the controller using PCI power management
  6469. * states or the using the doorbell register.
  6470. */
  6471. static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
  6472. {
  6473. u64 cfg_offset;
  6474. u32 cfg_base_addr;
  6475. u64 cfg_base_addr_index;
  6476. void __iomem *vaddr;
  6477. unsigned long paddr;
  6478. u32 misc_fw_support;
  6479. int rc;
  6480. struct CfgTable __iomem *cfgtable;
  6481. u32 use_doorbell;
  6482. u16 command_register;
  6483. /* For controllers as old as the P600, this is very nearly
  6484. * the same thing as
  6485. *
  6486. * pci_save_state(pci_dev);
  6487. * pci_set_power_state(pci_dev, PCI_D3hot);
  6488. * pci_set_power_state(pci_dev, PCI_D0);
  6489. * pci_restore_state(pci_dev);
  6490. *
  6491. * For controllers newer than the P600, the pci power state
  6492. * method of resetting doesn't work so we have another way
  6493. * using the doorbell register.
  6494. */
  6495. if (!ctlr_is_resettable(board_id)) {
  6496. dev_warn(&pdev->dev, "Controller not resettable\n");
  6497. return -ENODEV;
  6498. }
  6499. /* if controller is soft- but not hard resettable... */
  6500. if (!ctlr_is_hard_resettable(board_id))
  6501. return -ENOTSUPP; /* try soft reset later. */
  6502. /* Save the PCI command register */
  6503. pci_read_config_word(pdev, 4, &command_register);
  6504. pci_save_state(pdev);
  6505. /* find the first memory BAR, so we can find the cfg table */
  6506. rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
  6507. if (rc)
  6508. return rc;
  6509. vaddr = remap_pci_mem(paddr, 0x250);
  6510. if (!vaddr)
  6511. return -ENOMEM;
  6512. /* find cfgtable in order to check if reset via doorbell is supported */
  6513. rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
  6514. &cfg_base_addr_index, &cfg_offset);
  6515. if (rc)
  6516. goto unmap_vaddr;
  6517. cfgtable = remap_pci_mem(pci_resource_start(pdev,
  6518. cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
  6519. if (!cfgtable) {
  6520. rc = -ENOMEM;
  6521. goto unmap_vaddr;
  6522. }
  6523. rc = write_driver_ver_to_cfgtable(cfgtable);
  6524. if (rc)
  6525. goto unmap_cfgtable;
  6526. /* If reset via doorbell register is supported, use that.
  6527. * There are two such methods. Favor the newest method.
  6528. */
  6529. misc_fw_support = readl(&cfgtable->misc_fw_support);
  6530. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
  6531. if (use_doorbell) {
  6532. use_doorbell = DOORBELL_CTLR_RESET2;
  6533. } else {
  6534. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
  6535. if (use_doorbell) {
  6536. dev_warn(&pdev->dev,
  6537. "Soft reset not supported. Firmware update is required.\n");
  6538. rc = -ENOTSUPP; /* try soft reset */
  6539. goto unmap_cfgtable;
  6540. }
  6541. }
  6542. rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
  6543. if (rc)
  6544. goto unmap_cfgtable;
  6545. pci_restore_state(pdev);
  6546. pci_write_config_word(pdev, 4, command_register);
  6547. /* Some devices (notably the HP Smart Array 5i Controller)
  6548. need a little pause here */
  6549. msleep(HPSA_POST_RESET_PAUSE_MSECS);
  6550. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
  6551. if (rc) {
  6552. dev_warn(&pdev->dev,
  6553. "Failed waiting for board to become ready after hard reset\n");
  6554. goto unmap_cfgtable;
  6555. }
  6556. rc = controller_reset_failed(vaddr);
  6557. if (rc < 0)
  6558. goto unmap_cfgtable;
  6559. if (rc) {
  6560. dev_warn(&pdev->dev, "Unable to successfully reset "
  6561. "controller. Will try soft reset.\n");
  6562. rc = -ENOTSUPP;
  6563. } else {
  6564. dev_info(&pdev->dev, "board ready after hard reset.\n");
  6565. }
  6566. unmap_cfgtable:
  6567. iounmap(cfgtable);
  6568. unmap_vaddr:
  6569. iounmap(vaddr);
  6570. return rc;
  6571. }
  6572. /*
  6573. * We cannot read the structure directly, for portability we must use
  6574. * the io functions.
  6575. * This is for debug only.
  6576. */
  6577. static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
  6578. {
  6579. #ifdef HPSA_DEBUG
  6580. int i;
  6581. char temp_name[17];
  6582. dev_info(dev, "Controller Configuration information\n");
  6583. dev_info(dev, "------------------------------------\n");
  6584. for (i = 0; i < 4; i++)
  6585. temp_name[i] = readb(&(tb->Signature[i]));
  6586. temp_name[4] = '\0';
  6587. dev_info(dev, " Signature = %s\n", temp_name);
  6588. dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
  6589. dev_info(dev, " Transport methods supported = 0x%x\n",
  6590. readl(&(tb->TransportSupport)));
  6591. dev_info(dev, " Transport methods active = 0x%x\n",
  6592. readl(&(tb->TransportActive)));
  6593. dev_info(dev, " Requested transport Method = 0x%x\n",
  6594. readl(&(tb->HostWrite.TransportRequest)));
  6595. dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
  6596. readl(&(tb->HostWrite.CoalIntDelay)));
  6597. dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
  6598. readl(&(tb->HostWrite.CoalIntCount)));
  6599. dev_info(dev, " Max outstanding commands = %d\n",
  6600. readl(&(tb->CmdsOutMax)));
  6601. dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
  6602. for (i = 0; i < 16; i++)
  6603. temp_name[i] = readb(&(tb->ServerName[i]));
  6604. temp_name[16] = '\0';
  6605. dev_info(dev, " Server Name = %s\n", temp_name);
  6606. dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
  6607. readl(&(tb->HeartBeat)));
  6608. #endif /* HPSA_DEBUG */
  6609. }
  6610. static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
  6611. {
  6612. int i, offset, mem_type, bar_type;
  6613. if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
  6614. return 0;
  6615. offset = 0;
  6616. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  6617. bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
  6618. if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
  6619. offset += 4;
  6620. else {
  6621. mem_type = pci_resource_flags(pdev, i) &
  6622. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  6623. switch (mem_type) {
  6624. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  6625. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  6626. offset += 4; /* 32 bit */
  6627. break;
  6628. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  6629. offset += 8;
  6630. break;
  6631. default: /* reserved in PCI 2.2 */
  6632. dev_warn(&pdev->dev,
  6633. "base address is invalid\n");
  6634. return -1;
  6635. }
  6636. }
  6637. if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
  6638. return i + 1;
  6639. }
  6640. return -1;
  6641. }
  6642. static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
  6643. {
  6644. pci_free_irq_vectors(h->pdev);
  6645. h->msix_vectors = 0;
  6646. }
  6647. static void hpsa_setup_reply_map(struct ctlr_info *h)
  6648. {
  6649. const struct cpumask *mask;
  6650. unsigned int queue, cpu;
  6651. for (queue = 0; queue < h->msix_vectors; queue++) {
  6652. mask = pci_irq_get_affinity(h->pdev, queue);
  6653. if (!mask)
  6654. goto fallback;
  6655. for_each_cpu(cpu, mask)
  6656. h->reply_map[cpu] = queue;
  6657. }
  6658. return;
  6659. fallback:
  6660. for_each_possible_cpu(cpu)
  6661. h->reply_map[cpu] = 0;
  6662. }
  6663. /* If MSI/MSI-X is supported by the kernel we will try to enable it on
  6664. * controllers that are capable. If not, we use legacy INTx mode.
  6665. */
  6666. static int hpsa_interrupt_mode(struct ctlr_info *h)
  6667. {
  6668. unsigned int flags = PCI_IRQ_INTX;
  6669. int ret;
  6670. /* Some boards advertise MSI but don't really support it */
  6671. switch (h->board_id) {
  6672. case 0x40700E11:
  6673. case 0x40800E11:
  6674. case 0x40820E11:
  6675. case 0x40830E11:
  6676. break;
  6677. default:
  6678. ret = pci_alloc_irq_vectors(h->pdev, 1, MAX_REPLY_QUEUES,
  6679. PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
  6680. if (ret > 0) {
  6681. h->msix_vectors = ret;
  6682. return 0;
  6683. }
  6684. flags |= PCI_IRQ_MSI;
  6685. break;
  6686. }
  6687. ret = pci_alloc_irq_vectors(h->pdev, 1, 1, flags);
  6688. if (ret < 0)
  6689. return ret;
  6690. return 0;
  6691. }
  6692. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id,
  6693. bool *legacy_board)
  6694. {
  6695. int i;
  6696. u32 subsystem_vendor_id, subsystem_device_id;
  6697. subsystem_vendor_id = pdev->subsystem_vendor;
  6698. subsystem_device_id = pdev->subsystem_device;
  6699. *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
  6700. subsystem_vendor_id;
  6701. if (legacy_board)
  6702. *legacy_board = false;
  6703. for (i = 0; i < ARRAY_SIZE(products); i++)
  6704. if (*board_id == products[i].board_id) {
  6705. if (products[i].access != &SA5A_access &&
  6706. products[i].access != &SA5B_access)
  6707. return i;
  6708. dev_warn(&pdev->dev,
  6709. "legacy board ID: 0x%08x\n",
  6710. *board_id);
  6711. if (legacy_board)
  6712. *legacy_board = true;
  6713. return i;
  6714. }
  6715. dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x\n", *board_id);
  6716. if (legacy_board)
  6717. *legacy_board = true;
  6718. return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
  6719. }
  6720. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  6721. unsigned long *memory_bar)
  6722. {
  6723. int i;
  6724. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  6725. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  6726. /* addressing mode bits already removed */
  6727. *memory_bar = pci_resource_start(pdev, i);
  6728. dev_dbg(&pdev->dev, "memory BAR = %lx\n",
  6729. *memory_bar);
  6730. return 0;
  6731. }
  6732. dev_warn(&pdev->dev, "no memory BAR found\n");
  6733. return -ENODEV;
  6734. }
  6735. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  6736. int wait_for_ready)
  6737. {
  6738. int i, iterations;
  6739. u32 scratchpad;
  6740. if (wait_for_ready)
  6741. iterations = HPSA_BOARD_READY_ITERATIONS;
  6742. else
  6743. iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
  6744. for (i = 0; i < iterations; i++) {
  6745. scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
  6746. if (wait_for_ready) {
  6747. if (scratchpad == HPSA_FIRMWARE_READY)
  6748. return 0;
  6749. } else {
  6750. if (scratchpad != HPSA_FIRMWARE_READY)
  6751. return 0;
  6752. }
  6753. msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
  6754. }
  6755. dev_warn(&pdev->dev, "board not ready, timed out.\n");
  6756. return -ENODEV;
  6757. }
  6758. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  6759. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  6760. u64 *cfg_offset)
  6761. {
  6762. *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
  6763. *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
  6764. *cfg_base_addr &= (u32) 0x0000ffff;
  6765. *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
  6766. if (*cfg_base_addr_index == -1) {
  6767. dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
  6768. return -ENODEV;
  6769. }
  6770. return 0;
  6771. }
  6772. static void hpsa_free_cfgtables(struct ctlr_info *h)
  6773. {
  6774. if (h->transtable) {
  6775. iounmap(h->transtable);
  6776. h->transtable = NULL;
  6777. }
  6778. if (h->cfgtable) {
  6779. iounmap(h->cfgtable);
  6780. h->cfgtable = NULL;
  6781. }
  6782. }
  6783. /* Find and map CISS config table and transfer table
  6784. * several items must be unmapped (freed) later
  6785. */
  6786. static int hpsa_find_cfgtables(struct ctlr_info *h)
  6787. {
  6788. u64 cfg_offset;
  6789. u32 cfg_base_addr;
  6790. u64 cfg_base_addr_index;
  6791. u32 trans_offset;
  6792. int rc;
  6793. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  6794. &cfg_base_addr_index, &cfg_offset);
  6795. if (rc)
  6796. return rc;
  6797. h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
  6798. cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
  6799. if (!h->cfgtable) {
  6800. dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
  6801. return -ENOMEM;
  6802. }
  6803. rc = write_driver_ver_to_cfgtable(h->cfgtable);
  6804. if (rc)
  6805. return rc;
  6806. /* Find performant mode table. */
  6807. trans_offset = readl(&h->cfgtable->TransMethodOffset);
  6808. h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
  6809. cfg_base_addr_index)+cfg_offset+trans_offset,
  6810. sizeof(*h->transtable));
  6811. if (!h->transtable) {
  6812. dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
  6813. hpsa_free_cfgtables(h);
  6814. return -ENOMEM;
  6815. }
  6816. return 0;
  6817. }
  6818. static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
  6819. {
  6820. #define MIN_MAX_COMMANDS 16
  6821. BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
  6822. h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
  6823. /* Limit commands in memory limited kdump scenario. */
  6824. if (reset_devices && h->max_commands > 32)
  6825. h->max_commands = 32;
  6826. if (h->max_commands < MIN_MAX_COMMANDS) {
  6827. dev_warn(&h->pdev->dev,
  6828. "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
  6829. h->max_commands,
  6830. MIN_MAX_COMMANDS);
  6831. h->max_commands = MIN_MAX_COMMANDS;
  6832. }
  6833. }
  6834. /* If the controller reports that the total max sg entries is greater than 512,
  6835. * then we know that chained SG blocks work. (Original smart arrays did not
  6836. * support chained SG blocks and would return zero for max sg entries.)
  6837. */
  6838. static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
  6839. {
  6840. return h->maxsgentries > 512;
  6841. }
  6842. /* Interrogate the hardware for some limits:
  6843. * max commands, max SG elements without chaining, and with chaining,
  6844. * SG chain block size, etc.
  6845. */
  6846. static void hpsa_find_board_params(struct ctlr_info *h)
  6847. {
  6848. hpsa_get_max_perf_mode_cmds(h);
  6849. h->nr_cmds = h->max_commands;
  6850. h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
  6851. h->fw_support = readl(&(h->cfgtable->misc_fw_support));
  6852. if (hpsa_supports_chained_sg_blocks(h)) {
  6853. /* Limit in-command s/g elements to 32 save dma'able memory. */
  6854. h->max_cmd_sg_entries = 32;
  6855. h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
  6856. h->maxsgentries--; /* save one for chain pointer */
  6857. } else {
  6858. /*
  6859. * Original smart arrays supported at most 31 s/g entries
  6860. * embedded inline in the command (trying to use more
  6861. * would lock up the controller)
  6862. */
  6863. h->max_cmd_sg_entries = 31;
  6864. h->maxsgentries = 31; /* default to traditional values */
  6865. h->chainsize = 0;
  6866. }
  6867. /* Find out what task management functions are supported and cache */
  6868. h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
  6869. if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
  6870. dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
  6871. if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
  6872. dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
  6873. if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
  6874. dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
  6875. }
  6876. static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
  6877. {
  6878. if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
  6879. dev_err(&h->pdev->dev, "not a valid CISS config table\n");
  6880. return false;
  6881. }
  6882. return true;
  6883. }
  6884. static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
  6885. {
  6886. u32 driver_support;
  6887. driver_support = readl(&(h->cfgtable->driver_support));
  6888. /* Need to enable prefetch in the SCSI core for 6400 in x86 */
  6889. #ifdef CONFIG_X86
  6890. driver_support |= ENABLE_SCSI_PREFETCH;
  6891. #endif
  6892. driver_support |= ENABLE_UNIT_ATTN;
  6893. writel(driver_support, &(h->cfgtable->driver_support));
  6894. }
  6895. /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
  6896. * in a prefetch beyond physical memory.
  6897. */
  6898. static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
  6899. {
  6900. u32 dma_prefetch;
  6901. if (h->board_id != 0x3225103C)
  6902. return;
  6903. dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
  6904. dma_prefetch |= 0x8000;
  6905. writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
  6906. }
  6907. static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
  6908. {
  6909. int i;
  6910. u32 doorbell_value;
  6911. unsigned long flags;
  6912. /* wait until the clear_event_notify bit 6 is cleared by controller. */
  6913. for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
  6914. spin_lock_irqsave(&h->lock, flags);
  6915. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  6916. spin_unlock_irqrestore(&h->lock, flags);
  6917. if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
  6918. goto done;
  6919. /* delay and try again */
  6920. msleep(CLEAR_EVENT_WAIT_INTERVAL);
  6921. }
  6922. return -ENODEV;
  6923. done:
  6924. return 0;
  6925. }
  6926. static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
  6927. {
  6928. int i;
  6929. u32 doorbell_value;
  6930. unsigned long flags;
  6931. /* under certain very rare conditions, this can take awhile.
  6932. * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
  6933. * as we enter this code.)
  6934. */
  6935. for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
  6936. if (h->remove_in_progress)
  6937. goto done;
  6938. spin_lock_irqsave(&h->lock, flags);
  6939. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  6940. spin_unlock_irqrestore(&h->lock, flags);
  6941. if (!(doorbell_value & CFGTBL_ChangeReq))
  6942. goto done;
  6943. /* delay and try again */
  6944. msleep(MODE_CHANGE_WAIT_INTERVAL);
  6945. }
  6946. return -ENODEV;
  6947. done:
  6948. return 0;
  6949. }
  6950. /* return -ENODEV or other reason on error, 0 on success */
  6951. static int hpsa_enter_simple_mode(struct ctlr_info *h)
  6952. {
  6953. u32 trans_support;
  6954. trans_support = readl(&(h->cfgtable->TransportSupport));
  6955. if (!(trans_support & SIMPLE_MODE))
  6956. return -ENOTSUPP;
  6957. h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
  6958. /* Update the field, and then ring the doorbell */
  6959. writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
  6960. writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
  6961. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  6962. if (hpsa_wait_for_mode_change_ack(h))
  6963. goto error;
  6964. print_cfg_table(&h->pdev->dev, h->cfgtable);
  6965. if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
  6966. goto error;
  6967. h->transMethod = CFGTBL_Trans_Simple;
  6968. return 0;
  6969. error:
  6970. dev_err(&h->pdev->dev, "failed to enter simple mode\n");
  6971. return -ENODEV;
  6972. }
  6973. /* free items allocated or mapped by hpsa_pci_init */
  6974. static void hpsa_free_pci_init(struct ctlr_info *h)
  6975. {
  6976. hpsa_free_cfgtables(h); /* pci_init 4 */
  6977. iounmap(h->vaddr); /* pci_init 3 */
  6978. h->vaddr = NULL;
  6979. hpsa_disable_interrupt_mode(h); /* pci_init 2 */
  6980. /*
  6981. * call pci_disable_device before pci_release_regions per
  6982. * Documentation/driver-api/pci/pci.rst
  6983. */
  6984. pci_disable_device(h->pdev); /* pci_init 1 */
  6985. pci_release_regions(h->pdev); /* pci_init 2 */
  6986. }
  6987. /* several items must be freed later */
  6988. static int hpsa_pci_init(struct ctlr_info *h)
  6989. {
  6990. int prod_index, err;
  6991. bool legacy_board;
  6992. prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id, &legacy_board);
  6993. if (prod_index < 0)
  6994. return prod_index;
  6995. h->product_name = products[prod_index].product_name;
  6996. h->access = *(products[prod_index].access);
  6997. h->legacy_board = legacy_board;
  6998. pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
  6999. PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
  7000. err = pci_enable_device(h->pdev);
  7001. if (err) {
  7002. dev_err(&h->pdev->dev, "failed to enable PCI device\n");
  7003. pci_disable_device(h->pdev);
  7004. return err;
  7005. }
  7006. err = pci_request_regions(h->pdev, HPSA);
  7007. if (err) {
  7008. dev_err(&h->pdev->dev,
  7009. "failed to obtain PCI resources\n");
  7010. pci_disable_device(h->pdev);
  7011. return err;
  7012. }
  7013. pci_set_master(h->pdev);
  7014. err = hpsa_interrupt_mode(h);
  7015. if (err)
  7016. goto clean1;
  7017. /* setup mapping between CPU and reply queue */
  7018. hpsa_setup_reply_map(h);
  7019. err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
  7020. if (err)
  7021. goto clean2; /* intmode+region, pci */
  7022. h->vaddr = remap_pci_mem(h->paddr, 0x250);
  7023. if (!h->vaddr) {
  7024. dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
  7025. err = -ENOMEM;
  7026. goto clean2; /* intmode+region, pci */
  7027. }
  7028. err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  7029. if (err)
  7030. goto clean3; /* vaddr, intmode+region, pci */
  7031. err = hpsa_find_cfgtables(h);
  7032. if (err)
  7033. goto clean3; /* vaddr, intmode+region, pci */
  7034. hpsa_find_board_params(h);
  7035. if (!hpsa_CISS_signature_present(h)) {
  7036. err = -ENODEV;
  7037. goto clean4; /* cfgtables, vaddr, intmode+region, pci */
  7038. }
  7039. hpsa_set_driver_support_bits(h);
  7040. hpsa_p600_dma_prefetch_quirk(h);
  7041. err = hpsa_enter_simple_mode(h);
  7042. if (err)
  7043. goto clean4; /* cfgtables, vaddr, intmode+region, pci */
  7044. return 0;
  7045. clean4: /* cfgtables, vaddr, intmode+region, pci */
  7046. hpsa_free_cfgtables(h);
  7047. clean3: /* vaddr, intmode+region, pci */
  7048. iounmap(h->vaddr);
  7049. h->vaddr = NULL;
  7050. clean2: /* intmode+region, pci */
  7051. hpsa_disable_interrupt_mode(h);
  7052. clean1:
  7053. /*
  7054. * call pci_disable_device before pci_release_regions per
  7055. * Documentation/driver-api/pci/pci.rst
  7056. */
  7057. pci_disable_device(h->pdev);
  7058. pci_release_regions(h->pdev);
  7059. return err;
  7060. }
  7061. static void hpsa_hba_inquiry(struct ctlr_info *h)
  7062. {
  7063. int rc;
  7064. #define HBA_INQUIRY_BYTE_COUNT 64
  7065. h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
  7066. if (!h->hba_inquiry_data)
  7067. return;
  7068. rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
  7069. h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
  7070. if (rc != 0) {
  7071. kfree(h->hba_inquiry_data);
  7072. h->hba_inquiry_data = NULL;
  7073. }
  7074. }
  7075. static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
  7076. {
  7077. int rc, i;
  7078. void __iomem *vaddr;
  7079. if (!reset_devices)
  7080. return 0;
  7081. /* kdump kernel is loading, we don't know in which state is
  7082. * the pci interface. The dev->enable_cnt is equal zero
  7083. * so we call enable+disable, wait a while and switch it on.
  7084. */
  7085. rc = pci_enable_device(pdev);
  7086. if (rc) {
  7087. dev_warn(&pdev->dev, "Failed to enable PCI device\n");
  7088. return -ENODEV;
  7089. }
  7090. pci_disable_device(pdev);
  7091. msleep(260); /* a randomly chosen number */
  7092. rc = pci_enable_device(pdev);
  7093. if (rc) {
  7094. dev_warn(&pdev->dev, "failed to enable device.\n");
  7095. return -ENODEV;
  7096. }
  7097. pci_set_master(pdev);
  7098. vaddr = pci_ioremap_bar(pdev, 0);
  7099. if (vaddr == NULL) {
  7100. rc = -ENOMEM;
  7101. goto out_disable;
  7102. }
  7103. writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  7104. iounmap(vaddr);
  7105. /* Reset the controller with a PCI power-cycle or via doorbell */
  7106. rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
  7107. /* -ENOTSUPP here means we cannot reset the controller
  7108. * but it's already (and still) up and running in
  7109. * "performant mode". Or, it might be 640x, which can't reset
  7110. * due to concerns about shared bbwc between 6402/6404 pair.
  7111. */
  7112. if (rc)
  7113. goto out_disable;
  7114. /* Now try to get the controller to respond to a no-op */
  7115. dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
  7116. for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
  7117. if (hpsa_noop(pdev) == 0)
  7118. break;
  7119. else
  7120. dev_warn(&pdev->dev, "no-op failed%s\n",
  7121. (i < 11 ? "; re-trying" : ""));
  7122. }
  7123. out_disable:
  7124. pci_disable_device(pdev);
  7125. return rc;
  7126. }
  7127. static void hpsa_free_cmd_pool(struct ctlr_info *h)
  7128. {
  7129. bitmap_free(h->cmd_pool_bits);
  7130. h->cmd_pool_bits = NULL;
  7131. if (h->cmd_pool) {
  7132. dma_free_coherent(&h->pdev->dev,
  7133. h->nr_cmds * sizeof(struct CommandList),
  7134. h->cmd_pool,
  7135. h->cmd_pool_dhandle);
  7136. h->cmd_pool = NULL;
  7137. h->cmd_pool_dhandle = 0;
  7138. }
  7139. if (h->errinfo_pool) {
  7140. dma_free_coherent(&h->pdev->dev,
  7141. h->nr_cmds * sizeof(struct ErrorInfo),
  7142. h->errinfo_pool,
  7143. h->errinfo_pool_dhandle);
  7144. h->errinfo_pool = NULL;
  7145. h->errinfo_pool_dhandle = 0;
  7146. }
  7147. }
  7148. static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
  7149. {
  7150. h->cmd_pool_bits = bitmap_zalloc(h->nr_cmds, GFP_KERNEL);
  7151. h->cmd_pool = dma_alloc_coherent(&h->pdev->dev,
  7152. h->nr_cmds * sizeof(*h->cmd_pool),
  7153. &h->cmd_pool_dhandle, GFP_KERNEL);
  7154. h->errinfo_pool = dma_alloc_coherent(&h->pdev->dev,
  7155. h->nr_cmds * sizeof(*h->errinfo_pool),
  7156. &h->errinfo_pool_dhandle, GFP_KERNEL);
  7157. if ((h->cmd_pool_bits == NULL)
  7158. || (h->cmd_pool == NULL)
  7159. || (h->errinfo_pool == NULL)) {
  7160. dev_err(&h->pdev->dev, "out of memory in %s", __func__);
  7161. goto clean_up;
  7162. }
  7163. hpsa_preinitialize_commands(h);
  7164. return 0;
  7165. clean_up:
  7166. hpsa_free_cmd_pool(h);
  7167. return -ENOMEM;
  7168. }
  7169. /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
  7170. static void hpsa_free_irqs(struct ctlr_info *h)
  7171. {
  7172. int i;
  7173. int irq_vector = 0;
  7174. if (hpsa_simple_mode)
  7175. irq_vector = h->intr_mode;
  7176. if (!h->msix_vectors || h->intr_mode != PERF_MODE_INT) {
  7177. /* Single reply queue, only one irq to free */
  7178. free_irq(pci_irq_vector(h->pdev, irq_vector),
  7179. &h->q[h->intr_mode]);
  7180. h->q[h->intr_mode] = 0;
  7181. return;
  7182. }
  7183. for (i = 0; i < h->msix_vectors; i++) {
  7184. free_irq(pci_irq_vector(h->pdev, i), &h->q[i]);
  7185. h->q[i] = 0;
  7186. }
  7187. for (; i < MAX_REPLY_QUEUES; i++)
  7188. h->q[i] = 0;
  7189. }
  7190. /* returns 0 on success; cleans up and returns -Enn on error */
  7191. static int hpsa_request_irqs(struct ctlr_info *h,
  7192. irqreturn_t (*msixhandler)(int, void *),
  7193. irqreturn_t (*intxhandler)(int, void *))
  7194. {
  7195. int rc, i;
  7196. int irq_vector = 0;
  7197. if (hpsa_simple_mode)
  7198. irq_vector = h->intr_mode;
  7199. /*
  7200. * initialize h->q[x] = x so that interrupt handlers know which
  7201. * queue to process.
  7202. */
  7203. for (i = 0; i < MAX_REPLY_QUEUES; i++)
  7204. h->q[i] = (u8) i;
  7205. if (h->intr_mode == PERF_MODE_INT && h->msix_vectors > 0) {
  7206. /* If performant mode and MSI-X, use multiple reply queues */
  7207. for (i = 0; i < h->msix_vectors; i++) {
  7208. sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
  7209. rc = request_irq(pci_irq_vector(h->pdev, i), msixhandler,
  7210. 0, h->intrname[i],
  7211. &h->q[i]);
  7212. if (rc) {
  7213. int j;
  7214. dev_err(&h->pdev->dev,
  7215. "failed to get irq %d for %s\n",
  7216. pci_irq_vector(h->pdev, i), h->devname);
  7217. for (j = 0; j < i; j++) {
  7218. free_irq(pci_irq_vector(h->pdev, j), &h->q[j]);
  7219. h->q[j] = 0;
  7220. }
  7221. for (; j < MAX_REPLY_QUEUES; j++)
  7222. h->q[j] = 0;
  7223. return rc;
  7224. }
  7225. }
  7226. } else {
  7227. /* Use single reply pool */
  7228. if (h->msix_vectors > 0 || h->pdev->msi_enabled) {
  7229. sprintf(h->intrname[0], "%s-msi%s", h->devname,
  7230. h->msix_vectors ? "x" : "");
  7231. rc = request_irq(pci_irq_vector(h->pdev, irq_vector),
  7232. msixhandler, 0,
  7233. h->intrname[0],
  7234. &h->q[h->intr_mode]);
  7235. } else {
  7236. sprintf(h->intrname[h->intr_mode],
  7237. "%s-intx", h->devname);
  7238. rc = request_irq(pci_irq_vector(h->pdev, irq_vector),
  7239. intxhandler, IRQF_SHARED,
  7240. h->intrname[0],
  7241. &h->q[h->intr_mode]);
  7242. }
  7243. }
  7244. if (rc) {
  7245. dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
  7246. pci_irq_vector(h->pdev, irq_vector), h->devname);
  7247. hpsa_free_irqs(h);
  7248. return -ENODEV;
  7249. }
  7250. return 0;
  7251. }
  7252. static int hpsa_kdump_soft_reset(struct ctlr_info *h)
  7253. {
  7254. int rc;
  7255. hpsa_send_host_reset(h, HPSA_RESET_TYPE_CONTROLLER);
  7256. dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
  7257. rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
  7258. if (rc) {
  7259. dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
  7260. return rc;
  7261. }
  7262. dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
  7263. rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  7264. if (rc) {
  7265. dev_warn(&h->pdev->dev, "Board failed to become ready "
  7266. "after soft reset.\n");
  7267. return rc;
  7268. }
  7269. return 0;
  7270. }
  7271. static void hpsa_free_reply_queues(struct ctlr_info *h)
  7272. {
  7273. int i;
  7274. for (i = 0; i < h->nreply_queues; i++) {
  7275. if (!h->reply_queue[i].head)
  7276. continue;
  7277. dma_free_coherent(&h->pdev->dev,
  7278. h->reply_queue_size,
  7279. h->reply_queue[i].head,
  7280. h->reply_queue[i].busaddr);
  7281. h->reply_queue[i].head = NULL;
  7282. h->reply_queue[i].busaddr = 0;
  7283. }
  7284. h->reply_queue_size = 0;
  7285. }
  7286. static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
  7287. {
  7288. hpsa_free_performant_mode(h); /* init_one 7 */
  7289. hpsa_free_sg_chain_blocks(h); /* init_one 6 */
  7290. hpsa_free_cmd_pool(h); /* init_one 5 */
  7291. hpsa_free_irqs(h); /* init_one 4 */
  7292. scsi_host_put(h->scsi_host); /* init_one 3 */
  7293. h->scsi_host = NULL; /* init_one 3 */
  7294. hpsa_free_pci_init(h); /* init_one 2_5 */
  7295. free_percpu(h->lockup_detected); /* init_one 2 */
  7296. h->lockup_detected = NULL; /* init_one 2 */
  7297. if (h->resubmit_wq) {
  7298. destroy_workqueue(h->resubmit_wq); /* init_one 1 */
  7299. h->resubmit_wq = NULL;
  7300. }
  7301. if (h->rescan_ctlr_wq) {
  7302. destroy_workqueue(h->rescan_ctlr_wq);
  7303. h->rescan_ctlr_wq = NULL;
  7304. }
  7305. if (h->monitor_ctlr_wq) {
  7306. destroy_workqueue(h->monitor_ctlr_wq);
  7307. h->monitor_ctlr_wq = NULL;
  7308. }
  7309. kfree(h); /* init_one 1 */
  7310. }
  7311. /* Called when controller lockup detected. */
  7312. static void fail_all_outstanding_cmds(struct ctlr_info *h)
  7313. {
  7314. int i, refcount;
  7315. struct CommandList *c;
  7316. int failcount = 0;
  7317. flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
  7318. for (i = 0; i < h->nr_cmds; i++) {
  7319. c = h->cmd_pool + i;
  7320. refcount = atomic_inc_return(&c->refcount);
  7321. if (refcount > 1) {
  7322. c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
  7323. finish_cmd(c);
  7324. atomic_dec(&h->commands_outstanding);
  7325. failcount++;
  7326. }
  7327. cmd_free(h, c);
  7328. }
  7329. dev_warn(&h->pdev->dev,
  7330. "failed %d commands in fail_all\n", failcount);
  7331. }
  7332. static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
  7333. {
  7334. int cpu;
  7335. for_each_online_cpu(cpu) {
  7336. u32 *lockup_detected;
  7337. lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
  7338. *lockup_detected = value;
  7339. }
  7340. wmb(); /* be sure the per-cpu variables are out to memory */
  7341. }
  7342. static void controller_lockup_detected(struct ctlr_info *h)
  7343. {
  7344. unsigned long flags;
  7345. u32 lockup_detected;
  7346. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7347. spin_lock_irqsave(&h->lock, flags);
  7348. lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
  7349. if (!lockup_detected) {
  7350. /* no heartbeat, but controller gave us a zero. */
  7351. dev_warn(&h->pdev->dev,
  7352. "lockup detected after %d but scratchpad register is zero\n",
  7353. h->heartbeat_sample_interval / HZ);
  7354. lockup_detected = 0xffffffff;
  7355. }
  7356. set_lockup_detected_for_all_cpus(h, lockup_detected);
  7357. spin_unlock_irqrestore(&h->lock, flags);
  7358. dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
  7359. lockup_detected, h->heartbeat_sample_interval / HZ);
  7360. if (lockup_detected == 0xffff0000) {
  7361. dev_warn(&h->pdev->dev, "Telling controller to do a CHKPT\n");
  7362. writel(DOORBELL_GENERATE_CHKPT, h->vaddr + SA5_DOORBELL);
  7363. }
  7364. pci_disable_device(h->pdev);
  7365. fail_all_outstanding_cmds(h);
  7366. }
  7367. static int detect_controller_lockup(struct ctlr_info *h)
  7368. {
  7369. u64 now;
  7370. u32 heartbeat;
  7371. unsigned long flags;
  7372. now = get_jiffies_64();
  7373. /* If we've received an interrupt recently, we're ok. */
  7374. if (time_after64(h->last_intr_timestamp +
  7375. (h->heartbeat_sample_interval), now))
  7376. return false;
  7377. /*
  7378. * If we've already checked the heartbeat recently, we're ok.
  7379. * This could happen if someone sends us a signal. We
  7380. * otherwise don't care about signals in this thread.
  7381. */
  7382. if (time_after64(h->last_heartbeat_timestamp +
  7383. (h->heartbeat_sample_interval), now))
  7384. return false;
  7385. /* If heartbeat has not changed since we last looked, we're not ok. */
  7386. spin_lock_irqsave(&h->lock, flags);
  7387. heartbeat = readl(&h->cfgtable->HeartBeat);
  7388. spin_unlock_irqrestore(&h->lock, flags);
  7389. if (h->last_heartbeat == heartbeat) {
  7390. controller_lockup_detected(h);
  7391. return true;
  7392. }
  7393. /* We're ok. */
  7394. h->last_heartbeat = heartbeat;
  7395. h->last_heartbeat_timestamp = now;
  7396. return false;
  7397. }
  7398. /*
  7399. * Set ioaccel status for all ioaccel volumes.
  7400. *
  7401. * Called from monitor controller worker (hpsa_event_monitor_worker)
  7402. *
  7403. * A Volume (or Volumes that comprise an Array set) may be undergoing a
  7404. * transformation, so we will be turning off ioaccel for all volumes that
  7405. * make up the Array.
  7406. */
  7407. static void hpsa_set_ioaccel_status(struct ctlr_info *h)
  7408. {
  7409. int rc;
  7410. int i;
  7411. u8 ioaccel_status;
  7412. unsigned char *buf;
  7413. struct hpsa_scsi_dev_t *device;
  7414. if (!h)
  7415. return;
  7416. buf = kmalloc(64, GFP_KERNEL);
  7417. if (!buf)
  7418. return;
  7419. /*
  7420. * Run through current device list used during I/O requests.
  7421. */
  7422. for (i = 0; i < h->ndevices; i++) {
  7423. int offload_to_be_enabled = 0;
  7424. int offload_config = 0;
  7425. device = h->dev[i];
  7426. if (!device)
  7427. continue;
  7428. if (!hpsa_vpd_page_supported(h, device->scsi3addr,
  7429. HPSA_VPD_LV_IOACCEL_STATUS))
  7430. continue;
  7431. memset(buf, 0, 64);
  7432. rc = hpsa_scsi_do_inquiry(h, device->scsi3addr,
  7433. VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS,
  7434. buf, 64);
  7435. if (rc != 0)
  7436. continue;
  7437. ioaccel_status = buf[IOACCEL_STATUS_BYTE];
  7438. /*
  7439. * Check if offload is still configured on
  7440. */
  7441. offload_config =
  7442. !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
  7443. /*
  7444. * If offload is configured on, check to see if ioaccel
  7445. * needs to be enabled.
  7446. */
  7447. if (offload_config)
  7448. offload_to_be_enabled =
  7449. !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
  7450. /*
  7451. * If ioaccel is to be re-enabled, re-enable later during the
  7452. * scan operation so the driver can get a fresh raidmap
  7453. * before turning ioaccel back on.
  7454. */
  7455. if (offload_to_be_enabled)
  7456. continue;
  7457. /*
  7458. * Immediately turn off ioaccel for any volume the
  7459. * controller tells us to. Some of the reasons could be:
  7460. * transformation - change to the LVs of an Array.
  7461. * degraded volume - component failure
  7462. */
  7463. hpsa_turn_off_ioaccel_for_device(device);
  7464. }
  7465. kfree(buf);
  7466. }
  7467. static void hpsa_ack_ctlr_events(struct ctlr_info *h)
  7468. {
  7469. char *event_type;
  7470. if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
  7471. return;
  7472. /* Ask the controller to clear the events we're handling. */
  7473. if ((h->transMethod & (CFGTBL_Trans_io_accel1
  7474. | CFGTBL_Trans_io_accel2)) &&
  7475. (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
  7476. h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
  7477. if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
  7478. event_type = "state change";
  7479. if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
  7480. event_type = "configuration change";
  7481. /* Stop sending new RAID offload reqs via the IO accelerator */
  7482. scsi_block_requests(h->scsi_host);
  7483. hpsa_set_ioaccel_status(h);
  7484. hpsa_drain_accel_commands(h);
  7485. /* Set 'accelerator path config change' bit */
  7486. dev_warn(&h->pdev->dev,
  7487. "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
  7488. h->events, event_type);
  7489. writel(h->events, &(h->cfgtable->clear_event_notify));
  7490. /* Set the "clear event notify field update" bit 6 */
  7491. writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
  7492. /* Wait until ctlr clears 'clear event notify field', bit 6 */
  7493. hpsa_wait_for_clear_event_notify_ack(h);
  7494. scsi_unblock_requests(h->scsi_host);
  7495. } else {
  7496. /* Acknowledge controller notification events. */
  7497. writel(h->events, &(h->cfgtable->clear_event_notify));
  7498. writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
  7499. hpsa_wait_for_clear_event_notify_ack(h);
  7500. }
  7501. return;
  7502. }
  7503. /* Check a register on the controller to see if there are configuration
  7504. * changes (added/changed/removed logical drives, etc.) which mean that
  7505. * we should rescan the controller for devices.
  7506. * Also check flag for driver-initiated rescan.
  7507. */
  7508. static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
  7509. {
  7510. if (h->drv_req_rescan) {
  7511. h->drv_req_rescan = 0;
  7512. return 1;
  7513. }
  7514. if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
  7515. return 0;
  7516. h->events = readl(&(h->cfgtable->event_notify));
  7517. return h->events & RESCAN_REQUIRED_EVENT_BITS;
  7518. }
  7519. /*
  7520. * Check if any of the offline devices have become ready
  7521. */
  7522. static int hpsa_offline_devices_ready(struct ctlr_info *h)
  7523. {
  7524. unsigned long flags;
  7525. struct offline_device_entry *d;
  7526. struct list_head *this, *tmp;
  7527. spin_lock_irqsave(&h->offline_device_lock, flags);
  7528. list_for_each_safe(this, tmp, &h->offline_device_list) {
  7529. d = list_entry(this, struct offline_device_entry,
  7530. offline_list);
  7531. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7532. if (!hpsa_volume_offline(h, d->scsi3addr)) {
  7533. spin_lock_irqsave(&h->offline_device_lock, flags);
  7534. list_del(&d->offline_list);
  7535. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7536. return 1;
  7537. }
  7538. spin_lock_irqsave(&h->offline_device_lock, flags);
  7539. }
  7540. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7541. return 0;
  7542. }
  7543. static int hpsa_luns_changed(struct ctlr_info *h)
  7544. {
  7545. int rc = 1; /* assume there are changes */
  7546. struct ReportLUNdata *logdev = NULL;
  7547. /* if we can't find out if lun data has changed,
  7548. * assume that it has.
  7549. */
  7550. if (!h->lastlogicals)
  7551. return rc;
  7552. logdev = kzalloc_obj(*logdev);
  7553. if (!logdev)
  7554. return rc;
  7555. if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
  7556. dev_warn(&h->pdev->dev,
  7557. "report luns failed, can't track lun changes.\n");
  7558. goto out;
  7559. }
  7560. if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
  7561. dev_info(&h->pdev->dev,
  7562. "Lun changes detected.\n");
  7563. memcpy(h->lastlogicals, logdev, sizeof(*logdev));
  7564. goto out;
  7565. } else
  7566. rc = 0; /* no changes detected. */
  7567. out:
  7568. kfree(logdev);
  7569. return rc;
  7570. }
  7571. static void hpsa_perform_rescan(struct ctlr_info *h)
  7572. {
  7573. struct Scsi_Host *sh = NULL;
  7574. unsigned long flags;
  7575. /*
  7576. * Do the scan after the reset
  7577. */
  7578. spin_lock_irqsave(&h->reset_lock, flags);
  7579. if (h->reset_in_progress) {
  7580. h->drv_req_rescan = 1;
  7581. spin_unlock_irqrestore(&h->reset_lock, flags);
  7582. return;
  7583. }
  7584. spin_unlock_irqrestore(&h->reset_lock, flags);
  7585. sh = scsi_host_get(h->scsi_host);
  7586. if (sh != NULL) {
  7587. hpsa_scan_start(sh);
  7588. scsi_host_put(sh);
  7589. h->drv_req_rescan = 0;
  7590. }
  7591. }
  7592. /*
  7593. * watch for controller events
  7594. */
  7595. static void hpsa_event_monitor_worker(struct work_struct *work)
  7596. {
  7597. struct ctlr_info *h = container_of(to_delayed_work(work),
  7598. struct ctlr_info, event_monitor_work);
  7599. unsigned long flags;
  7600. spin_lock_irqsave(&h->lock, flags);
  7601. if (h->remove_in_progress) {
  7602. spin_unlock_irqrestore(&h->lock, flags);
  7603. return;
  7604. }
  7605. spin_unlock_irqrestore(&h->lock, flags);
  7606. if (hpsa_ctlr_needs_rescan(h)) {
  7607. hpsa_ack_ctlr_events(h);
  7608. hpsa_perform_rescan(h);
  7609. }
  7610. spin_lock_irqsave(&h->lock, flags);
  7611. if (!h->remove_in_progress)
  7612. queue_delayed_work(h->monitor_ctlr_wq, &h->event_monitor_work,
  7613. HPSA_EVENT_MONITOR_INTERVAL);
  7614. spin_unlock_irqrestore(&h->lock, flags);
  7615. }
  7616. static void hpsa_rescan_ctlr_worker(struct work_struct *work)
  7617. {
  7618. unsigned long flags;
  7619. struct ctlr_info *h = container_of(to_delayed_work(work),
  7620. struct ctlr_info, rescan_ctlr_work);
  7621. spin_lock_irqsave(&h->lock, flags);
  7622. if (h->remove_in_progress) {
  7623. spin_unlock_irqrestore(&h->lock, flags);
  7624. return;
  7625. }
  7626. spin_unlock_irqrestore(&h->lock, flags);
  7627. if (h->drv_req_rescan || hpsa_offline_devices_ready(h)) {
  7628. hpsa_perform_rescan(h);
  7629. } else if (h->discovery_polling) {
  7630. if (hpsa_luns_changed(h)) {
  7631. dev_info(&h->pdev->dev,
  7632. "driver discovery polling rescan.\n");
  7633. hpsa_perform_rescan(h);
  7634. }
  7635. }
  7636. spin_lock_irqsave(&h->lock, flags);
  7637. if (!h->remove_in_progress)
  7638. queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
  7639. h->heartbeat_sample_interval);
  7640. spin_unlock_irqrestore(&h->lock, flags);
  7641. }
  7642. static void hpsa_monitor_ctlr_worker(struct work_struct *work)
  7643. {
  7644. unsigned long flags;
  7645. struct ctlr_info *h = container_of(to_delayed_work(work),
  7646. struct ctlr_info, monitor_ctlr_work);
  7647. detect_controller_lockup(h);
  7648. if (lockup_detected(h))
  7649. return;
  7650. spin_lock_irqsave(&h->lock, flags);
  7651. if (!h->remove_in_progress)
  7652. queue_delayed_work(h->monitor_ctlr_wq, &h->monitor_ctlr_work,
  7653. h->heartbeat_sample_interval);
  7654. spin_unlock_irqrestore(&h->lock, flags);
  7655. }
  7656. static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
  7657. char *name)
  7658. {
  7659. struct workqueue_struct *wq = NULL;
  7660. wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
  7661. if (!wq)
  7662. dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
  7663. return wq;
  7664. }
  7665. static void hpda_free_ctlr_info(struct ctlr_info *h)
  7666. {
  7667. kfree(h->reply_map);
  7668. kfree(h);
  7669. }
  7670. static struct ctlr_info *hpda_alloc_ctlr_info(void)
  7671. {
  7672. struct ctlr_info *h;
  7673. h = kzalloc_obj(*h);
  7674. if (!h)
  7675. return NULL;
  7676. h->reply_map = kcalloc(nr_cpu_ids, sizeof(*h->reply_map), GFP_KERNEL);
  7677. if (!h->reply_map) {
  7678. kfree(h);
  7679. return NULL;
  7680. }
  7681. return h;
  7682. }
  7683. static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  7684. {
  7685. int rc;
  7686. struct ctlr_info *h;
  7687. int try_soft_reset = 0;
  7688. unsigned long flags;
  7689. u32 board_id;
  7690. if (number_of_controllers == 0)
  7691. printk(KERN_INFO DRIVER_NAME "\n");
  7692. rc = hpsa_lookup_board_id(pdev, &board_id, NULL);
  7693. if (rc < 0) {
  7694. dev_warn(&pdev->dev, "Board ID not found\n");
  7695. return rc;
  7696. }
  7697. rc = hpsa_init_reset_devices(pdev, board_id);
  7698. if (rc) {
  7699. if (rc != -ENOTSUPP)
  7700. return rc;
  7701. /* If the reset fails in a particular way (it has no way to do
  7702. * a proper hard reset, so returns -ENOTSUPP) we can try to do
  7703. * a soft reset once we get the controller configured up to the
  7704. * point that it can accept a command.
  7705. */
  7706. try_soft_reset = 1;
  7707. rc = 0;
  7708. }
  7709. reinit_after_soft_reset:
  7710. /* Command structures must be aligned on a 32-byte boundary because
  7711. * the 5 lower bits of the address are used by the hardware. and by
  7712. * the driver. See comments in hpsa.h for more info.
  7713. */
  7714. BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
  7715. h = hpda_alloc_ctlr_info();
  7716. if (!h) {
  7717. dev_err(&pdev->dev, "Failed to allocate controller head\n");
  7718. return -ENOMEM;
  7719. }
  7720. h->pdev = pdev;
  7721. h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
  7722. INIT_LIST_HEAD(&h->offline_device_list);
  7723. spin_lock_init(&h->lock);
  7724. spin_lock_init(&h->offline_device_lock);
  7725. spin_lock_init(&h->scan_lock);
  7726. spin_lock_init(&h->reset_lock);
  7727. atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
  7728. /* Allocate and clear per-cpu variable lockup_detected */
  7729. h->lockup_detected = alloc_percpu(u32);
  7730. if (!h->lockup_detected) {
  7731. dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
  7732. rc = -ENOMEM;
  7733. goto clean1; /* aer/h */
  7734. }
  7735. set_lockup_detected_for_all_cpus(h, 0);
  7736. rc = hpsa_pci_init(h);
  7737. if (rc)
  7738. goto clean2; /* lu, aer/h */
  7739. /* relies on h-> settings made by hpsa_pci_init, including
  7740. * interrupt_mode h->intr */
  7741. rc = hpsa_scsi_host_alloc(h);
  7742. if (rc)
  7743. goto clean2_5; /* pci, lu, aer/h */
  7744. sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
  7745. h->ctlr = number_of_controllers;
  7746. number_of_controllers++;
  7747. /* configure PCI DMA stuff */
  7748. rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
  7749. if (rc != 0) {
  7750. rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  7751. if (rc != 0) {
  7752. dev_err(&pdev->dev, "no suitable DMA available\n");
  7753. goto clean3; /* shost, pci, lu, aer/h */
  7754. }
  7755. }
  7756. /* make sure the board interrupts are off */
  7757. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7758. rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
  7759. if (rc)
  7760. goto clean3; /* shost, pci, lu, aer/h */
  7761. rc = hpsa_alloc_cmd_pool(h);
  7762. if (rc)
  7763. goto clean4; /* irq, shost, pci, lu, aer/h */
  7764. rc = hpsa_alloc_sg_chain_blocks(h);
  7765. if (rc)
  7766. goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
  7767. init_waitqueue_head(&h->scan_wait_queue);
  7768. init_waitqueue_head(&h->event_sync_wait_queue);
  7769. mutex_init(&h->reset_mutex);
  7770. h->scan_finished = 1; /* no scan currently in progress */
  7771. h->scan_waiting = 0;
  7772. pci_set_drvdata(pdev, h);
  7773. h->ndevices = 0;
  7774. spin_lock_init(&h->devlock);
  7775. rc = hpsa_put_ctlr_into_performant_mode(h);
  7776. if (rc)
  7777. goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
  7778. /* create the resubmit workqueue */
  7779. h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
  7780. if (!h->rescan_ctlr_wq) {
  7781. rc = -ENOMEM;
  7782. goto clean7;
  7783. }
  7784. h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
  7785. if (!h->resubmit_wq) {
  7786. rc = -ENOMEM;
  7787. goto clean7; /* aer/h */
  7788. }
  7789. h->monitor_ctlr_wq = hpsa_create_controller_wq(h, "monitor");
  7790. if (!h->monitor_ctlr_wq) {
  7791. rc = -ENOMEM;
  7792. goto clean7;
  7793. }
  7794. /*
  7795. * At this point, the controller is ready to take commands.
  7796. * Now, if reset_devices and the hard reset didn't work, try
  7797. * the soft reset and see if that works.
  7798. */
  7799. if (try_soft_reset) {
  7800. /* This is kind of gross. We may or may not get a completion
  7801. * from the soft reset command, and if we do, then the value
  7802. * from the fifo may or may not be valid. So, we wait 10 secs
  7803. * after the reset throwing away any completions we get during
  7804. * that time. Unregister the interrupt handler and register
  7805. * fake ones to scoop up any residual completions.
  7806. */
  7807. spin_lock_irqsave(&h->lock, flags);
  7808. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7809. spin_unlock_irqrestore(&h->lock, flags);
  7810. hpsa_free_irqs(h);
  7811. rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
  7812. hpsa_intx_discard_completions);
  7813. if (rc) {
  7814. dev_warn(&h->pdev->dev,
  7815. "Failed to request_irq after soft reset.\n");
  7816. /*
  7817. * cannot goto clean7 or free_irqs will be called
  7818. * again. Instead, do its work
  7819. */
  7820. hpsa_free_performant_mode(h); /* clean7 */
  7821. hpsa_free_sg_chain_blocks(h); /* clean6 */
  7822. hpsa_free_cmd_pool(h); /* clean5 */
  7823. /*
  7824. * skip hpsa_free_irqs(h) clean4 since that
  7825. * was just called before request_irqs failed
  7826. */
  7827. goto clean3;
  7828. }
  7829. rc = hpsa_kdump_soft_reset(h);
  7830. if (rc)
  7831. /* Neither hard nor soft reset worked, we're hosed. */
  7832. goto clean7;
  7833. dev_info(&h->pdev->dev, "Board READY.\n");
  7834. dev_info(&h->pdev->dev,
  7835. "Waiting for stale completions to drain.\n");
  7836. h->access.set_intr_mask(h, HPSA_INTR_ON);
  7837. msleep(10000);
  7838. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7839. rc = controller_reset_failed(h->cfgtable);
  7840. if (rc)
  7841. dev_info(&h->pdev->dev,
  7842. "Soft reset appears to have failed.\n");
  7843. /* since the controller's reset, we have to go back and re-init
  7844. * everything. Easiest to just forget what we've done and do it
  7845. * all over again.
  7846. */
  7847. hpsa_undo_allocations_after_kdump_soft_reset(h);
  7848. try_soft_reset = 0;
  7849. if (rc)
  7850. /* don't goto clean, we already unallocated */
  7851. return -ENODEV;
  7852. goto reinit_after_soft_reset;
  7853. }
  7854. /* Enable Accelerated IO path at driver layer */
  7855. h->acciopath_status = 1;
  7856. /* Disable discovery polling.*/
  7857. h->discovery_polling = 0;
  7858. /* Turn the interrupts on so we can service requests */
  7859. h->access.set_intr_mask(h, HPSA_INTR_ON);
  7860. hpsa_hba_inquiry(h);
  7861. h->lastlogicals = kzalloc_obj(*(h->lastlogicals));
  7862. if (!h->lastlogicals)
  7863. dev_info(&h->pdev->dev,
  7864. "Can't track change to report lun data\n");
  7865. /* hook into SCSI subsystem */
  7866. rc = hpsa_scsi_add_host(h);
  7867. if (rc)
  7868. goto clean8; /* lastlogicals, perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7869. /* Monitor the controller for firmware lockups */
  7870. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  7871. INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
  7872. schedule_delayed_work(&h->monitor_ctlr_work,
  7873. h->heartbeat_sample_interval);
  7874. INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
  7875. queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
  7876. h->heartbeat_sample_interval);
  7877. INIT_DELAYED_WORK(&h->event_monitor_work, hpsa_event_monitor_worker);
  7878. schedule_delayed_work(&h->event_monitor_work,
  7879. HPSA_EVENT_MONITOR_INTERVAL);
  7880. return 0;
  7881. clean8: /* lastlogicals, perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7882. kfree(h->lastlogicals);
  7883. clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7884. hpsa_free_performant_mode(h);
  7885. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7886. clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
  7887. hpsa_free_sg_chain_blocks(h);
  7888. clean5: /* cmd, irq, shost, pci, lu, aer/h */
  7889. hpsa_free_cmd_pool(h);
  7890. clean4: /* irq, shost, pci, lu, aer/h */
  7891. hpsa_free_irqs(h);
  7892. clean3: /* shost, pci, lu, aer/h */
  7893. scsi_host_put(h->scsi_host);
  7894. h->scsi_host = NULL;
  7895. clean2_5: /* pci, lu, aer/h */
  7896. hpsa_free_pci_init(h);
  7897. clean2: /* lu, aer/h */
  7898. if (h->lockup_detected) {
  7899. free_percpu(h->lockup_detected);
  7900. h->lockup_detected = NULL;
  7901. }
  7902. clean1: /* wq/aer/h */
  7903. if (h->resubmit_wq) {
  7904. destroy_workqueue(h->resubmit_wq);
  7905. h->resubmit_wq = NULL;
  7906. }
  7907. if (h->rescan_ctlr_wq) {
  7908. destroy_workqueue(h->rescan_ctlr_wq);
  7909. h->rescan_ctlr_wq = NULL;
  7910. }
  7911. if (h->monitor_ctlr_wq) {
  7912. destroy_workqueue(h->monitor_ctlr_wq);
  7913. h->monitor_ctlr_wq = NULL;
  7914. }
  7915. hpda_free_ctlr_info(h);
  7916. return rc;
  7917. }
  7918. static void hpsa_flush_cache(struct ctlr_info *h)
  7919. {
  7920. char *flush_buf;
  7921. struct CommandList *c;
  7922. int rc;
  7923. if (unlikely(lockup_detected(h)))
  7924. return;
  7925. flush_buf = kzalloc(4, GFP_KERNEL);
  7926. if (!flush_buf)
  7927. return;
  7928. c = cmd_alloc(h);
  7929. if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
  7930. RAID_CTLR_LUNID, TYPE_CMD)) {
  7931. goto out;
  7932. }
  7933. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE,
  7934. DEFAULT_TIMEOUT);
  7935. if (rc)
  7936. goto out;
  7937. if (c->err_info->CommandStatus != 0)
  7938. out:
  7939. dev_warn(&h->pdev->dev,
  7940. "error flushing cache on controller\n");
  7941. cmd_free(h, c);
  7942. kfree(flush_buf);
  7943. }
  7944. /* Make controller gather fresh report lun data each time we
  7945. * send down a report luns request
  7946. */
  7947. static void hpsa_disable_rld_caching(struct ctlr_info *h)
  7948. {
  7949. u32 *options;
  7950. struct CommandList *c;
  7951. int rc;
  7952. /* Don't bother trying to set diag options if locked up */
  7953. if (unlikely(h->lockup_detected))
  7954. return;
  7955. options = kzalloc_obj(*options);
  7956. if (!options)
  7957. return;
  7958. c = cmd_alloc(h);
  7959. /* first, get the current diag options settings */
  7960. if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
  7961. RAID_CTLR_LUNID, TYPE_CMD))
  7962. goto errout;
  7963. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  7964. NO_TIMEOUT);
  7965. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  7966. goto errout;
  7967. /* Now, set the bit for disabling the RLD caching */
  7968. *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
  7969. if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
  7970. RAID_CTLR_LUNID, TYPE_CMD))
  7971. goto errout;
  7972. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE,
  7973. NO_TIMEOUT);
  7974. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  7975. goto errout;
  7976. /* Now verify that it got set: */
  7977. if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
  7978. RAID_CTLR_LUNID, TYPE_CMD))
  7979. goto errout;
  7980. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  7981. NO_TIMEOUT);
  7982. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  7983. goto errout;
  7984. if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
  7985. goto out;
  7986. errout:
  7987. dev_err(&h->pdev->dev,
  7988. "Error: failed to disable report lun data caching.\n");
  7989. out:
  7990. cmd_free(h, c);
  7991. kfree(options);
  7992. }
  7993. static void __hpsa_shutdown(struct pci_dev *pdev)
  7994. {
  7995. struct ctlr_info *h;
  7996. h = pci_get_drvdata(pdev);
  7997. /* Turn board interrupts off and send the flush cache command
  7998. * sendcmd will turn off interrupt, and send the flush...
  7999. * To write all data in the battery backed cache to disks
  8000. */
  8001. hpsa_flush_cache(h);
  8002. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  8003. hpsa_free_irqs(h); /* init_one 4 */
  8004. hpsa_disable_interrupt_mode(h); /* pci_init 2 */
  8005. }
  8006. static void hpsa_shutdown(struct pci_dev *pdev)
  8007. {
  8008. __hpsa_shutdown(pdev);
  8009. pci_disable_device(pdev);
  8010. }
  8011. static void hpsa_free_device_info(struct ctlr_info *h)
  8012. {
  8013. int i;
  8014. for (i = 0; i < h->ndevices; i++) {
  8015. kfree(h->dev[i]);
  8016. h->dev[i] = NULL;
  8017. }
  8018. }
  8019. static void hpsa_remove_one(struct pci_dev *pdev)
  8020. {
  8021. struct ctlr_info *h;
  8022. unsigned long flags;
  8023. if (pci_get_drvdata(pdev) == NULL) {
  8024. dev_err(&pdev->dev, "unable to remove device\n");
  8025. return;
  8026. }
  8027. h = pci_get_drvdata(pdev);
  8028. /* Get rid of any controller monitoring work items */
  8029. spin_lock_irqsave(&h->lock, flags);
  8030. h->remove_in_progress = 1;
  8031. spin_unlock_irqrestore(&h->lock, flags);
  8032. cancel_delayed_work_sync(&h->monitor_ctlr_work);
  8033. cancel_delayed_work_sync(&h->rescan_ctlr_work);
  8034. cancel_delayed_work_sync(&h->event_monitor_work);
  8035. destroy_workqueue(h->rescan_ctlr_wq);
  8036. destroy_workqueue(h->resubmit_wq);
  8037. destroy_workqueue(h->monitor_ctlr_wq);
  8038. hpsa_delete_sas_host(h);
  8039. /*
  8040. * Call before disabling interrupts.
  8041. * scsi_remove_host can trigger I/O operations especially
  8042. * when multipath is enabled. There can be SYNCHRONIZE CACHE
  8043. * operations which cannot complete and will hang the system.
  8044. */
  8045. if (h->scsi_host)
  8046. scsi_remove_host(h->scsi_host); /* init_one 8 */
  8047. /* includes hpsa_free_irqs - init_one 4 */
  8048. /* includes hpsa_disable_interrupt_mode - pci_init 2 */
  8049. __hpsa_shutdown(pdev);
  8050. hpsa_free_device_info(h); /* scan */
  8051. kfree(h->hba_inquiry_data); /* init_one 10 */
  8052. h->hba_inquiry_data = NULL; /* init_one 10 */
  8053. hpsa_free_ioaccel2_sg_chain_blocks(h);
  8054. hpsa_free_performant_mode(h); /* init_one 7 */
  8055. hpsa_free_sg_chain_blocks(h); /* init_one 6 */
  8056. hpsa_free_cmd_pool(h); /* init_one 5 */
  8057. kfree(h->lastlogicals);
  8058. /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
  8059. scsi_host_put(h->scsi_host); /* init_one 3 */
  8060. h->scsi_host = NULL; /* init_one 3 */
  8061. /* includes hpsa_disable_interrupt_mode - pci_init 2 */
  8062. hpsa_free_pci_init(h); /* init_one 2.5 */
  8063. free_percpu(h->lockup_detected); /* init_one 2 */
  8064. h->lockup_detected = NULL; /* init_one 2 */
  8065. hpda_free_ctlr_info(h); /* init_one 1 */
  8066. }
  8067. static int __maybe_unused hpsa_suspend(
  8068. __attribute__((unused)) struct device *dev)
  8069. {
  8070. return -ENOSYS;
  8071. }
  8072. static int __maybe_unused hpsa_resume
  8073. (__attribute__((unused)) struct device *dev)
  8074. {
  8075. return -ENOSYS;
  8076. }
  8077. static SIMPLE_DEV_PM_OPS(hpsa_pm_ops, hpsa_suspend, hpsa_resume);
  8078. static struct pci_driver hpsa_pci_driver = {
  8079. .name = HPSA,
  8080. .probe = hpsa_init_one,
  8081. .remove = hpsa_remove_one,
  8082. .id_table = hpsa_pci_device_id, /* id_table */
  8083. .shutdown = hpsa_shutdown,
  8084. .driver.pm = &hpsa_pm_ops,
  8085. };
  8086. /* Fill in bucket_map[], given nsgs (the max number of
  8087. * scatter gather elements supported) and bucket[],
  8088. * which is an array of 8 integers. The bucket[] array
  8089. * contains 8 different DMA transfer sizes (in 16
  8090. * byte increments) which the controller uses to fetch
  8091. * commands. This function fills in bucket_map[], which
  8092. * maps a given number of scatter gather elements to one of
  8093. * the 8 DMA transfer sizes. The point of it is to allow the
  8094. * controller to only do as much DMA as needed to fetch the
  8095. * command, with the DMA transfer size encoded in the lower
  8096. * bits of the command address.
  8097. */
  8098. static void calc_bucket_map(int bucket[], int num_buckets,
  8099. int nsgs, int min_blocks, u32 *bucket_map)
  8100. {
  8101. int i, j, b, size;
  8102. /* Note, bucket_map must have nsgs+1 entries. */
  8103. for (i = 0; i <= nsgs; i++) {
  8104. /* Compute size of a command with i SG entries */
  8105. size = i + min_blocks;
  8106. b = num_buckets; /* Assume the biggest bucket */
  8107. /* Find the bucket that is just big enough */
  8108. for (j = 0; j < num_buckets; j++) {
  8109. if (bucket[j] >= size) {
  8110. b = j;
  8111. break;
  8112. }
  8113. }
  8114. /* for a command with i SG entries, use bucket b. */
  8115. bucket_map[i] = b;
  8116. }
  8117. }
  8118. /*
  8119. * return -ENODEV on err, 0 on success (or no action)
  8120. * allocates numerous items that must be freed later
  8121. */
  8122. static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
  8123. {
  8124. int i;
  8125. unsigned long register_value;
  8126. unsigned long transMethod = CFGTBL_Trans_Performant |
  8127. (trans_support & CFGTBL_Trans_use_short_tags) |
  8128. CFGTBL_Trans_enable_directed_msix |
  8129. (trans_support & (CFGTBL_Trans_io_accel1 |
  8130. CFGTBL_Trans_io_accel2));
  8131. struct access_method access = SA5_performant_access;
  8132. /* This is a bit complicated. There are 8 registers on
  8133. * the controller which we write to to tell it 8 different
  8134. * sizes of commands which there may be. It's a way of
  8135. * reducing the DMA done to fetch each command. Encoded into
  8136. * each command's tag are 3 bits which communicate to the controller
  8137. * which of the eight sizes that command fits within. The size of
  8138. * each command depends on how many scatter gather entries there are.
  8139. * Each SG entry requires 16 bytes. The eight registers are programmed
  8140. * with the number of 16-byte blocks a command of that size requires.
  8141. * The smallest command possible requires 5 such 16 byte blocks.
  8142. * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
  8143. * blocks. Note, this only extends to the SG entries contained
  8144. * within the command block, and does not extend to chained blocks
  8145. * of SG elements. bft[] contains the eight values we write to
  8146. * the registers. They are not evenly distributed, but have more
  8147. * sizes for small commands, and fewer sizes for larger commands.
  8148. */
  8149. int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
  8150. #define MIN_IOACCEL2_BFT_ENTRY 5
  8151. #define HPSA_IOACCEL2_HEADER_SZ 4
  8152. int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
  8153. 13, 14, 15, 16, 17, 18, 19,
  8154. HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
  8155. BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
  8156. BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
  8157. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
  8158. 16 * MIN_IOACCEL2_BFT_ENTRY);
  8159. BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
  8160. BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
  8161. /* 5 = 1 s/g entry or 4k
  8162. * 6 = 2 s/g entry or 8k
  8163. * 8 = 4 s/g entry or 16k
  8164. * 10 = 6 s/g entry or 24k
  8165. */
  8166. /* If the controller supports either ioaccel method then
  8167. * we can also use the RAID stack submit path that does not
  8168. * perform the superfluous readl() after each command submission.
  8169. */
  8170. if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
  8171. access = SA5_performant_access_no_read;
  8172. /* Controller spec: zero out this buffer. */
  8173. for (i = 0; i < h->nreply_queues; i++)
  8174. memset(h->reply_queue[i].head, 0, h->reply_queue_size);
  8175. bft[7] = SG_ENTRIES_IN_CMD + 4;
  8176. calc_bucket_map(bft, ARRAY_SIZE(bft),
  8177. SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
  8178. for (i = 0; i < 8; i++)
  8179. writel(bft[i], &h->transtable->BlockFetch[i]);
  8180. /* size of controller ring buffer */
  8181. writel(h->max_commands, &h->transtable->RepQSize);
  8182. writel(h->nreply_queues, &h->transtable->RepQCount);
  8183. writel(0, &h->transtable->RepQCtrAddrLow32);
  8184. writel(0, &h->transtable->RepQCtrAddrHigh32);
  8185. for (i = 0; i < h->nreply_queues; i++) {
  8186. writel(0, &h->transtable->RepQAddr[i].upper);
  8187. writel(h->reply_queue[i].busaddr,
  8188. &h->transtable->RepQAddr[i].lower);
  8189. }
  8190. writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
  8191. writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
  8192. /*
  8193. * enable outbound interrupt coalescing in accelerator mode;
  8194. */
  8195. if (trans_support & CFGTBL_Trans_io_accel1) {
  8196. access = SA5_ioaccel_mode1_access;
  8197. writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
  8198. writel(4, &h->cfgtable->HostWrite.CoalIntCount);
  8199. } else
  8200. if (trans_support & CFGTBL_Trans_io_accel2)
  8201. access = SA5_ioaccel_mode2_access;
  8202. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  8203. if (hpsa_wait_for_mode_change_ack(h)) {
  8204. dev_err(&h->pdev->dev,
  8205. "performant mode problem - doorbell timeout\n");
  8206. return -ENODEV;
  8207. }
  8208. register_value = readl(&(h->cfgtable->TransportActive));
  8209. if (!(register_value & CFGTBL_Trans_Performant)) {
  8210. dev_err(&h->pdev->dev,
  8211. "performant mode problem - transport not active\n");
  8212. return -ENODEV;
  8213. }
  8214. /* Change the access methods to the performant access methods */
  8215. h->access = access;
  8216. h->transMethod = transMethod;
  8217. if (!((trans_support & CFGTBL_Trans_io_accel1) ||
  8218. (trans_support & CFGTBL_Trans_io_accel2)))
  8219. return 0;
  8220. if (trans_support & CFGTBL_Trans_io_accel1) {
  8221. /* Set up I/O accelerator mode */
  8222. for (i = 0; i < h->nreply_queues; i++) {
  8223. writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
  8224. h->reply_queue[i].current_entry =
  8225. readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
  8226. }
  8227. bft[7] = h->ioaccel_maxsg + 8;
  8228. calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
  8229. h->ioaccel1_blockFetchTable);
  8230. /* initialize all reply queue entries to unused */
  8231. for (i = 0; i < h->nreply_queues; i++)
  8232. memset(h->reply_queue[i].head,
  8233. (u8) IOACCEL_MODE1_REPLY_UNUSED,
  8234. h->reply_queue_size);
  8235. /* set all the constant fields in the accelerator command
  8236. * frames once at init time to save CPU cycles later.
  8237. */
  8238. for (i = 0; i < h->nr_cmds; i++) {
  8239. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
  8240. cp->function = IOACCEL1_FUNCTION_SCSIIO;
  8241. cp->err_info = (u32) (h->errinfo_pool_dhandle +
  8242. (i * sizeof(struct ErrorInfo)));
  8243. cp->err_info_len = sizeof(struct ErrorInfo);
  8244. cp->sgl_offset = IOACCEL1_SGLOFFSET;
  8245. cp->host_context_flags =
  8246. cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
  8247. cp->timeout_sec = 0;
  8248. cp->ReplyQueue = 0;
  8249. cp->tag =
  8250. cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
  8251. cp->host_addr =
  8252. cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
  8253. (i * sizeof(struct io_accel1_cmd)));
  8254. }
  8255. } else if (trans_support & CFGTBL_Trans_io_accel2) {
  8256. u64 cfg_offset, cfg_base_addr_index;
  8257. u32 bft2_offset, cfg_base_addr;
  8258. hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  8259. &cfg_base_addr_index, &cfg_offset);
  8260. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
  8261. bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
  8262. calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
  8263. 4, h->ioaccel2_blockFetchTable);
  8264. bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
  8265. BUILD_BUG_ON(offsetof(struct CfgTable,
  8266. io_accel_request_size_offset) != 0xb8);
  8267. h->ioaccel2_bft2_regs =
  8268. remap_pci_mem(pci_resource_start(h->pdev,
  8269. cfg_base_addr_index) +
  8270. cfg_offset + bft2_offset,
  8271. ARRAY_SIZE(bft2) *
  8272. sizeof(*h->ioaccel2_bft2_regs));
  8273. for (i = 0; i < ARRAY_SIZE(bft2); i++)
  8274. writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
  8275. }
  8276. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  8277. if (hpsa_wait_for_mode_change_ack(h)) {
  8278. dev_err(&h->pdev->dev,
  8279. "performant mode problem - enabling ioaccel mode\n");
  8280. return -ENODEV;
  8281. }
  8282. return 0;
  8283. }
  8284. /* Free ioaccel1 mode command blocks and block fetch table */
  8285. static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
  8286. {
  8287. if (h->ioaccel_cmd_pool) {
  8288. dma_free_coherent(&h->pdev->dev,
  8289. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
  8290. h->ioaccel_cmd_pool,
  8291. h->ioaccel_cmd_pool_dhandle);
  8292. h->ioaccel_cmd_pool = NULL;
  8293. h->ioaccel_cmd_pool_dhandle = 0;
  8294. }
  8295. kfree(h->ioaccel1_blockFetchTable);
  8296. h->ioaccel1_blockFetchTable = NULL;
  8297. }
  8298. /* Allocate ioaccel1 mode command blocks and block fetch table */
  8299. static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
  8300. {
  8301. h->ioaccel_maxsg =
  8302. readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
  8303. if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
  8304. h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
  8305. /* Command structures must be aligned on a 128-byte boundary
  8306. * because the 7 lower bits of the address are used by the
  8307. * hardware.
  8308. */
  8309. BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
  8310. IOACCEL1_COMMANDLIST_ALIGNMENT);
  8311. h->ioaccel_cmd_pool =
  8312. dma_alloc_coherent(&h->pdev->dev,
  8313. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
  8314. &h->ioaccel_cmd_pool_dhandle, GFP_KERNEL);
  8315. h->ioaccel1_blockFetchTable =
  8316. kmalloc(((h->ioaccel_maxsg + 1) *
  8317. sizeof(u32)), GFP_KERNEL);
  8318. if ((h->ioaccel_cmd_pool == NULL) ||
  8319. (h->ioaccel1_blockFetchTable == NULL))
  8320. goto clean_up;
  8321. memset(h->ioaccel_cmd_pool, 0,
  8322. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
  8323. return 0;
  8324. clean_up:
  8325. hpsa_free_ioaccel1_cmd_and_bft(h);
  8326. return -ENOMEM;
  8327. }
  8328. /* Free ioaccel2 mode command blocks and block fetch table */
  8329. static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
  8330. {
  8331. hpsa_free_ioaccel2_sg_chain_blocks(h);
  8332. if (h->ioaccel2_cmd_pool) {
  8333. dma_free_coherent(&h->pdev->dev,
  8334. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
  8335. h->ioaccel2_cmd_pool,
  8336. h->ioaccel2_cmd_pool_dhandle);
  8337. h->ioaccel2_cmd_pool = NULL;
  8338. h->ioaccel2_cmd_pool_dhandle = 0;
  8339. }
  8340. kfree(h->ioaccel2_blockFetchTable);
  8341. h->ioaccel2_blockFetchTable = NULL;
  8342. }
  8343. /* Allocate ioaccel2 mode command blocks and block fetch table */
  8344. static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
  8345. {
  8346. int rc;
  8347. /* Allocate ioaccel2 mode command blocks and block fetch table */
  8348. h->ioaccel_maxsg =
  8349. readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
  8350. if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
  8351. h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
  8352. BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
  8353. IOACCEL2_COMMANDLIST_ALIGNMENT);
  8354. h->ioaccel2_cmd_pool =
  8355. dma_alloc_coherent(&h->pdev->dev,
  8356. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
  8357. &h->ioaccel2_cmd_pool_dhandle, GFP_KERNEL);
  8358. h->ioaccel2_blockFetchTable =
  8359. kmalloc(((h->ioaccel_maxsg + 1) *
  8360. sizeof(u32)), GFP_KERNEL);
  8361. if ((h->ioaccel2_cmd_pool == NULL) ||
  8362. (h->ioaccel2_blockFetchTable == NULL)) {
  8363. rc = -ENOMEM;
  8364. goto clean_up;
  8365. }
  8366. rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
  8367. if (rc)
  8368. goto clean_up;
  8369. memset(h->ioaccel2_cmd_pool, 0,
  8370. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
  8371. return 0;
  8372. clean_up:
  8373. hpsa_free_ioaccel2_cmd_and_bft(h);
  8374. return rc;
  8375. }
  8376. /* Free items allocated by hpsa_put_ctlr_into_performant_mode */
  8377. static void hpsa_free_performant_mode(struct ctlr_info *h)
  8378. {
  8379. kfree(h->blockFetchTable);
  8380. h->blockFetchTable = NULL;
  8381. hpsa_free_reply_queues(h);
  8382. hpsa_free_ioaccel1_cmd_and_bft(h);
  8383. hpsa_free_ioaccel2_cmd_and_bft(h);
  8384. }
  8385. /* return -ENODEV on error, 0 on success (or no action)
  8386. * allocates numerous items that must be freed later
  8387. */
  8388. static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
  8389. {
  8390. u32 trans_support;
  8391. int i, rc;
  8392. if (hpsa_simple_mode)
  8393. return 0;
  8394. trans_support = readl(&(h->cfgtable->TransportSupport));
  8395. if (!(trans_support & PERFORMANT_MODE))
  8396. return 0;
  8397. /* Check for I/O accelerator mode support */
  8398. if (trans_support & CFGTBL_Trans_io_accel1) {
  8399. rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
  8400. if (rc)
  8401. return rc;
  8402. } else if (trans_support & CFGTBL_Trans_io_accel2) {
  8403. rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
  8404. if (rc)
  8405. return rc;
  8406. }
  8407. h->nreply_queues = h->msix_vectors > 0 ? h->msix_vectors : 1;
  8408. hpsa_get_max_perf_mode_cmds(h);
  8409. /* Performant mode ring buffer and supporting data structures */
  8410. h->reply_queue_size = h->max_commands * sizeof(u64);
  8411. for (i = 0; i < h->nreply_queues; i++) {
  8412. h->reply_queue[i].head = dma_alloc_coherent(&h->pdev->dev,
  8413. h->reply_queue_size,
  8414. &h->reply_queue[i].busaddr,
  8415. GFP_KERNEL);
  8416. if (!h->reply_queue[i].head) {
  8417. rc = -ENOMEM;
  8418. goto clean1; /* rq, ioaccel */
  8419. }
  8420. h->reply_queue[i].size = h->max_commands;
  8421. h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
  8422. h->reply_queue[i].current_entry = 0;
  8423. }
  8424. /* Need a block fetch table for performant mode */
  8425. h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
  8426. sizeof(u32)), GFP_KERNEL);
  8427. if (!h->blockFetchTable) {
  8428. rc = -ENOMEM;
  8429. goto clean1; /* rq, ioaccel */
  8430. }
  8431. rc = hpsa_enter_performant_mode(h, trans_support);
  8432. if (rc)
  8433. goto clean2; /* bft, rq, ioaccel */
  8434. return 0;
  8435. clean2: /* bft, rq, ioaccel */
  8436. kfree(h->blockFetchTable);
  8437. h->blockFetchTable = NULL;
  8438. clean1: /* rq, ioaccel */
  8439. hpsa_free_reply_queues(h);
  8440. hpsa_free_ioaccel1_cmd_and_bft(h);
  8441. hpsa_free_ioaccel2_cmd_and_bft(h);
  8442. return rc;
  8443. }
  8444. static int is_accelerated_cmd(struct CommandList *c)
  8445. {
  8446. return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
  8447. }
  8448. static void hpsa_drain_accel_commands(struct ctlr_info *h)
  8449. {
  8450. struct CommandList *c = NULL;
  8451. int i, accel_cmds_out;
  8452. int refcount;
  8453. do { /* wait for all outstanding ioaccel commands to drain out */
  8454. accel_cmds_out = 0;
  8455. for (i = 0; i < h->nr_cmds; i++) {
  8456. c = h->cmd_pool + i;
  8457. refcount = atomic_inc_return(&c->refcount);
  8458. if (refcount > 1) /* Command is allocated */
  8459. accel_cmds_out += is_accelerated_cmd(c);
  8460. cmd_free(h, c);
  8461. }
  8462. if (accel_cmds_out <= 0)
  8463. break;
  8464. msleep(100);
  8465. } while (1);
  8466. }
  8467. static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
  8468. struct hpsa_sas_port *hpsa_sas_port)
  8469. {
  8470. struct hpsa_sas_phy *hpsa_sas_phy;
  8471. struct sas_phy *phy;
  8472. hpsa_sas_phy = kzalloc_obj(*hpsa_sas_phy);
  8473. if (!hpsa_sas_phy)
  8474. return NULL;
  8475. phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
  8476. hpsa_sas_port->next_phy_index);
  8477. if (!phy) {
  8478. kfree(hpsa_sas_phy);
  8479. return NULL;
  8480. }
  8481. hpsa_sas_port->next_phy_index++;
  8482. hpsa_sas_phy->phy = phy;
  8483. hpsa_sas_phy->parent_port = hpsa_sas_port;
  8484. return hpsa_sas_phy;
  8485. }
  8486. static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
  8487. {
  8488. struct sas_phy *phy = hpsa_sas_phy->phy;
  8489. sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
  8490. if (hpsa_sas_phy->added_to_port)
  8491. list_del(&hpsa_sas_phy->phy_list_entry);
  8492. sas_phy_delete(phy);
  8493. kfree(hpsa_sas_phy);
  8494. }
  8495. static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
  8496. {
  8497. int rc;
  8498. struct hpsa_sas_port *hpsa_sas_port;
  8499. struct sas_phy *phy;
  8500. struct sas_identify *identify;
  8501. hpsa_sas_port = hpsa_sas_phy->parent_port;
  8502. phy = hpsa_sas_phy->phy;
  8503. identify = &phy->identify;
  8504. memset(identify, 0, sizeof(*identify));
  8505. identify->sas_address = hpsa_sas_port->sas_address;
  8506. identify->device_type = SAS_END_DEVICE;
  8507. identify->initiator_port_protocols = SAS_PROTOCOL_STP;
  8508. identify->target_port_protocols = SAS_PROTOCOL_STP;
  8509. phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
  8510. phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
  8511. phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
  8512. phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
  8513. phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
  8514. rc = sas_phy_add(hpsa_sas_phy->phy);
  8515. if (rc)
  8516. return rc;
  8517. sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
  8518. list_add_tail(&hpsa_sas_phy->phy_list_entry,
  8519. &hpsa_sas_port->phy_list_head);
  8520. hpsa_sas_phy->added_to_port = true;
  8521. return 0;
  8522. }
  8523. static int
  8524. hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
  8525. struct sas_rphy *rphy)
  8526. {
  8527. struct sas_identify *identify;
  8528. identify = &rphy->identify;
  8529. identify->sas_address = hpsa_sas_port->sas_address;
  8530. identify->initiator_port_protocols = SAS_PROTOCOL_STP;
  8531. identify->target_port_protocols = SAS_PROTOCOL_STP;
  8532. return sas_rphy_add(rphy);
  8533. }
  8534. static struct hpsa_sas_port
  8535. *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
  8536. u64 sas_address)
  8537. {
  8538. int rc;
  8539. struct hpsa_sas_port *hpsa_sas_port;
  8540. struct sas_port *port;
  8541. hpsa_sas_port = kzalloc_obj(*hpsa_sas_port);
  8542. if (!hpsa_sas_port)
  8543. return NULL;
  8544. INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
  8545. hpsa_sas_port->parent_node = hpsa_sas_node;
  8546. port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
  8547. if (!port)
  8548. goto free_hpsa_port;
  8549. rc = sas_port_add(port);
  8550. if (rc)
  8551. goto free_sas_port;
  8552. hpsa_sas_port->port = port;
  8553. hpsa_sas_port->sas_address = sas_address;
  8554. list_add_tail(&hpsa_sas_port->port_list_entry,
  8555. &hpsa_sas_node->port_list_head);
  8556. return hpsa_sas_port;
  8557. free_sas_port:
  8558. sas_port_free(port);
  8559. free_hpsa_port:
  8560. kfree(hpsa_sas_port);
  8561. return NULL;
  8562. }
  8563. static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
  8564. {
  8565. struct hpsa_sas_phy *hpsa_sas_phy;
  8566. struct hpsa_sas_phy *next;
  8567. list_for_each_entry_safe(hpsa_sas_phy, next,
  8568. &hpsa_sas_port->phy_list_head, phy_list_entry)
  8569. hpsa_free_sas_phy(hpsa_sas_phy);
  8570. sas_port_delete(hpsa_sas_port->port);
  8571. list_del(&hpsa_sas_port->port_list_entry);
  8572. kfree(hpsa_sas_port);
  8573. }
  8574. static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
  8575. {
  8576. struct hpsa_sas_node *hpsa_sas_node;
  8577. hpsa_sas_node = kzalloc_obj(*hpsa_sas_node);
  8578. if (hpsa_sas_node) {
  8579. hpsa_sas_node->parent_dev = parent_dev;
  8580. INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
  8581. }
  8582. return hpsa_sas_node;
  8583. }
  8584. static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
  8585. {
  8586. struct hpsa_sas_port *hpsa_sas_port;
  8587. struct hpsa_sas_port *next;
  8588. if (!hpsa_sas_node)
  8589. return;
  8590. list_for_each_entry_safe(hpsa_sas_port, next,
  8591. &hpsa_sas_node->port_list_head, port_list_entry)
  8592. hpsa_free_sas_port(hpsa_sas_port);
  8593. kfree(hpsa_sas_node);
  8594. }
  8595. static struct hpsa_scsi_dev_t
  8596. *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
  8597. struct sas_rphy *rphy)
  8598. {
  8599. int i;
  8600. struct hpsa_scsi_dev_t *device;
  8601. for (i = 0; i < h->ndevices; i++) {
  8602. device = h->dev[i];
  8603. if (!device->sas_port)
  8604. continue;
  8605. if (device->sas_port->rphy == rphy)
  8606. return device;
  8607. }
  8608. return NULL;
  8609. }
  8610. static int hpsa_add_sas_host(struct ctlr_info *h)
  8611. {
  8612. int rc;
  8613. struct device *parent_dev;
  8614. struct hpsa_sas_node *hpsa_sas_node;
  8615. struct hpsa_sas_port *hpsa_sas_port;
  8616. struct hpsa_sas_phy *hpsa_sas_phy;
  8617. parent_dev = &h->scsi_host->shost_dev;
  8618. hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
  8619. if (!hpsa_sas_node)
  8620. return -ENOMEM;
  8621. hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
  8622. if (!hpsa_sas_port) {
  8623. rc = -ENODEV;
  8624. goto free_sas_node;
  8625. }
  8626. hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
  8627. if (!hpsa_sas_phy) {
  8628. rc = -ENODEV;
  8629. goto free_sas_port;
  8630. }
  8631. rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
  8632. if (rc)
  8633. goto free_sas_phy;
  8634. h->sas_host = hpsa_sas_node;
  8635. return 0;
  8636. free_sas_phy:
  8637. sas_phy_free(hpsa_sas_phy->phy);
  8638. kfree(hpsa_sas_phy);
  8639. free_sas_port:
  8640. hpsa_free_sas_port(hpsa_sas_port);
  8641. free_sas_node:
  8642. hpsa_free_sas_node(hpsa_sas_node);
  8643. return rc;
  8644. }
  8645. static void hpsa_delete_sas_host(struct ctlr_info *h)
  8646. {
  8647. hpsa_free_sas_node(h->sas_host);
  8648. }
  8649. static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
  8650. struct hpsa_scsi_dev_t *device)
  8651. {
  8652. int rc;
  8653. struct hpsa_sas_port *hpsa_sas_port;
  8654. struct sas_rphy *rphy;
  8655. hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
  8656. if (!hpsa_sas_port)
  8657. return -ENOMEM;
  8658. rphy = sas_end_device_alloc(hpsa_sas_port->port);
  8659. if (!rphy) {
  8660. rc = -ENODEV;
  8661. goto free_sas_port;
  8662. }
  8663. hpsa_sas_port->rphy = rphy;
  8664. device->sas_port = hpsa_sas_port;
  8665. rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
  8666. if (rc)
  8667. goto free_sas_rphy;
  8668. return 0;
  8669. free_sas_rphy:
  8670. sas_rphy_free(rphy);
  8671. free_sas_port:
  8672. hpsa_free_sas_port(hpsa_sas_port);
  8673. device->sas_port = NULL;
  8674. return rc;
  8675. }
  8676. static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
  8677. {
  8678. if (device->sas_port) {
  8679. hpsa_free_sas_port(device->sas_port);
  8680. device->sas_port = NULL;
  8681. }
  8682. }
  8683. static int
  8684. hpsa_sas_get_linkerrors(struct sas_phy *phy)
  8685. {
  8686. return 0;
  8687. }
  8688. static int
  8689. hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
  8690. {
  8691. struct Scsi_Host *shost = phy_to_shost(rphy);
  8692. struct ctlr_info *h;
  8693. struct hpsa_scsi_dev_t *sd;
  8694. if (!shost)
  8695. return -ENXIO;
  8696. h = shost_to_hba(shost);
  8697. if (!h)
  8698. return -ENXIO;
  8699. sd = hpsa_find_device_by_sas_rphy(h, rphy);
  8700. if (!sd)
  8701. return -ENXIO;
  8702. *identifier = sd->eli;
  8703. return 0;
  8704. }
  8705. static int
  8706. hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
  8707. {
  8708. return -ENXIO;
  8709. }
  8710. static int
  8711. hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
  8712. {
  8713. return 0;
  8714. }
  8715. static int
  8716. hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
  8717. {
  8718. return 0;
  8719. }
  8720. static int
  8721. hpsa_sas_phy_setup(struct sas_phy *phy)
  8722. {
  8723. return 0;
  8724. }
  8725. static void
  8726. hpsa_sas_phy_release(struct sas_phy *phy)
  8727. {
  8728. }
  8729. static int
  8730. hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
  8731. {
  8732. return -EINVAL;
  8733. }
  8734. static struct sas_function_template hpsa_sas_transport_functions = {
  8735. .get_linkerrors = hpsa_sas_get_linkerrors,
  8736. .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
  8737. .get_bay_identifier = hpsa_sas_get_bay_identifier,
  8738. .phy_reset = hpsa_sas_phy_reset,
  8739. .phy_enable = hpsa_sas_phy_enable,
  8740. .phy_setup = hpsa_sas_phy_setup,
  8741. .phy_release = hpsa_sas_phy_release,
  8742. .set_phy_speed = hpsa_sas_phy_speed,
  8743. };
  8744. /*
  8745. * This is it. Register the PCI driver information for the cards we control
  8746. * the OS will call our registered routines when it finds one of our cards.
  8747. */
  8748. static int __init hpsa_init(void)
  8749. {
  8750. int rc;
  8751. hpsa_sas_transport_template =
  8752. sas_attach_transport(&hpsa_sas_transport_functions);
  8753. if (!hpsa_sas_transport_template)
  8754. return -ENODEV;
  8755. rc = pci_register_driver(&hpsa_pci_driver);
  8756. if (rc)
  8757. sas_release_transport(hpsa_sas_transport_template);
  8758. return rc;
  8759. }
  8760. static void __exit hpsa_cleanup(void)
  8761. {
  8762. pci_unregister_driver(&hpsa_pci_driver);
  8763. sas_release_transport(hpsa_sas_transport_template);
  8764. }
  8765. static void __attribute__((unused)) verify_offsets(void)
  8766. {
  8767. #define VERIFY_OFFSET(member, offset) \
  8768. BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
  8769. VERIFY_OFFSET(structure_size, 0);
  8770. VERIFY_OFFSET(volume_blk_size, 4);
  8771. VERIFY_OFFSET(volume_blk_cnt, 8);
  8772. VERIFY_OFFSET(phys_blk_shift, 16);
  8773. VERIFY_OFFSET(parity_rotation_shift, 17);
  8774. VERIFY_OFFSET(strip_size, 18);
  8775. VERIFY_OFFSET(disk_starting_blk, 20);
  8776. VERIFY_OFFSET(disk_blk_cnt, 28);
  8777. VERIFY_OFFSET(data_disks_per_row, 36);
  8778. VERIFY_OFFSET(metadata_disks_per_row, 38);
  8779. VERIFY_OFFSET(row_cnt, 40);
  8780. VERIFY_OFFSET(layout_map_count, 42);
  8781. VERIFY_OFFSET(flags, 44);
  8782. VERIFY_OFFSET(dekindex, 46);
  8783. /* VERIFY_OFFSET(reserved, 48 */
  8784. VERIFY_OFFSET(data, 64);
  8785. #undef VERIFY_OFFSET
  8786. #define VERIFY_OFFSET(member, offset) \
  8787. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
  8788. VERIFY_OFFSET(IU_type, 0);
  8789. VERIFY_OFFSET(direction, 1);
  8790. VERIFY_OFFSET(reply_queue, 2);
  8791. /* VERIFY_OFFSET(reserved1, 3); */
  8792. VERIFY_OFFSET(scsi_nexus, 4);
  8793. VERIFY_OFFSET(Tag, 8);
  8794. VERIFY_OFFSET(cdb, 16);
  8795. VERIFY_OFFSET(cciss_lun, 32);
  8796. VERIFY_OFFSET(data_len, 40);
  8797. VERIFY_OFFSET(cmd_priority_task_attr, 44);
  8798. VERIFY_OFFSET(sg_count, 45);
  8799. /* VERIFY_OFFSET(reserved3 */
  8800. VERIFY_OFFSET(err_ptr, 48);
  8801. VERIFY_OFFSET(err_len, 56);
  8802. /* VERIFY_OFFSET(reserved4 */
  8803. VERIFY_OFFSET(sg, 64);
  8804. #undef VERIFY_OFFSET
  8805. #define VERIFY_OFFSET(member, offset) \
  8806. BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
  8807. VERIFY_OFFSET(dev_handle, 0x00);
  8808. VERIFY_OFFSET(reserved1, 0x02);
  8809. VERIFY_OFFSET(function, 0x03);
  8810. VERIFY_OFFSET(reserved2, 0x04);
  8811. VERIFY_OFFSET(err_info, 0x0C);
  8812. VERIFY_OFFSET(reserved3, 0x10);
  8813. VERIFY_OFFSET(err_info_len, 0x12);
  8814. VERIFY_OFFSET(reserved4, 0x13);
  8815. VERIFY_OFFSET(sgl_offset, 0x14);
  8816. VERIFY_OFFSET(reserved5, 0x15);
  8817. VERIFY_OFFSET(transfer_len, 0x1C);
  8818. VERIFY_OFFSET(reserved6, 0x20);
  8819. VERIFY_OFFSET(io_flags, 0x24);
  8820. VERIFY_OFFSET(reserved7, 0x26);
  8821. VERIFY_OFFSET(LUN, 0x34);
  8822. VERIFY_OFFSET(control, 0x3C);
  8823. VERIFY_OFFSET(CDB, 0x40);
  8824. VERIFY_OFFSET(reserved8, 0x50);
  8825. VERIFY_OFFSET(host_context_flags, 0x60);
  8826. VERIFY_OFFSET(timeout_sec, 0x62);
  8827. VERIFY_OFFSET(ReplyQueue, 0x64);
  8828. VERIFY_OFFSET(reserved9, 0x65);
  8829. VERIFY_OFFSET(tag, 0x68);
  8830. VERIFY_OFFSET(host_addr, 0x70);
  8831. VERIFY_OFFSET(CISS_LUN, 0x78);
  8832. VERIFY_OFFSET(SG, 0x78 + 8);
  8833. #undef VERIFY_OFFSET
  8834. }
  8835. module_init(hpsa_init);
  8836. module_exit(hpsa_cleanup);