rtc-max77686.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // RTC driver for Maxim MAX77686 and MAX77802
  4. //
  5. // Copyright (C) 2012 Samsung Electronics Co.Ltd
  6. //
  7. // based on rtc-max8997.c
  8. #include <linux/i2c.h>
  9. #include <linux/slab.h>
  10. #include <linux/rtc.h>
  11. #include <linux/delay.h>
  12. #include <linux/mutex.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/mfd/max77686-private.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/regmap.h>
  18. #define MAX77686_I2C_ADDR_RTC (0x0C >> 1)
  19. #define MAX77620_I2C_ADDR_RTC 0x68
  20. #define MAX77714_I2C_ADDR_RTC 0x48
  21. #define MAX77686_INVALID_I2C_ADDR (-1)
  22. /* Define non existing register */
  23. #define MAX77686_INVALID_REG (-1)
  24. /* RTC Control Register */
  25. #define BCD_EN_SHIFT 0
  26. #define BCD_EN_MASK BIT(BCD_EN_SHIFT)
  27. #define MODEL24_SHIFT 1
  28. #define MODEL24_MASK BIT(MODEL24_SHIFT)
  29. /* RTC Update Register1 */
  30. #define RTC_UDR_SHIFT 0
  31. #define RTC_UDR_MASK BIT(RTC_UDR_SHIFT)
  32. #define RTC_RBUDR_SHIFT 4
  33. #define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT)
  34. /* RTC Alarm Enable */
  35. #define ALARM_ENABLE_SHIFT 7
  36. #define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT)
  37. #define REG_RTC_NONE 0xdeadbeef
  38. /*
  39. * MAX77802 has separate register (RTCAE1) for alarm enable instead
  40. * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE}
  41. * as in done in MAX77686.
  42. */
  43. #define MAX77802_ALARM_ENABLE_VALUE 0x77
  44. enum {
  45. RTC_SEC = 0,
  46. RTC_MIN,
  47. RTC_HOUR,
  48. RTC_WEEKDAY,
  49. RTC_MONTH,
  50. RTC_YEAR,
  51. RTC_MONTHDAY,
  52. RTC_NR_TIME
  53. };
  54. /**
  55. * struct max77686_rtc_driver_data - model-specific configuration
  56. * @delay: Minimum usecs needed for a RTC update
  57. * @mask: Mask used to read RTC registers value
  58. * @map: Registers offset to I2C addresses map
  59. * @alarm_enable_reg: Has a separate alarm enable register?
  60. * @rtc_i2c_addr: I2C address for RTC block
  61. * @rtc_irq_from_platform: RTC interrupt via platform resource
  62. * @alarm_pending_status_reg: Pending alarm status register
  63. * @rtc_irq_chip: RTC IRQ CHIP for regmap
  64. * @regmap_config: regmap configuration for the chip
  65. */
  66. struct max77686_rtc_driver_data {
  67. unsigned long delay;
  68. u8 mask;
  69. const unsigned int *map;
  70. bool alarm_enable_reg;
  71. int rtc_i2c_addr;
  72. bool rtc_irq_from_platform;
  73. int alarm_pending_status_reg;
  74. const struct regmap_irq_chip *rtc_irq_chip;
  75. const struct regmap_config *regmap_config;
  76. };
  77. struct max77686_rtc_info {
  78. struct device *dev;
  79. struct rtc_device *rtc_dev;
  80. struct mutex lock;
  81. struct regmap *regmap;
  82. struct regmap *rtc_regmap;
  83. const struct max77686_rtc_driver_data *drv_data;
  84. struct regmap_irq_chip_data *rtc_irq_data;
  85. int rtc_irq;
  86. int virq;
  87. };
  88. enum MAX77686_RTC_OP {
  89. MAX77686_RTC_WRITE,
  90. MAX77686_RTC_READ,
  91. };
  92. /* These are not registers but just offsets that are mapped to addresses */
  93. enum max77686_rtc_reg_offset {
  94. REG_RTC_CONTROLM = 0,
  95. REG_RTC_CONTROL,
  96. REG_RTC_UPDATE0,
  97. REG_WTSR_SMPL_CNTL,
  98. REG_RTC_SEC,
  99. REG_RTC_MIN,
  100. REG_RTC_HOUR,
  101. REG_RTC_WEEKDAY,
  102. REG_RTC_MONTH,
  103. REG_RTC_YEAR,
  104. REG_RTC_MONTHDAY,
  105. REG_ALARM1_SEC,
  106. REG_ALARM1_MIN,
  107. REG_ALARM1_HOUR,
  108. REG_ALARM1_WEEKDAY,
  109. REG_ALARM1_MONTH,
  110. REG_ALARM1_YEAR,
  111. REG_ALARM1_DATE,
  112. REG_ALARM2_SEC,
  113. REG_ALARM2_MIN,
  114. REG_ALARM2_HOUR,
  115. REG_ALARM2_WEEKDAY,
  116. REG_ALARM2_MONTH,
  117. REG_ALARM2_YEAR,
  118. REG_ALARM2_DATE,
  119. REG_RTC_AE1,
  120. REG_RTC_END,
  121. };
  122. /* Maps RTC registers offset to the MAX77686 register addresses */
  123. static const unsigned int max77686_map[REG_RTC_END] = {
  124. [REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM,
  125. [REG_RTC_CONTROL] = MAX77686_RTC_CONTROL,
  126. [REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0,
  127. [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL,
  128. [REG_RTC_SEC] = MAX77686_RTC_SEC,
  129. [REG_RTC_MIN] = MAX77686_RTC_MIN,
  130. [REG_RTC_HOUR] = MAX77686_RTC_HOUR,
  131. [REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY,
  132. [REG_RTC_MONTH] = MAX77686_RTC_MONTH,
  133. [REG_RTC_YEAR] = MAX77686_RTC_YEAR,
  134. [REG_RTC_MONTHDAY] = MAX77686_RTC_MONTHDAY,
  135. [REG_ALARM1_SEC] = MAX77686_ALARM1_SEC,
  136. [REG_ALARM1_MIN] = MAX77686_ALARM1_MIN,
  137. [REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR,
  138. [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY,
  139. [REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH,
  140. [REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR,
  141. [REG_ALARM1_DATE] = MAX77686_ALARM1_DATE,
  142. [REG_ALARM2_SEC] = MAX77686_ALARM2_SEC,
  143. [REG_ALARM2_MIN] = MAX77686_ALARM2_MIN,
  144. [REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR,
  145. [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY,
  146. [REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH,
  147. [REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR,
  148. [REG_ALARM2_DATE] = MAX77686_ALARM2_DATE,
  149. [REG_RTC_AE1] = REG_RTC_NONE,
  150. };
  151. static const struct regmap_irq max77686_rtc_irqs[] = {
  152. /* RTC interrupts */
  153. REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK),
  154. REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK),
  155. REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK),
  156. REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK),
  157. REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK),
  158. REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK),
  159. };
  160. static const struct regmap_irq_chip max77686_rtc_irq_chip = {
  161. .name = "max77686-rtc",
  162. .status_base = MAX77686_RTC_INT,
  163. .mask_base = MAX77686_RTC_INTM,
  164. .num_regs = 1,
  165. .irqs = max77686_rtc_irqs,
  166. .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
  167. };
  168. static const struct regmap_config max77686_rtc_regmap_config = {
  169. .reg_bits = 8,
  170. .val_bits = 8,
  171. };
  172. static const struct max77686_rtc_driver_data max77686_drv_data = {
  173. .delay = 16000,
  174. .mask = 0x7f,
  175. .map = max77686_map,
  176. .alarm_enable_reg = false,
  177. .rtc_irq_from_platform = false,
  178. .alarm_pending_status_reg = MAX77686_REG_STATUS2,
  179. .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC,
  180. .rtc_irq_chip = &max77686_rtc_irq_chip,
  181. .regmap_config = &max77686_rtc_regmap_config,
  182. };
  183. static const struct regmap_irq_chip max77714_rtc_irq_chip = {
  184. .name = "max77714-rtc",
  185. .status_base = MAX77686_RTC_INT,
  186. .mask_base = MAX77686_RTC_INTM,
  187. .num_regs = 1,
  188. .irqs = max77686_rtc_irqs,
  189. .num_irqs = ARRAY_SIZE(max77686_rtc_irqs) - 1, /* no WTSR on 77714 */
  190. };
  191. static const struct max77686_rtc_driver_data max77714_drv_data = {
  192. .delay = 16000,
  193. .mask = 0x7f,
  194. .map = max77686_map,
  195. .alarm_enable_reg = false,
  196. .rtc_irq_from_platform = false,
  197. /* On MAX77714 RTCA1 is BIT 1 of RTCINT (0x00). Not supported by this driver. */
  198. .alarm_pending_status_reg = MAX77686_INVALID_REG,
  199. .rtc_i2c_addr = MAX77714_I2C_ADDR_RTC,
  200. .rtc_irq_chip = &max77714_rtc_irq_chip,
  201. .regmap_config = &max77686_rtc_regmap_config,
  202. };
  203. static const struct regmap_config max77620_rtc_regmap_config = {
  204. .reg_bits = 8,
  205. .val_bits = 8,
  206. .use_single_write = true,
  207. };
  208. static const struct max77686_rtc_driver_data max77620_drv_data = {
  209. .delay = 16000,
  210. .mask = 0x7f,
  211. .map = max77686_map,
  212. .alarm_enable_reg = false,
  213. .rtc_irq_from_platform = true,
  214. .alarm_pending_status_reg = MAX77686_INVALID_REG,
  215. .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC,
  216. .rtc_irq_chip = &max77686_rtc_irq_chip,
  217. .regmap_config = &max77620_rtc_regmap_config,
  218. };
  219. static const unsigned int max77802_map[REG_RTC_END] = {
  220. [REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM,
  221. [REG_RTC_CONTROL] = MAX77802_RTC_CONTROL,
  222. [REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0,
  223. [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL,
  224. [REG_RTC_SEC] = MAX77802_RTC_SEC,
  225. [REG_RTC_MIN] = MAX77802_RTC_MIN,
  226. [REG_RTC_HOUR] = MAX77802_RTC_HOUR,
  227. [REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY,
  228. [REG_RTC_MONTH] = MAX77802_RTC_MONTH,
  229. [REG_RTC_YEAR] = MAX77802_RTC_YEAR,
  230. [REG_RTC_MONTHDAY] = MAX77802_RTC_MONTHDAY,
  231. [REG_ALARM1_SEC] = MAX77802_ALARM1_SEC,
  232. [REG_ALARM1_MIN] = MAX77802_ALARM1_MIN,
  233. [REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR,
  234. [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY,
  235. [REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH,
  236. [REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR,
  237. [REG_ALARM1_DATE] = MAX77802_ALARM1_DATE,
  238. [REG_ALARM2_SEC] = MAX77802_ALARM2_SEC,
  239. [REG_ALARM2_MIN] = MAX77802_ALARM2_MIN,
  240. [REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR,
  241. [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY,
  242. [REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH,
  243. [REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR,
  244. [REG_ALARM2_DATE] = MAX77802_ALARM2_DATE,
  245. [REG_RTC_AE1] = MAX77802_RTC_AE1,
  246. };
  247. static const struct regmap_irq_chip max77802_rtc_irq_chip = {
  248. .name = "max77802-rtc",
  249. .status_base = MAX77802_RTC_INT,
  250. .mask_base = MAX77802_RTC_INTM,
  251. .num_regs = 1,
  252. .irqs = max77686_rtc_irqs, /* same masks as 77686 */
  253. .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
  254. };
  255. static const struct max77686_rtc_driver_data max77802_drv_data = {
  256. .delay = 200,
  257. .mask = 0xff,
  258. .map = max77802_map,
  259. .alarm_enable_reg = true,
  260. .rtc_irq_from_platform = false,
  261. .alarm_pending_status_reg = MAX77686_REG_STATUS2,
  262. .rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR,
  263. .rtc_irq_chip = &max77802_rtc_irq_chip,
  264. };
  265. static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
  266. struct max77686_rtc_info *info)
  267. {
  268. u8 mask = info->drv_data->mask;
  269. tm->tm_sec = data[RTC_SEC] & mask;
  270. tm->tm_min = data[RTC_MIN] & mask;
  271. tm->tm_hour = data[RTC_HOUR] & 0x1f;
  272. /* Only a single bit is set in data[], so fls() would be equivalent */
  273. tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1;
  274. tm->tm_mday = data[RTC_MONTHDAY] & 0x1f;
  275. tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
  276. tm->tm_year = data[RTC_YEAR] & mask;
  277. tm->tm_yday = 0;
  278. tm->tm_isdst = 0;
  279. /*
  280. * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the
  281. * year values are just 0..99 so add 100 to support up to 2099.
  282. */
  283. if (!info->drv_data->alarm_enable_reg)
  284. tm->tm_year += 100;
  285. }
  286. static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data,
  287. struct max77686_rtc_info *info)
  288. {
  289. data[RTC_SEC] = tm->tm_sec;
  290. data[RTC_MIN] = tm->tm_min;
  291. data[RTC_HOUR] = tm->tm_hour;
  292. data[RTC_WEEKDAY] = 1 << tm->tm_wday;
  293. data[RTC_MONTHDAY] = tm->tm_mday;
  294. data[RTC_MONTH] = tm->tm_mon + 1;
  295. if (info->drv_data->alarm_enable_reg) {
  296. data[RTC_YEAR] = tm->tm_year;
  297. return 0;
  298. }
  299. data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
  300. if (tm->tm_year < 100) {
  301. dev_err(info->dev, "RTC cannot handle the year %d.\n",
  302. 1900 + tm->tm_year);
  303. return -EINVAL;
  304. }
  305. return 0;
  306. }
  307. static int max77686_rtc_update(struct max77686_rtc_info *info,
  308. enum MAX77686_RTC_OP op)
  309. {
  310. int ret;
  311. unsigned int data;
  312. unsigned long delay = info->drv_data->delay;
  313. if (op == MAX77686_RTC_WRITE)
  314. data = 1 << RTC_UDR_SHIFT;
  315. else
  316. data = 1 << RTC_RBUDR_SHIFT;
  317. ret = regmap_update_bits(info->rtc_regmap,
  318. info->drv_data->map[REG_RTC_UPDATE0],
  319. data, data);
  320. if (ret < 0)
  321. dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n",
  322. ret, data);
  323. else {
  324. /* Minimum delay required before RTC update. */
  325. usleep_range(delay, delay * 2);
  326. }
  327. return ret;
  328. }
  329. static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm)
  330. {
  331. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  332. u8 data[RTC_NR_TIME];
  333. int ret;
  334. mutex_lock(&info->lock);
  335. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  336. if (ret < 0)
  337. goto out;
  338. ret = regmap_bulk_read(info->rtc_regmap,
  339. info->drv_data->map[REG_RTC_SEC],
  340. data, ARRAY_SIZE(data));
  341. if (ret < 0) {
  342. dev_err(info->dev, "Fail to read time reg(%d)\n", ret);
  343. goto out;
  344. }
  345. max77686_rtc_data_to_tm(data, tm, info);
  346. out:
  347. mutex_unlock(&info->lock);
  348. return ret;
  349. }
  350. static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
  351. {
  352. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  353. u8 data[RTC_NR_TIME];
  354. int ret;
  355. ret = max77686_rtc_tm_to_data(tm, data, info);
  356. if (ret < 0)
  357. return ret;
  358. mutex_lock(&info->lock);
  359. ret = regmap_bulk_write(info->rtc_regmap,
  360. info->drv_data->map[REG_RTC_SEC],
  361. data, ARRAY_SIZE(data));
  362. if (ret < 0) {
  363. dev_err(info->dev, "Fail to write time reg(%d)\n", ret);
  364. goto out;
  365. }
  366. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  367. out:
  368. mutex_unlock(&info->lock);
  369. return ret;
  370. }
  371. static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  372. {
  373. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  374. u8 data[RTC_NR_TIME];
  375. unsigned int val;
  376. const unsigned int *map = info->drv_data->map;
  377. int i, ret;
  378. mutex_lock(&info->lock);
  379. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  380. if (ret < 0)
  381. goto out;
  382. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  383. data, ARRAY_SIZE(data));
  384. if (ret < 0) {
  385. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  386. goto out;
  387. }
  388. max77686_rtc_data_to_tm(data, &alrm->time, info);
  389. alrm->enabled = 0;
  390. if (info->drv_data->alarm_enable_reg) {
  391. if (map[REG_RTC_AE1] == REG_RTC_NONE) {
  392. ret = -EINVAL;
  393. dev_err(info->dev,
  394. "alarm enable register not set(%d)\n", ret);
  395. goto out;
  396. }
  397. ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val);
  398. if (ret < 0) {
  399. dev_err(info->dev,
  400. "fail to read alarm enable(%d)\n", ret);
  401. goto out;
  402. }
  403. if (val)
  404. alrm->enabled = 1;
  405. } else {
  406. for (i = 0; i < ARRAY_SIZE(data); i++) {
  407. if (data[i] & ALARM_ENABLE_MASK) {
  408. alrm->enabled = 1;
  409. break;
  410. }
  411. }
  412. }
  413. alrm->pending = 0;
  414. if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG)
  415. goto out;
  416. ret = regmap_read(info->regmap,
  417. info->drv_data->alarm_pending_status_reg, &val);
  418. if (ret < 0) {
  419. dev_err(info->dev,
  420. "Fail to read alarm pending status reg(%d)\n", ret);
  421. goto out;
  422. }
  423. if (val & (1 << 4)) /* RTCA1 */
  424. alrm->pending = 1;
  425. out:
  426. mutex_unlock(&info->lock);
  427. return ret;
  428. }
  429. static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info)
  430. {
  431. u8 data[RTC_NR_TIME];
  432. int ret, i;
  433. struct rtc_time tm;
  434. const unsigned int *map = info->drv_data->map;
  435. if (!mutex_is_locked(&info->lock))
  436. dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
  437. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  438. if (ret < 0)
  439. goto out;
  440. if (info->drv_data->alarm_enable_reg) {
  441. if (map[REG_RTC_AE1] == REG_RTC_NONE) {
  442. ret = -EINVAL;
  443. dev_err(info->dev,
  444. "alarm enable register not set(%d)\n", ret);
  445. goto out;
  446. }
  447. ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0);
  448. } else {
  449. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  450. data, ARRAY_SIZE(data));
  451. if (ret < 0) {
  452. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  453. goto out;
  454. }
  455. max77686_rtc_data_to_tm(data, &tm, info);
  456. for (i = 0; i < ARRAY_SIZE(data); i++)
  457. data[i] &= ~ALARM_ENABLE_MASK;
  458. ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
  459. data, ARRAY_SIZE(data));
  460. }
  461. if (ret < 0) {
  462. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  463. goto out;
  464. }
  465. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  466. out:
  467. return ret;
  468. }
  469. static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
  470. {
  471. u8 data[RTC_NR_TIME];
  472. int ret;
  473. struct rtc_time tm;
  474. const unsigned int *map = info->drv_data->map;
  475. if (!mutex_is_locked(&info->lock))
  476. dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
  477. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  478. if (ret < 0)
  479. goto out;
  480. if (info->drv_data->alarm_enable_reg) {
  481. ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1],
  482. MAX77802_ALARM_ENABLE_VALUE);
  483. } else {
  484. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  485. data, ARRAY_SIZE(data));
  486. if (ret < 0) {
  487. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  488. goto out;
  489. }
  490. max77686_rtc_data_to_tm(data, &tm, info);
  491. data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
  492. data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
  493. data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
  494. data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
  495. if (data[RTC_MONTH] & 0xf)
  496. data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
  497. if (data[RTC_YEAR] & info->drv_data->mask)
  498. data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
  499. if (data[RTC_MONTHDAY] & 0x1f)
  500. data[RTC_MONTHDAY] |= (1 << ALARM_ENABLE_SHIFT);
  501. ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
  502. data, ARRAY_SIZE(data));
  503. }
  504. if (ret < 0) {
  505. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  506. goto out;
  507. }
  508. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  509. out:
  510. return ret;
  511. }
  512. static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  513. {
  514. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  515. u8 data[RTC_NR_TIME];
  516. int ret;
  517. ret = max77686_rtc_tm_to_data(&alrm->time, data, info);
  518. if (ret < 0)
  519. return ret;
  520. mutex_lock(&info->lock);
  521. ret = max77686_rtc_stop_alarm(info);
  522. if (ret < 0)
  523. goto out;
  524. ret = regmap_bulk_write(info->rtc_regmap,
  525. info->drv_data->map[REG_ALARM1_SEC],
  526. data, ARRAY_SIZE(data));
  527. if (ret < 0) {
  528. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  529. goto out;
  530. }
  531. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  532. if (ret < 0)
  533. goto out;
  534. if (alrm->enabled)
  535. ret = max77686_rtc_start_alarm(info);
  536. out:
  537. mutex_unlock(&info->lock);
  538. return ret;
  539. }
  540. static int max77686_rtc_alarm_irq_enable(struct device *dev,
  541. unsigned int enabled)
  542. {
  543. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  544. int ret;
  545. mutex_lock(&info->lock);
  546. if (enabled)
  547. ret = max77686_rtc_start_alarm(info);
  548. else
  549. ret = max77686_rtc_stop_alarm(info);
  550. mutex_unlock(&info->lock);
  551. return ret;
  552. }
  553. static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data)
  554. {
  555. struct max77686_rtc_info *info = data;
  556. dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq);
  557. rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
  558. return IRQ_HANDLED;
  559. }
  560. static const struct rtc_class_ops max77686_rtc_ops = {
  561. .read_time = max77686_rtc_read_time,
  562. .set_time = max77686_rtc_set_time,
  563. .read_alarm = max77686_rtc_read_alarm,
  564. .set_alarm = max77686_rtc_set_alarm,
  565. .alarm_irq_enable = max77686_rtc_alarm_irq_enable,
  566. };
  567. static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
  568. {
  569. u8 data[2];
  570. int ret;
  571. /* Set RTC control register : Binary mode, 24hour mdoe */
  572. data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  573. data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  574. ret = regmap_bulk_write(info->rtc_regmap,
  575. info->drv_data->map[REG_RTC_CONTROLM],
  576. data, ARRAY_SIZE(data));
  577. if (ret < 0) {
  578. dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret);
  579. return ret;
  580. }
  581. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  582. return ret;
  583. }
  584. static int max77686_init_rtc_regmap(struct max77686_rtc_info *info)
  585. {
  586. struct device *parent = info->dev->parent;
  587. struct i2c_client *parent_i2c = to_i2c_client(parent);
  588. struct i2c_client *client;
  589. int ret;
  590. if (info->drv_data->rtc_irq_from_platform) {
  591. struct platform_device *pdev = to_platform_device(info->dev);
  592. info->rtc_irq = platform_get_irq(pdev, 0);
  593. if (info->rtc_irq < 0)
  594. return info->rtc_irq;
  595. } else {
  596. info->rtc_irq = parent_i2c->irq;
  597. }
  598. info->regmap = dev_get_regmap(parent, NULL);
  599. if (!info->regmap)
  600. return dev_err_probe(info->dev, -ENODEV,
  601. "Failed to get rtc regmap\n");
  602. if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) {
  603. info->rtc_regmap = info->regmap;
  604. goto add_rtc_irq;
  605. }
  606. client = devm_i2c_new_dummy_device(info->dev, parent_i2c->adapter,
  607. info->drv_data->rtc_i2c_addr);
  608. if (IS_ERR(client))
  609. return dev_err_probe(info->dev, PTR_ERR(client),
  610. "Failed to allocate I2C device for RTC\n");
  611. info->rtc_regmap = devm_regmap_init_i2c(client,
  612. info->drv_data->regmap_config);
  613. if (IS_ERR(info->rtc_regmap))
  614. return dev_err_probe(info->dev, PTR_ERR(info->rtc_regmap),
  615. "Failed to allocate RTC regmap\n");
  616. add_rtc_irq:
  617. ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq,
  618. IRQF_ONESHOT | IRQF_SHARED,
  619. 0, info->drv_data->rtc_irq_chip,
  620. &info->rtc_irq_data);
  621. if (ret < 0)
  622. return dev_err_probe(info->dev, ret,
  623. "Failed to add RTC irq chip\n");
  624. return 0;
  625. }
  626. static int max77686_rtc_probe(struct platform_device *pdev)
  627. {
  628. struct max77686_rtc_info *info;
  629. const struct platform_device_id *id = platform_get_device_id(pdev);
  630. int ret;
  631. info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info),
  632. GFP_KERNEL);
  633. if (!info)
  634. return -ENOMEM;
  635. mutex_init(&info->lock);
  636. info->dev = &pdev->dev;
  637. info->drv_data = (const struct max77686_rtc_driver_data *)
  638. id->driver_data;
  639. ret = max77686_init_rtc_regmap(info);
  640. if (ret < 0)
  641. return ret;
  642. platform_set_drvdata(pdev, info);
  643. ret = max77686_rtc_init_reg(info);
  644. if (ret < 0) {
  645. dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
  646. goto err_rtc;
  647. }
  648. device_init_wakeup(&pdev->dev, true);
  649. info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name,
  650. &max77686_rtc_ops, THIS_MODULE);
  651. if (IS_ERR(info->rtc_dev)) {
  652. ret = PTR_ERR(info->rtc_dev);
  653. dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
  654. if (ret == 0)
  655. ret = -EINVAL;
  656. goto err_rtc;
  657. }
  658. info->virq = regmap_irq_get_virq(info->rtc_irq_data,
  659. MAX77686_RTCIRQ_RTCA1);
  660. if (info->virq <= 0) {
  661. ret = -ENXIO;
  662. goto err_rtc;
  663. }
  664. ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0,
  665. "rtc-alarm1", info);
  666. if (ret < 0) {
  667. dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
  668. info->virq, ret);
  669. goto err_rtc;
  670. }
  671. return 0;
  672. err_rtc:
  673. regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
  674. return ret;
  675. }
  676. static void max77686_rtc_remove(struct platform_device *pdev)
  677. {
  678. struct max77686_rtc_info *info = platform_get_drvdata(pdev);
  679. free_irq(info->virq, info);
  680. regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
  681. }
  682. #ifdef CONFIG_PM_SLEEP
  683. static int max77686_rtc_suspend(struct device *dev)
  684. {
  685. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  686. int ret = 0;
  687. if (device_may_wakeup(dev)) {
  688. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  689. ret = enable_irq_wake(info->virq);
  690. }
  691. /*
  692. * If the main IRQ (not virtual) is the parent IRQ, then it must be
  693. * disabled during suspend because if it happens while suspended it
  694. * will be handled before resuming I2C.
  695. *
  696. * Since Main IRQ is shared, all its users should disable it to be sure
  697. * it won't fire while one of them is still suspended.
  698. */
  699. if (!info->drv_data->rtc_irq_from_platform)
  700. disable_irq(info->rtc_irq);
  701. return ret;
  702. }
  703. static int max77686_rtc_resume(struct device *dev)
  704. {
  705. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  706. if (!info->drv_data->rtc_irq_from_platform)
  707. enable_irq(info->rtc_irq);
  708. if (device_may_wakeup(dev)) {
  709. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  710. return disable_irq_wake(info->virq);
  711. }
  712. return 0;
  713. }
  714. #endif
  715. static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
  716. max77686_rtc_suspend, max77686_rtc_resume);
  717. static const struct platform_device_id rtc_id[] = {
  718. { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, },
  719. { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, },
  720. { "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, },
  721. { "max77714-rtc", .driver_data = (kernel_ulong_t)&max77714_drv_data, },
  722. {},
  723. };
  724. MODULE_DEVICE_TABLE(platform, rtc_id);
  725. static struct platform_driver max77686_rtc_driver = {
  726. .driver = {
  727. .name = "max77686-rtc",
  728. .pm = &max77686_rtc_pm_ops,
  729. },
  730. .probe = max77686_rtc_probe,
  731. .remove = max77686_rtc_remove,
  732. .id_table = rtc_id,
  733. };
  734. module_platform_driver(max77686_rtc_driver);
  735. MODULE_DESCRIPTION("Maxim MAX77686 RTC driver");
  736. MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
  737. MODULE_LICENSE("GPL");