Kconfig 13 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. config ARCH_HAS_RESET_CONTROLLER
  3. bool
  4. menuconfig RESET_CONTROLLER
  5. bool "Reset Controller Support"
  6. default y if ARCH_HAS_RESET_CONTROLLER
  7. help
  8. Generic Reset Controller support.
  9. This framework is designed to abstract reset handling of devices
  10. via GPIOs or SoC-internal reset controller modules.
  11. If unsure, say no.
  12. if RESET_CONTROLLER
  13. config RESET_A10SR
  14. tristate "Altera Arria10 System Resource Reset"
  15. depends on MFD_ALTERA_A10SR || COMPILE_TEST
  16. help
  17. This option enables support for the external reset functions for
  18. peripheral PHYs on the Altera Arria10 System Resource Chip.
  19. config RESET_ASPEED
  20. tristate "ASPEED Reset Driver"
  21. depends on ARCH_ASPEED || COMPILE_TEST
  22. select AUXILIARY_BUS
  23. help
  24. This enables the reset controller driver for AST2700.
  25. config RESET_ATH79
  26. bool "AR71xx Reset Driver" if COMPILE_TEST
  27. default ATH79
  28. help
  29. This enables the ATH79 reset controller driver that supports the
  30. AR71xx SoC reset controller.
  31. config RESET_AXS10X
  32. bool "AXS10x Reset Driver" if COMPILE_TEST
  33. default ARC_PLAT_AXS10X
  34. help
  35. This enables the reset controller driver for AXS10x.
  36. config RESET_BCM6345
  37. bool "BCM6345 Reset Controller"
  38. depends on BMIPS_GENERIC || COMPILE_TEST
  39. default BMIPS_GENERIC
  40. help
  41. This enables the reset controller driver for BCM6345 SoCs.
  42. config RESET_BERLIN
  43. tristate "Berlin Reset Driver"
  44. depends on ARCH_BERLIN || COMPILE_TEST
  45. default m if ARCH_BERLIN
  46. help
  47. This enables the reset controller driver for Marvell Berlin SoCs.
  48. config RESET_BRCMSTB
  49. tristate "Broadcom STB reset controller"
  50. depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
  51. default ARCH_BRCMSTB || ARCH_BCM2835
  52. help
  53. This enables the reset controller driver for Broadcom STB SoCs using
  54. a SUN_TOP_CTRL_SW_INIT style controller.
  55. config RESET_BRCMSTB_RESCAL
  56. tristate "Broadcom STB RESCAL reset controller"
  57. depends on HAS_IOMEM
  58. depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
  59. default ARCH_BRCMSTB || ARCH_BCM2835
  60. help
  61. This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
  62. BCM7216 or the BCM2712.
  63. config RESET_EIC7700
  64. bool "Reset controller driver for ESWIN SoCs"
  65. depends on ARCH_ESWIN || COMPILE_TEST
  66. default ARCH_ESWIN
  67. help
  68. This enables the reset controller driver for ESWIN SoCs. This driver is
  69. specific to ESWIN SoCs and should only be enabled if using such hardware.
  70. The driver supports eic7700 series chips and provides functionality for
  71. asserting and deasserting resets on the chip.
  72. config RESET_EYEQ
  73. bool "Mobileye EyeQ reset controller"
  74. depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
  75. select AUXILIARY_BUS
  76. default MACH_EYEQ5 || MACH_EYEQ6H
  77. help
  78. This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
  79. and EyeQ6H SoCs.
  80. It has one or more domains, with a varying number of resets in each.
  81. Registers are located in a shared register region called OLB. EyeQ6H
  82. has multiple reset instances.
  83. config RESET_GPIO
  84. tristate "GPIO reset controller"
  85. depends on GPIOLIB
  86. select AUXILIARY_BUS
  87. help
  88. This enables a generic reset controller for resets attached via
  89. GPIOs. Typically for OF platforms this driver expects "reset-gpios"
  90. property.
  91. If compiled as module, it will be called reset-gpio.
  92. config RESET_HSDK
  93. bool "Synopsys HSDK Reset Driver"
  94. depends on HAS_IOMEM
  95. depends on ARC_SOC_HSDK || COMPILE_TEST
  96. help
  97. This enables the reset controller driver for HSDK board.
  98. config RESET_IMX_SCU
  99. tristate "i.MX8Q Reset Driver"
  100. depends on IMX_SCU && HAVE_ARM_SMCCC
  101. depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
  102. help
  103. This enables the reset controller driver for i.MX8QM/i.MX8QXP
  104. config RESET_IMX7
  105. tristate "i.MX7/8 Reset Driver"
  106. depends on HAS_IOMEM
  107. depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
  108. default y if SOC_IMX7D
  109. select MFD_SYSCON
  110. help
  111. This enables the reset controller driver for i.MX7 SoCs.
  112. config RESET_IMX8MP_AUDIOMIX
  113. tristate "i.MX8MP AudioMix Reset Driver"
  114. depends on ARCH_MXC || COMPILE_TEST
  115. select AUXILIARY_BUS
  116. default CLK_IMX8MP
  117. help
  118. This enables the reset controller driver for i.MX8MP AudioMix
  119. config RESET_INTEL_GW
  120. bool "Intel Reset Controller Driver"
  121. depends on X86 || COMPILE_TEST
  122. depends on OF && HAS_IOMEM
  123. select REGMAP_MMIO
  124. help
  125. This enables the reset controller driver for Intel Gateway SoCs.
  126. Say Y to control the reset signals provided by reset controller.
  127. Otherwise, say N.
  128. config RESET_K210
  129. bool "Reset controller driver for Canaan Kendryte K210 SoC"
  130. depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
  131. select MFD_SYSCON
  132. default SOC_CANAAN_K210
  133. help
  134. Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
  135. Say Y if you want to control reset signals provided by this
  136. controller.
  137. config RESET_K230
  138. tristate "Reset controller driver for Canaan Kendryte K230 SoC"
  139. depends on ARCH_CANAAN || COMPILE_TEST
  140. default ARCH_CANAAN
  141. help
  142. Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
  143. Say Y if you want to control reset signals provided by this
  144. controller.
  145. config RESET_LANTIQ
  146. bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
  147. default SOC_TYPE_XWAY
  148. help
  149. This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
  150. config RESET_LPC18XX
  151. bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
  152. default ARCH_LPC18XX
  153. help
  154. This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
  155. config RESET_MCHP_SPARX5
  156. tristate "Microchip Sparx5 reset driver"
  157. depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
  158. default y if SPARX5_SWITCH
  159. select MFD_SYSCON
  160. help
  161. This driver supports switch core reset for the Microchip Sparx5 SoC.
  162. config RESET_NPCM
  163. bool "NPCM BMC Reset Driver" if COMPILE_TEST
  164. default ARCH_NPCM
  165. select AUXILIARY_BUS
  166. help
  167. This enables the reset controller driver for Nuvoton NPCM
  168. BMC SoCs.
  169. config RESET_NUVOTON_MA35D1
  170. bool "Nuvoton MA35D1 Reset Driver"
  171. depends on ARCH_MA35 || COMPILE_TEST
  172. default ARCH_MA35
  173. help
  174. This enables the reset controller driver for Nuvoton MA35D1 SoC.
  175. config RESET_PISTACHIO
  176. bool "Pistachio Reset Driver"
  177. depends on MIPS || COMPILE_TEST
  178. help
  179. This enables the reset driver for ImgTec Pistachio SoCs.
  180. config RESET_POLARFIRE_SOC
  181. bool "Microchip PolarFire SoC (MPFS) Reset Driver"
  182. depends on MCHP_CLK_MPFS
  183. depends on MFD_SYSCON
  184. select AUXILIARY_BUS
  185. default MCHP_CLK_MPFS
  186. help
  187. This driver supports peripheral reset for the Microchip PolarFire SoC
  188. config RESET_QCOM_AOSS
  189. tristate "Qcom AOSS Reset Driver"
  190. depends on ARCH_QCOM || COMPILE_TEST
  191. help
  192. This enables the AOSS (always on subsystem) reset driver
  193. for Qualcomm SDM845 SoCs. Say Y if you want to control
  194. reset signals provided by AOSS for Modem, Venus, ADSP,
  195. GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
  196. config RESET_QCOM_PDC
  197. tristate "Qualcomm PDC Reset Driver"
  198. depends on ARCH_QCOM || COMPILE_TEST
  199. help
  200. This enables the PDC (Power Domain Controller) reset driver
  201. for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
  202. to control reset signals provided by PDC for Modem, Compute,
  203. Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
  204. config RESET_RASPBERRYPI
  205. tristate "Raspberry Pi 4 Firmware Reset Driver"
  206. depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
  207. default USB_XHCI_PCI
  208. help
  209. Raspberry Pi 4's co-processor controls some of the board's HW
  210. initialization process, but it's up to Linux to trigger it when
  211. relevant. This driver provides a reset controller capable of
  212. interfacing with RPi4's co-processor and model these firmware
  213. initialization routines as reset lines.
  214. config RESET_RZG2L_USBPHY_CTRL
  215. tristate "Renesas RZ/G2L USBPHY control driver"
  216. depends on ARCH_RZG2L || COMPILE_TEST
  217. select MFD_SYSCON
  218. help
  219. Support for USBPHY Control found on RZ/G2L family. It mainly
  220. controls reset and power down of the USB/PHY.
  221. config RESET_RZV2H_USB2PHY
  222. tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver"
  223. depends on ARCH_RENESAS || COMPILE_TEST
  224. help
  225. Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC
  226. (and similar SoCs).
  227. config RESET_SCMI
  228. tristate "Reset driver controlled via ARM SCMI interface"
  229. depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
  230. default ARM_SCMI_PROTOCOL
  231. help
  232. This driver provides support for reset signal/domains that are
  233. controlled by firmware that implements the SCMI interface.
  234. This driver uses SCMI Message Protocol to interact with the
  235. firmware controlling all the reset signals.
  236. config RESET_SIMPLE
  237. bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
  238. default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
  239. depends on HAS_IOMEM
  240. help
  241. This enables a simple reset controller driver for reset lines that
  242. that can be asserted and deasserted by toggling bits in a contiguous,
  243. exclusive register space.
  244. Currently this driver supports:
  245. - Altera SoCFPGAs
  246. - ASPEED BMC SoCs
  247. - Bitmain BM1880 SoC
  248. - Realtek SoCs
  249. - RCC reset controller in STM32 MCUs
  250. - Allwinner SoCs
  251. - SiFive FU740 SoCs
  252. - Sophgo SoCs
  253. config RESET_SOCFPGA
  254. bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
  255. default ARM && ARCH_INTEL_SOCFPGA
  256. select RESET_SIMPLE
  257. help
  258. This enables the reset driver for the SoCFPGA ARMv7 platforms. This
  259. driver gets initialized early during platform init calls.
  260. config RESET_SUNPLUS
  261. bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
  262. default ARCH_SUNPLUS
  263. help
  264. This enables the reset driver support for Sunplus SoCs.
  265. The reset lines that can be asserted and deasserted by toggling bits
  266. in a contiguous, exclusive register space. The register is HIWORD_MASKED,
  267. which means each register holds 16 reset lines.
  268. config RESET_SUNXI
  269. bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
  270. default ARCH_SUNXI
  271. select RESET_SIMPLE
  272. help
  273. This enables the reset driver for Allwinner SoCs.
  274. config RESET_TH1520
  275. tristate "T-HEAD TH1520 reset controller"
  276. depends on ARCH_THEAD || COMPILE_TEST
  277. select REGMAP_MMIO
  278. help
  279. This driver provides support for the T-HEAD TH1520 SoC reset controller,
  280. which manages hardware reset lines for SoC components such as the GPU.
  281. Enable this option if you need to control hardware resets on TH1520-based
  282. systems.
  283. config RESET_TI_SCI
  284. tristate "TI System Control Interface (TI-SCI) reset driver"
  285. depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
  286. help
  287. This enables the reset driver support over TI System Control Interface
  288. available on some new TI's SoCs. If you wish to use reset resources
  289. managed by the TI System Controller, say Y here. Otherwise, say N.
  290. config RESET_TI_SYSCON
  291. tristate "TI SYSCON Reset Driver"
  292. depends on HAS_IOMEM
  293. select MFD_SYSCON
  294. help
  295. This enables the reset driver support for TI devices with
  296. memory-mapped reset registers as part of a syscon device node. If
  297. you wish to use the reset framework for such memory-mapped devices,
  298. say Y here. Otherwise, say N.
  299. config RESET_TI_TPS380X
  300. tristate "TI TPS380x Reset Driver"
  301. select GPIOLIB
  302. help
  303. This enables the reset driver support for TI TPS380x devices. If
  304. you wish to use the reset framework for such devices, say Y here.
  305. Otherwise, say N.
  306. config RESET_TN48M_CPLD
  307. tristate "Delta Networks TN48M switch CPLD reset controller"
  308. depends on MFD_TN48M_CPLD || COMPILE_TEST
  309. default MFD_TN48M_CPLD
  310. help
  311. This enables the reset controller driver for the Delta TN48M CPLD.
  312. It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
  313. switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
  314. Microchip PD69200 PoE PSE controller.
  315. This driver can also be built as a module. If so, the module will be
  316. called reset-tn48m.
  317. config RESET_UNIPHIER
  318. tristate "Reset controller driver for UniPhier SoCs"
  319. depends on ARCH_UNIPHIER || COMPILE_TEST
  320. depends on OF && MFD_SYSCON
  321. default ARCH_UNIPHIER
  322. help
  323. Support for reset controllers on UniPhier SoCs.
  324. Say Y if you want to control reset signals provided by System Control
  325. block, Media I/O block, Peripheral Block.
  326. config RESET_UNIPHIER_GLUE
  327. tristate "Reset driver in glue layer for UniPhier SoCs"
  328. depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
  329. default ARCH_UNIPHIER
  330. select RESET_SIMPLE
  331. help
  332. Support for peripheral core reset included in its own glue layer
  333. on UniPhier SoCs. Say Y if you want to control reset signals
  334. provided by the glue layer.
  335. config RESET_ZYNQ
  336. bool "ZYNQ Reset Driver" if COMPILE_TEST
  337. default ARCH_ZYNQ
  338. help
  339. This enables the reset controller driver for Xilinx Zynq SoCs.
  340. config RESET_ZYNQMP
  341. bool "ZYNQMP Reset Driver" if COMPILE_TEST
  342. default ARCH_ZYNQMP
  343. help
  344. This enables the reset controller driver for Xilinx ZynqMP SoCs.
  345. source "drivers/reset/amlogic/Kconfig"
  346. source "drivers/reset/hisilicon/Kconfig"
  347. source "drivers/reset/spacemit/Kconfig"
  348. source "drivers/reset/starfive/Kconfig"
  349. source "drivers/reset/sti/Kconfig"
  350. source "drivers/reset/tegra/Kconfig"
  351. endif