s5m8767.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright (c) 2011 Samsung Electronics Co., Ltd
  4. // http://www.samsung.com
  5. #include <linux/cleanup.h>
  6. #include <linux/err.h>
  7. #include <linux/of.h>
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/regulator/driver.h>
  12. #include <linux/regulator/machine.h>
  13. #include <linux/mfd/samsung/core.h>
  14. #include <linux/mfd/samsung/s5m8767.h>
  15. #include <linux/regulator/of_regulator.h>
  16. #include <linux/regmap.h>
  17. #define S5M8767_OPMODE_NORMAL_MODE 0x1
  18. struct s5m8767_info {
  19. struct device *dev;
  20. struct sec_pmic_dev *iodev;
  21. int num_regulators;
  22. struct sec_opmode_data *opmode;
  23. int ramp_delay;
  24. bool buck2_ramp;
  25. bool buck3_ramp;
  26. bool buck4_ramp;
  27. bool buck2_gpiodvs;
  28. bool buck3_gpiodvs;
  29. bool buck4_gpiodvs;
  30. u8 buck2_vol[8];
  31. u8 buck3_vol[8];
  32. u8 buck4_vol[8];
  33. struct gpio_desc *buck_gpios[3];
  34. struct gpio_desc *buck_ds[3];
  35. int buck_gpioindex;
  36. };
  37. struct sec_voltage_desc {
  38. int max;
  39. int min;
  40. int step;
  41. };
  42. static const struct sec_voltage_desc buck_voltage_val1 = {
  43. .max = 2225000,
  44. .min = 650000,
  45. .step = 6250,
  46. };
  47. static const struct sec_voltage_desc buck_voltage_val2 = {
  48. .max = 1600000,
  49. .min = 600000,
  50. .step = 6250,
  51. };
  52. static const struct sec_voltage_desc buck_voltage_val3 = {
  53. .max = 3000000,
  54. .min = 750000,
  55. .step = 12500,
  56. };
  57. static const struct sec_voltage_desc ldo_voltage_val1 = {
  58. .max = 3950000,
  59. .min = 800000,
  60. .step = 50000,
  61. };
  62. static const struct sec_voltage_desc ldo_voltage_val2 = {
  63. .max = 2375000,
  64. .min = 800000,
  65. .step = 25000,
  66. };
  67. static const struct sec_voltage_desc *reg_voltage_map[] = {
  68. [S5M8767_LDO1] = &ldo_voltage_val2,
  69. [S5M8767_LDO2] = &ldo_voltage_val2,
  70. [S5M8767_LDO3] = &ldo_voltage_val1,
  71. [S5M8767_LDO4] = &ldo_voltage_val1,
  72. [S5M8767_LDO5] = &ldo_voltage_val1,
  73. [S5M8767_LDO6] = &ldo_voltage_val2,
  74. [S5M8767_LDO7] = &ldo_voltage_val2,
  75. [S5M8767_LDO8] = &ldo_voltage_val2,
  76. [S5M8767_LDO9] = &ldo_voltage_val1,
  77. [S5M8767_LDO10] = &ldo_voltage_val1,
  78. [S5M8767_LDO11] = &ldo_voltage_val1,
  79. [S5M8767_LDO12] = &ldo_voltage_val1,
  80. [S5M8767_LDO13] = &ldo_voltage_val1,
  81. [S5M8767_LDO14] = &ldo_voltage_val1,
  82. [S5M8767_LDO15] = &ldo_voltage_val2,
  83. [S5M8767_LDO16] = &ldo_voltage_val1,
  84. [S5M8767_LDO17] = &ldo_voltage_val1,
  85. [S5M8767_LDO18] = &ldo_voltage_val1,
  86. [S5M8767_LDO19] = &ldo_voltage_val1,
  87. [S5M8767_LDO20] = &ldo_voltage_val1,
  88. [S5M8767_LDO21] = &ldo_voltage_val1,
  89. [S5M8767_LDO22] = &ldo_voltage_val1,
  90. [S5M8767_LDO23] = &ldo_voltage_val1,
  91. [S5M8767_LDO24] = &ldo_voltage_val1,
  92. [S5M8767_LDO25] = &ldo_voltage_val1,
  93. [S5M8767_LDO26] = &ldo_voltage_val1,
  94. [S5M8767_LDO27] = &ldo_voltage_val1,
  95. [S5M8767_LDO28] = &ldo_voltage_val1,
  96. [S5M8767_BUCK1] = &buck_voltage_val1,
  97. [S5M8767_BUCK2] = &buck_voltage_val2,
  98. [S5M8767_BUCK3] = &buck_voltage_val2,
  99. [S5M8767_BUCK4] = &buck_voltage_val2,
  100. [S5M8767_BUCK5] = &buck_voltage_val1,
  101. [S5M8767_BUCK6] = &buck_voltage_val1,
  102. [S5M8767_BUCK7] = &buck_voltage_val3,
  103. [S5M8767_BUCK8] = &buck_voltage_val3,
  104. [S5M8767_BUCK9] = &buck_voltage_val3,
  105. };
  106. static const unsigned int s5m8767_opmode_reg[][4] = {
  107. /* {OFF, ON, LOWPOWER, SUSPEND} */
  108. /* LDO1 ... LDO28 */
  109. {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
  110. {0x0, 0x3, 0x2, 0x1},
  111. {0x0, 0x3, 0x2, 0x1},
  112. {0x0, 0x0, 0x0, 0x0},
  113. {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
  114. {0x0, 0x3, 0x2, 0x1},
  115. {0x0, 0x3, 0x2, 0x1},
  116. {0x0, 0x3, 0x2, 0x1},
  117. {0x0, 0x3, 0x2, 0x1},
  118. {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
  119. {0x0, 0x3, 0x2, 0x1},
  120. {0x0, 0x3, 0x2, 0x1},
  121. {0x0, 0x3, 0x2, 0x1},
  122. {0x0, 0x3, 0x2, 0x1},
  123. {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
  124. {0x0, 0x3, 0x2, 0x1},
  125. {0x0, 0x3, 0x2, 0x1},
  126. {0x0, 0x0, 0x0, 0x0},
  127. {0x0, 0x3, 0x2, 0x1},
  128. {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
  129. {0x0, 0x3, 0x2, 0x1},
  130. {0x0, 0x3, 0x2, 0x1},
  131. {0x0, 0x0, 0x0, 0x0},
  132. {0x0, 0x3, 0x2, 0x1},
  133. {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
  134. {0x0, 0x3, 0x2, 0x1},
  135. {0x0, 0x3, 0x2, 0x1},
  136. {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
  137. /* BUCK1 ... BUCK9 */
  138. {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */
  139. {0x0, 0x3, 0x1, 0x1},
  140. {0x0, 0x3, 0x1, 0x1},
  141. {0x0, 0x3, 0x1, 0x1},
  142. {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
  143. {0x0, 0x3, 0x1, 0x1},
  144. {0x0, 0x3, 0x1, 0x1},
  145. {0x0, 0x3, 0x1, 0x1},
  146. {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */
  147. };
  148. static int s5m8767_get_register(struct s5m8767_info *s5m8767, int reg_id,
  149. int *reg, int *enable_ctrl)
  150. {
  151. int i;
  152. unsigned int mode;
  153. switch (reg_id) {
  154. case S5M8767_LDO1 ... S5M8767_LDO2:
  155. *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
  156. break;
  157. case S5M8767_LDO3 ... S5M8767_LDO28:
  158. *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
  159. break;
  160. case S5M8767_BUCK1:
  161. *reg = S5M8767_REG_BUCK1CTRL1;
  162. break;
  163. case S5M8767_BUCK2 ... S5M8767_BUCK4:
  164. *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9;
  165. break;
  166. case S5M8767_BUCK5:
  167. *reg = S5M8767_REG_BUCK5CTRL1;
  168. break;
  169. case S5M8767_BUCK6 ... S5M8767_BUCK9:
  170. *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2;
  171. break;
  172. default:
  173. return -EINVAL;
  174. }
  175. for (i = 0; i < s5m8767->num_regulators; i++) {
  176. if (s5m8767->opmode[i].id == reg_id) {
  177. mode = s5m8767->opmode[i].mode;
  178. break;
  179. }
  180. }
  181. if (i >= s5m8767->num_regulators)
  182. return -EINVAL;
  183. *enable_ctrl = s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT;
  184. return 0;
  185. }
  186. static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767)
  187. {
  188. int reg;
  189. switch (reg_id) {
  190. case S5M8767_LDO1 ... S5M8767_LDO2:
  191. reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
  192. break;
  193. case S5M8767_LDO3 ... S5M8767_LDO28:
  194. reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
  195. break;
  196. case S5M8767_BUCK1:
  197. reg = S5M8767_REG_BUCK1CTRL2;
  198. break;
  199. case S5M8767_BUCK2:
  200. reg = S5M8767_REG_BUCK2DVS1;
  201. if (s5m8767->buck2_gpiodvs)
  202. reg += s5m8767->buck_gpioindex;
  203. break;
  204. case S5M8767_BUCK3:
  205. reg = S5M8767_REG_BUCK3DVS1;
  206. if (s5m8767->buck3_gpiodvs)
  207. reg += s5m8767->buck_gpioindex;
  208. break;
  209. case S5M8767_BUCK4:
  210. reg = S5M8767_REG_BUCK4DVS1;
  211. if (s5m8767->buck4_gpiodvs)
  212. reg += s5m8767->buck_gpioindex;
  213. break;
  214. case S5M8767_BUCK5:
  215. reg = S5M8767_REG_BUCK5CTRL2;
  216. break;
  217. case S5M8767_BUCK6 ... S5M8767_BUCK9:
  218. reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2;
  219. break;
  220. default:
  221. return -EINVAL;
  222. }
  223. return reg;
  224. }
  225. static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc,
  226. int min_vol)
  227. {
  228. int selector = 0;
  229. if (desc == NULL)
  230. return -EINVAL;
  231. if (min_vol > desc->max)
  232. return -EINVAL;
  233. if (min_vol < desc->min)
  234. min_vol = desc->min;
  235. selector = DIV_ROUND_UP(min_vol - desc->min, desc->step);
  236. if (desc->min + desc->step * selector > desc->max)
  237. return -EINVAL;
  238. return selector;
  239. }
  240. static inline int s5m8767_set_high(struct s5m8767_info *s5m8767)
  241. {
  242. int temp_index = s5m8767->buck_gpioindex;
  243. gpiod_set_value(s5m8767->buck_gpios[0], !!(temp_index & BIT(2)));
  244. gpiod_set_value(s5m8767->buck_gpios[1], !!(temp_index & BIT(1)));
  245. gpiod_set_value(s5m8767->buck_gpios[2], !!(temp_index & BIT(0)));
  246. return 0;
  247. }
  248. static inline int s5m8767_set_low(struct s5m8767_info *s5m8767)
  249. {
  250. int temp_index = s5m8767->buck_gpioindex;
  251. gpiod_set_value(s5m8767->buck_gpios[2], !!(temp_index & BIT(0)));
  252. gpiod_set_value(s5m8767->buck_gpios[1], !!(temp_index & BIT(1)));
  253. gpiod_set_value(s5m8767->buck_gpios[0], !!(temp_index & BIT(2)));
  254. return 0;
  255. }
  256. static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
  257. unsigned selector)
  258. {
  259. struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
  260. int reg_id = rdev_get_id(rdev);
  261. int old_index, index = 0;
  262. u8 *buck234_vol = NULL;
  263. switch (reg_id) {
  264. case S5M8767_LDO1 ... S5M8767_LDO28:
  265. break;
  266. case S5M8767_BUCK1 ... S5M8767_BUCK6:
  267. if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs)
  268. buck234_vol = &s5m8767->buck2_vol[0];
  269. else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs)
  270. buck234_vol = &s5m8767->buck3_vol[0];
  271. else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs)
  272. buck234_vol = &s5m8767->buck4_vol[0];
  273. break;
  274. case S5M8767_BUCK7 ... S5M8767_BUCK8:
  275. return -EINVAL;
  276. case S5M8767_BUCK9:
  277. break;
  278. default:
  279. return -EINVAL;
  280. }
  281. /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */
  282. if (buck234_vol) {
  283. while (*buck234_vol != selector) {
  284. buck234_vol++;
  285. index++;
  286. }
  287. old_index = s5m8767->buck_gpioindex;
  288. s5m8767->buck_gpioindex = index;
  289. if (index > old_index)
  290. return s5m8767_set_high(s5m8767);
  291. else
  292. return s5m8767_set_low(s5m8767);
  293. } else {
  294. return regulator_set_voltage_sel_regmap(rdev, selector);
  295. }
  296. }
  297. static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
  298. unsigned int old_sel,
  299. unsigned int new_sel)
  300. {
  301. struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
  302. if ((old_sel < new_sel) && s5m8767->ramp_delay)
  303. return DIV_ROUND_UP(rdev->desc->uV_step * (new_sel - old_sel),
  304. s5m8767->ramp_delay * 1000);
  305. return 0;
  306. }
  307. static const struct regulator_ops s5m8767_ops = {
  308. .list_voltage = regulator_list_voltage_linear,
  309. .is_enabled = regulator_is_enabled_regmap,
  310. .enable = regulator_enable_regmap,
  311. .disable = regulator_disable_regmap,
  312. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  313. .set_voltage_sel = s5m8767_set_voltage_sel,
  314. .set_voltage_time_sel = s5m8767_set_voltage_time_sel,
  315. };
  316. static const struct regulator_ops s5m8767_buck78_ops = {
  317. .list_voltage = regulator_list_voltage_linear,
  318. .is_enabled = regulator_is_enabled_regmap,
  319. .enable = regulator_enable_regmap,
  320. .disable = regulator_disable_regmap,
  321. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  322. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  323. };
  324. #define s5m8767_regulator_desc(_name) { \
  325. .name = #_name, \
  326. .id = S5M8767_##_name, \
  327. .ops = &s5m8767_ops, \
  328. .type = REGULATOR_VOLTAGE, \
  329. .owner = THIS_MODULE, \
  330. }
  331. #define s5m8767_regulator_buck78_desc(_name) { \
  332. .name = #_name, \
  333. .id = S5M8767_##_name, \
  334. .ops = &s5m8767_buck78_ops, \
  335. .type = REGULATOR_VOLTAGE, \
  336. .owner = THIS_MODULE, \
  337. }
  338. static struct regulator_desc regulators[] = {
  339. s5m8767_regulator_desc(LDO1),
  340. s5m8767_regulator_desc(LDO2),
  341. s5m8767_regulator_desc(LDO3),
  342. s5m8767_regulator_desc(LDO4),
  343. s5m8767_regulator_desc(LDO5),
  344. s5m8767_regulator_desc(LDO6),
  345. s5m8767_regulator_desc(LDO7),
  346. s5m8767_regulator_desc(LDO8),
  347. s5m8767_regulator_desc(LDO9),
  348. s5m8767_regulator_desc(LDO10),
  349. s5m8767_regulator_desc(LDO11),
  350. s5m8767_regulator_desc(LDO12),
  351. s5m8767_regulator_desc(LDO13),
  352. s5m8767_regulator_desc(LDO14),
  353. s5m8767_regulator_desc(LDO15),
  354. s5m8767_regulator_desc(LDO16),
  355. s5m8767_regulator_desc(LDO17),
  356. s5m8767_regulator_desc(LDO18),
  357. s5m8767_regulator_desc(LDO19),
  358. s5m8767_regulator_desc(LDO20),
  359. s5m8767_regulator_desc(LDO21),
  360. s5m8767_regulator_desc(LDO22),
  361. s5m8767_regulator_desc(LDO23),
  362. s5m8767_regulator_desc(LDO24),
  363. s5m8767_regulator_desc(LDO25),
  364. s5m8767_regulator_desc(LDO26),
  365. s5m8767_regulator_desc(LDO27),
  366. s5m8767_regulator_desc(LDO28),
  367. s5m8767_regulator_desc(BUCK1),
  368. s5m8767_regulator_desc(BUCK2),
  369. s5m8767_regulator_desc(BUCK3),
  370. s5m8767_regulator_desc(BUCK4),
  371. s5m8767_regulator_desc(BUCK5),
  372. s5m8767_regulator_desc(BUCK6),
  373. s5m8767_regulator_buck78_desc(BUCK7),
  374. s5m8767_regulator_buck78_desc(BUCK8),
  375. s5m8767_regulator_desc(BUCK9),
  376. };
  377. /*
  378. * Enable GPIO control over BUCK9 in regulator_config for that regulator.
  379. */
  380. static void s5m8767_regulator_config_ext_control(struct s5m8767_info *s5m8767,
  381. struct sec_regulator_data *rdata,
  382. struct regulator_config *config)
  383. {
  384. int i, mode = 0;
  385. if (rdata->id != S5M8767_BUCK9)
  386. return;
  387. /* Check if opmode for regulator matches S5M8767_ENCTRL_USE_GPIO */
  388. for (i = 0; i < s5m8767->num_regulators; i++) {
  389. const struct sec_opmode_data *opmode = &s5m8767->opmode[i];
  390. if (opmode->id == rdata->id) {
  391. mode = s5m8767_opmode_reg[rdata->id][opmode->mode];
  392. break;
  393. }
  394. }
  395. if (mode != S5M8767_ENCTRL_USE_GPIO) {
  396. dev_warn(s5m8767->dev,
  397. "ext-control for %pOFn: mismatched op_mode (%x), ignoring\n",
  398. rdata->reg_node, mode);
  399. return;
  400. }
  401. if (!rdata->ext_control_gpiod) {
  402. dev_warn(s5m8767->dev,
  403. "ext-control for %pOFn: GPIO not valid, ignoring\n",
  404. rdata->reg_node);
  405. return;
  406. }
  407. config->ena_gpiod = rdata->ext_control_gpiod;
  408. }
  409. /*
  410. * Turn on GPIO control over BUCK9.
  411. */
  412. static int s5m8767_enable_ext_control(struct s5m8767_info *s5m8767,
  413. struct regulator_dev *rdev)
  414. {
  415. int id = rdev_get_id(rdev);
  416. int ret, reg, enable_ctrl;
  417. if (id != S5M8767_BUCK9)
  418. return -EINVAL;
  419. ret = s5m8767_get_register(s5m8767, id, &reg, &enable_ctrl);
  420. if (ret)
  421. return ret;
  422. return regmap_update_bits(s5m8767->iodev->regmap_pmic,
  423. reg, S5M8767_ENCTRL_MASK,
  424. S5M8767_ENCTRL_USE_GPIO << S5M8767_ENCTRL_SHIFT);
  425. }
  426. #ifdef CONFIG_OF
  427. static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
  428. struct sec_platform_data *pdata)
  429. {
  430. struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
  431. struct device_node *pmic_np, *reg_np;
  432. struct sec_regulator_data *rdata;
  433. struct sec_opmode_data *rmode;
  434. unsigned int i, dvs_voltage_nr = 8;
  435. pmic_np = iodev->dev->of_node;
  436. if (!pmic_np) {
  437. dev_err(iodev->dev, "could not find pmic sub-node\n");
  438. return -ENODEV;
  439. }
  440. struct device_node *regulators_np __free(device_node) = of_get_child_by_name(pmic_np,
  441. "regulators");
  442. if (!regulators_np) {
  443. dev_err(iodev->dev, "could not find regulators sub-node\n");
  444. return -EINVAL;
  445. }
  446. /* count the number of regulators to be supported in pmic */
  447. pdata->num_regulators = of_get_child_count(regulators_np);
  448. rdata = devm_kcalloc(&pdev->dev,
  449. pdata->num_regulators, sizeof(*rdata),
  450. GFP_KERNEL);
  451. if (!rdata)
  452. return -ENOMEM;
  453. rmode = devm_kcalloc(&pdev->dev,
  454. pdata->num_regulators, sizeof(*rmode),
  455. GFP_KERNEL);
  456. if (!rmode)
  457. return -ENOMEM;
  458. pdata->regulators = rdata;
  459. pdata->opmode = rmode;
  460. for_each_child_of_node(regulators_np, reg_np) {
  461. for (i = 0; i < ARRAY_SIZE(regulators); i++)
  462. if (of_node_name_eq(reg_np, regulators[i].name))
  463. break;
  464. if (i == ARRAY_SIZE(regulators)) {
  465. dev_warn(iodev->dev,
  466. "don't know how to configure regulator %pOFn\n",
  467. reg_np);
  468. continue;
  469. }
  470. rdata->ext_control_gpiod = devm_fwnode_gpiod_get(
  471. &pdev->dev,
  472. of_fwnode_handle(reg_np),
  473. "s5m8767,pmic-ext-control",
  474. GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
  475. "s5m8767");
  476. if (PTR_ERR(rdata->ext_control_gpiod) == -ENOENT) {
  477. rdata->ext_control_gpiod = NULL;
  478. } else if (IS_ERR(rdata->ext_control_gpiod)) {
  479. of_node_put(reg_np);
  480. return PTR_ERR(rdata->ext_control_gpiod);
  481. }
  482. rdata->id = i;
  483. rdata->initdata = of_get_regulator_init_data(
  484. &pdev->dev, reg_np,
  485. &regulators[i]);
  486. rdata->reg_node = reg_np;
  487. rdata++;
  488. rmode->id = i;
  489. if (of_property_read_u32(reg_np, "op_mode",
  490. &rmode->mode)) {
  491. dev_warn(iodev->dev,
  492. "no op_mode property at %pOF\n",
  493. reg_np);
  494. rmode->mode = S5M8767_OPMODE_NORMAL_MODE;
  495. }
  496. rmode++;
  497. }
  498. if (of_property_read_bool(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs")) {
  499. pdata->buck2_gpiodvs = true;
  500. if (of_property_read_u32_array(pmic_np,
  501. "s5m8767,pmic-buck2-dvs-voltage",
  502. pdata->buck2_voltage, dvs_voltage_nr)) {
  503. dev_err(iodev->dev, "buck2 voltages not specified\n");
  504. return -EINVAL;
  505. }
  506. }
  507. if (of_property_read_bool(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs")) {
  508. pdata->buck3_gpiodvs = true;
  509. if (of_property_read_u32_array(pmic_np,
  510. "s5m8767,pmic-buck3-dvs-voltage",
  511. pdata->buck3_voltage, dvs_voltage_nr)) {
  512. dev_err(iodev->dev, "buck3 voltages not specified\n");
  513. return -EINVAL;
  514. }
  515. }
  516. if (of_property_read_bool(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs")) {
  517. pdata->buck4_gpiodvs = true;
  518. if (of_property_read_u32_array(pmic_np,
  519. "s5m8767,pmic-buck4-dvs-voltage",
  520. pdata->buck4_voltage, dvs_voltage_nr)) {
  521. dev_err(iodev->dev, "buck4 voltages not specified\n");
  522. return -EINVAL;
  523. }
  524. }
  525. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  526. pdata->buck4_gpiodvs) {
  527. if (of_property_read_u32(pmic_np,
  528. "s5m8767,pmic-buck-default-dvs-idx",
  529. &pdata->buck_default_idx)) {
  530. pdata->buck_default_idx = 0;
  531. } else {
  532. if (pdata->buck_default_idx >= 8) {
  533. pdata->buck_default_idx = 0;
  534. dev_info(iodev->dev,
  535. "invalid value for default dvs index, use 0\n");
  536. }
  537. }
  538. }
  539. pdata->buck2_ramp_enable = of_property_read_bool(pmic_np, "s5m8767,pmic-buck2-ramp-enable");
  540. pdata->buck3_ramp_enable = of_property_read_bool(pmic_np, "s5m8767,pmic-buck3-ramp-enable");
  541. pdata->buck4_ramp_enable = of_property_read_bool(pmic_np, "s5m8767,pmic-buck4-ramp-enable");
  542. if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable
  543. || pdata->buck4_ramp_enable) {
  544. if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay",
  545. &pdata->buck_ramp_delay))
  546. pdata->buck_ramp_delay = 0;
  547. }
  548. return 0;
  549. }
  550. #else
  551. static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
  552. struct sec_platform_data *pdata)
  553. {
  554. return 0;
  555. }
  556. #endif /* CONFIG_OF */
  557. static int s5m8767_pmic_probe(struct platform_device *pdev)
  558. {
  559. struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
  560. struct sec_platform_data *pdata = iodev->pdata;
  561. struct regulator_config config = { };
  562. struct s5m8767_info *s5m8767;
  563. int i, ret, buck_init;
  564. const char *gpiods_names[3] = { "S5M8767 DS2", "S5M8767 DS3", "S5M8767 DS4" };
  565. const char *gpiodvs_names[3] = { "S5M8767 SET1", "S5M8767 SET2", "S5M8767 SET3" };
  566. if (!pdata) {
  567. dev_err(pdev->dev.parent, "Platform data not supplied\n");
  568. return -ENODEV;
  569. }
  570. if (iodev->dev->of_node) {
  571. ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata);
  572. if (ret)
  573. return ret;
  574. }
  575. if (pdata->buck2_gpiodvs) {
  576. if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) {
  577. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  578. return -EINVAL;
  579. }
  580. }
  581. if (pdata->buck3_gpiodvs) {
  582. if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) {
  583. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  584. return -EINVAL;
  585. }
  586. }
  587. if (pdata->buck4_gpiodvs) {
  588. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) {
  589. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  590. return -EINVAL;
  591. }
  592. }
  593. s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info),
  594. GFP_KERNEL);
  595. if (!s5m8767)
  596. return -ENOMEM;
  597. s5m8767->dev = &pdev->dev;
  598. s5m8767->iodev = iodev;
  599. s5m8767->num_regulators = pdata->num_regulators;
  600. platform_set_drvdata(pdev, s5m8767);
  601. s5m8767->buck_gpioindex = pdata->buck_default_idx;
  602. s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs;
  603. s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs;
  604. s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs;
  605. s5m8767->ramp_delay = pdata->buck_ramp_delay;
  606. s5m8767->buck2_ramp = pdata->buck2_ramp_enable;
  607. s5m8767->buck3_ramp = pdata->buck3_ramp_enable;
  608. s5m8767->buck4_ramp = pdata->buck4_ramp_enable;
  609. s5m8767->opmode = pdata->opmode;
  610. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  611. pdata->buck2_init);
  612. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2,
  613. buck_init);
  614. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  615. pdata->buck3_init);
  616. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2,
  617. buck_init);
  618. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  619. pdata->buck4_init);
  620. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2,
  621. buck_init);
  622. for (i = 0; i < 8; i++) {
  623. if (s5m8767->buck2_gpiodvs) {
  624. s5m8767->buck2_vol[i] =
  625. s5m8767_convert_voltage_to_sel(
  626. &buck_voltage_val2,
  627. pdata->buck2_voltage[i]);
  628. }
  629. if (s5m8767->buck3_gpiodvs) {
  630. s5m8767->buck3_vol[i] =
  631. s5m8767_convert_voltage_to_sel(
  632. &buck_voltage_val2,
  633. pdata->buck3_voltage[i]);
  634. }
  635. if (s5m8767->buck4_gpiodvs) {
  636. s5m8767->buck4_vol[i] =
  637. s5m8767_convert_voltage_to_sel(
  638. &buck_voltage_val2,
  639. pdata->buck4_voltage[i]);
  640. }
  641. }
  642. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  643. pdata->buck4_gpiodvs) {
  644. for (i = 0; i < 3; i++) {
  645. enum gpiod_flags flags;
  646. if (s5m8767->buck_gpioindex & BIT(2 - i))
  647. flags = GPIOD_OUT_HIGH;
  648. else
  649. flags = GPIOD_OUT_LOW;
  650. s5m8767->buck_gpios[i] = devm_gpiod_get_index(iodev->dev,
  651. "s5m8767,pmic-buck-dvs", i,
  652. flags);
  653. if (IS_ERR(s5m8767->buck_gpios[i])) {
  654. return dev_err_probe(iodev->dev, PTR_ERR(s5m8767->buck_gpios[i]),
  655. "invalid gpio[%d]\n", i);
  656. }
  657. gpiod_set_consumer_name(s5m8767->buck_gpios[i], gpiodvs_names[i]);
  658. }
  659. }
  660. for (i = 0; i < 3; i++) {
  661. s5m8767->buck_ds[i] = devm_gpiod_get_index(iodev->dev,
  662. "s5m8767,pmic-buck-ds", i,
  663. GPIOD_OUT_LOW);
  664. if (IS_ERR(s5m8767->buck_ds[i])) {
  665. return dev_err_probe(iodev->dev, PTR_ERR(s5m8767->buck_ds[i]),
  666. "can't get GPIO %d\n", i);
  667. }
  668. gpiod_set_consumer_name(s5m8767->buck_ds[i], gpiods_names[i]);
  669. }
  670. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  671. S5M8767_REG_BUCK2CTRL, 1 << 1,
  672. (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1));
  673. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  674. S5M8767_REG_BUCK3CTRL, 1 << 1,
  675. (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1));
  676. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  677. S5M8767_REG_BUCK4CTRL, 1 << 1,
  678. (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1));
  679. /* Initialize GPIO DVS registers */
  680. for (i = 0; i < 8; i++) {
  681. if (s5m8767->buck2_gpiodvs) {
  682. regmap_write(s5m8767->iodev->regmap_pmic,
  683. S5M8767_REG_BUCK2DVS1 + i,
  684. s5m8767->buck2_vol[i]);
  685. }
  686. if (s5m8767->buck3_gpiodvs) {
  687. regmap_write(s5m8767->iodev->regmap_pmic,
  688. S5M8767_REG_BUCK3DVS1 + i,
  689. s5m8767->buck3_vol[i]);
  690. }
  691. if (s5m8767->buck4_gpiodvs) {
  692. regmap_write(s5m8767->iodev->regmap_pmic,
  693. S5M8767_REG_BUCK4DVS1 + i,
  694. s5m8767->buck4_vol[i]);
  695. }
  696. }
  697. if (s5m8767->buck2_ramp)
  698. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  699. S5M8767_REG_DVSRAMP, 0x08, 0x08);
  700. if (s5m8767->buck3_ramp)
  701. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  702. S5M8767_REG_DVSRAMP, 0x04, 0x04);
  703. if (s5m8767->buck4_ramp)
  704. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  705. S5M8767_REG_DVSRAMP, 0x02, 0x02);
  706. if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
  707. || s5m8767->buck4_ramp) {
  708. unsigned int val;
  709. switch (s5m8767->ramp_delay) {
  710. case 5:
  711. val = S5M8767_DVS_BUCK_RAMP_5;
  712. break;
  713. case 10:
  714. val = S5M8767_DVS_BUCK_RAMP_10;
  715. break;
  716. case 25:
  717. val = S5M8767_DVS_BUCK_RAMP_25;
  718. break;
  719. case 50:
  720. val = S5M8767_DVS_BUCK_RAMP_50;
  721. break;
  722. case 100:
  723. val = S5M8767_DVS_BUCK_RAMP_100;
  724. break;
  725. default:
  726. val = S5M8767_DVS_BUCK_RAMP_10;
  727. }
  728. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  729. S5M8767_REG_DVSRAMP,
  730. S5M8767_DVS_BUCK_RAMP_MASK,
  731. val << S5M8767_DVS_BUCK_RAMP_SHIFT);
  732. }
  733. for (i = 0; i < pdata->num_regulators; i++) {
  734. const struct sec_voltage_desc *desc;
  735. unsigned int id = pdata->regulators[i].id;
  736. int enable_reg, enable_val;
  737. struct regulator_dev *rdev;
  738. BUILD_BUG_ON(ARRAY_SIZE(regulators) != ARRAY_SIZE(reg_voltage_map));
  739. if (WARN_ON_ONCE(id >= ARRAY_SIZE(regulators)))
  740. continue;
  741. desc = reg_voltage_map[id];
  742. if (desc) {
  743. regulators[id].n_voltages =
  744. (desc->max - desc->min) / desc->step + 1;
  745. regulators[id].min_uV = desc->min;
  746. regulators[id].uV_step = desc->step;
  747. regulators[id].vsel_reg =
  748. s5m8767_get_vsel_reg(id, s5m8767);
  749. if (id < S5M8767_BUCK1)
  750. regulators[id].vsel_mask = 0x3f;
  751. else
  752. regulators[id].vsel_mask = 0xff;
  753. ret = s5m8767_get_register(s5m8767, id, &enable_reg,
  754. &enable_val);
  755. if (ret) {
  756. dev_err(s5m8767->dev, "error reading registers\n");
  757. return ret;
  758. }
  759. regulators[id].enable_reg = enable_reg;
  760. regulators[id].enable_mask = S5M8767_ENCTRL_MASK;
  761. regulators[id].enable_val = enable_val;
  762. }
  763. config.dev = s5m8767->dev;
  764. config.init_data = pdata->regulators[i].initdata;
  765. config.driver_data = s5m8767;
  766. config.regmap = iodev->regmap_pmic;
  767. config.of_node = pdata->regulators[i].reg_node;
  768. config.ena_gpiod = NULL;
  769. if (pdata->regulators[i].ext_control_gpiod) {
  770. /* Assigns config.ena_gpiod */
  771. s5m8767_regulator_config_ext_control(s5m8767,
  772. &pdata->regulators[i], &config);
  773. /*
  774. * Hand the GPIO descriptor management over to the
  775. * regulator core, remove it from devres management.
  776. */
  777. devm_gpiod_unhinge(s5m8767->dev, config.ena_gpiod);
  778. }
  779. rdev = devm_regulator_register(&pdev->dev, &regulators[id],
  780. &config);
  781. if (IS_ERR(rdev)) {
  782. ret = PTR_ERR(rdev);
  783. dev_err(s5m8767->dev, "regulator init failed for %d\n",
  784. id);
  785. return ret;
  786. }
  787. if (pdata->regulators[i].ext_control_gpiod) {
  788. ret = s5m8767_enable_ext_control(s5m8767, rdev);
  789. if (ret < 0) {
  790. dev_err(s5m8767->dev,
  791. "failed to enable gpio control over %s: %d\n",
  792. rdev->desc->name, ret);
  793. return ret;
  794. }
  795. }
  796. }
  797. return 0;
  798. }
  799. static const struct platform_device_id s5m8767_pmic_id[] = {
  800. { "s5m8767-pmic", 0},
  801. { },
  802. };
  803. MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id);
  804. static struct platform_driver s5m8767_pmic_driver = {
  805. .driver = {
  806. .name = "s5m8767-pmic",
  807. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  808. },
  809. .probe = s5m8767_pmic_probe,
  810. .id_table = s5m8767_pmic_id,
  811. };
  812. module_platform_driver(s5m8767_pmic_driver);
  813. /* Module information */
  814. MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
  815. MODULE_DESCRIPTION("Samsung S5M8767 Regulator Driver");
  816. MODULE_LICENSE("GPL");