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ARK-OS
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arkos
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kernel
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drivers
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pinctrl
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starfive
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pinctrl-starfive-jh7110.h

pinctrl-starfive-jh7110.h 1.9 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /*
    3. 

  3.  * Pinctrl / GPIO driver for StarFive JH7110 SoC
    4. 

  4.  *
    5. 

  5.  * Copyright (C) 2022 StarFive Technology Co., Ltd.
    6. 

  6.  */
    7. 

  7. 

  8. #ifndef __PINCTRL_STARFIVE_JH7110_H__
    9. 

  9. #define __PINCTRL_STARFIVE_JH7110_H__
    10. 

  10. 

  11. #include <linux/pinctrl/pinconf-generic.h>
    12. 

  12. #include <linux/pinctrl/pinmux.h>
    13. 

  13. 

  14. struct jh7110_pinctrl {
    15. 

  15. 	struct device *dev;
    16. 

  16. 	struct gpio_chip gc;
    17. 

  17. 	struct pinctrl_gpio_range gpios;
    18. 

  18. 	raw_spinlock_t lock;
    19. 

  19. 	void __iomem *base;
    20. 

  20. 	struct pinctrl_dev *pctl;
    21. 

  21. 	/* register read/write mutex */
    22. 

  22. 	struct mutex mutex;
    23. 

  23. 	const struct jh7110_pinctrl_soc_info *info;
    24. 

  24. 	u32 *saved_regs;
    25. 

  25. };
    26. 

  26. 

  27. struct jh7110_gpio_irq_reg {
    28. 

  28. 	unsigned int is_reg_base;
    29. 

  29. 	unsigned int ic_reg_base;
    30. 

  30. 	unsigned int ibe_reg_base;
    31. 

  31. 	unsigned int iev_reg_base;
    32. 

  32. 	unsigned int ie_reg_base;
    33. 

  33. 	unsigned int ris_reg_base;
    34. 

  34. 	unsigned int mis_reg_base;
    35. 

  35. };
    36. 

  36. 

  37. struct jh7110_pinctrl_soc_info {
    38. 

  38. 	const struct pinctrl_pin_desc *pins;
    39. 

  39. 	unsigned int npins;
    40. 

  40. 	unsigned int ngpios;
    41. 

  41. 

  42. 	/* gpio dout/doen/din/gpioinput register */
    43. 

  43. 	unsigned int dout_reg_base;
    44. 

  44. 	unsigned int dout_mask;
    45. 

  45. 	unsigned int doen_reg_base;
    46. 

  46. 	unsigned int doen_mask;
    47. 

  47. 	unsigned int gpi_reg_base;
    48. 

  48. 	unsigned int gpi_mask;
    49. 

  49. 	unsigned int gpioin_reg_base;
    50. 

  50. 

  51. 	const struct jh7110_gpio_irq_reg *irq_reg;
    52. 

  52. 

  53. 	unsigned int nsaved_regs;
    54. 

  54. 

  55. 	/* generic pinmux */
    56. 

  56. 	int (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *sfp,
    57. 

  57. 				      unsigned int pin,
    58. 

  58. 				      unsigned int din, u32 dout,
    59. 

  59. 				      u32 doen, u32 func);
    60. 

  60. 	/* gpio chip */
    61. 

  61. 	int (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *sfp,
    62. 

  62. 				      unsigned int pin);
    63. 

  63. 	void (*jh7110_gpio_irq_handler)(struct irq_desc *desc);
    64. 

  64. 	int (*jh7110_gpio_init_hw)(struct gpio_chip *gc);
    65. 

  65. };
    66. 

  66. 

  67. void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
    68. 

  68. 			unsigned int din, u32 dout, u32 doen);
    69. 

  69. int jh7110_pinctrl_probe(struct platform_device *pdev);
    70. 

  70. struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc);
    71. 

  71. extern const struct dev_pm_ops jh7110_pinctrl_pm_ops;
    72. 

  72. 

  73. #endif /* __PINCTRL_STARFIVE_JH7110_H__ */
    74.