pinctrl-sprd.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Spreadtrum pin controller driver
  4. * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
  5. */
  6. #include <linux/debugfs.h>
  7. #include <linux/err.h>
  8. #include <linux/init.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/seq_file.h>
  15. #include <linux/slab.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/pinctrl/machine.h>
  18. #include <linux/pinctrl/pinconf-generic.h>
  19. #include <linux/pinctrl/pinconf.h>
  20. #include <linux/pinctrl/pinctrl.h>
  21. #include <linux/pinctrl/pinmux.h>
  22. #include "../core.h"
  23. #include "../pinmux.h"
  24. #include "../pinconf.h"
  25. #include "../pinctrl-utils.h"
  26. #include "pinctrl-sprd.h"
  27. #define PINCTRL_BIT_MASK(width) (~(~0UL << (width)))
  28. #define PINCTRL_REG_OFFSET 0x20
  29. #define PINCTRL_REG_MISC_OFFSET 0x4020
  30. #define PINCTRL_REG_LEN 0x4
  31. #define PIN_FUNC_MASK (BIT(4) | BIT(5))
  32. #define PIN_FUNC_SEL_1 ~PIN_FUNC_MASK
  33. #define PIN_FUNC_SEL_2 BIT(4)
  34. #define PIN_FUNC_SEL_3 BIT(5)
  35. #define PIN_FUNC_SEL_4 PIN_FUNC_MASK
  36. #define AP_SLEEP_MODE BIT(13)
  37. #define PUBCP_SLEEP_MODE BIT(14)
  38. #define TGLDSP_SLEEP_MODE BIT(15)
  39. #define AGDSP_SLEEP_MODE BIT(16)
  40. #define CM4_SLEEP_MODE BIT(17)
  41. #define SLEEP_MODE_MASK GENMASK(5, 0)
  42. #define SLEEP_MODE_SHIFT 13
  43. #define SLEEP_INPUT BIT(1)
  44. #define SLEEP_INPUT_MASK 0x1
  45. #define SLEEP_INPUT_SHIFT 1
  46. #define SLEEP_OUTPUT BIT(0)
  47. #define SLEEP_OUTPUT_MASK 0x1
  48. #define SLEEP_OUTPUT_SHIFT 0
  49. #define DRIVE_STRENGTH_MASK GENMASK(3, 0)
  50. #define DRIVE_STRENGTH_SHIFT 19
  51. #define SLEEP_PULL_DOWN BIT(2)
  52. #define SLEEP_PULL_DOWN_MASK 0x1
  53. #define SLEEP_PULL_DOWN_SHIFT 2
  54. #define PULL_DOWN BIT(6)
  55. #define PULL_DOWN_MASK 0x1
  56. #define PULL_DOWN_SHIFT 6
  57. #define SLEEP_PULL_UP BIT(3)
  58. #define SLEEP_PULL_UP_MASK 0x1
  59. #define SLEEP_PULL_UP_SHIFT 3
  60. #define PULL_UP_4_7K (BIT(12) | BIT(7))
  61. #define PULL_UP_20K BIT(7)
  62. #define PULL_UP_MASK 0x21
  63. #define PULL_UP_SHIFT 7
  64. #define INPUT_SCHMITT BIT(11)
  65. #define INPUT_SCHMITT_MASK 0x1
  66. #define INPUT_SCHMITT_SHIFT 11
  67. enum pin_sleep_mode {
  68. AP_SLEEP = BIT(0),
  69. PUBCP_SLEEP = BIT(1),
  70. TGLDSP_SLEEP = BIT(2),
  71. AGDSP_SLEEP = BIT(3),
  72. CM4_SLEEP = BIT(4),
  73. };
  74. enum pin_func_sel {
  75. PIN_FUNC_1,
  76. PIN_FUNC_2,
  77. PIN_FUNC_3,
  78. PIN_FUNC_4,
  79. PIN_FUNC_MAX,
  80. };
  81. /**
  82. * struct sprd_pin: represent one pin's description
  83. * @name: pin name
  84. * @number: pin number
  85. * @type: pin type, can be GLOBAL_CTRL_PIN/COMMON_PIN/MISC_PIN
  86. * @reg: pin register address
  87. * @bit_offset: bit offset in pin register
  88. * @bit_width: bit width in pin register
  89. */
  90. struct sprd_pin {
  91. const char *name;
  92. unsigned int number;
  93. enum pin_type type;
  94. unsigned long reg;
  95. unsigned long bit_offset;
  96. unsigned long bit_width;
  97. };
  98. /**
  99. * struct sprd_pin_group: represent one group's description
  100. * @name: group name
  101. * @npins: pin numbers of this group
  102. * @pins: pointer to pins array
  103. */
  104. struct sprd_pin_group {
  105. const char *name;
  106. unsigned int npins;
  107. unsigned int *pins;
  108. };
  109. /**
  110. * struct sprd_pinctrl_soc_info: represent the SoC's pins description
  111. * @groups: pointer to groups of pins
  112. * @ngroups: group numbers of the whole SoC
  113. * @pins: pointer to pins description
  114. * @npins: pin numbers of the whole SoC
  115. * @grp_names: pointer to group names array
  116. */
  117. struct sprd_pinctrl_soc_info {
  118. struct sprd_pin_group *groups;
  119. unsigned int ngroups;
  120. struct sprd_pin *pins;
  121. unsigned int npins;
  122. const char **grp_names;
  123. };
  124. /**
  125. * struct sprd_pinctrl: represent the pin controller device
  126. * @dev: pointer to the device structure
  127. * @pctl: pointer to the pinctrl handle
  128. * @base: base address of the controller
  129. * @info: pointer to SoC's pins description information
  130. */
  131. struct sprd_pinctrl {
  132. struct device *dev;
  133. struct pinctrl_dev *pctl;
  134. void __iomem *base;
  135. struct sprd_pinctrl_soc_info *info;
  136. };
  137. #define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
  138. #define SPRD_PIN_CONFIG_SLEEP_MODE (PIN_CONFIG_END + 2)
  139. static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl,
  140. const char *name)
  141. {
  142. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  143. int i;
  144. for (i = 0; i < info->npins; i++) {
  145. if (!strcmp(info->pins[i].name, name))
  146. return info->pins[i].number;
  147. }
  148. return -ENODEV;
  149. }
  150. static struct sprd_pin *
  151. sprd_pinctrl_get_pin_by_id(struct sprd_pinctrl *sprd_pctl, unsigned int id)
  152. {
  153. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  154. struct sprd_pin *pin = NULL;
  155. int i;
  156. for (i = 0; i < info->npins; i++) {
  157. if (info->pins[i].number == id) {
  158. pin = &info->pins[i];
  159. break;
  160. }
  161. }
  162. return pin;
  163. }
  164. static const struct sprd_pin_group *
  165. sprd_pinctrl_find_group_by_name(struct sprd_pinctrl *sprd_pctl,
  166. const char *name)
  167. {
  168. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  169. const struct sprd_pin_group *grp = NULL;
  170. int i;
  171. for (i = 0; i < info->ngroups; i++) {
  172. if (!strcmp(info->groups[i].name, name)) {
  173. grp = &info->groups[i];
  174. break;
  175. }
  176. }
  177. return grp;
  178. }
  179. static int sprd_pctrl_group_count(struct pinctrl_dev *pctldev)
  180. {
  181. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  182. struct sprd_pinctrl_soc_info *info = pctl->info;
  183. return info->ngroups;
  184. }
  185. static const char *sprd_pctrl_group_name(struct pinctrl_dev *pctldev,
  186. unsigned int selector)
  187. {
  188. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  189. struct sprd_pinctrl_soc_info *info = pctl->info;
  190. return info->groups[selector].name;
  191. }
  192. static int sprd_pctrl_group_pins(struct pinctrl_dev *pctldev,
  193. unsigned int selector,
  194. const unsigned int **pins,
  195. unsigned int *npins)
  196. {
  197. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  198. struct sprd_pinctrl_soc_info *info = pctl->info;
  199. if (selector >= info->ngroups)
  200. return -EINVAL;
  201. *pins = info->groups[selector].pins;
  202. *npins = info->groups[selector].npins;
  203. return 0;
  204. }
  205. static int sprd_dt_node_to_map(struct pinctrl_dev *pctldev,
  206. struct device_node *np,
  207. struct pinctrl_map **map,
  208. unsigned int *num_maps)
  209. {
  210. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  211. const struct sprd_pin_group *grp;
  212. unsigned long *configs = NULL;
  213. unsigned int num_configs = 0;
  214. unsigned int reserved_maps = 0;
  215. unsigned int reserve = 0;
  216. const char *function;
  217. enum pinctrl_map_type type;
  218. int ret;
  219. grp = sprd_pinctrl_find_group_by_name(pctl, np->name);
  220. if (!grp) {
  221. dev_err(pctl->dev, "unable to find group for node %pOF\n", np);
  222. return -EINVAL;
  223. }
  224. ret = of_property_count_strings(np, "pins");
  225. if (ret < 0)
  226. return ret;
  227. if (ret == 1)
  228. type = PIN_MAP_TYPE_CONFIGS_PIN;
  229. else
  230. type = PIN_MAP_TYPE_CONFIGS_GROUP;
  231. ret = of_property_read_string(np, "function", &function);
  232. if (ret < 0) {
  233. if (ret != -EINVAL)
  234. dev_err(pctl->dev,
  235. "%pOF: could not parse property function\n", np);
  236. function = NULL;
  237. }
  238. ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
  239. &num_configs);
  240. if (ret < 0) {
  241. dev_err(pctl->dev, "%pOF: could not parse node property\n", np);
  242. return ret;
  243. }
  244. *map = NULL;
  245. *num_maps = 0;
  246. if (function != NULL)
  247. reserve++;
  248. if (num_configs)
  249. reserve++;
  250. ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
  251. num_maps, reserve);
  252. if (ret < 0)
  253. goto out;
  254. if (function) {
  255. ret = pinctrl_utils_add_map_mux(pctldev, map,
  256. &reserved_maps, num_maps,
  257. grp->name, function);
  258. if (ret < 0)
  259. goto out;
  260. }
  261. if (num_configs) {
  262. const char *group_or_pin;
  263. unsigned int pin_id;
  264. if (type == PIN_MAP_TYPE_CONFIGS_PIN) {
  265. pin_id = grp->pins[0];
  266. group_or_pin = pin_get_name(pctldev, pin_id);
  267. } else {
  268. group_or_pin = grp->name;
  269. }
  270. ret = pinctrl_utils_add_map_configs(pctldev, map,
  271. &reserved_maps, num_maps,
  272. group_or_pin, configs,
  273. num_configs, type);
  274. }
  275. out:
  276. kfree(configs);
  277. return ret;
  278. }
  279. static void sprd_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  280. unsigned int offset)
  281. {
  282. seq_printf(s, "%s", dev_name(pctldev->dev));
  283. }
  284. static const struct pinctrl_ops sprd_pctrl_ops = {
  285. .get_groups_count = sprd_pctrl_group_count,
  286. .get_group_name = sprd_pctrl_group_name,
  287. .get_group_pins = sprd_pctrl_group_pins,
  288. .pin_dbg_show = sprd_pctrl_dbg_show,
  289. .dt_node_to_map = sprd_dt_node_to_map,
  290. .dt_free_map = pinctrl_utils_free_map,
  291. };
  292. static int sprd_pmx_get_function_count(struct pinctrl_dev *pctldev)
  293. {
  294. return PIN_FUNC_MAX;
  295. }
  296. static const char *sprd_pmx_get_function_name(struct pinctrl_dev *pctldev,
  297. unsigned int selector)
  298. {
  299. switch (selector) {
  300. case PIN_FUNC_1:
  301. return "func1";
  302. case PIN_FUNC_2:
  303. return "func2";
  304. case PIN_FUNC_3:
  305. return "func3";
  306. case PIN_FUNC_4:
  307. return "func4";
  308. default:
  309. return "null";
  310. }
  311. }
  312. static int sprd_pmx_get_function_groups(struct pinctrl_dev *pctldev,
  313. unsigned int selector,
  314. const char * const **groups,
  315. unsigned int * const num_groups)
  316. {
  317. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  318. struct sprd_pinctrl_soc_info *info = pctl->info;
  319. *groups = info->grp_names;
  320. *num_groups = info->ngroups;
  321. return 0;
  322. }
  323. static int sprd_pmx_set_mux(struct pinctrl_dev *pctldev,
  324. unsigned int func_selector,
  325. unsigned int group_selector)
  326. {
  327. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  328. struct sprd_pinctrl_soc_info *info = pctl->info;
  329. struct sprd_pin_group *grp = &info->groups[group_selector];
  330. unsigned int i, grp_pins = grp->npins;
  331. unsigned long reg;
  332. unsigned int val = 0;
  333. if (group_selector >= info->ngroups)
  334. return -EINVAL;
  335. switch (func_selector) {
  336. case PIN_FUNC_1:
  337. val &= PIN_FUNC_SEL_1;
  338. break;
  339. case PIN_FUNC_2:
  340. val |= PIN_FUNC_SEL_2;
  341. break;
  342. case PIN_FUNC_3:
  343. val |= PIN_FUNC_SEL_3;
  344. break;
  345. case PIN_FUNC_4:
  346. val |= PIN_FUNC_SEL_4;
  347. break;
  348. default:
  349. break;
  350. }
  351. for (i = 0; i < grp_pins; i++) {
  352. unsigned int pin_id = grp->pins[i];
  353. struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
  354. if (!pin || pin->type != COMMON_PIN)
  355. continue;
  356. reg = readl((void __iomem *)pin->reg);
  357. reg &= ~PIN_FUNC_MASK;
  358. reg |= val;
  359. writel(reg, (void __iomem *)pin->reg);
  360. }
  361. return 0;
  362. }
  363. static const struct pinmux_ops sprd_pmx_ops = {
  364. .get_functions_count = sprd_pmx_get_function_count,
  365. .get_function_name = sprd_pmx_get_function_name,
  366. .get_function_groups = sprd_pmx_get_function_groups,
  367. .set_mux = sprd_pmx_set_mux,
  368. };
  369. static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
  370. unsigned long *config)
  371. {
  372. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  373. struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
  374. unsigned int param = pinconf_to_config_param(*config);
  375. unsigned int reg, arg;
  376. if (!pin)
  377. return -EINVAL;
  378. if (pin->type == GLOBAL_CTRL_PIN) {
  379. reg = (readl((void __iomem *)pin->reg) >>
  380. pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
  381. } else {
  382. reg = readl((void __iomem *)pin->reg);
  383. }
  384. if (pin->type == GLOBAL_CTRL_PIN &&
  385. param == SPRD_PIN_CONFIG_CONTROL) {
  386. arg = reg;
  387. } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
  388. switch (param) {
  389. case SPRD_PIN_CONFIG_SLEEP_MODE:
  390. arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK;
  391. break;
  392. case PIN_CONFIG_INPUT_ENABLE:
  393. arg = (reg >> SLEEP_INPUT_SHIFT) & SLEEP_INPUT_MASK;
  394. break;
  395. case PIN_CONFIG_OUTPUT_ENABLE:
  396. arg = reg & SLEEP_OUTPUT_MASK;
  397. break;
  398. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  399. if ((reg & SLEEP_OUTPUT) || (reg & SLEEP_INPUT))
  400. return -EINVAL;
  401. arg = 1;
  402. break;
  403. case PIN_CONFIG_DRIVE_STRENGTH:
  404. arg = (reg >> DRIVE_STRENGTH_SHIFT) &
  405. DRIVE_STRENGTH_MASK;
  406. break;
  407. case PIN_CONFIG_BIAS_PULL_DOWN:
  408. /* combine sleep pull down and pull down config */
  409. arg = ((reg >> SLEEP_PULL_DOWN_SHIFT) &
  410. SLEEP_PULL_DOWN_MASK) << 16;
  411. arg |= (reg >> PULL_DOWN_SHIFT) & PULL_DOWN_MASK;
  412. break;
  413. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  414. arg = (reg >> INPUT_SCHMITT_SHIFT) & INPUT_SCHMITT_MASK;
  415. break;
  416. case PIN_CONFIG_BIAS_PULL_UP:
  417. /* combine sleep pull up and pull up config */
  418. arg = ((reg >> SLEEP_PULL_UP_SHIFT) &
  419. SLEEP_PULL_UP_MASK) << 16;
  420. arg |= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK;
  421. break;
  422. case PIN_CONFIG_BIAS_DISABLE:
  423. if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
  424. (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
  425. return -EINVAL;
  426. arg = 1;
  427. break;
  428. case PIN_CONFIG_SLEEP_HARDWARE_STATE:
  429. arg = 0;
  430. break;
  431. default:
  432. return -ENOTSUPP;
  433. }
  434. } else {
  435. return -ENOTSUPP;
  436. }
  437. *config = pinconf_to_config_packed(param, arg);
  438. return 0;
  439. }
  440. static unsigned int sprd_pinconf_drive(unsigned int mA)
  441. {
  442. unsigned int val = 0;
  443. switch (mA) {
  444. case 2:
  445. break;
  446. case 4:
  447. val |= BIT(19);
  448. break;
  449. case 6:
  450. val |= BIT(20);
  451. break;
  452. case 8:
  453. val |= BIT(19) | BIT(20);
  454. break;
  455. case 10:
  456. val |= BIT(21);
  457. break;
  458. case 12:
  459. val |= BIT(21) | BIT(19);
  460. break;
  461. case 14:
  462. val |= BIT(21) | BIT(20);
  463. break;
  464. case 16:
  465. val |= BIT(19) | BIT(20) | BIT(21);
  466. break;
  467. case 20:
  468. val |= BIT(22);
  469. break;
  470. case 21:
  471. val |= BIT(22) | BIT(19);
  472. break;
  473. case 24:
  474. val |= BIT(22) | BIT(20);
  475. break;
  476. case 25:
  477. val |= BIT(22) | BIT(20) | BIT(19);
  478. break;
  479. case 27:
  480. val |= BIT(22) | BIT(21);
  481. break;
  482. case 29:
  483. val |= BIT(22) | BIT(21) | BIT(19);
  484. break;
  485. case 31:
  486. val |= BIT(22) | BIT(21) | BIT(20);
  487. break;
  488. case 33:
  489. val |= BIT(22) | BIT(21) | BIT(20) | BIT(19);
  490. break;
  491. default:
  492. break;
  493. }
  494. return val;
  495. }
  496. static bool sprd_pinctrl_check_sleep_config(unsigned long *configs,
  497. unsigned int num_configs)
  498. {
  499. unsigned int param;
  500. int i;
  501. for (i = 0; i < num_configs; i++) {
  502. param = pinconf_to_config_param(configs[i]);
  503. if (param == PIN_CONFIG_SLEEP_HARDWARE_STATE)
  504. return true;
  505. }
  506. return false;
  507. }
  508. static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
  509. unsigned long *configs, unsigned int num_configs)
  510. {
  511. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  512. struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
  513. bool is_sleep_config;
  514. unsigned long reg;
  515. int i;
  516. if (!pin)
  517. return -EINVAL;
  518. is_sleep_config = sprd_pinctrl_check_sleep_config(configs, num_configs);
  519. for (i = 0; i < num_configs; i++) {
  520. unsigned int param, arg, shift, mask, val;
  521. param = pinconf_to_config_param(configs[i]);
  522. arg = pinconf_to_config_argument(configs[i]);
  523. val = 0;
  524. shift = 0;
  525. mask = 0;
  526. if (pin->type == GLOBAL_CTRL_PIN &&
  527. param == SPRD_PIN_CONFIG_CONTROL) {
  528. val = arg;
  529. } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
  530. switch (param) {
  531. case SPRD_PIN_CONFIG_SLEEP_MODE:
  532. if (arg & AP_SLEEP)
  533. val |= AP_SLEEP_MODE;
  534. if (arg & PUBCP_SLEEP)
  535. val |= PUBCP_SLEEP_MODE;
  536. if (arg & TGLDSP_SLEEP)
  537. val |= TGLDSP_SLEEP_MODE;
  538. if (arg & AGDSP_SLEEP)
  539. val |= AGDSP_SLEEP_MODE;
  540. if (arg & CM4_SLEEP)
  541. val |= CM4_SLEEP_MODE;
  542. mask = SLEEP_MODE_MASK;
  543. shift = SLEEP_MODE_SHIFT;
  544. break;
  545. case PIN_CONFIG_INPUT_ENABLE:
  546. if (is_sleep_config == true) {
  547. if (arg > 0)
  548. val |= SLEEP_INPUT;
  549. else
  550. val &= ~SLEEP_INPUT;
  551. mask = SLEEP_INPUT_MASK;
  552. shift = SLEEP_INPUT_SHIFT;
  553. }
  554. break;
  555. case PIN_CONFIG_OUTPUT_ENABLE:
  556. if (is_sleep_config == true) {
  557. if (arg > 0)
  558. val |= SLEEP_OUTPUT;
  559. else
  560. val &= ~SLEEP_OUTPUT;
  561. mask = SLEEP_OUTPUT_MASK;
  562. shift = SLEEP_OUTPUT_SHIFT;
  563. }
  564. break;
  565. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  566. if (is_sleep_config == true) {
  567. val = shift = 0;
  568. mask = SLEEP_OUTPUT | SLEEP_INPUT;
  569. }
  570. break;
  571. case PIN_CONFIG_DRIVE_STRENGTH:
  572. if (arg < 2 || arg > 60)
  573. return -EINVAL;
  574. val = sprd_pinconf_drive(arg);
  575. mask = DRIVE_STRENGTH_MASK;
  576. shift = DRIVE_STRENGTH_SHIFT;
  577. break;
  578. case PIN_CONFIG_BIAS_PULL_DOWN:
  579. if (is_sleep_config == true) {
  580. val |= SLEEP_PULL_DOWN;
  581. mask = SLEEP_PULL_DOWN_MASK;
  582. shift = SLEEP_PULL_DOWN_SHIFT;
  583. } else {
  584. val |= PULL_DOWN;
  585. mask = PULL_DOWN_MASK;
  586. shift = PULL_DOWN_SHIFT;
  587. }
  588. break;
  589. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  590. if (arg > 0)
  591. val |= INPUT_SCHMITT;
  592. else
  593. val &= ~INPUT_SCHMITT;
  594. mask = INPUT_SCHMITT_MASK;
  595. shift = INPUT_SCHMITT_SHIFT;
  596. break;
  597. case PIN_CONFIG_BIAS_PULL_UP:
  598. if (is_sleep_config) {
  599. val |= SLEEP_PULL_UP;
  600. mask = SLEEP_PULL_UP_MASK;
  601. shift = SLEEP_PULL_UP_SHIFT;
  602. } else {
  603. if (arg == 20000)
  604. val |= PULL_UP_20K;
  605. else if (arg == 4700)
  606. val |= PULL_UP_4_7K;
  607. mask = PULL_UP_MASK;
  608. shift = PULL_UP_SHIFT;
  609. }
  610. break;
  611. case PIN_CONFIG_BIAS_DISABLE:
  612. if (is_sleep_config == true) {
  613. val = shift = 0;
  614. mask = SLEEP_PULL_DOWN | SLEEP_PULL_UP;
  615. } else {
  616. val = shift = 0;
  617. mask = PULL_DOWN | PULL_UP_20K |
  618. PULL_UP_4_7K;
  619. }
  620. break;
  621. case PIN_CONFIG_SLEEP_HARDWARE_STATE:
  622. continue;
  623. default:
  624. return -ENOTSUPP;
  625. }
  626. } else {
  627. return -ENOTSUPP;
  628. }
  629. if (pin->type == GLOBAL_CTRL_PIN) {
  630. reg = readl((void __iomem *)pin->reg);
  631. reg &= ~(PINCTRL_BIT_MASK(pin->bit_width)
  632. << pin->bit_offset);
  633. reg |= (val & PINCTRL_BIT_MASK(pin->bit_width))
  634. << pin->bit_offset;
  635. writel(reg, (void __iomem *)pin->reg);
  636. } else {
  637. reg = readl((void __iomem *)pin->reg);
  638. reg &= ~(mask << shift);
  639. reg |= val;
  640. writel(reg, (void __iomem *)pin->reg);
  641. }
  642. }
  643. return 0;
  644. }
  645. static int sprd_pinconf_group_get(struct pinctrl_dev *pctldev,
  646. unsigned int selector, unsigned long *config)
  647. {
  648. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  649. struct sprd_pinctrl_soc_info *info = pctl->info;
  650. struct sprd_pin_group *grp;
  651. unsigned int pin_id;
  652. if (selector >= info->ngroups)
  653. return -EINVAL;
  654. grp = &info->groups[selector];
  655. pin_id = grp->pins[0];
  656. return sprd_pinconf_get(pctldev, pin_id, config);
  657. }
  658. static int sprd_pinconf_group_set(struct pinctrl_dev *pctldev,
  659. unsigned int selector,
  660. unsigned long *configs,
  661. unsigned int num_configs)
  662. {
  663. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  664. struct sprd_pinctrl_soc_info *info = pctl->info;
  665. struct sprd_pin_group *grp;
  666. int ret, i;
  667. if (selector >= info->ngroups)
  668. return -EINVAL;
  669. grp = &info->groups[selector];
  670. for (i = 0; i < grp->npins; i++) {
  671. unsigned int pin_id = grp->pins[i];
  672. ret = sprd_pinconf_set(pctldev, pin_id, configs, num_configs);
  673. if (ret)
  674. return ret;
  675. }
  676. return 0;
  677. }
  678. static int sprd_pinconf_get_config(struct pinctrl_dev *pctldev,
  679. unsigned int pin_id,
  680. unsigned long *config)
  681. {
  682. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  683. struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
  684. if (!pin)
  685. return -EINVAL;
  686. if (pin->type == GLOBAL_CTRL_PIN) {
  687. *config = (readl((void __iomem *)pin->reg) >>
  688. pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
  689. } else {
  690. *config = readl((void __iomem *)pin->reg);
  691. }
  692. return 0;
  693. }
  694. static void sprd_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  695. struct seq_file *s, unsigned int pin_id)
  696. {
  697. unsigned long config;
  698. int ret;
  699. ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
  700. if (ret)
  701. return;
  702. seq_printf(s, "0x%lx", config);
  703. }
  704. static void sprd_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
  705. struct seq_file *s,
  706. unsigned int selector)
  707. {
  708. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  709. struct sprd_pinctrl_soc_info *info = pctl->info;
  710. struct sprd_pin_group *grp;
  711. unsigned long config;
  712. const char *name;
  713. int i, ret;
  714. if (selector >= info->ngroups)
  715. return;
  716. grp = &info->groups[selector];
  717. seq_putc(s, '\n');
  718. for (i = 0; i < grp->npins; i++, config++) {
  719. unsigned int pin_id = grp->pins[i];
  720. name = pin_get_name(pctldev, pin_id);
  721. ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
  722. if (ret)
  723. return;
  724. seq_printf(s, "%s: 0x%lx ", name, config);
  725. }
  726. }
  727. static const struct pinconf_ops sprd_pinconf_ops = {
  728. .is_generic = true,
  729. .pin_config_get = sprd_pinconf_get,
  730. .pin_config_set = sprd_pinconf_set,
  731. .pin_config_group_get = sprd_pinconf_group_get,
  732. .pin_config_group_set = sprd_pinconf_group_set,
  733. .pin_config_dbg_show = sprd_pinconf_dbg_show,
  734. .pin_config_group_dbg_show = sprd_pinconf_group_dbg_show,
  735. };
  736. static const struct pinconf_generic_params sprd_dt_params[] = {
  737. {"sprd,control", SPRD_PIN_CONFIG_CONTROL, 0},
  738. {"sprd,sleep-mode", SPRD_PIN_CONFIG_SLEEP_MODE, 0},
  739. };
  740. #ifdef CONFIG_DEBUG_FS
  741. static const struct pin_config_item sprd_conf_items[] = {
  742. PCONFDUMP(SPRD_PIN_CONFIG_CONTROL, "global control", NULL, true),
  743. PCONFDUMP(SPRD_PIN_CONFIG_SLEEP_MODE, "sleep mode", NULL, true),
  744. };
  745. #endif
  746. static struct pinctrl_desc sprd_pinctrl_desc = {
  747. .pctlops = &sprd_pctrl_ops,
  748. .pmxops = &sprd_pmx_ops,
  749. .confops = &sprd_pinconf_ops,
  750. .num_custom_params = ARRAY_SIZE(sprd_dt_params),
  751. .custom_params = sprd_dt_params,
  752. #ifdef CONFIG_DEBUG_FS
  753. .custom_conf_items = sprd_conf_items,
  754. #endif
  755. .owner = THIS_MODULE,
  756. };
  757. static int sprd_pinctrl_parse_groups(struct device_node *np,
  758. struct sprd_pinctrl *sprd_pctl,
  759. struct sprd_pin_group *grp)
  760. {
  761. struct property *prop;
  762. const char *pin_name;
  763. int ret, i = 0;
  764. ret = of_property_count_strings(np, "pins");
  765. if (ret < 0)
  766. return ret;
  767. grp->name = np->name;
  768. grp->npins = ret;
  769. grp->pins = devm_kcalloc(sprd_pctl->dev,
  770. grp->npins, sizeof(unsigned int),
  771. GFP_KERNEL);
  772. if (!grp->pins)
  773. return -ENOMEM;
  774. of_property_for_each_string(np, "pins", prop, pin_name) {
  775. ret = sprd_pinctrl_get_id_by_name(sprd_pctl, pin_name);
  776. if (ret >= 0)
  777. grp->pins[i++] = ret;
  778. }
  779. for (i = 0; i < grp->npins; i++) {
  780. dev_dbg(sprd_pctl->dev,
  781. "Group[%s] contains [%d] pins: id = %d\n",
  782. grp->name, grp->npins, grp->pins[i]);
  783. }
  784. return 0;
  785. }
  786. static unsigned int sprd_pinctrl_get_groups(struct device_node *np)
  787. {
  788. struct device_node *child;
  789. unsigned int group_cnt, cnt;
  790. group_cnt = of_get_child_count(np);
  791. for_each_child_of_node(np, child) {
  792. cnt = of_get_child_count(child);
  793. if (cnt > 0)
  794. group_cnt += cnt;
  795. }
  796. return group_cnt;
  797. }
  798. static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
  799. {
  800. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  801. struct device_node *np = sprd_pctl->dev->of_node;
  802. struct sprd_pin_group *grp;
  803. const char **temp;
  804. int ret;
  805. if (!np)
  806. return -ENODEV;
  807. info->ngroups = sprd_pinctrl_get_groups(np);
  808. if (!info->ngroups)
  809. return 0;
  810. info->groups = devm_kcalloc(sprd_pctl->dev,
  811. info->ngroups,
  812. sizeof(struct sprd_pin_group),
  813. GFP_KERNEL);
  814. if (!info->groups)
  815. return -ENOMEM;
  816. info->grp_names = devm_kcalloc(sprd_pctl->dev,
  817. info->ngroups, sizeof(char *),
  818. GFP_KERNEL);
  819. if (!info->grp_names)
  820. return -ENOMEM;
  821. temp = info->grp_names;
  822. grp = info->groups;
  823. for_each_child_of_node_scoped(np, child) {
  824. ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp);
  825. if (ret)
  826. return ret;
  827. *temp++ = grp->name;
  828. grp++;
  829. if (of_get_child_count(child) > 0) {
  830. for_each_child_of_node_scoped(child, sub_child) {
  831. ret = sprd_pinctrl_parse_groups(sub_child,
  832. sprd_pctl, grp);
  833. if (ret)
  834. return ret;
  835. *temp++ = grp->name;
  836. grp++;
  837. }
  838. }
  839. }
  840. return 0;
  841. }
  842. static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
  843. struct sprd_pins_info *sprd_soc_pin_info,
  844. int pins_cnt)
  845. {
  846. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  847. unsigned int ctrl_pin = 0, com_pin = 0;
  848. struct sprd_pin *pin;
  849. int i;
  850. info->npins = pins_cnt;
  851. info->pins = devm_kcalloc(sprd_pctl->dev,
  852. info->npins, sizeof(struct sprd_pin),
  853. GFP_KERNEL);
  854. if (!info->pins)
  855. return -ENOMEM;
  856. for (i = 0, pin = info->pins; i < info->npins; i++, pin++) {
  857. unsigned int reg;
  858. pin->name = sprd_soc_pin_info[i].name;
  859. pin->type = sprd_soc_pin_info[i].type;
  860. pin->number = sprd_soc_pin_info[i].num;
  861. reg = sprd_soc_pin_info[i].reg;
  862. if (pin->type == GLOBAL_CTRL_PIN) {
  863. pin->reg = (unsigned long)sprd_pctl->base +
  864. PINCTRL_REG_LEN * reg;
  865. pin->bit_offset = sprd_soc_pin_info[i].bit_offset;
  866. pin->bit_width = sprd_soc_pin_info[i].bit_width;
  867. ctrl_pin++;
  868. } else if (pin->type == COMMON_PIN) {
  869. pin->reg = (unsigned long)sprd_pctl->base +
  870. PINCTRL_REG_OFFSET + PINCTRL_REG_LEN *
  871. (i - ctrl_pin);
  872. com_pin++;
  873. } else if (pin->type == MISC_PIN) {
  874. pin->reg = (unsigned long)sprd_pctl->base +
  875. PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN *
  876. (i - ctrl_pin - com_pin);
  877. }
  878. }
  879. for (i = 0, pin = info->pins; i < info->npins; pin++, i++) {
  880. dev_dbg(sprd_pctl->dev, "pin name[%s-%d], type = %d, "
  881. "bit offset = %ld, bit width = %ld, reg = 0x%lx\n",
  882. pin->name, pin->number, pin->type,
  883. pin->bit_offset, pin->bit_width, pin->reg);
  884. }
  885. return 0;
  886. }
  887. int sprd_pinctrl_core_probe(struct platform_device *pdev,
  888. struct sprd_pins_info *sprd_soc_pin_info,
  889. int pins_cnt)
  890. {
  891. struct sprd_pinctrl *sprd_pctl;
  892. struct sprd_pinctrl_soc_info *pinctrl_info;
  893. struct pinctrl_pin_desc *pin_desc;
  894. int ret, i;
  895. sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl),
  896. GFP_KERNEL);
  897. if (!sprd_pctl)
  898. return -ENOMEM;
  899. sprd_pctl->base = devm_platform_ioremap_resource(pdev, 0);
  900. if (IS_ERR(sprd_pctl->base))
  901. return PTR_ERR(sprd_pctl->base);
  902. pinctrl_info = devm_kzalloc(&pdev->dev,
  903. sizeof(struct sprd_pinctrl_soc_info),
  904. GFP_KERNEL);
  905. if (!pinctrl_info)
  906. return -ENOMEM;
  907. sprd_pctl->info = pinctrl_info;
  908. sprd_pctl->dev = &pdev->dev;
  909. platform_set_drvdata(pdev, sprd_pctl);
  910. ret = sprd_pinctrl_add_pins(sprd_pctl, sprd_soc_pin_info, pins_cnt);
  911. if (ret) {
  912. dev_err(&pdev->dev, "fail to add pins information\n");
  913. return ret;
  914. }
  915. ret = sprd_pinctrl_parse_dt(sprd_pctl);
  916. if (ret) {
  917. dev_err(&pdev->dev, "fail to parse dt properties\n");
  918. return ret;
  919. }
  920. pin_desc = devm_kcalloc(&pdev->dev,
  921. pinctrl_info->npins,
  922. sizeof(struct pinctrl_pin_desc),
  923. GFP_KERNEL);
  924. if (!pin_desc)
  925. return -ENOMEM;
  926. for (i = 0; i < pinctrl_info->npins; i++) {
  927. pin_desc[i].number = pinctrl_info->pins[i].number;
  928. pin_desc[i].name = pinctrl_info->pins[i].name;
  929. pin_desc[i].drv_data = pinctrl_info;
  930. }
  931. sprd_pinctrl_desc.pins = pin_desc;
  932. sprd_pinctrl_desc.name = dev_name(&pdev->dev);
  933. sprd_pinctrl_desc.npins = pinctrl_info->npins;
  934. sprd_pctl->pctl = pinctrl_register(&sprd_pinctrl_desc,
  935. &pdev->dev, (void *)sprd_pctl);
  936. if (IS_ERR(sprd_pctl->pctl)) {
  937. dev_err(&pdev->dev, "could not register pinctrl driver\n");
  938. return PTR_ERR(sprd_pctl->pctl);
  939. }
  940. return 0;
  941. }
  942. EXPORT_SYMBOL_GPL(sprd_pinctrl_core_probe);
  943. void sprd_pinctrl_remove(struct platform_device *pdev)
  944. {
  945. struct sprd_pinctrl *sprd_pctl = platform_get_drvdata(pdev);
  946. pinctrl_unregister(sprd_pctl->pctl);
  947. }
  948. EXPORT_SYMBOL_GPL(sprd_pinctrl_remove);
  949. void sprd_pinctrl_shutdown(struct platform_device *pdev)
  950. {
  951. struct pinctrl *pinctl;
  952. struct pinctrl_state *state;
  953. pinctl = devm_pinctrl_get(&pdev->dev);
  954. if (IS_ERR(pinctl))
  955. return;
  956. state = pinctrl_lookup_state(pinctl, "shutdown");
  957. if (IS_ERR(state))
  958. return;
  959. pinctrl_select_state(pinctl, state);
  960. }
  961. EXPORT_SYMBOL_GPL(sprd_pinctrl_shutdown);
  962. MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver");
  963. MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
  964. MODULE_LICENSE("GPL v2");