pinctrl-aw9523.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Awinic AW9523B i2c pin controller driver
  4. * Copyright (c) 2020, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
  5. */
  6. #include <linux/bitfield.h>
  7. #include <linux/errno.h>
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/gpio/driver.h>
  10. #include <linux/i2c.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irq.h>
  14. #include <linux/module.h>
  15. #include <linux/mutex.h>
  16. #include <linux/property.h>
  17. #include <linux/regmap.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/slab.h>
  20. #include <linux/pinctrl/pinconf-generic.h>
  21. #include <linux/pinctrl/pinconf.h>
  22. #include <linux/pinctrl/pinctrl.h>
  23. #include <linux/pinctrl/pinmux.h>
  24. #define AW9523_MAX_FUNCS 2
  25. #define AW9523_NUM_PORTS 2
  26. #define AW9523_PINS_PER_PORT 8
  27. /*
  28. * HW needs at least 20uS for reset and at least 1-2uS to recover from
  29. * reset, but we have to account for eventual board quirks, if any:
  30. * for this reason, keep reset asserted for 50uS and wait for 20uS
  31. * to recover from the reset.
  32. */
  33. #define AW9523_HW_RESET_US 50
  34. #define AW9523_HW_RESET_RECOVERY_US 20
  35. /* Port 0: P0_0...P0_7 - Port 1: P1_0...P1_7 */
  36. #define AW9523_PIN_TO_PORT(pin) (pin >> 3)
  37. #define AW9523_REG_IN_STATE(pin) (0x00 + AW9523_PIN_TO_PORT(pin))
  38. #define AW9523_REG_OUT_STATE(pin) (0x02 + AW9523_PIN_TO_PORT(pin))
  39. #define AW9523_REG_CONF_STATE(pin) (0x04 + AW9523_PIN_TO_PORT(pin))
  40. #define AW9523_REG_INTR_DIS(pin) (0x06 + AW9523_PIN_TO_PORT(pin))
  41. #define AW9523_REG_CHIPID 0x10
  42. #define AW9523_VAL_EXPECTED_CHIPID 0x23
  43. #define AW9523_REG_GCR 0x11
  44. #define AW9523_GCR_ISEL_MASK GENMASK(0, 1)
  45. #define AW9523_GCR_GPOMD_MASK BIT(4)
  46. #define AW9523_REG_PORT_MODE(pin) (0x12 + AW9523_PIN_TO_PORT(pin))
  47. #define AW9523_REG_SOFT_RESET 0x7f
  48. #define AW9523_VAL_RESET 0x00
  49. /*
  50. * struct aw9523_irq - Interrupt controller structure
  51. * @lock: mutex locking for the irq bus
  52. * @cached_gpio: stores the previous gpio status for bit comparison
  53. */
  54. struct aw9523_irq {
  55. struct mutex lock;
  56. u16 cached_gpio;
  57. };
  58. /*
  59. * struct aw9523 - Main driver structure
  60. * @dev: device handle
  61. * @regmap: regmap handle for current device
  62. * @i2c_lock: Mutex lock for i2c operations
  63. * @reset_gpio: Hardware reset (RSTN) signal GPIO
  64. * @vio_vreg: VCC regulator (Optional)
  65. * @pctl: pinctrl handle for current device
  66. * @gpio: structure holding gpiochip params
  67. * @irq: Interrupt controller structure
  68. */
  69. struct aw9523 {
  70. struct device *dev;
  71. struct regmap *regmap;
  72. struct mutex i2c_lock;
  73. struct gpio_desc *reset_gpio;
  74. int vio_vreg;
  75. struct pinctrl_dev *pctl;
  76. struct gpio_chip gpio;
  77. struct aw9523_irq *irq;
  78. };
  79. static const struct pinctrl_pin_desc aw9523_pins[] = {
  80. /* Port 0 */
  81. PINCTRL_PIN(0, "gpio0"),
  82. PINCTRL_PIN(1, "gpio1"),
  83. PINCTRL_PIN(2, "gpio2"),
  84. PINCTRL_PIN(3, "gpio3"),
  85. PINCTRL_PIN(4, "gpio4"),
  86. PINCTRL_PIN(5, "gpio5"),
  87. PINCTRL_PIN(6, "gpio6"),
  88. PINCTRL_PIN(7, "gpio7"),
  89. /* Port 1 */
  90. PINCTRL_PIN(8, "gpio8"),
  91. PINCTRL_PIN(9, "gpio9"),
  92. PINCTRL_PIN(10, "gpio10"),
  93. PINCTRL_PIN(11, "gpio11"),
  94. PINCTRL_PIN(12, "gpio12"),
  95. PINCTRL_PIN(13, "gpio13"),
  96. PINCTRL_PIN(14, "gpio14"),
  97. PINCTRL_PIN(15, "gpio15"),
  98. };
  99. static int aw9523_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  100. {
  101. return ARRAY_SIZE(aw9523_pins);
  102. }
  103. static const char *aw9523_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  104. unsigned int selector)
  105. {
  106. return aw9523_pins[selector].name;
  107. }
  108. static int aw9523_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  109. unsigned int selector,
  110. const unsigned int **pins,
  111. unsigned int *num_pins)
  112. {
  113. *pins = &aw9523_pins[selector].number;
  114. *num_pins = 1;
  115. return 0;
  116. }
  117. static const struct pinctrl_ops aw9523_pinctrl_ops = {
  118. .get_groups_count = aw9523_pinctrl_get_groups_count,
  119. .get_group_pins = aw9523_pinctrl_get_group_pins,
  120. .get_group_name = aw9523_pinctrl_get_group_name,
  121. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  122. .dt_free_map = pinconf_generic_dt_free_map,
  123. };
  124. static const char * const gpio_pwm_groups[] = {
  125. "gpio0", "gpio1", "gpio2", "gpio3", /* 0-3 */
  126. "gpio4", "gpio5", "gpio6", "gpio7", /* 4-7 */
  127. "gpio8", "gpio9", "gpio10", "gpio11", /* 8-11 */
  128. "gpio12", "gpio13", "gpio14", "gpio15", /* 11-15 */
  129. };
  130. /* Warning: Do NOT reorder this array */
  131. static const struct pinfunction aw9523_pmx[] = {
  132. PINCTRL_PINFUNCTION("pwm", gpio_pwm_groups, ARRAY_SIZE(gpio_pwm_groups)),
  133. PINCTRL_PINFUNCTION("gpio", gpio_pwm_groups, ARRAY_SIZE(gpio_pwm_groups)),
  134. };
  135. static int aw9523_pmx_get_funcs_count(struct pinctrl_dev *pctl)
  136. {
  137. return ARRAY_SIZE(aw9523_pmx);
  138. }
  139. static const char *aw9523_pmx_get_fname(struct pinctrl_dev *pctl,
  140. unsigned int sel)
  141. {
  142. return aw9523_pmx[sel].name;
  143. }
  144. static int aw9523_pmx_get_groups(struct pinctrl_dev *pctl, unsigned int sel,
  145. const char * const **groups,
  146. unsigned int * const ngroups)
  147. {
  148. *groups = aw9523_pmx[sel].groups;
  149. *ngroups = aw9523_pmx[sel].ngroups;
  150. return 0;
  151. }
  152. static int aw9523_pmx_set_mux(struct pinctrl_dev *pctl, unsigned int fsel,
  153. unsigned int grp)
  154. {
  155. struct aw9523 *awi = pinctrl_dev_get_drvdata(pctl);
  156. int ret, pin = aw9523_pins[grp].number % AW9523_PINS_PER_PORT;
  157. if (fsel >= ARRAY_SIZE(aw9523_pmx))
  158. return -EINVAL;
  159. /*
  160. * This maps directly to the aw9523_pmx array: programming a
  161. * high bit means "gpio" and a low bit means "pwm".
  162. */
  163. mutex_lock(&awi->i2c_lock);
  164. ret = regmap_update_bits(awi->regmap, AW9523_REG_PORT_MODE(pin),
  165. BIT(pin), (fsel ? BIT(pin) : 0));
  166. mutex_unlock(&awi->i2c_lock);
  167. return ret;
  168. }
  169. static const struct pinmux_ops aw9523_pinmux_ops = {
  170. .get_functions_count = aw9523_pmx_get_funcs_count,
  171. .get_function_name = aw9523_pmx_get_fname,
  172. .get_function_groups = aw9523_pmx_get_groups,
  173. .set_mux = aw9523_pmx_set_mux,
  174. };
  175. static int aw9523_pcfg_param_to_reg(enum pin_config_param pcp, int pin, u8 *r)
  176. {
  177. u8 reg;
  178. switch (pcp) {
  179. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  180. case PIN_CONFIG_BIAS_PULL_DOWN:
  181. case PIN_CONFIG_BIAS_PULL_UP:
  182. reg = AW9523_REG_IN_STATE(pin);
  183. break;
  184. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  185. case PIN_CONFIG_DRIVE_PUSH_PULL:
  186. reg = AW9523_REG_GCR;
  187. break;
  188. case PIN_CONFIG_INPUT_ENABLE:
  189. case PIN_CONFIG_OUTPUT_ENABLE:
  190. reg = AW9523_REG_CONF_STATE(pin);
  191. break;
  192. case PIN_CONFIG_LEVEL:
  193. reg = AW9523_REG_OUT_STATE(pin);
  194. break;
  195. default:
  196. return -ENOTSUPP;
  197. }
  198. *r = reg;
  199. return 0;
  200. }
  201. static int aw9523_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
  202. unsigned long *config)
  203. {
  204. struct aw9523 *awi = pinctrl_dev_get_drvdata(pctldev);
  205. enum pin_config_param param = pinconf_to_config_param(*config);
  206. int regbit = pin % AW9523_PINS_PER_PORT;
  207. unsigned int val;
  208. u8 reg;
  209. int rc;
  210. rc = aw9523_pcfg_param_to_reg(param, pin, &reg);
  211. if (rc)
  212. return rc;
  213. mutex_lock(&awi->i2c_lock);
  214. rc = regmap_read(awi->regmap, reg, &val);
  215. mutex_unlock(&awi->i2c_lock);
  216. if (rc)
  217. return rc;
  218. switch (param) {
  219. case PIN_CONFIG_BIAS_PULL_UP:
  220. case PIN_CONFIG_INPUT_ENABLE:
  221. case PIN_CONFIG_LEVEL:
  222. val &= BIT(regbit);
  223. break;
  224. case PIN_CONFIG_BIAS_PULL_DOWN:
  225. case PIN_CONFIG_OUTPUT_ENABLE:
  226. val &= BIT(regbit);
  227. val = !val;
  228. break;
  229. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  230. if (pin >= AW9523_PINS_PER_PORT)
  231. val = 0;
  232. else
  233. val = !FIELD_GET(AW9523_GCR_GPOMD_MASK, val);
  234. break;
  235. case PIN_CONFIG_DRIVE_PUSH_PULL:
  236. if (pin >= AW9523_PINS_PER_PORT)
  237. val = 1;
  238. else
  239. val = FIELD_GET(AW9523_GCR_GPOMD_MASK, val);
  240. break;
  241. default:
  242. return -ENOTSUPP;
  243. }
  244. if (val < 1)
  245. return -EINVAL;
  246. *config = pinconf_to_config_packed(param, !!val);
  247. return rc;
  248. }
  249. static int aw9523_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  250. unsigned long *configs, unsigned int num_configs)
  251. {
  252. struct aw9523 *awi = pinctrl_dev_get_drvdata(pctldev);
  253. enum pin_config_param param;
  254. int regbit = pin % AW9523_PINS_PER_PORT;
  255. u32 arg;
  256. u8 reg;
  257. unsigned int mask, val;
  258. int i, rc;
  259. guard(mutex)(&awi->i2c_lock);
  260. for (i = 0; i < num_configs; i++) {
  261. param = pinconf_to_config_param(configs[i]);
  262. arg = pinconf_to_config_argument(configs[i]);
  263. rc = aw9523_pcfg_param_to_reg(param, pin, &reg);
  264. if (rc)
  265. return rc;
  266. switch (param) {
  267. case PIN_CONFIG_LEVEL:
  268. /* First, enable pin output */
  269. rc = regmap_update_bits(awi->regmap,
  270. AW9523_REG_CONF_STATE(pin),
  271. BIT(regbit), 0);
  272. if (rc)
  273. return rc;
  274. /* Then, fall through to config output level */
  275. fallthrough;
  276. case PIN_CONFIG_OUTPUT_ENABLE:
  277. arg = !arg;
  278. fallthrough;
  279. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  280. case PIN_CONFIG_BIAS_PULL_DOWN:
  281. case PIN_CONFIG_BIAS_PULL_UP:
  282. case PIN_CONFIG_INPUT_ENABLE:
  283. mask = BIT(regbit);
  284. val = arg ? BIT(regbit) : 0;
  285. break;
  286. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  287. /* Open-Drain is supported only on port 0 */
  288. if (pin >= AW9523_PINS_PER_PORT)
  289. return -ENOTSUPP;
  290. mask = AW9523_GCR_GPOMD_MASK;
  291. val = 0;
  292. break;
  293. case PIN_CONFIG_DRIVE_PUSH_PULL:
  294. /* Port 1 is always Push-Pull */
  295. if (pin >= AW9523_PINS_PER_PORT) {
  296. mask = 0;
  297. val = 0;
  298. continue;
  299. }
  300. mask = AW9523_GCR_GPOMD_MASK;
  301. val = AW9523_GCR_GPOMD_MASK;
  302. break;
  303. default:
  304. return -ENOTSUPP;
  305. }
  306. rc = regmap_update_bits(awi->regmap, reg, mask, val);
  307. if (rc)
  308. return rc;
  309. }
  310. return 0;
  311. }
  312. static const struct pinconf_ops aw9523_pinconf_ops = {
  313. .pin_config_get = aw9523_pconf_get,
  314. .pin_config_set = aw9523_pconf_set,
  315. .is_generic = true,
  316. };
  317. /*
  318. * aw9523_get_pin_direction - Get pin direction
  319. * @regmap: Regmap structure
  320. * @pin: gpiolib pin number
  321. * @n: pin index in port register
  322. *
  323. * Return: Pin direction for success or negative number for error
  324. */
  325. static int aw9523_get_pin_direction(struct regmap *regmap, u8 pin, u8 n)
  326. {
  327. int ret;
  328. ret = regmap_test_bits(regmap, AW9523_REG_CONF_STATE(pin), BIT(n));
  329. if (ret < 0)
  330. return ret;
  331. return ret ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
  332. }
  333. /*
  334. * aw9523_get_port_state - Get input or output state for entire port
  335. * @regmap: Regmap structure
  336. * @pin: gpiolib pin number
  337. * @regbit: hw pin index, used to retrieve port number
  338. * @state: returned port state
  339. *
  340. * Return: Zero for success or negative number for error
  341. */
  342. static int aw9523_get_port_state(struct regmap *regmap, u8 pin, u8 regbit,
  343. unsigned int *state)
  344. {
  345. u8 reg;
  346. int dir;
  347. dir = aw9523_get_pin_direction(regmap, pin, regbit);
  348. if (dir < 0)
  349. return dir;
  350. if (dir == GPIO_LINE_DIRECTION_IN)
  351. reg = AW9523_REG_IN_STATE(pin);
  352. else
  353. reg = AW9523_REG_OUT_STATE(pin);
  354. return regmap_read(regmap, reg, state);
  355. }
  356. static int aw9523_gpio_irq_type(struct irq_data *d, unsigned int type)
  357. {
  358. switch (type) {
  359. case IRQ_TYPE_NONE:
  360. case IRQ_TYPE_EDGE_BOTH:
  361. return 0;
  362. default:
  363. return -EINVAL;
  364. };
  365. }
  366. /*
  367. * aw9523_irq_mask - Mask interrupt
  368. * @d: irq data
  369. *
  370. * Sets which interrupt to mask in the bitmap;
  371. * The interrupt will be masked when unlocking the irq bus.
  372. */
  373. static void aw9523_irq_mask(struct irq_data *d)
  374. {
  375. struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  376. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  377. unsigned int n = hwirq % AW9523_PINS_PER_PORT;
  378. regmap_update_bits(awi->regmap, AW9523_REG_INTR_DIS(hwirq),
  379. BIT(n), BIT(n));
  380. gpiochip_disable_irq(&awi->gpio, hwirq);
  381. }
  382. /*
  383. * aw9523_irq_unmask - Unmask interrupt
  384. * @d: irq data
  385. *
  386. * Sets which interrupt to unmask in the bitmap;
  387. * The interrupt will be masked when unlocking the irq bus.
  388. */
  389. static void aw9523_irq_unmask(struct irq_data *d)
  390. {
  391. struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  392. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  393. unsigned int n = hwirq % AW9523_PINS_PER_PORT;
  394. gpiochip_enable_irq(&awi->gpio, hwirq);
  395. regmap_update_bits(awi->regmap, AW9523_REG_INTR_DIS(hwirq),
  396. BIT(n), 0);
  397. }
  398. static irqreturn_t aw9523_irq_thread_func(int irq, void *dev_id)
  399. {
  400. struct aw9523 *awi = (struct aw9523 *)dev_id;
  401. unsigned long n, val = 0;
  402. unsigned long changed_gpio;
  403. unsigned int tmp, port_pin, i, ret;
  404. for (i = 0; i < AW9523_NUM_PORTS; i++) {
  405. port_pin = i * AW9523_PINS_PER_PORT;
  406. ret = regmap_read(awi->regmap,
  407. AW9523_REG_IN_STATE(port_pin),
  408. &tmp);
  409. if (ret)
  410. return ret;
  411. val |= (u8)tmp << (i * 8);
  412. }
  413. /* Handle GPIO input release interrupt as well */
  414. changed_gpio = awi->irq->cached_gpio ^ val;
  415. awi->irq->cached_gpio = val;
  416. /*
  417. * To avoid up to four *slow* i2c reads from any driver hooked
  418. * up to our interrupts, just check for the irq_find_mapping
  419. * result: if the interrupt is not mapped, then we don't want
  420. * to care about it.
  421. */
  422. for_each_set_bit(n, &changed_gpio, awi->gpio.ngpio) {
  423. tmp = irq_find_mapping(awi->gpio.irq.domain, n);
  424. if (tmp <= 0)
  425. continue;
  426. handle_nested_irq(tmp);
  427. }
  428. return IRQ_HANDLED;
  429. }
  430. /*
  431. * aw9523_irq_bus_lock - Grab lock for interrupt operation
  432. * @d: irq data
  433. */
  434. static void aw9523_irq_bus_lock(struct irq_data *d)
  435. {
  436. struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  437. mutex_lock(&awi->irq->lock);
  438. regcache_cache_only(awi->regmap, true);
  439. }
  440. /*
  441. * aw9523_irq_bus_sync_unlock - Synchronize state and unlock
  442. * @d: irq data
  443. *
  444. * Writes the interrupt mask bits (found in the bit map) to the
  445. * hardware, then unlocks the bus.
  446. */
  447. static void aw9523_irq_bus_sync_unlock(struct irq_data *d)
  448. {
  449. struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  450. regcache_cache_only(awi->regmap, false);
  451. regcache_sync(awi->regmap);
  452. mutex_unlock(&awi->irq->lock);
  453. }
  454. static int aw9523_gpio_get_direction(struct gpio_chip *chip,
  455. unsigned int offset)
  456. {
  457. struct aw9523 *awi = gpiochip_get_data(chip);
  458. u8 regbit = offset % AW9523_PINS_PER_PORT;
  459. int ret;
  460. mutex_lock(&awi->i2c_lock);
  461. ret = aw9523_get_pin_direction(awi->regmap, offset, regbit);
  462. mutex_unlock(&awi->i2c_lock);
  463. return ret;
  464. }
  465. static int aw9523_gpio_get(struct gpio_chip *chip, unsigned int offset)
  466. {
  467. struct aw9523 *awi = gpiochip_get_data(chip);
  468. u8 regbit = offset % AW9523_PINS_PER_PORT;
  469. unsigned int val;
  470. int ret;
  471. mutex_lock(&awi->i2c_lock);
  472. ret = aw9523_get_port_state(awi->regmap, offset, regbit, &val);
  473. mutex_unlock(&awi->i2c_lock);
  474. if (ret)
  475. return ret;
  476. return !!(val & BIT(regbit));
  477. }
  478. /**
  479. * _aw9523_gpio_get_multiple - Get I/O state for an entire port
  480. * @awi: Controller data
  481. * @regbit: hw pin index, used to retrieve port number
  482. * @state: returned port I/O state
  483. * @mask: lines to read values for
  484. *
  485. * Return: Zero for success or negative number for error
  486. */
  487. static int _aw9523_gpio_get_multiple(struct aw9523 *awi, u8 regbit,
  488. u8 *state, u8 mask)
  489. {
  490. u32 dir_in, val;
  491. u8 m;
  492. int ret;
  493. /* Registers are 8-bits wide */
  494. ret = regmap_read(awi->regmap, AW9523_REG_CONF_STATE(regbit), &dir_in);
  495. if (ret)
  496. return ret;
  497. *state = 0;
  498. m = mask & dir_in;
  499. if (m) {
  500. ret = regmap_read(awi->regmap, AW9523_REG_IN_STATE(regbit),
  501. &val);
  502. if (ret)
  503. return ret;
  504. *state |= (u8)val & m;
  505. }
  506. m = mask & ~dir_in;
  507. if (m) {
  508. ret = regmap_read(awi->regmap, AW9523_REG_OUT_STATE(regbit),
  509. &val);
  510. if (ret)
  511. return ret;
  512. *state |= (u8)val & m;
  513. }
  514. return 0;
  515. }
  516. static int aw9523_gpio_get_multiple(struct gpio_chip *chip,
  517. unsigned long *mask,
  518. unsigned long *bits)
  519. {
  520. struct aw9523 *awi = gpiochip_get_data(chip);
  521. u8 m, state = 0;
  522. int ret;
  523. guard(mutex)(&awi->i2c_lock);
  524. /* Port 0 (gpio 0-7) */
  525. m = *mask;
  526. if (m) {
  527. ret = _aw9523_gpio_get_multiple(awi, 0, &state, m);
  528. if (ret)
  529. return ret;
  530. }
  531. *bits = state;
  532. /* Port 1 (gpio 8-15) */
  533. m = *mask >> 8;
  534. if (m) {
  535. ret = _aw9523_gpio_get_multiple(awi, AW9523_PINS_PER_PORT,
  536. &state, m);
  537. if (ret)
  538. return ret;
  539. *bits |= (state << 8);
  540. }
  541. return 0;
  542. }
  543. static int aw9523_gpio_set_multiple(struct gpio_chip *chip,
  544. unsigned long *mask,
  545. unsigned long *bits)
  546. {
  547. struct aw9523 *awi = gpiochip_get_data(chip);
  548. u8 mask_lo, mask_hi, bits_lo, bits_hi;
  549. unsigned int reg;
  550. int ret;
  551. mask_lo = *mask;
  552. mask_hi = *mask >> 8;
  553. bits_lo = *bits;
  554. bits_hi = *bits >> 8;
  555. guard(mutex)(&awi->i2c_lock);
  556. if (mask_hi) {
  557. reg = AW9523_REG_OUT_STATE(AW9523_PINS_PER_PORT);
  558. ret = regmap_write_bits(awi->regmap, reg, mask_hi, bits_hi);
  559. if (ret)
  560. return ret;
  561. }
  562. if (mask_lo) {
  563. reg = AW9523_REG_OUT_STATE(0);
  564. ret = regmap_write_bits(awi->regmap, reg, mask_lo, bits_lo);
  565. if (ret)
  566. return ret;
  567. }
  568. return 0;
  569. }
  570. static int aw9523_gpio_set(struct gpio_chip *chip, unsigned int offset,
  571. int value)
  572. {
  573. struct aw9523 *awi = gpiochip_get_data(chip);
  574. u8 regbit = offset % AW9523_PINS_PER_PORT;
  575. int ret;
  576. mutex_lock(&awi->i2c_lock);
  577. ret = regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset),
  578. BIT(regbit), value ? BIT(regbit) : 0);
  579. mutex_unlock(&awi->i2c_lock);
  580. return ret;
  581. }
  582. static int aw9523_direction_input(struct gpio_chip *chip, unsigned int offset)
  583. {
  584. struct aw9523 *awi = gpiochip_get_data(chip);
  585. u8 regbit = offset % AW9523_PINS_PER_PORT;
  586. int ret;
  587. mutex_lock(&awi->i2c_lock);
  588. ret = regmap_update_bits(awi->regmap, AW9523_REG_CONF_STATE(offset),
  589. BIT(regbit), BIT(regbit));
  590. mutex_unlock(&awi->i2c_lock);
  591. return ret;
  592. }
  593. static int aw9523_direction_output(struct gpio_chip *chip,
  594. unsigned int offset, int value)
  595. {
  596. struct aw9523 *awi = gpiochip_get_data(chip);
  597. u8 regbit = offset % AW9523_PINS_PER_PORT;
  598. int ret;
  599. guard(mutex)(&awi->i2c_lock);
  600. ret = regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset),
  601. BIT(regbit), value ? BIT(regbit) : 0);
  602. if (ret)
  603. return ret;
  604. ret = regmap_update_bits(awi->regmap, AW9523_REG_CONF_STATE(offset),
  605. BIT(regbit), 0);
  606. return ret;
  607. }
  608. static int aw9523_drive_reset_gpio(struct aw9523 *awi)
  609. {
  610. unsigned int chip_id;
  611. int ret;
  612. /*
  613. * If the chip is already configured for any reason, then we
  614. * will probably succeed in sending the soft reset signal to
  615. * the hardware through I2C: this operation takes less time
  616. * compared to a full HW reset and it gives the same results.
  617. */
  618. ret = regmap_write(awi->regmap, AW9523_REG_SOFT_RESET, 0);
  619. if (ret == 0)
  620. goto done;
  621. dev_dbg(awi->dev, "Cannot execute soft reset: trying hard reset\n");
  622. ret = gpiod_direction_output(awi->reset_gpio, 0);
  623. if (ret)
  624. return ret;
  625. /* The reset pulse has to be longer than 20uS due to deglitch */
  626. usleep_range(AW9523_HW_RESET_US, AW9523_HW_RESET_US + 1);
  627. ret = gpiod_direction_output(awi->reset_gpio, 1);
  628. if (ret)
  629. return ret;
  630. done:
  631. /* The HW needs at least 1uS to reliably recover after reset */
  632. usleep_range(AW9523_HW_RESET_RECOVERY_US,
  633. AW9523_HW_RESET_RECOVERY_US + 1);
  634. /* Check the ChipID */
  635. ret = regmap_read(awi->regmap, AW9523_REG_CHIPID, &chip_id);
  636. if (ret) {
  637. dev_err(awi->dev, "Cannot read Chip ID: %d\n", ret);
  638. return ret;
  639. }
  640. if (chip_id != AW9523_VAL_EXPECTED_CHIPID) {
  641. dev_err(awi->dev, "Bad ChipID; read 0x%x, expected 0x%x\n",
  642. chip_id, AW9523_VAL_EXPECTED_CHIPID);
  643. return -EINVAL;
  644. }
  645. return 0;
  646. }
  647. static int aw9523_hw_reset(struct aw9523 *awi)
  648. {
  649. int ret, max_retries = 2;
  650. /* Sometimes the chip needs more than one reset cycle */
  651. do {
  652. ret = aw9523_drive_reset_gpio(awi);
  653. if (ret == 0)
  654. break;
  655. max_retries--;
  656. } while (max_retries);
  657. return ret;
  658. }
  659. static int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins)
  660. {
  661. struct device *dev = awi->dev;
  662. struct gpio_chip *gc = &awi->gpio;
  663. gc->label = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
  664. if (!gc->label)
  665. return -ENOMEM;
  666. gc->base = -1;
  667. gc->ngpio = npins;
  668. gc->get_direction = aw9523_gpio_get_direction;
  669. gc->direction_input = aw9523_direction_input;
  670. gc->direction_output = aw9523_direction_output;
  671. gc->get = aw9523_gpio_get;
  672. gc->get_multiple = aw9523_gpio_get_multiple;
  673. gc->set = aw9523_gpio_set;
  674. gc->set_multiple = aw9523_gpio_set_multiple;
  675. gc->set_config = gpiochip_generic_config;
  676. gc->parent = dev;
  677. gc->owner = THIS_MODULE;
  678. gc->can_sleep = true;
  679. return 0;
  680. }
  681. static const struct irq_chip aw9523_irq_chip = {
  682. .name = "aw9523",
  683. .irq_mask = aw9523_irq_mask,
  684. .irq_unmask = aw9523_irq_unmask,
  685. .irq_bus_lock = aw9523_irq_bus_lock,
  686. .irq_bus_sync_unlock = aw9523_irq_bus_sync_unlock,
  687. .irq_set_type = aw9523_gpio_irq_type,
  688. .flags = IRQCHIP_IMMUTABLE,
  689. GPIOCHIP_IRQ_RESOURCE_HELPERS,
  690. };
  691. static int aw9523_init_irq(struct aw9523 *awi, int irq)
  692. {
  693. struct device *dev = awi->dev;
  694. struct gpio_irq_chip *girq;
  695. int ret;
  696. if (!device_property_read_bool(dev, "interrupt-controller"))
  697. return 0;
  698. awi->irq = devm_kzalloc(dev, sizeof(*awi->irq), GFP_KERNEL);
  699. if (!awi->irq)
  700. return -ENOMEM;
  701. mutex_init(&awi->irq->lock);
  702. ret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func,
  703. IRQF_ONESHOT, dev_name(dev), awi);
  704. if (ret)
  705. return dev_err_probe(dev, ret, "Failed to request irq %d\n", irq);
  706. girq = &awi->gpio.irq;
  707. gpio_irq_chip_set_chip(girq, &aw9523_irq_chip);
  708. girq->parent_handler = NULL;
  709. girq->num_parents = 0;
  710. girq->parents = NULL;
  711. girq->default_type = IRQ_TYPE_EDGE_BOTH;
  712. girq->handler = handle_simple_irq;
  713. girq->threaded = true;
  714. return 0;
  715. }
  716. static bool aw9523_is_reg_hole(unsigned int reg)
  717. {
  718. return (reg > AW9523_REG_PORT_MODE(AW9523_PINS_PER_PORT) &&
  719. reg < AW9523_REG_SOFT_RESET) ||
  720. (reg > AW9523_REG_INTR_DIS(AW9523_PINS_PER_PORT) &&
  721. reg < AW9523_REG_CHIPID);
  722. }
  723. static bool aw9523_readable_reg(struct device *dev, unsigned int reg)
  724. {
  725. /* All available registers (minus holes) can be read */
  726. return !aw9523_is_reg_hole(reg);
  727. }
  728. static bool aw9523_volatile_reg(struct device *dev, unsigned int reg)
  729. {
  730. return aw9523_is_reg_hole(reg) ||
  731. reg == AW9523_REG_IN_STATE(0) ||
  732. reg == AW9523_REG_IN_STATE(AW9523_PINS_PER_PORT) ||
  733. reg == AW9523_REG_CHIPID ||
  734. reg == AW9523_REG_SOFT_RESET;
  735. }
  736. static bool aw9523_writeable_reg(struct device *dev, unsigned int reg)
  737. {
  738. return !aw9523_is_reg_hole(reg) && reg != AW9523_REG_CHIPID;
  739. }
  740. static bool aw9523_precious_reg(struct device *dev, unsigned int reg)
  741. {
  742. /* Reading AW9523_REG_IN_STATE clears interrupt status */
  743. return aw9523_is_reg_hole(reg) ||
  744. reg == AW9523_REG_IN_STATE(0) ||
  745. reg == AW9523_REG_IN_STATE(AW9523_PINS_PER_PORT);
  746. }
  747. static const struct regmap_config aw9523_regmap = {
  748. .reg_bits = 8,
  749. .val_bits = 8,
  750. .reg_stride = 1,
  751. .precious_reg = aw9523_precious_reg,
  752. .readable_reg = aw9523_readable_reg,
  753. .volatile_reg = aw9523_volatile_reg,
  754. .writeable_reg = aw9523_writeable_reg,
  755. .cache_type = REGCACHE_FLAT,
  756. .disable_locking = true,
  757. .num_reg_defaults_raw = AW9523_REG_SOFT_RESET,
  758. };
  759. static int aw9523_hw_init(struct aw9523 *awi)
  760. {
  761. u8 p1_pin = AW9523_PINS_PER_PORT;
  762. unsigned int val;
  763. int ret;
  764. /* No register caching during initialization */
  765. regcache_cache_bypass(awi->regmap, true);
  766. /* Bring up the chip */
  767. ret = aw9523_hw_reset(awi);
  768. if (ret) {
  769. dev_err(awi->dev, "HW Reset failed: %d\n", ret);
  770. return ret;
  771. }
  772. /*
  773. * This is the expected chip and it is running: it's time to
  774. * set a safe default configuration in case the user doesn't
  775. * configure (all of the available) pins in this chip.
  776. * P.S.: The writes order doesn't matter.
  777. */
  778. /* Set all pins as GPIO */
  779. ret = regmap_write(awi->regmap, AW9523_REG_PORT_MODE(0), U8_MAX);
  780. if (ret)
  781. return ret;
  782. ret = regmap_write(awi->regmap, AW9523_REG_PORT_MODE(p1_pin), U8_MAX);
  783. if (ret)
  784. return ret;
  785. /* Set Open-Drain mode on Port 0 (Port 1 is always P-P) */
  786. ret = regmap_write(awi->regmap, AW9523_REG_GCR, 0);
  787. if (ret)
  788. return ret;
  789. /* Set all pins as inputs */
  790. ret = regmap_write(awi->regmap, AW9523_REG_CONF_STATE(0), U8_MAX);
  791. if (ret)
  792. return ret;
  793. ret = regmap_write(awi->regmap, AW9523_REG_CONF_STATE(p1_pin), U8_MAX);
  794. if (ret)
  795. return ret;
  796. /* Disable all interrupts to avoid unreasoned wakeups */
  797. ret = regmap_write(awi->regmap, AW9523_REG_INTR_DIS(0), U8_MAX);
  798. if (ret)
  799. return ret;
  800. ret = regmap_write(awi->regmap, AW9523_REG_INTR_DIS(p1_pin), U8_MAX);
  801. if (ret)
  802. return ret;
  803. /* Clear setup-generated interrupts by performing a port state read */
  804. ret = aw9523_get_port_state(awi->regmap, 0, 0, &val);
  805. if (ret)
  806. return ret;
  807. ret = aw9523_get_port_state(awi->regmap, p1_pin, 0, &val);
  808. if (ret)
  809. return ret;
  810. /* Everything went fine: activate and reinitialize register cache */
  811. regcache_cache_bypass(awi->regmap, false);
  812. return regmap_reinit_cache(awi->regmap, &aw9523_regmap);
  813. }
  814. static int aw9523_probe(struct i2c_client *client)
  815. {
  816. struct device *dev = &client->dev;
  817. struct pinctrl_desc *pdesc;
  818. struct aw9523 *awi;
  819. int ret;
  820. awi = devm_kzalloc(dev, sizeof(*awi), GFP_KERNEL);
  821. if (!awi)
  822. return -ENOMEM;
  823. i2c_set_clientdata(client, awi);
  824. awi->dev = dev;
  825. awi->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
  826. if (IS_ERR(awi->reset_gpio))
  827. return PTR_ERR(awi->reset_gpio);
  828. gpiod_set_consumer_name(awi->reset_gpio, "aw9523 reset");
  829. awi->regmap = devm_regmap_init_i2c(client, &aw9523_regmap);
  830. if (IS_ERR(awi->regmap))
  831. return PTR_ERR(awi->regmap);
  832. awi->vio_vreg = devm_regulator_get_enable_optional(dev, "vio");
  833. if (awi->vio_vreg && awi->vio_vreg != -ENODEV)
  834. return awi->vio_vreg;
  835. ret = devm_mutex_init(dev, &awi->i2c_lock);
  836. if (ret)
  837. return ret;
  838. lockdep_set_subclass(&awi->i2c_lock, i2c_adapter_depth(client->adapter));
  839. pdesc = devm_kzalloc(dev, sizeof(*pdesc), GFP_KERNEL);
  840. if (!pdesc)
  841. return -ENOMEM;
  842. ret = aw9523_hw_init(awi);
  843. if (ret)
  844. return ret;
  845. pdesc->name = dev_name(dev);
  846. pdesc->owner = THIS_MODULE;
  847. pdesc->pctlops = &aw9523_pinctrl_ops;
  848. pdesc->pmxops = &aw9523_pinmux_ops;
  849. pdesc->confops = &aw9523_pinconf_ops;
  850. pdesc->pins = aw9523_pins;
  851. pdesc->npins = ARRAY_SIZE(aw9523_pins);
  852. ret = aw9523_init_gpiochip(awi, pdesc->npins);
  853. if (ret)
  854. return ret;
  855. if (client->irq) {
  856. ret = aw9523_init_irq(awi, client->irq);
  857. if (ret)
  858. return ret;
  859. }
  860. awi->pctl = devm_pinctrl_register(dev, pdesc, awi);
  861. if (IS_ERR(awi->pctl))
  862. return dev_err_probe(dev, PTR_ERR(awi->pctl),
  863. "Cannot register pinctrl");
  864. return devm_gpiochip_add_data(dev, &awi->gpio, awi);
  865. }
  866. static void aw9523_remove(struct i2c_client *client)
  867. {
  868. struct aw9523 *awi = i2c_get_clientdata(client);
  869. /*
  870. * If the chip VIO is connected to a regulator that we can turn
  871. * off, life is easy... otherwise, reinitialize the chip and
  872. * set the pins to hardware defaults before removing the driver
  873. * to leave it in a clean, safe and predictable state.
  874. */
  875. if (awi->vio_vreg == -ENODEV) {
  876. mutex_lock(&awi->i2c_lock);
  877. aw9523_hw_init(awi);
  878. mutex_unlock(&awi->i2c_lock);
  879. }
  880. }
  881. static const struct i2c_device_id aw9523_i2c_id_table[] = {
  882. { "aw9523_i2c" },
  883. { }
  884. };
  885. MODULE_DEVICE_TABLE(i2c, aw9523_i2c_id_table);
  886. static const struct of_device_id of_aw9523_i2c_match[] = {
  887. { .compatible = "awinic,aw9523-pinctrl", },
  888. { }
  889. };
  890. MODULE_DEVICE_TABLE(of, of_aw9523_i2c_match);
  891. static struct i2c_driver aw9523_driver = {
  892. .driver = {
  893. .name = "aw9523-pinctrl",
  894. .of_match_table = of_aw9523_i2c_match,
  895. },
  896. .probe = aw9523_probe,
  897. .remove = aw9523_remove,
  898. .id_table = aw9523_i2c_id_table,
  899. };
  900. module_i2c_driver(aw9523_driver);
  901. MODULE_DESCRIPTION("Awinic AW9523 I2C GPIO Expander driver");
  902. MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>");
  903. MODULE_LICENSE("GPL v2");