phy-meson-axg-pcie.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic AXG PCIE PHY driver
  4. *
  5. * Copyright (C) 2020 Remi Pommarel <repk@triplefau.lt>
  6. */
  7. #include <linux/mod_devicetable.h>
  8. #include <linux/module.h>
  9. #include <linux/phy/phy.h>
  10. #include <linux/regmap.h>
  11. #include <linux/reset.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/bitfield.h>
  14. #include <dt-bindings/phy/phy.h>
  15. #define MESON_PCIE_REG0 0x00
  16. #define MESON_PCIE_COMMON_CLK BIT(4)
  17. #define MESON_PCIE_PORT_SEL GENMASK(3, 2)
  18. #define MESON_PCIE_CLK BIT(1)
  19. #define MESON_PCIE_POWERDOWN BIT(0)
  20. #define MESON_PCIE_TWO_X1 FIELD_PREP(MESON_PCIE_PORT_SEL, 0x3)
  21. #define MESON_PCIE_COMMON_REF_CLK FIELD_PREP(MESON_PCIE_COMMON_CLK, 0x1)
  22. #define MESON_PCIE_PHY_INIT (MESON_PCIE_TWO_X1 | \
  23. MESON_PCIE_COMMON_REF_CLK)
  24. #define MESON_PCIE_RESET_DELAY 500
  25. struct phy_axg_pcie_priv {
  26. struct phy *phy;
  27. struct phy *analog;
  28. struct regmap *regmap;
  29. struct reset_control *reset;
  30. };
  31. static const struct regmap_config phy_axg_pcie_regmap_conf = {
  32. .reg_bits = 8,
  33. .val_bits = 32,
  34. .reg_stride = 4,
  35. .max_register = MESON_PCIE_REG0,
  36. };
  37. static int phy_axg_pcie_power_on(struct phy *phy)
  38. {
  39. struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
  40. int ret;
  41. ret = phy_power_on(priv->analog);
  42. if (ret != 0)
  43. return ret;
  44. regmap_update_bits(priv->regmap, MESON_PCIE_REG0,
  45. MESON_PCIE_POWERDOWN, 0);
  46. return 0;
  47. }
  48. static int phy_axg_pcie_power_off(struct phy *phy)
  49. {
  50. struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
  51. int ret;
  52. ret = phy_power_off(priv->analog);
  53. if (ret != 0)
  54. return ret;
  55. regmap_update_bits(priv->regmap, MESON_PCIE_REG0,
  56. MESON_PCIE_POWERDOWN, 1);
  57. return 0;
  58. }
  59. static int phy_axg_pcie_init(struct phy *phy)
  60. {
  61. struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
  62. int ret;
  63. ret = phy_init(priv->analog);
  64. if (ret != 0)
  65. return ret;
  66. regmap_write(priv->regmap, MESON_PCIE_REG0, MESON_PCIE_PHY_INIT);
  67. return reset_control_reset(priv->reset);
  68. }
  69. static int phy_axg_pcie_exit(struct phy *phy)
  70. {
  71. struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
  72. int ret;
  73. ret = phy_exit(priv->analog);
  74. if (ret != 0)
  75. return ret;
  76. return reset_control_reset(priv->reset);
  77. }
  78. static int phy_axg_pcie_reset(struct phy *phy)
  79. {
  80. struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
  81. int ret = 0;
  82. ret = phy_reset(priv->analog);
  83. if (ret != 0)
  84. goto out;
  85. ret = reset_control_assert(priv->reset);
  86. if (ret != 0)
  87. goto out;
  88. udelay(MESON_PCIE_RESET_DELAY);
  89. ret = reset_control_deassert(priv->reset);
  90. if (ret != 0)
  91. goto out;
  92. udelay(MESON_PCIE_RESET_DELAY);
  93. out:
  94. return ret;
  95. }
  96. static const struct phy_ops phy_axg_pcie_ops = {
  97. .init = phy_axg_pcie_init,
  98. .exit = phy_axg_pcie_exit,
  99. .power_on = phy_axg_pcie_power_on,
  100. .power_off = phy_axg_pcie_power_off,
  101. .reset = phy_axg_pcie_reset,
  102. .owner = THIS_MODULE,
  103. };
  104. static int phy_axg_pcie_probe(struct platform_device *pdev)
  105. {
  106. struct phy_provider *pphy;
  107. struct device *dev = &pdev->dev;
  108. struct phy_axg_pcie_priv *priv;
  109. struct device_node *np = dev->of_node;
  110. void __iomem *base;
  111. priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
  112. if (!priv)
  113. return -ENOMEM;
  114. base = devm_platform_ioremap_resource(pdev, 0);
  115. if (IS_ERR(base))
  116. return PTR_ERR(base);
  117. priv->regmap = devm_regmap_init_mmio(dev, base,
  118. &phy_axg_pcie_regmap_conf);
  119. if (IS_ERR(priv->regmap))
  120. return PTR_ERR(priv->regmap);
  121. priv->reset = devm_reset_control_array_get_exclusive(dev);
  122. if (IS_ERR(priv->reset))
  123. return PTR_ERR(priv->reset);
  124. priv->analog = devm_phy_get(dev, "analog");
  125. if (IS_ERR(priv->analog))
  126. return PTR_ERR(priv->analog);
  127. priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops);
  128. if (IS_ERR(priv->phy))
  129. return dev_err_probe(dev, PTR_ERR(priv->phy),
  130. "failed to create PHY\n");
  131. phy_set_drvdata(priv->phy, priv);
  132. dev_set_drvdata(dev, priv);
  133. pphy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  134. return PTR_ERR_OR_ZERO(pphy);
  135. }
  136. static const struct of_device_id phy_axg_pcie_of_match[] = {
  137. {
  138. .compatible = "amlogic,axg-pcie-phy",
  139. },
  140. { },
  141. };
  142. MODULE_DEVICE_TABLE(of, phy_axg_pcie_of_match);
  143. static struct platform_driver phy_axg_pcie_driver = {
  144. .probe = phy_axg_pcie_probe,
  145. .driver = {
  146. .name = "phy-axg-pcie",
  147. .of_match_table = phy_axg_pcie_of_match,
  148. },
  149. };
  150. module_platform_driver(phy_axg_pcie_driver);
  151. MODULE_AUTHOR("Remi Pommarel <repk@triplefau.lt>");
  152. MODULE_DESCRIPTION("Amlogic AXG PCIE PHY driver");
  153. MODULE_LICENSE("GPL v2");