pcie-hisi.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe host controller driver for HiSilicon SoCs
  4. *
  5. * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
  6. *
  7. * Authors: Zhou Wang <wangzhou1@hisilicon.com>
  8. * Dacai Zhu <zhudacai@hisilicon.com>
  9. * Gabriele Paoloni <gabriele.paoloni@huawei.com>
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/init.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pci.h>
  15. #include <linux/pci-acpi.h>
  16. #include <linux/pci-ecam.h>
  17. #include "../../pci.h"
  18. #include "../pci-host-common.h"
  19. #if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
  20. struct hisi_pcie {
  21. void __iomem *reg_base;
  22. };
  23. static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  24. int size, u32 *val)
  25. {
  26. struct pci_config_window *cfg = bus->sysdata;
  27. int dev = PCI_SLOT(devfn);
  28. if (bus->number == cfg->busr.start) {
  29. /* access only one slot on each root port */
  30. if (dev > 0)
  31. return PCIBIOS_DEVICE_NOT_FOUND;
  32. else
  33. return pci_generic_config_read32(bus, devfn, where,
  34. size, val);
  35. }
  36. return pci_generic_config_read(bus, devfn, where, size, val);
  37. }
  38. static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
  39. int where, int size, u32 val)
  40. {
  41. struct pci_config_window *cfg = bus->sysdata;
  42. int dev = PCI_SLOT(devfn);
  43. if (bus->number == cfg->busr.start) {
  44. /* access only one slot on each root port */
  45. if (dev > 0)
  46. return PCIBIOS_DEVICE_NOT_FOUND;
  47. else
  48. return pci_generic_config_write32(bus, devfn, where,
  49. size, val);
  50. }
  51. return pci_generic_config_write(bus, devfn, where, size, val);
  52. }
  53. static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
  54. int where)
  55. {
  56. struct pci_config_window *cfg = bus->sysdata;
  57. struct hisi_pcie *pcie = cfg->priv;
  58. if (bus->number == cfg->busr.start)
  59. return pcie->reg_base + where;
  60. else
  61. return pci_ecam_map_bus(bus, devfn, where);
  62. }
  63. #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
  64. static int hisi_pcie_init(struct pci_config_window *cfg)
  65. {
  66. struct device *dev = cfg->parent;
  67. struct hisi_pcie *pcie;
  68. struct acpi_device *adev = to_acpi_device(dev);
  69. struct acpi_pci_root *root = acpi_driver_data(adev);
  70. struct resource *res;
  71. int ret;
  72. pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
  73. if (!pcie)
  74. return -ENOMEM;
  75. /*
  76. * Retrieve RC base and size from a HISI0081 device with _UID
  77. * matching our segment.
  78. */
  79. res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
  80. if (!res)
  81. return -ENOMEM;
  82. ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
  83. if (ret) {
  84. dev_err(dev, "can't get rc base address\n");
  85. return -ENOMEM;
  86. }
  87. pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
  88. if (!pcie->reg_base)
  89. return -ENOMEM;
  90. cfg->priv = pcie;
  91. return 0;
  92. }
  93. const struct pci_ecam_ops hisi_pcie_ops = {
  94. .init = hisi_pcie_init,
  95. .pci_ops = {
  96. .map_bus = hisi_pcie_map_bus,
  97. .read = hisi_pcie_rd_conf,
  98. .write = hisi_pcie_wr_conf,
  99. }
  100. };
  101. #endif
  102. #ifdef CONFIG_PCI_HISI
  103. static int hisi_pcie_platform_init(struct pci_config_window *cfg)
  104. {
  105. struct device *dev = cfg->parent;
  106. struct hisi_pcie *pcie;
  107. struct platform_device *pdev = to_platform_device(dev);
  108. struct resource *res;
  109. pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
  110. if (!pcie)
  111. return -ENOMEM;
  112. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  113. if (!res) {
  114. dev_err(dev, "missing \"reg[1]\"property\n");
  115. return -EINVAL;
  116. }
  117. pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
  118. if (!pcie->reg_base)
  119. return -ENOMEM;
  120. cfg->priv = pcie;
  121. return 0;
  122. }
  123. static const struct pci_ecam_ops hisi_pcie_platform_ops = {
  124. .init = hisi_pcie_platform_init,
  125. .pci_ops = {
  126. .map_bus = hisi_pcie_map_bus,
  127. .read = hisi_pcie_rd_conf,
  128. .write = hisi_pcie_wr_conf,
  129. }
  130. };
  131. static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
  132. {
  133. .compatible = "hisilicon,hip06-pcie-ecam",
  134. .data = &hisi_pcie_platform_ops,
  135. },
  136. {
  137. .compatible = "hisilicon,hip07-pcie-ecam",
  138. .data = &hisi_pcie_platform_ops,
  139. },
  140. {},
  141. };
  142. static struct platform_driver hisi_pcie_almost_ecam_driver = {
  143. .probe = pci_host_common_probe,
  144. .driver = {
  145. .name = "hisi-pcie-almost-ecam",
  146. .of_match_table = hisi_pcie_almost_ecam_of_match,
  147. .suppress_bind_attrs = true,
  148. },
  149. };
  150. builtin_platform_driver(hisi_pcie_almost_ecam_driver);
  151. #endif
  152. #endif