pcie-designware-plat.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe RC driver for Synopsys DesignWare Core
  4. *
  5. * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
  6. *
  7. * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/gpio.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/of.h>
  16. #include <linux/pci.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/resource.h>
  19. #include <linux/types.h>
  20. #include "pcie-designware.h"
  21. struct dw_plat_pcie {
  22. struct dw_pcie *pci;
  23. enum dw_pcie_device_mode mode;
  24. };
  25. struct dw_plat_pcie_of_data {
  26. enum dw_pcie_device_mode mode;
  27. };
  28. static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
  29. };
  30. static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
  31. {
  32. struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
  33. enum pci_barno bar;
  34. for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
  35. dw_pcie_ep_reset_bar(pci, bar);
  36. }
  37. static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
  38. unsigned int type, u16 interrupt_num)
  39. {
  40. struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
  41. switch (type) {
  42. case PCI_IRQ_INTX:
  43. return dw_pcie_ep_raise_intx_irq(ep, func_no);
  44. case PCI_IRQ_MSI:
  45. return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
  46. case PCI_IRQ_MSIX:
  47. return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
  48. default:
  49. dev_err(pci->dev, "UNKNOWN IRQ type\n");
  50. }
  51. return 0;
  52. }
  53. static const struct pci_epc_features dw_plat_pcie_epc_features = {
  54. DWC_EPC_COMMON_FEATURES,
  55. .msi_capable = true,
  56. .msix_capable = true,
  57. };
  58. static const struct pci_epc_features*
  59. dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
  60. {
  61. return &dw_plat_pcie_epc_features;
  62. }
  63. static const struct dw_pcie_ep_ops pcie_ep_ops = {
  64. .init = dw_plat_pcie_ep_init,
  65. .raise_irq = dw_plat_pcie_ep_raise_irq,
  66. .get_features = dw_plat_pcie_get_features,
  67. };
  68. static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
  69. struct platform_device *pdev)
  70. {
  71. struct dw_pcie *pci = dw_plat_pcie->pci;
  72. struct dw_pcie_rp *pp = &pci->pp;
  73. struct device *dev = &pdev->dev;
  74. int ret;
  75. pp->irq = platform_get_irq(pdev, 1);
  76. if (pp->irq < 0)
  77. return pp->irq;
  78. pp->num_vectors = MAX_MSI_IRQS;
  79. pp->ops = &dw_plat_pcie_host_ops;
  80. ret = dw_pcie_host_init(pp);
  81. if (ret) {
  82. dev_err(dev, "Failed to initialize host\n");
  83. return ret;
  84. }
  85. return 0;
  86. }
  87. static int dw_plat_pcie_probe(struct platform_device *pdev)
  88. {
  89. struct device *dev = &pdev->dev;
  90. struct dw_plat_pcie *dw_plat_pcie;
  91. struct dw_pcie *pci;
  92. int ret;
  93. const struct dw_plat_pcie_of_data *data;
  94. enum dw_pcie_device_mode mode;
  95. data = of_device_get_match_data(dev);
  96. if (!data)
  97. return -EINVAL;
  98. mode = (enum dw_pcie_device_mode)data->mode;
  99. dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
  100. if (!dw_plat_pcie)
  101. return -ENOMEM;
  102. pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
  103. if (!pci)
  104. return -ENOMEM;
  105. pci->dev = dev;
  106. dw_plat_pcie->pci = pci;
  107. dw_plat_pcie->mode = mode;
  108. platform_set_drvdata(pdev, dw_plat_pcie);
  109. switch (dw_plat_pcie->mode) {
  110. case DW_PCIE_RC_TYPE:
  111. if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST))
  112. return -ENODEV;
  113. ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev);
  114. break;
  115. case DW_PCIE_EP_TYPE:
  116. if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
  117. return -ENODEV;
  118. pci->ep.ops = &pcie_ep_ops;
  119. ret = dw_pcie_ep_init(&pci->ep);
  120. if (ret)
  121. return ret;
  122. ret = dw_pcie_ep_init_registers(&pci->ep);
  123. if (ret) {
  124. dev_err(dev, "Failed to initialize DWC endpoint registers\n");
  125. dw_pcie_ep_deinit(&pci->ep);
  126. }
  127. pci_epc_init_notify(pci->ep.epc);
  128. break;
  129. default:
  130. dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
  131. ret = -EINVAL;
  132. break;
  133. }
  134. return ret;
  135. }
  136. static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = {
  137. .mode = DW_PCIE_RC_TYPE,
  138. };
  139. static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = {
  140. .mode = DW_PCIE_EP_TYPE,
  141. };
  142. static const struct of_device_id dw_plat_pcie_of_match[] = {
  143. {
  144. .compatible = "snps,dw-pcie",
  145. .data = &dw_plat_pcie_rc_of_data,
  146. },
  147. {
  148. .compatible = "snps,dw-pcie-ep",
  149. .data = &dw_plat_pcie_ep_of_data,
  150. },
  151. {},
  152. };
  153. static struct platform_driver dw_plat_pcie_driver = {
  154. .driver = {
  155. .name = "dw-pcie",
  156. .of_match_table = dw_plat_pcie_of_match,
  157. .suppress_bind_attrs = true,
  158. },
  159. .probe = dw_plat_pcie_probe,
  160. };
  161. builtin_platform_driver(dw_plat_pcie_driver);