main.c 65 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2. /* Copyright(c) 2018-2019 Realtek Corporation
  3. */
  4. #include <linux/devcoredump.h>
  5. #include "main.h"
  6. #include "regd.h"
  7. #include "fw.h"
  8. #include "ps.h"
  9. #include "sec.h"
  10. #include "mac.h"
  11. #include "coex.h"
  12. #include "phy.h"
  13. #include "reg.h"
  14. #include "efuse.h"
  15. #include "tx.h"
  16. #include "debug.h"
  17. #include "bf.h"
  18. #include "sar.h"
  19. #include "sdio.h"
  20. #include "led.h"
  21. bool rtw_disable_lps_deep_mode;
  22. EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
  23. bool rtw_bf_support = true;
  24. unsigned int rtw_debug_mask;
  25. EXPORT_SYMBOL(rtw_debug_mask);
  26. /* EDCCA is enabled during normal behavior. For debugging purpose in
  27. * a noisy environment, it can be disabled via edcca debugfs. Because
  28. * all rtw88 devices will probably be affected if environment is noisy,
  29. * rtw_edcca_enabled is just declared by driver instead of by device.
  30. * So, turning it off will take effect for all rtw88 devices before
  31. * there is a tough reason to maintain rtw_edcca_enabled by device.
  32. */
  33. bool rtw_edcca_enabled = true;
  34. module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
  35. module_param_named(support_bf, rtw_bf_support, bool, 0644);
  36. module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
  37. MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
  38. MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
  39. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  40. static struct ieee80211_channel rtw_channeltable_2g[] = {
  41. {.center_freq = 2412, .hw_value = 1,},
  42. {.center_freq = 2417, .hw_value = 2,},
  43. {.center_freq = 2422, .hw_value = 3,},
  44. {.center_freq = 2427, .hw_value = 4,},
  45. {.center_freq = 2432, .hw_value = 5,},
  46. {.center_freq = 2437, .hw_value = 6,},
  47. {.center_freq = 2442, .hw_value = 7,},
  48. {.center_freq = 2447, .hw_value = 8,},
  49. {.center_freq = 2452, .hw_value = 9,},
  50. {.center_freq = 2457, .hw_value = 10,},
  51. {.center_freq = 2462, .hw_value = 11,},
  52. {.center_freq = 2467, .hw_value = 12,},
  53. {.center_freq = 2472, .hw_value = 13,},
  54. {.center_freq = 2484, .hw_value = 14,},
  55. };
  56. static struct ieee80211_channel rtw_channeltable_5g[] = {
  57. {.center_freq = 5180, .hw_value = 36,},
  58. {.center_freq = 5200, .hw_value = 40,},
  59. {.center_freq = 5220, .hw_value = 44,},
  60. {.center_freq = 5240, .hw_value = 48,},
  61. {.center_freq = 5260, .hw_value = 52,},
  62. {.center_freq = 5280, .hw_value = 56,},
  63. {.center_freq = 5300, .hw_value = 60,},
  64. {.center_freq = 5320, .hw_value = 64,},
  65. {.center_freq = 5500, .hw_value = 100,},
  66. {.center_freq = 5520, .hw_value = 104,},
  67. {.center_freq = 5540, .hw_value = 108,},
  68. {.center_freq = 5560, .hw_value = 112,},
  69. {.center_freq = 5580, .hw_value = 116,},
  70. {.center_freq = 5600, .hw_value = 120,},
  71. {.center_freq = 5620, .hw_value = 124,},
  72. {.center_freq = 5640, .hw_value = 128,},
  73. {.center_freq = 5660, .hw_value = 132,},
  74. {.center_freq = 5680, .hw_value = 136,},
  75. {.center_freq = 5700, .hw_value = 140,},
  76. {.center_freq = 5720, .hw_value = 144,},
  77. {.center_freq = 5745, .hw_value = 149,},
  78. {.center_freq = 5765, .hw_value = 153,},
  79. {.center_freq = 5785, .hw_value = 157,},
  80. {.center_freq = 5805, .hw_value = 161,},
  81. {.center_freq = 5825, .hw_value = 165,
  82. .flags = IEEE80211_CHAN_NO_HT40MINUS},
  83. };
  84. static struct ieee80211_rate rtw_ratetable[] = {
  85. {.bitrate = 10, .hw_value = 0x00,},
  86. {.bitrate = 20, .hw_value = 0x01,},
  87. {.bitrate = 55, .hw_value = 0x02,},
  88. {.bitrate = 110, .hw_value = 0x03,},
  89. {.bitrate = 60, .hw_value = 0x04,},
  90. {.bitrate = 90, .hw_value = 0x05,},
  91. {.bitrate = 120, .hw_value = 0x06,},
  92. {.bitrate = 180, .hw_value = 0x07,},
  93. {.bitrate = 240, .hw_value = 0x08,},
  94. {.bitrate = 360, .hw_value = 0x09,},
  95. {.bitrate = 480, .hw_value = 0x0a,},
  96. {.bitrate = 540, .hw_value = 0x0b,},
  97. };
  98. static const struct ieee80211_iface_limit rtw_iface_limits[] = {
  99. {
  100. .max = 1,
  101. .types = BIT(NL80211_IFTYPE_STATION),
  102. },
  103. {
  104. .max = 1,
  105. .types = BIT(NL80211_IFTYPE_AP),
  106. }
  107. };
  108. static const struct ieee80211_iface_combination rtw_iface_combs[] = {
  109. {
  110. .limits = rtw_iface_limits,
  111. .n_limits = ARRAY_SIZE(rtw_iface_limits),
  112. .max_interfaces = 2,
  113. .num_different_channels = 1,
  114. }
  115. };
  116. u16 rtw_desc_to_bitrate(u8 desc_rate)
  117. {
  118. struct ieee80211_rate rate;
  119. if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
  120. return 0;
  121. rate = rtw_ratetable[desc_rate];
  122. return rate.bitrate;
  123. }
  124. static const struct ieee80211_supported_band rtw_band_2ghz = {
  125. .band = NL80211_BAND_2GHZ,
  126. .channels = rtw_channeltable_2g,
  127. .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
  128. .bitrates = rtw_ratetable,
  129. .n_bitrates = ARRAY_SIZE(rtw_ratetable),
  130. .ht_cap = {0},
  131. .vht_cap = {0},
  132. };
  133. static const struct ieee80211_supported_band rtw_band_5ghz = {
  134. .band = NL80211_BAND_5GHZ,
  135. .channels = rtw_channeltable_5g,
  136. .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
  137. /* 5G has no CCK rates */
  138. .bitrates = rtw_ratetable + 4,
  139. .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
  140. .ht_cap = {0},
  141. .vht_cap = {0},
  142. };
  143. struct rtw_watch_dog_iter_data {
  144. struct rtw_dev *rtwdev;
  145. struct rtw_vif *rtwvif;
  146. };
  147. static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
  148. {
  149. struct rtw_bf_info *bf_info = &rtwdev->bf_info;
  150. u8 fix_rate_enable = 0;
  151. u8 new_csi_rate_idx;
  152. if (rtwvif->bfee.role != RTW_BFEE_SU &&
  153. rtwvif->bfee.role != RTW_BFEE_MU)
  154. return;
  155. rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
  156. bf_info->cur_csi_rpt_rate,
  157. fix_rate_enable, &new_csi_rate_idx);
  158. if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
  159. bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
  160. }
  161. static void rtw_vif_watch_dog_iter(void *data, struct ieee80211_vif *vif)
  162. {
  163. struct rtw_watch_dog_iter_data *iter_data = data;
  164. struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
  165. if (vif->type == NL80211_IFTYPE_STATION)
  166. if (vif->cfg.assoc)
  167. iter_data->rtwvif = rtwvif;
  168. rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
  169. rtwvif->stats.tx_unicast = 0;
  170. rtwvif->stats.rx_unicast = 0;
  171. rtwvif->stats.tx_cnt = 0;
  172. rtwvif->stats.rx_cnt = 0;
  173. }
  174. static void rtw_sw_beacon_loss_check(struct rtw_dev *rtwdev,
  175. struct rtw_vif *rtwvif, int received_beacons)
  176. {
  177. int watchdog_delay = 2000000 / 1024; /* TU */
  178. int beacon_int, expected_beacons;
  179. if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_BCN_FILTER) || !rtwvif)
  180. return;
  181. beacon_int = rtwvif_to_vif(rtwvif)->bss_conf.beacon_int;
  182. expected_beacons = DIV_ROUND_UP(watchdog_delay, beacon_int);
  183. rtwdev->beacon_loss = received_beacons < expected_beacons / 2;
  184. }
  185. /* process TX/RX statistics periodically for hardware,
  186. * the information helps hardware to enhance performance
  187. */
  188. static void rtw_watch_dog_work(struct work_struct *work)
  189. {
  190. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
  191. watch_dog_work.work);
  192. struct rtw_traffic_stats *stats = &rtwdev->stats;
  193. struct rtw_watch_dog_iter_data data = {};
  194. bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
  195. int received_beacons = rtwdev->dm_info.cur_pkt_count.num_bcn_pkt;
  196. u32 tx_unicast_mbps, rx_unicast_mbps;
  197. bool ps_active;
  198. mutex_lock(&rtwdev->mutex);
  199. if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
  200. goto unlock;
  201. ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
  202. RTW_WATCH_DOG_DELAY_TIME);
  203. if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
  204. set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
  205. else
  206. clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
  207. if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
  208. rtw_coex_wl_status_change_notify(rtwdev, 0);
  209. if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
  210. stats->rx_cnt > RTW_LPS_THRESHOLD)
  211. ps_active = true;
  212. else
  213. ps_active = false;
  214. tx_unicast_mbps = stats->tx_unicast >> RTW_TP_SHIFT;
  215. rx_unicast_mbps = stats->rx_unicast >> RTW_TP_SHIFT;
  216. ewma_tp_add(&stats->tx_ewma_tp, tx_unicast_mbps);
  217. ewma_tp_add(&stats->rx_ewma_tp, rx_unicast_mbps);
  218. stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
  219. stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
  220. /* reset tx/rx statictics */
  221. stats->tx_unicast = 0;
  222. stats->rx_unicast = 0;
  223. stats->tx_cnt = 0;
  224. stats->rx_cnt = 0;
  225. if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
  226. goto unlock;
  227. /* make sure BB/RF is working for dynamic mech */
  228. rtw_leave_lps(rtwdev);
  229. rtw_coex_wl_status_check(rtwdev);
  230. rtw_coex_query_bt_hid_list(rtwdev);
  231. rtw_coex_active_query_bt_info(rtwdev);
  232. rtw_phy_dynamic_mechanism(rtwdev);
  233. rtw_hci_dynamic_rx_agg(rtwdev,
  234. tx_unicast_mbps >= 1 || rx_unicast_mbps >= 1);
  235. data.rtwdev = rtwdev;
  236. /* rtw_iterate_vifs internally uses an atomic iterator which is needed
  237. * to avoid taking local->iflist_mtx mutex
  238. */
  239. rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data);
  240. rtw_sw_beacon_loss_check(rtwdev, data.rtwvif, received_beacons);
  241. /* fw supports only one station associated to enter lps, if there are
  242. * more than two stations associated to the AP, then we can not enter
  243. * lps, because fw does not handle the overlapped beacon interval
  244. *
  245. * rtw_recalc_lps() iterate vifs and determine if driver can enter
  246. * ps by vif->type and vif->cfg.ps, all we need to do here is to
  247. * get that vif and check if device is having traffic more than the
  248. * threshold.
  249. */
  250. if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
  251. !rtwdev->beacon_loss && !rtwdev->ap_active)
  252. rtw_enter_lps(rtwdev, data.rtwvif->port);
  253. rtwdev->watch_dog_cnt++;
  254. unlock:
  255. mutex_unlock(&rtwdev->mutex);
  256. }
  257. static void rtw_c2h_work(struct work_struct *work)
  258. {
  259. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
  260. struct sk_buff *skb, *tmp;
  261. skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
  262. skb_unlink(skb, &rtwdev->c2h_queue);
  263. rtw_fw_c2h_cmd_handle(rtwdev, skb);
  264. dev_kfree_skb_any(skb);
  265. }
  266. }
  267. static void rtw_ips_work(struct work_struct *work)
  268. {
  269. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work);
  270. mutex_lock(&rtwdev->mutex);
  271. if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
  272. rtw_enter_ips(rtwdev);
  273. mutex_unlock(&rtwdev->mutex);
  274. }
  275. static void rtw_sta_rc_work(struct work_struct *work)
  276. {
  277. struct rtw_sta_info *si = container_of(work, struct rtw_sta_info,
  278. rc_work);
  279. struct rtw_dev *rtwdev = si->rtwdev;
  280. mutex_lock(&rtwdev->mutex);
  281. rtw_update_sta_info(rtwdev, si, true);
  282. mutex_unlock(&rtwdev->mutex);
  283. }
  284. int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
  285. struct ieee80211_vif *vif)
  286. {
  287. struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
  288. struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
  289. int i;
  290. if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
  291. si->mac_id = rtwvif->mac_id;
  292. } else {
  293. si->mac_id = rtw_acquire_macid(rtwdev);
  294. if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
  295. return -ENOSPC;
  296. }
  297. si->rtwdev = rtwdev;
  298. si->sta = sta;
  299. si->vif = vif;
  300. si->init_ra_lv = 1;
  301. ewma_rssi_init(&si->avg_rssi);
  302. for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
  303. rtw_txq_init(rtwdev, sta->txq[i]);
  304. INIT_WORK(&si->rc_work, rtw_sta_rc_work);
  305. rtw_update_sta_info(rtwdev, si, true);
  306. rtw_fw_media_status_report(rtwdev, si->mac_id, true);
  307. rtwdev->sta_cnt++;
  308. rtwdev->beacon_loss = false;
  309. rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n",
  310. sta->addr, si->mac_id);
  311. return 0;
  312. }
  313. void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
  314. bool fw_exist)
  315. {
  316. struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
  317. struct ieee80211_vif *vif = si->vif;
  318. int i;
  319. cancel_work_sync(&si->rc_work);
  320. if (vif->type != NL80211_IFTYPE_STATION || sta->tdls)
  321. rtw_release_macid(rtwdev, si->mac_id);
  322. if (fw_exist)
  323. rtw_fw_media_status_report(rtwdev, si->mac_id, false);
  324. for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
  325. rtw_txq_cleanup(rtwdev, sta->txq[i]);
  326. kfree(si->mask);
  327. rtwdev->sta_cnt--;
  328. rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n",
  329. sta->addr, si->mac_id);
  330. }
  331. struct rtw_fwcd_hdr {
  332. u32 item;
  333. u32 size;
  334. u32 padding1;
  335. u32 padding2;
  336. } __packed;
  337. static int rtw_fwcd_prep(struct rtw_dev *rtwdev)
  338. {
  339. const struct rtw_chip_info *chip = rtwdev->chip;
  340. struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
  341. const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
  342. u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
  343. u8 i;
  344. if (segs) {
  345. prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
  346. for (i = 0; i < segs->num; i++)
  347. prep_size += segs->segs[i];
  348. }
  349. desc->data = vmalloc(prep_size);
  350. if (!desc->data)
  351. return -ENOMEM;
  352. desc->size = prep_size;
  353. desc->next = desc->data;
  354. return 0;
  355. }
  356. static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
  357. {
  358. struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
  359. struct rtw_fwcd_hdr *hdr;
  360. u8 *next;
  361. if (!desc->data) {
  362. rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n");
  363. return NULL;
  364. }
  365. next = desc->next + sizeof(struct rtw_fwcd_hdr);
  366. if (next - desc->data + size > desc->size) {
  367. rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n");
  368. return NULL;
  369. }
  370. hdr = (struct rtw_fwcd_hdr *)(desc->next);
  371. hdr->item = item;
  372. hdr->size = size;
  373. hdr->padding1 = 0x01234567;
  374. hdr->padding2 = 0x89abcdef;
  375. desc->next = next + size;
  376. return next;
  377. }
  378. static void rtw_fwcd_dump(struct rtw_dev *rtwdev)
  379. {
  380. struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
  381. rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n");
  382. /* Data will be freed after lifetime of device coredump. After calling
  383. * dev_coredump, data is supposed to be handled by the device coredump
  384. * framework. Note that a new dump will be discarded if a previous one
  385. * hasn't been released yet.
  386. */
  387. dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
  388. }
  389. static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self)
  390. {
  391. struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
  392. if (free_self) {
  393. rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n");
  394. vfree(desc->data);
  395. }
  396. desc->data = NULL;
  397. desc->next = NULL;
  398. }
  399. static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
  400. {
  401. u32 size = rtwdev->chip->fw_rxff_size;
  402. u32 *buf;
  403. u8 seq;
  404. buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
  405. if (!buf)
  406. return -ENOMEM;
  407. if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
  408. rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
  409. return -EINVAL;
  410. }
  411. if (GET_FW_DUMP_LEN(buf) == 0) {
  412. rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
  413. return -EINVAL;
  414. }
  415. seq = GET_FW_DUMP_SEQ(buf);
  416. if (seq > 0) {
  417. rtw_dbg(rtwdev, RTW_DBG_FW,
  418. "fw crash dump's seq is wrong: %d\n", seq);
  419. return -EINVAL;
  420. }
  421. return 0;
  422. }
  423. int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
  424. u32 fwcd_item)
  425. {
  426. u32 rxff = rtwdev->chip->fw_rxff_size;
  427. u32 dump_size, done_size = 0;
  428. u8 *buf;
  429. int ret;
  430. buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
  431. if (!buf)
  432. return -ENOMEM;
  433. while (size) {
  434. dump_size = size > rxff ? rxff : size;
  435. ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size,
  436. dump_size);
  437. if (ret) {
  438. rtw_err(rtwdev,
  439. "ddma fw 0x%x [+0x%x] to fw fifo fail\n",
  440. ocp_src, done_size);
  441. return ret;
  442. }
  443. ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,
  444. dump_size, (u32 *)(buf + done_size));
  445. if (ret) {
  446. rtw_err(rtwdev,
  447. "dump fw 0x%x [+0x%x] from fw fifo fail\n",
  448. ocp_src, done_size);
  449. return ret;
  450. }
  451. size -= dump_size;
  452. done_size += dump_size;
  453. }
  454. return 0;
  455. }
  456. EXPORT_SYMBOL(rtw_dump_fw);
  457. int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
  458. {
  459. u8 *buf;
  460. u32 i;
  461. if (addr & 0x3) {
  462. WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
  463. return -EINVAL;
  464. }
  465. buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
  466. if (!buf)
  467. return -ENOMEM;
  468. for (i = 0; i < size; i += 4)
  469. *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i);
  470. return 0;
  471. }
  472. EXPORT_SYMBOL(rtw_dump_reg);
  473. void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
  474. struct ieee80211_bss_conf *conf)
  475. {
  476. struct ieee80211_vif *vif = NULL;
  477. if (conf)
  478. vif = container_of(conf, struct ieee80211_vif, bss_conf);
  479. if (conf && vif->cfg.assoc) {
  480. rtwvif->aid = vif->cfg.aid;
  481. rtwvif->net_type = RTW_NET_MGD_LINKED;
  482. } else {
  483. rtwvif->aid = 0;
  484. rtwvif->net_type = RTW_NET_NO_LINK;
  485. }
  486. }
  487. static void rtw_reset_key_iter(struct ieee80211_hw *hw,
  488. struct ieee80211_vif *vif,
  489. struct ieee80211_sta *sta,
  490. struct ieee80211_key_conf *key,
  491. void *data)
  492. {
  493. struct rtw_dev *rtwdev = (struct rtw_dev *)data;
  494. struct rtw_sec_desc *sec = &rtwdev->sec;
  495. rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
  496. }
  497. static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
  498. {
  499. struct rtw_dev *rtwdev = (struct rtw_dev *)data;
  500. if (rtwdev->sta_cnt == 0) {
  501. rtw_warn(rtwdev, "sta count before reset should not be 0\n");
  502. return;
  503. }
  504. rtw_sta_remove(rtwdev, sta, false);
  505. }
  506. static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  507. {
  508. struct rtw_dev *rtwdev = (struct rtw_dev *)data;
  509. struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
  510. rtw_bf_disassoc(rtwdev, vif, NULL);
  511. rtw_vif_assoc_changed(rtwvif, NULL);
  512. rtw_txq_cleanup(rtwdev, vif->txq);
  513. rtw_release_macid(rtwdev, rtwvif->mac_id);
  514. }
  515. void rtw_fw_recovery(struct rtw_dev *rtwdev)
  516. {
  517. if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
  518. ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
  519. }
  520. EXPORT_SYMBOL(rtw_fw_recovery);
  521. static void __fw_recovery_work(struct rtw_dev *rtwdev)
  522. {
  523. int ret = 0;
  524. set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
  525. clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags);
  526. ret = rtw_fwcd_prep(rtwdev);
  527. if (ret)
  528. goto free;
  529. ret = rtw_fw_dump_crash_log(rtwdev);
  530. if (ret)
  531. goto free;
  532. ret = rtw_chip_dump_fw_crash(rtwdev);
  533. if (ret)
  534. goto free;
  535. rtw_fwcd_dump(rtwdev);
  536. free:
  537. rtw_fwcd_free(rtwdev, !!ret);
  538. rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
  539. WARN(1, "firmware crash, start reset and recover\n");
  540. rcu_read_lock();
  541. rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
  542. rcu_read_unlock();
  543. rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
  544. rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
  545. bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM);
  546. rtw_enter_ips(rtwdev);
  547. }
  548. static void rtw_fw_recovery_work(struct work_struct *work)
  549. {
  550. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
  551. fw_recovery_work);
  552. mutex_lock(&rtwdev->mutex);
  553. __fw_recovery_work(rtwdev);
  554. mutex_unlock(&rtwdev->mutex);
  555. ieee80211_restart_hw(rtwdev->hw);
  556. }
  557. struct rtw_txq_ba_iter_data {
  558. };
  559. static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
  560. {
  561. struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
  562. int ret;
  563. u8 tid;
  564. tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
  565. while (tid != IEEE80211_NUM_TIDS) {
  566. clear_bit(tid, si->tid_ba);
  567. ret = ieee80211_start_tx_ba_session(sta, tid, 0);
  568. if (ret == -EINVAL) {
  569. struct ieee80211_txq *txq;
  570. struct rtw_txq *rtwtxq;
  571. txq = sta->txq[tid];
  572. rtwtxq = (struct rtw_txq *)txq->drv_priv;
  573. set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
  574. }
  575. tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
  576. }
  577. }
  578. static void rtw_txq_ba_work(struct work_struct *work)
  579. {
  580. struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
  581. struct rtw_txq_ba_iter_data data;
  582. rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
  583. }
  584. void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel)
  585. {
  586. if (IS_CH_2G_BAND(channel))
  587. pkt_stat->band = NL80211_BAND_2GHZ;
  588. else if (IS_CH_5G_BAND(channel))
  589. pkt_stat->band = NL80211_BAND_5GHZ;
  590. else
  591. return;
  592. pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band);
  593. }
  594. EXPORT_SYMBOL(rtw_set_rx_freq_band);
  595. void rtw_set_dtim_period(struct rtw_dev *rtwdev, u8 dtim_period)
  596. {
  597. rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
  598. rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period ? dtim_period - 1 : 0);
  599. }
  600. void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
  601. u8 primary_channel, enum rtw_supported_band band,
  602. enum rtw_bandwidth bandwidth)
  603. {
  604. enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band);
  605. struct rtw_hal *hal = &rtwdev->hal;
  606. u8 *cch_by_bw = hal->cch_by_bw;
  607. u32 center_freq, primary_freq;
  608. enum rtw_sar_bands sar_band;
  609. u8 primary_channel_idx;
  610. center_freq = ieee80211_channel_to_frequency(center_channel, nl_band);
  611. primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band);
  612. /* assign the center channel used while 20M bw is selected */
  613. cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel;
  614. /* assign the center channel used while current bw is selected */
  615. cch_by_bw[bandwidth] = center_channel;
  616. switch (bandwidth) {
  617. case RTW_CHANNEL_WIDTH_20:
  618. default:
  619. primary_channel_idx = RTW_SC_DONT_CARE;
  620. break;
  621. case RTW_CHANNEL_WIDTH_40:
  622. if (primary_freq > center_freq)
  623. primary_channel_idx = RTW_SC_20_UPPER;
  624. else
  625. primary_channel_idx = RTW_SC_20_LOWER;
  626. break;
  627. case RTW_CHANNEL_WIDTH_80:
  628. if (primary_freq > center_freq) {
  629. if (primary_freq - center_freq == 10)
  630. primary_channel_idx = RTW_SC_20_UPPER;
  631. else
  632. primary_channel_idx = RTW_SC_20_UPMOST;
  633. /* assign the center channel used
  634. * while 40M bw is selected
  635. */
  636. cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4;
  637. } else {
  638. if (center_freq - primary_freq == 10)
  639. primary_channel_idx = RTW_SC_20_LOWER;
  640. else
  641. primary_channel_idx = RTW_SC_20_LOWEST;
  642. /* assign the center channel used
  643. * while 40M bw is selected
  644. */
  645. cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4;
  646. }
  647. break;
  648. }
  649. switch (center_channel) {
  650. case 1 ... 14:
  651. sar_band = RTW_SAR_BAND_0;
  652. break;
  653. case 36 ... 64:
  654. sar_band = RTW_SAR_BAND_1;
  655. break;
  656. case 100 ... 144:
  657. sar_band = RTW_SAR_BAND_3;
  658. break;
  659. case 149 ... 177:
  660. sar_band = RTW_SAR_BAND_4;
  661. break;
  662. default:
  663. WARN(1, "unknown ch(%u) to SAR band\n", center_channel);
  664. sar_band = RTW_SAR_BAND_0;
  665. break;
  666. }
  667. hal->current_primary_channel_index = primary_channel_idx;
  668. hal->current_band_width = bandwidth;
  669. hal->primary_channel = primary_channel;
  670. hal->current_channel = center_channel;
  671. hal->current_band_type = band;
  672. hal->sar_band = sar_band;
  673. }
  674. void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
  675. struct rtw_channel_params *chan_params)
  676. {
  677. struct ieee80211_channel *channel = chandef->chan;
  678. enum nl80211_chan_width width = chandef->width;
  679. u32 primary_freq, center_freq;
  680. u8 center_chan;
  681. u8 bandwidth = RTW_CHANNEL_WIDTH_20;
  682. center_chan = channel->hw_value;
  683. primary_freq = channel->center_freq;
  684. center_freq = chandef->center_freq1;
  685. switch (width) {
  686. case NL80211_CHAN_WIDTH_20_NOHT:
  687. case NL80211_CHAN_WIDTH_20:
  688. bandwidth = RTW_CHANNEL_WIDTH_20;
  689. break;
  690. case NL80211_CHAN_WIDTH_40:
  691. bandwidth = RTW_CHANNEL_WIDTH_40;
  692. if (primary_freq > center_freq)
  693. center_chan -= 2;
  694. else
  695. center_chan += 2;
  696. break;
  697. case NL80211_CHAN_WIDTH_80:
  698. bandwidth = RTW_CHANNEL_WIDTH_80;
  699. if (primary_freq > center_freq) {
  700. if (primary_freq - center_freq == 10)
  701. center_chan -= 2;
  702. else
  703. center_chan -= 6;
  704. } else {
  705. if (center_freq - primary_freq == 10)
  706. center_chan += 2;
  707. else
  708. center_chan += 6;
  709. }
  710. break;
  711. default:
  712. center_chan = 0;
  713. break;
  714. }
  715. chan_params->center_chan = center_chan;
  716. chan_params->bandwidth = bandwidth;
  717. chan_params->primary_chan = channel->hw_value;
  718. }
  719. void rtw_set_channel(struct rtw_dev *rtwdev)
  720. {
  721. const struct rtw_chip_info *chip = rtwdev->chip;
  722. struct ieee80211_hw *hw = rtwdev->hw;
  723. struct rtw_hal *hal = &rtwdev->hal;
  724. struct rtw_channel_params ch_param;
  725. u8 center_chan, primary_chan, bandwidth, band;
  726. rtw_get_channel_params(&hw->conf.chandef, &ch_param);
  727. if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
  728. return;
  729. center_chan = ch_param.center_chan;
  730. primary_chan = ch_param.primary_chan;
  731. bandwidth = ch_param.bandwidth;
  732. band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
  733. rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth);
  734. if (rtwdev->scan_info.op_chan)
  735. rtw_store_op_chan(rtwdev, true);
  736. chip->ops->set_channel(rtwdev, center_chan, bandwidth,
  737. hal->current_primary_channel_index);
  738. if (hal->current_band_type == RTW_BAND_5G) {
  739. rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
  740. } else {
  741. if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
  742. rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
  743. else
  744. rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
  745. }
  746. rtw_phy_set_tx_power_level(rtwdev, center_chan);
  747. /* if the channel isn't set for scanning, we will do RF calibration
  748. * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
  749. * during scanning on each channel takes too long.
  750. */
  751. if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
  752. rtwdev->need_rfk = true;
  753. }
  754. void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
  755. {
  756. const struct rtw_chip_info *chip = rtwdev->chip;
  757. if (rtwdev->need_rfk) {
  758. rtwdev->need_rfk = false;
  759. chip->ops->phy_calibration(rtwdev);
  760. }
  761. }
  762. static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
  763. {
  764. int i;
  765. for (i = 0; i < ETH_ALEN; i++)
  766. rtw_write8(rtwdev, start + i, addr[i]);
  767. }
  768. void rtw_vif_port_config(struct rtw_dev *rtwdev,
  769. struct rtw_vif *rtwvif,
  770. u32 config)
  771. {
  772. u32 addr, mask;
  773. if (config & PORT_SET_MAC_ADDR) {
  774. addr = rtwvif->conf->mac_addr.addr;
  775. rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
  776. }
  777. if (config & PORT_SET_BSSID) {
  778. addr = rtwvif->conf->bssid.addr;
  779. rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
  780. }
  781. if (config & PORT_SET_NET_TYPE) {
  782. addr = rtwvif->conf->net_type.addr;
  783. mask = rtwvif->conf->net_type.mask;
  784. rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
  785. }
  786. if (config & PORT_SET_AID) {
  787. addr = rtwvif->conf->aid.addr;
  788. mask = rtwvif->conf->aid.mask;
  789. rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
  790. }
  791. if (config & PORT_SET_BCN_CTRL) {
  792. addr = rtwvif->conf->bcn_ctrl.addr;
  793. mask = rtwvif->conf->bcn_ctrl.mask;
  794. rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
  795. }
  796. }
  797. static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
  798. {
  799. u8 bw = 0;
  800. switch (bw_cap) {
  801. case EFUSE_HW_CAP_IGNORE:
  802. case EFUSE_HW_CAP_SUPP_BW80:
  803. bw |= BIT(RTW_CHANNEL_WIDTH_80);
  804. fallthrough;
  805. case EFUSE_HW_CAP_SUPP_BW40:
  806. bw |= BIT(RTW_CHANNEL_WIDTH_40);
  807. fallthrough;
  808. default:
  809. bw |= BIT(RTW_CHANNEL_WIDTH_20);
  810. break;
  811. }
  812. return bw;
  813. }
  814. static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
  815. {
  816. const struct rtw_chip_info *chip = rtwdev->chip;
  817. struct rtw_hal *hal = &rtwdev->hal;
  818. if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
  819. hw_ant_num >= hal->rf_path_num)
  820. return;
  821. switch (hw_ant_num) {
  822. case 1:
  823. hal->rf_type = RF_1T1R;
  824. hal->rf_path_num = 1;
  825. if (!chip->fix_rf_phy_num)
  826. hal->rf_phy_num = hal->rf_path_num;
  827. hal->antenna_tx = BB_PATH_A;
  828. hal->antenna_rx = BB_PATH_A;
  829. break;
  830. default:
  831. WARN(1, "invalid hw configuration from efuse\n");
  832. break;
  833. }
  834. }
  835. static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
  836. {
  837. u64 ra_mask = 0;
  838. u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
  839. u8 vht_mcs_cap;
  840. int i, nss;
  841. /* 4SS, every two bits for MCS7/8/9 */
  842. for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
  843. vht_mcs_cap = mcs_map & 0x3;
  844. switch (vht_mcs_cap) {
  845. case 2: /* MCS9 */
  846. ra_mask |= 0x3ffULL << nss;
  847. break;
  848. case 1: /* MCS8 */
  849. ra_mask |= 0x1ffULL << nss;
  850. break;
  851. case 0: /* MCS7 */
  852. ra_mask |= 0x0ffULL << nss;
  853. break;
  854. default:
  855. break;
  856. }
  857. }
  858. return ra_mask;
  859. }
  860. static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
  861. {
  862. u8 rate_id = 0;
  863. switch (wireless_set) {
  864. case WIRELESS_CCK:
  865. rate_id = RTW_RATEID_B_20M;
  866. break;
  867. case WIRELESS_OFDM:
  868. rate_id = RTW_RATEID_G;
  869. break;
  870. case WIRELESS_CCK | WIRELESS_OFDM:
  871. rate_id = RTW_RATEID_BG;
  872. break;
  873. case WIRELESS_OFDM | WIRELESS_HT:
  874. if (tx_num == 1)
  875. rate_id = RTW_RATEID_GN_N1SS;
  876. else if (tx_num == 2)
  877. rate_id = RTW_RATEID_GN_N2SS;
  878. else if (tx_num == 3)
  879. rate_id = RTW_RATEID_ARFR5_N_3SS;
  880. break;
  881. case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
  882. if (bw_mode == RTW_CHANNEL_WIDTH_40) {
  883. if (tx_num == 1)
  884. rate_id = RTW_RATEID_BGN_40M_1SS;
  885. else if (tx_num == 2)
  886. rate_id = RTW_RATEID_BGN_40M_2SS;
  887. else if (tx_num == 3)
  888. rate_id = RTW_RATEID_ARFR5_N_3SS;
  889. else if (tx_num == 4)
  890. rate_id = RTW_RATEID_ARFR7_N_4SS;
  891. } else {
  892. if (tx_num == 1)
  893. rate_id = RTW_RATEID_BGN_20M_1SS;
  894. else if (tx_num == 2)
  895. rate_id = RTW_RATEID_BGN_20M_2SS;
  896. else if (tx_num == 3)
  897. rate_id = RTW_RATEID_ARFR5_N_3SS;
  898. else if (tx_num == 4)
  899. rate_id = RTW_RATEID_ARFR7_N_4SS;
  900. }
  901. break;
  902. case WIRELESS_OFDM | WIRELESS_VHT:
  903. if (tx_num == 1)
  904. rate_id = RTW_RATEID_ARFR1_AC_1SS;
  905. else if (tx_num == 2)
  906. rate_id = RTW_RATEID_ARFR0_AC_2SS;
  907. else if (tx_num == 3)
  908. rate_id = RTW_RATEID_ARFR4_AC_3SS;
  909. else if (tx_num == 4)
  910. rate_id = RTW_RATEID_ARFR6_AC_4SS;
  911. break;
  912. case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
  913. if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
  914. if (tx_num == 1)
  915. rate_id = RTW_RATEID_ARFR1_AC_1SS;
  916. else if (tx_num == 2)
  917. rate_id = RTW_RATEID_ARFR0_AC_2SS;
  918. else if (tx_num == 3)
  919. rate_id = RTW_RATEID_ARFR4_AC_3SS;
  920. else if (tx_num == 4)
  921. rate_id = RTW_RATEID_ARFR6_AC_4SS;
  922. } else {
  923. if (tx_num == 1)
  924. rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
  925. else if (tx_num == 2)
  926. rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
  927. else if (tx_num == 3)
  928. rate_id = RTW_RATEID_ARFR4_AC_3SS;
  929. else if (tx_num == 4)
  930. rate_id = RTW_RATEID_ARFR6_AC_4SS;
  931. }
  932. break;
  933. default:
  934. break;
  935. }
  936. return rate_id;
  937. }
  938. #define RA_MASK_CCK_RATES 0x0000f
  939. #define RA_MASK_OFDM_RATES 0x00ff0
  940. #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
  941. #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
  942. #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
  943. #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
  944. RA_MASK_HT_RATES_2SS | \
  945. RA_MASK_HT_RATES_3SS)
  946. #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
  947. #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
  948. #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
  949. #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
  950. RA_MASK_VHT_RATES_2SS | \
  951. RA_MASK_VHT_RATES_3SS)
  952. #define RA_MASK_CCK_IN_BG 0x00005
  953. #define RA_MASK_CCK_IN_HT 0x00005
  954. #define RA_MASK_CCK_IN_VHT 0x00005
  955. #define RA_MASK_OFDM_IN_VHT 0x00010
  956. #define RA_MASK_OFDM_IN_HT_2G 0x00010
  957. #define RA_MASK_OFDM_IN_HT_5G 0x00030
  958. static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set)
  959. {
  960. u8 rssi_level = si->rssi_level;
  961. if (wireless_set == WIRELESS_CCK)
  962. return 0xffffffffffffffffULL;
  963. if (rssi_level == 0)
  964. return 0xffffffffffffffffULL;
  965. else if (rssi_level == 1)
  966. return 0xfffffffffffffff0ULL;
  967. else if (rssi_level == 2)
  968. return 0xffffffffffffefe0ULL;
  969. else if (rssi_level == 3)
  970. return 0xffffffffffffcfc0ULL;
  971. else if (rssi_level == 4)
  972. return 0xffffffffffff8f80ULL;
  973. else
  974. return 0xffffffffffff0f00ULL;
  975. }
  976. static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak)
  977. {
  978. if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
  979. ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
  980. if (ra_mask == 0)
  981. ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
  982. return ra_mask;
  983. }
  984. static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
  985. u64 ra_mask, bool is_vht_enable)
  986. {
  987. struct rtw_hal *hal = &rtwdev->hal;
  988. const struct cfg80211_bitrate_mask *mask = si->mask;
  989. u64 cfg_mask = GENMASK_ULL(63, 0);
  990. u8 band;
  991. if (!si->use_cfg_mask)
  992. return ra_mask;
  993. band = hal->current_band_type;
  994. if (band == RTW_BAND_2G) {
  995. band = NL80211_BAND_2GHZ;
  996. cfg_mask = mask->control[band].legacy;
  997. } else if (band == RTW_BAND_5G) {
  998. band = NL80211_BAND_5GHZ;
  999. cfg_mask = u64_encode_bits(mask->control[band].legacy,
  1000. RA_MASK_OFDM_RATES);
  1001. }
  1002. if (!is_vht_enable) {
  1003. if (ra_mask & RA_MASK_HT_RATES_1SS)
  1004. cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
  1005. RA_MASK_HT_RATES_1SS);
  1006. if (ra_mask & RA_MASK_HT_RATES_2SS)
  1007. cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
  1008. RA_MASK_HT_RATES_2SS);
  1009. } else {
  1010. if (ra_mask & RA_MASK_VHT_RATES_1SS)
  1011. cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
  1012. RA_MASK_VHT_RATES_1SS);
  1013. if (ra_mask & RA_MASK_VHT_RATES_2SS)
  1014. cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
  1015. RA_MASK_VHT_RATES_2SS);
  1016. }
  1017. ra_mask &= cfg_mask;
  1018. return ra_mask;
  1019. }
  1020. void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
  1021. bool reset_ra_mask)
  1022. {
  1023. struct rtw_dm_info *dm_info = &rtwdev->dm_info;
  1024. struct ieee80211_sta *sta = si->sta;
  1025. struct rtw_efuse *efuse = &rtwdev->efuse;
  1026. struct rtw_hal *hal = &rtwdev->hal;
  1027. u8 wireless_set;
  1028. u8 bw_mode;
  1029. u8 rate_id;
  1030. u8 stbc_en = 0;
  1031. u8 ldpc_en = 0;
  1032. u8 tx_num = 1;
  1033. u64 ra_mask = 0;
  1034. u64 ra_mask_bak = 0;
  1035. bool is_vht_enable = false;
  1036. bool is_support_sgi = false;
  1037. if (sta->deflink.vht_cap.vht_supported) {
  1038. is_vht_enable = true;
  1039. ra_mask |= get_vht_ra_mask(sta);
  1040. if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
  1041. stbc_en = VHT_STBC_EN;
  1042. if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
  1043. ldpc_en = VHT_LDPC_EN;
  1044. } else if (sta->deflink.ht_cap.ht_supported) {
  1045. ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 36) |
  1046. ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 28) |
  1047. (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) |
  1048. (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
  1049. if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
  1050. stbc_en = HT_STBC_EN;
  1051. if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
  1052. ldpc_en = HT_LDPC_EN;
  1053. }
  1054. if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss)
  1055. ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
  1056. else if (efuse->hw_cap.nss == 2)
  1057. ra_mask &= RA_MASK_VHT_RATES_2SS | RA_MASK_HT_RATES_2SS |
  1058. RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
  1059. if (hal->current_band_type == RTW_BAND_5G) {
  1060. ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
  1061. ra_mask_bak = ra_mask;
  1062. if (sta->deflink.vht_cap.vht_supported) {
  1063. ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
  1064. wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
  1065. } else if (sta->deflink.ht_cap.ht_supported) {
  1066. ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
  1067. wireless_set = WIRELESS_OFDM | WIRELESS_HT;
  1068. } else {
  1069. wireless_set = WIRELESS_OFDM;
  1070. }
  1071. dm_info->rrsr_val_init = RRSR_INIT_5G;
  1072. } else if (hal->current_band_type == RTW_BAND_2G) {
  1073. ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
  1074. ra_mask_bak = ra_mask;
  1075. if (sta->deflink.vht_cap.vht_supported) {
  1076. ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
  1077. RA_MASK_OFDM_IN_VHT;
  1078. wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
  1079. WIRELESS_HT | WIRELESS_VHT;
  1080. } else if (sta->deflink.ht_cap.ht_supported) {
  1081. ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
  1082. RA_MASK_OFDM_IN_HT_2G;
  1083. wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
  1084. WIRELESS_HT;
  1085. } else if (sta->deflink.supp_rates[0] <= 0xf) {
  1086. wireless_set = WIRELESS_CCK;
  1087. } else {
  1088. ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG;
  1089. wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
  1090. }
  1091. dm_info->rrsr_val_init = RRSR_INIT_2G;
  1092. } else {
  1093. rtw_err(rtwdev, "Unknown band type\n");
  1094. ra_mask_bak = ra_mask;
  1095. wireless_set = 0;
  1096. }
  1097. switch (sta->deflink.bandwidth) {
  1098. case IEEE80211_STA_RX_BW_80:
  1099. bw_mode = RTW_CHANNEL_WIDTH_80;
  1100. is_support_sgi = sta->deflink.vht_cap.vht_supported &&
  1101. (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
  1102. break;
  1103. case IEEE80211_STA_RX_BW_40:
  1104. bw_mode = RTW_CHANNEL_WIDTH_40;
  1105. is_support_sgi = sta->deflink.ht_cap.ht_supported &&
  1106. (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
  1107. break;
  1108. default:
  1109. bw_mode = RTW_CHANNEL_WIDTH_20;
  1110. is_support_sgi = sta->deflink.ht_cap.ht_supported &&
  1111. (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
  1112. break;
  1113. }
  1114. if (sta->deflink.vht_cap.vht_supported ||
  1115. sta->deflink.ht_cap.ht_supported)
  1116. tx_num = efuse->hw_cap.nss;
  1117. rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
  1118. ra_mask &= rtw_rate_mask_rssi(si, wireless_set);
  1119. ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak);
  1120. ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable);
  1121. si->bw_mode = bw_mode;
  1122. si->stbc_en = stbc_en;
  1123. si->ldpc_en = ldpc_en;
  1124. si->sgi_enable = is_support_sgi;
  1125. si->vht_enable = is_vht_enable;
  1126. si->ra_mask = ra_mask;
  1127. si->rate_id = rate_id;
  1128. rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask);
  1129. }
  1130. int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
  1131. {
  1132. const struct rtw_chip_info *chip = rtwdev->chip;
  1133. struct rtw_fw_state *fw;
  1134. int ret = 0;
  1135. fw = &rtwdev->fw;
  1136. wait_for_completion(&fw->completion);
  1137. if (!fw->firmware)
  1138. ret = -EINVAL;
  1139. if (chip->wow_fw_name) {
  1140. fw = &rtwdev->wow_fw;
  1141. wait_for_completion(&fw->completion);
  1142. if (!fw->firmware)
  1143. ret = -EINVAL;
  1144. }
  1145. return ret;
  1146. }
  1147. EXPORT_SYMBOL(rtw_wait_firmware_completion);
  1148. static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
  1149. struct rtw_fw_state *fw)
  1150. {
  1151. const struct rtw_chip_info *chip = rtwdev->chip;
  1152. if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
  1153. !fw->feature)
  1154. return LPS_DEEP_MODE_NONE;
  1155. if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
  1156. rtw_fw_feature_check(fw, FW_FEATURE_PG))
  1157. return LPS_DEEP_MODE_PG;
  1158. if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
  1159. rtw_fw_feature_check(fw, FW_FEATURE_LCLK))
  1160. return LPS_DEEP_MODE_LCLK;
  1161. return LPS_DEEP_MODE_NONE;
  1162. }
  1163. int rtw_power_on(struct rtw_dev *rtwdev)
  1164. {
  1165. const struct rtw_chip_info *chip = rtwdev->chip;
  1166. struct rtw_fw_state *fw = &rtwdev->fw;
  1167. bool wifi_only;
  1168. int ret;
  1169. ret = rtw_hci_setup(rtwdev);
  1170. if (ret) {
  1171. rtw_err(rtwdev, "failed to setup hci\n");
  1172. goto err;
  1173. }
  1174. /* power on MAC before firmware downloaded */
  1175. ret = rtw_mac_power_on(rtwdev);
  1176. if (ret) {
  1177. rtw_err(rtwdev, "failed to power on mac\n");
  1178. goto err;
  1179. }
  1180. ret = rtw_wait_firmware_completion(rtwdev);
  1181. if (ret) {
  1182. rtw_err(rtwdev, "failed to wait firmware completion\n");
  1183. goto err_off;
  1184. }
  1185. ret = rtw_download_firmware(rtwdev, fw);
  1186. if (ret) {
  1187. rtw_err(rtwdev, "failed to download firmware\n");
  1188. goto err_off;
  1189. }
  1190. /* config mac after firmware downloaded */
  1191. ret = rtw_mac_init(rtwdev);
  1192. if (ret) {
  1193. rtw_err(rtwdev, "failed to configure mac\n");
  1194. goto err_off;
  1195. }
  1196. chip->ops->phy_set_param(rtwdev);
  1197. ret = rtw_mac_postinit(rtwdev);
  1198. if (ret) {
  1199. rtw_err(rtwdev, "failed to configure mac in postinit\n");
  1200. goto err_off;
  1201. }
  1202. ret = rtw_hci_start(rtwdev);
  1203. if (ret) {
  1204. rtw_err(rtwdev, "failed to start hci\n");
  1205. goto err_off;
  1206. }
  1207. /* send H2C after HCI has started */
  1208. rtw_fw_send_general_info(rtwdev);
  1209. rtw_fw_send_phydm_info(rtwdev);
  1210. wifi_only = !rtwdev->efuse.btcoex;
  1211. rtw_coex_power_on_setting(rtwdev);
  1212. rtw_coex_init_hw_config(rtwdev, wifi_only);
  1213. return 0;
  1214. err_off:
  1215. rtw_mac_power_off(rtwdev);
  1216. err:
  1217. return ret;
  1218. }
  1219. EXPORT_SYMBOL(rtw_power_on);
  1220. void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start)
  1221. {
  1222. if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
  1223. return;
  1224. if (start) {
  1225. rtw_fw_scan_notify(rtwdev, true);
  1226. } else {
  1227. reinit_completion(&rtwdev->fw_scan_density);
  1228. rtw_fw_scan_notify(rtwdev, false);
  1229. if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
  1230. SCAN_NOTIFY_TIMEOUT))
  1231. rtw_warn(rtwdev, "firmware failed to report density after scan\n");
  1232. }
  1233. }
  1234. void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
  1235. const u8 *mac_addr, bool hw_scan)
  1236. {
  1237. u32 config = 0;
  1238. int ret = 0;
  1239. rtw_leave_lps(rtwdev);
  1240. if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) {
  1241. ret = rtw_leave_ips(rtwdev);
  1242. if (ret) {
  1243. rtw_err(rtwdev, "failed to leave idle state\n");
  1244. return;
  1245. }
  1246. }
  1247. ether_addr_copy(rtwvif->mac_addr, mac_addr);
  1248. config |= PORT_SET_MAC_ADDR;
  1249. rtw_vif_port_config(rtwdev, rtwvif, config);
  1250. rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
  1251. rtw_core_fw_scan_notify(rtwdev, true);
  1252. set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
  1253. set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
  1254. rtw_phy_dig_set_max_coverage(rtwdev);
  1255. }
  1256. void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
  1257. bool hw_scan)
  1258. {
  1259. struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL;
  1260. u32 config = 0;
  1261. if (!rtwvif)
  1262. return;
  1263. rtw_phy_dig_reset(rtwdev);
  1264. clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
  1265. clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
  1266. rtw_core_fw_scan_notify(rtwdev, false);
  1267. ether_addr_copy(rtwvif->mac_addr, vif->addr);
  1268. config |= PORT_SET_MAC_ADDR;
  1269. rtw_vif_port_config(rtwdev, rtwvif, config);
  1270. rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
  1271. if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
  1272. ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
  1273. }
  1274. int rtw_core_start(struct rtw_dev *rtwdev)
  1275. {
  1276. int ret;
  1277. ret = rtwdev->chip->ops->power_on(rtwdev);
  1278. if (ret)
  1279. return ret;
  1280. rtw_sec_enable_sec_engine(rtwdev);
  1281. rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
  1282. rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
  1283. /* rcr reset after powered on */
  1284. rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
  1285. ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
  1286. RTW_WATCH_DOG_DELAY_TIME);
  1287. set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
  1288. return 0;
  1289. }
  1290. void rtw_power_off(struct rtw_dev *rtwdev)
  1291. {
  1292. rtw_hci_stop(rtwdev);
  1293. rtw_coex_power_off_setting(rtwdev);
  1294. rtw_mac_power_off(rtwdev);
  1295. }
  1296. EXPORT_SYMBOL(rtw_power_off);
  1297. void rtw_core_stop(struct rtw_dev *rtwdev)
  1298. {
  1299. struct rtw_coex *coex = &rtwdev->coex;
  1300. clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
  1301. clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
  1302. mutex_unlock(&rtwdev->mutex);
  1303. cancel_work_sync(&rtwdev->c2h_work);
  1304. cancel_work_sync(&rtwdev->update_beacon_work);
  1305. cancel_delayed_work_sync(&rtwdev->watch_dog_work);
  1306. cancel_delayed_work_sync(&coex->bt_relink_work);
  1307. cancel_delayed_work_sync(&coex->bt_reenable_work);
  1308. cancel_delayed_work_sync(&coex->defreeze_work);
  1309. cancel_delayed_work_sync(&coex->wl_remain_work);
  1310. cancel_delayed_work_sync(&coex->bt_remain_work);
  1311. cancel_delayed_work_sync(&coex->wl_connecting_work);
  1312. cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
  1313. cancel_delayed_work_sync(&coex->wl_ccklock_work);
  1314. mutex_lock(&rtwdev->mutex);
  1315. rtwdev->chip->ops->power_off(rtwdev);
  1316. }
  1317. static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
  1318. struct ieee80211_sta_ht_cap *ht_cap)
  1319. {
  1320. const struct rtw_chip_info *chip = rtwdev->chip;
  1321. struct rtw_efuse *efuse = &rtwdev->efuse;
  1322. int i;
  1323. ht_cap->ht_supported = true;
  1324. ht_cap->cap = 0;
  1325. ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
  1326. IEEE80211_HT_CAP_MAX_AMSDU |
  1327. (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
  1328. if (rtw_chip_has_rx_ldpc(rtwdev))
  1329. ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
  1330. if (rtw_chip_has_tx_stbc(rtwdev))
  1331. ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
  1332. if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
  1333. ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  1334. IEEE80211_HT_CAP_DSSSCCK40 |
  1335. IEEE80211_HT_CAP_SGI_40;
  1336. ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  1337. ht_cap->ampdu_density = chip->ampdu_density;
  1338. ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  1339. for (i = 0; i < efuse->hw_cap.nss; i++)
  1340. ht_cap->mcs.rx_mask[i] = 0xFF;
  1341. ht_cap->mcs.rx_mask[4] = 0x01;
  1342. ht_cap->mcs.rx_highest = cpu_to_le16(150 * efuse->hw_cap.nss);
  1343. }
  1344. static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
  1345. struct ieee80211_sta_vht_cap *vht_cap)
  1346. {
  1347. struct rtw_efuse *efuse = &rtwdev->efuse;
  1348. u16 mcs_map = 0;
  1349. __le16 highest;
  1350. int i;
  1351. if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
  1352. efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
  1353. return;
  1354. vht_cap->vht_supported = true;
  1355. vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
  1356. IEEE80211_VHT_CAP_SHORT_GI_80 |
  1357. IEEE80211_VHT_CAP_RXSTBC_1 |
  1358. IEEE80211_VHT_CAP_HTC_VHT |
  1359. IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
  1360. 0;
  1361. if (rtwdev->hal.rf_path_num > 1)
  1362. vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
  1363. vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
  1364. IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
  1365. vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
  1366. IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
  1367. if (rtw_chip_has_rx_ldpc(rtwdev))
  1368. vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
  1369. for (i = 0; i < 8; i++) {
  1370. if (i < efuse->hw_cap.nss)
  1371. mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
  1372. else
  1373. mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
  1374. }
  1375. highest = cpu_to_le16(390 * efuse->hw_cap.nss);
  1376. vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
  1377. vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
  1378. vht_cap->vht_mcs.rx_highest = highest;
  1379. vht_cap->vht_mcs.tx_highest = highest;
  1380. }
  1381. static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev)
  1382. {
  1383. u16 len;
  1384. len = rtwdev->chip->max_scan_ie_len;
  1385. if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) &&
  1386. rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
  1387. len = IEEE80211_MAX_DATA_LEN;
  1388. else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM))
  1389. len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE;
  1390. return len;
  1391. }
  1392. static struct ieee80211_supported_band *
  1393. rtw_sband_dup(struct rtw_dev *rtwdev,
  1394. const struct ieee80211_supported_band *sband)
  1395. {
  1396. struct ieee80211_supported_band *dup;
  1397. dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL);
  1398. if (!dup)
  1399. return NULL;
  1400. dup->channels = devm_kmemdup_array(rtwdev->dev, sband->channels,
  1401. sband->n_channels,
  1402. sizeof(*sband->channels),
  1403. GFP_KERNEL);
  1404. if (!dup->channels)
  1405. return NULL;
  1406. dup->bitrates = devm_kmemdup_array(rtwdev->dev, sband->bitrates,
  1407. sband->n_bitrates,
  1408. sizeof(*sband->bitrates),
  1409. GFP_KERNEL);
  1410. if (!dup->bitrates)
  1411. return NULL;
  1412. return dup;
  1413. }
  1414. static void rtw_set_supported_band(struct ieee80211_hw *hw,
  1415. const struct rtw_chip_info *chip)
  1416. {
  1417. struct ieee80211_supported_band *sband;
  1418. struct rtw_dev *rtwdev = hw->priv;
  1419. if (chip->band & RTW_BAND_2G) {
  1420. sband = rtw_sband_dup(rtwdev, &rtw_band_2ghz);
  1421. if (!sband)
  1422. goto err_out;
  1423. if (chip->ht_supported)
  1424. rtw_init_ht_cap(rtwdev, &sband->ht_cap);
  1425. hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
  1426. }
  1427. if (chip->band & RTW_BAND_5G) {
  1428. sband = rtw_sband_dup(rtwdev, &rtw_band_5ghz);
  1429. if (!sband)
  1430. goto err_out;
  1431. if (chip->ht_supported)
  1432. rtw_init_ht_cap(rtwdev, &sband->ht_cap);
  1433. if (chip->vht_supported)
  1434. rtw_init_vht_cap(rtwdev, &sband->vht_cap);
  1435. hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
  1436. }
  1437. return;
  1438. err_out:
  1439. rtw_err(rtwdev, "failed to set supported band\n");
  1440. }
  1441. static void rtw_vif_smps_iter(void *data, u8 *mac,
  1442. struct ieee80211_vif *vif)
  1443. {
  1444. struct rtw_dev *rtwdev = (struct rtw_dev *)data;
  1445. if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
  1446. return;
  1447. if (rtwdev->hal.txrx_1ss)
  1448. ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC);
  1449. else
  1450. ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF);
  1451. }
  1452. void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss)
  1453. {
  1454. const struct rtw_chip_info *chip = rtwdev->chip;
  1455. struct rtw_hal *hal = &rtwdev->hal;
  1456. if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss)
  1457. return;
  1458. rtwdev->hal.txrx_1ss = txrx_1ss;
  1459. if (txrx_1ss)
  1460. chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false);
  1461. else
  1462. chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx,
  1463. hal->antenna_rx, false);
  1464. rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev);
  1465. }
  1466. static void __update_firmware_feature(struct rtw_dev *rtwdev,
  1467. struct rtw_fw_state *fw)
  1468. {
  1469. u32 feature;
  1470. const struct rtw_fw_hdr *fw_hdr =
  1471. (const struct rtw_fw_hdr *)fw->firmware->data;
  1472. feature = le32_to_cpu(fw_hdr->feature);
  1473. fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
  1474. if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C &&
  1475. RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13))
  1476. fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM;
  1477. }
  1478. static void __update_firmware_info(struct rtw_dev *rtwdev,
  1479. struct rtw_fw_state *fw)
  1480. {
  1481. const struct rtw_fw_hdr *fw_hdr =
  1482. (const struct rtw_fw_hdr *)fw->firmware->data;
  1483. fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
  1484. fw->version = le16_to_cpu(fw_hdr->version);
  1485. fw->sub_version = fw_hdr->subversion;
  1486. fw->sub_index = fw_hdr->subindex;
  1487. __update_firmware_feature(rtwdev, fw);
  1488. }
  1489. static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
  1490. struct rtw_fw_state *fw)
  1491. {
  1492. struct rtw_fw_hdr_legacy *legacy =
  1493. (struct rtw_fw_hdr_legacy *)fw->firmware->data;
  1494. fw->h2c_version = 0;
  1495. fw->version = le16_to_cpu(legacy->version);
  1496. fw->sub_version = legacy->subversion1;
  1497. fw->sub_index = legacy->subversion2;
  1498. }
  1499. static void update_firmware_info(struct rtw_dev *rtwdev,
  1500. struct rtw_fw_state *fw)
  1501. {
  1502. if (rtw_chip_wcpu_8051(rtwdev))
  1503. __update_firmware_info_legacy(rtwdev, fw);
  1504. else
  1505. __update_firmware_info(rtwdev, fw);
  1506. }
  1507. static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
  1508. {
  1509. struct rtw_fw_state *fw = context;
  1510. struct rtw_dev *rtwdev = fw->rtwdev;
  1511. if (!firmware || !firmware->data) {
  1512. rtw_err(rtwdev, "failed to request firmware\n");
  1513. complete_all(&fw->completion);
  1514. return;
  1515. }
  1516. fw->firmware = firmware;
  1517. update_firmware_info(rtwdev, fw);
  1518. complete_all(&fw->completion);
  1519. rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n",
  1520. fw->type == RTW_WOWLAN_FW ? "WOW " : "",
  1521. fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
  1522. }
  1523. static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
  1524. {
  1525. const char *fw_name;
  1526. struct rtw_fw_state *fw;
  1527. int ret;
  1528. switch (type) {
  1529. case RTW_WOWLAN_FW:
  1530. fw = &rtwdev->wow_fw;
  1531. fw_name = rtwdev->chip->wow_fw_name;
  1532. break;
  1533. case RTW_NORMAL_FW:
  1534. fw = &rtwdev->fw;
  1535. fw_name = rtwdev->chip->fw_name;
  1536. break;
  1537. default:
  1538. rtw_warn(rtwdev, "unsupported firmware type\n");
  1539. return -ENOENT;
  1540. }
  1541. fw->type = type;
  1542. fw->rtwdev = rtwdev;
  1543. init_completion(&fw->completion);
  1544. ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
  1545. GFP_KERNEL, fw, rtw_load_firmware_cb);
  1546. if (ret) {
  1547. rtw_err(rtwdev, "failed to async firmware request\n");
  1548. return ret;
  1549. }
  1550. return 0;
  1551. }
  1552. static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
  1553. {
  1554. const struct rtw_chip_info *chip = rtwdev->chip;
  1555. struct rtw_hal *hal = &rtwdev->hal;
  1556. struct rtw_efuse *efuse = &rtwdev->efuse;
  1557. switch (rtw_hci_type(rtwdev)) {
  1558. case RTW_HCI_TYPE_PCIE:
  1559. rtwdev->hci.rpwm_addr = 0x03d9;
  1560. rtwdev->hci.cpwm_addr = 0x03da;
  1561. break;
  1562. case RTW_HCI_TYPE_SDIO:
  1563. rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1;
  1564. rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2;
  1565. break;
  1566. case RTW_HCI_TYPE_USB:
  1567. rtwdev->hci.rpwm_addr = 0xfe58;
  1568. rtwdev->hci.cpwm_addr = 0xfe57;
  1569. break;
  1570. default:
  1571. rtw_err(rtwdev, "unsupported hci type\n");
  1572. return -EINVAL;
  1573. }
  1574. hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
  1575. hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
  1576. hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
  1577. if (hal->chip_version & BIT_RF_TYPE_ID) {
  1578. hal->rf_type = RF_2T2R;
  1579. hal->rf_path_num = 2;
  1580. hal->antenna_tx = BB_PATH_AB;
  1581. hal->antenna_rx = BB_PATH_AB;
  1582. } else {
  1583. hal->rf_type = RF_1T1R;
  1584. hal->rf_path_num = 1;
  1585. hal->antenna_tx = BB_PATH_A;
  1586. hal->antenna_rx = BB_PATH_A;
  1587. }
  1588. hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
  1589. hal->rf_path_num;
  1590. efuse->physical_size = chip->phy_efuse_size;
  1591. efuse->logical_size = chip->log_efuse_size;
  1592. efuse->protect_size = chip->ptct_efuse_size;
  1593. /* default use ack */
  1594. rtwdev->hal.rcr |= BIT_VHT_DACK;
  1595. hal->bfee_sts_cap = 3;
  1596. return 0;
  1597. }
  1598. static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
  1599. {
  1600. struct rtw_fw_state *fw = &rtwdev->fw;
  1601. int ret;
  1602. ret = rtw_hci_setup(rtwdev);
  1603. if (ret) {
  1604. rtw_err(rtwdev, "failed to setup hci\n");
  1605. goto err;
  1606. }
  1607. ret = rtw_mac_power_on(rtwdev);
  1608. if (ret) {
  1609. rtw_err(rtwdev, "failed to power on mac\n");
  1610. goto err;
  1611. }
  1612. rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
  1613. wait_for_completion(&fw->completion);
  1614. if (!fw->firmware) {
  1615. ret = -EINVAL;
  1616. rtw_err(rtwdev, "failed to load firmware\n");
  1617. goto err;
  1618. }
  1619. ret = rtw_download_firmware(rtwdev, fw);
  1620. if (ret) {
  1621. rtw_err(rtwdev, "failed to download firmware\n");
  1622. goto err_off;
  1623. }
  1624. return 0;
  1625. err_off:
  1626. rtw_mac_power_off(rtwdev);
  1627. err:
  1628. return ret;
  1629. }
  1630. static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
  1631. {
  1632. struct rtw_efuse *efuse = &rtwdev->efuse;
  1633. u8 hw_feature[HW_FEATURE_LEN];
  1634. u8 id;
  1635. u8 bw;
  1636. int i;
  1637. if (!rtwdev->chip->hw_feature_report)
  1638. return 0;
  1639. id = rtw_read8(rtwdev, REG_C2HEVT);
  1640. if (id != C2H_HW_FEATURE_REPORT) {
  1641. rtw_err(rtwdev, "failed to read hw feature report\n");
  1642. return -EBUSY;
  1643. }
  1644. for (i = 0; i < HW_FEATURE_LEN; i++)
  1645. hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
  1646. rtw_write8(rtwdev, REG_C2HEVT, 0);
  1647. bw = GET_EFUSE_HW_CAP_BW(hw_feature);
  1648. efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
  1649. efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
  1650. efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
  1651. efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
  1652. efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
  1653. rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
  1654. if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
  1655. efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
  1656. efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
  1657. rtw_dbg(rtwdev, RTW_DBG_EFUSE,
  1658. "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
  1659. efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
  1660. efuse->hw_cap.ant_num, efuse->hw_cap.nss);
  1661. return 0;
  1662. }
  1663. static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
  1664. {
  1665. rtw_hci_stop(rtwdev);
  1666. rtw_mac_power_off(rtwdev);
  1667. }
  1668. static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
  1669. {
  1670. struct rtw_efuse *efuse = &rtwdev->efuse;
  1671. int ret;
  1672. mutex_lock(&rtwdev->mutex);
  1673. /* power on mac to read efuse */
  1674. ret = rtw_chip_efuse_enable(rtwdev);
  1675. if (ret)
  1676. goto out_unlock;
  1677. ret = rtw_parse_efuse_map(rtwdev);
  1678. if (ret)
  1679. goto out_disable;
  1680. ret = rtw_dump_hw_feature(rtwdev);
  1681. if (ret)
  1682. goto out_disable;
  1683. ret = rtw_check_supported_rfe(rtwdev);
  1684. if (ret)
  1685. goto out_disable;
  1686. if (efuse->crystal_cap == 0xff)
  1687. efuse->crystal_cap = 0;
  1688. if (efuse->pa_type_2g == 0xff)
  1689. efuse->pa_type_2g = 0;
  1690. if (efuse->pa_type_5g == 0xff)
  1691. efuse->pa_type_5g = 0;
  1692. if (efuse->lna_type_2g == 0xff)
  1693. efuse->lna_type_2g = 0;
  1694. if (efuse->lna_type_5g == 0xff)
  1695. efuse->lna_type_5g = 0;
  1696. if (efuse->channel_plan == 0xff)
  1697. efuse->channel_plan = 0x7f;
  1698. if (efuse->rf_board_option == 0xff)
  1699. efuse->rf_board_option = 0;
  1700. if (efuse->bt_setting & BIT(0))
  1701. efuse->share_ant = true;
  1702. if (efuse->regd == 0xff)
  1703. efuse->regd = 0;
  1704. if (efuse->tx_bb_swing_setting_2g == 0xff)
  1705. efuse->tx_bb_swing_setting_2g = 0;
  1706. if (efuse->tx_bb_swing_setting_5g == 0xff)
  1707. efuse->tx_bb_swing_setting_5g = 0;
  1708. efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
  1709. efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
  1710. efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
  1711. efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
  1712. efuse->ext_lna_5g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
  1713. if (!is_valid_ether_addr(efuse->addr)) {
  1714. eth_random_addr(efuse->addr);
  1715. dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n");
  1716. }
  1717. out_disable:
  1718. rtw_chip_efuse_disable(rtwdev);
  1719. out_unlock:
  1720. mutex_unlock(&rtwdev->mutex);
  1721. return ret;
  1722. }
  1723. static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
  1724. {
  1725. struct rtw_hal *hal = &rtwdev->hal;
  1726. const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
  1727. if (!rfe_def)
  1728. return -ENODEV;
  1729. rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type);
  1730. rtw_phy_init_tx_power(rtwdev);
  1731. rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
  1732. rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
  1733. rtw_phy_tx_power_by_rate_config(hal);
  1734. rtw_phy_tx_power_limit_config(hal);
  1735. return 0;
  1736. }
  1737. int rtw_chip_info_setup(struct rtw_dev *rtwdev)
  1738. {
  1739. int ret;
  1740. ret = rtw_chip_parameter_setup(rtwdev);
  1741. if (ret) {
  1742. rtw_err(rtwdev, "failed to setup chip parameters\n");
  1743. goto err_out;
  1744. }
  1745. ret = rtw_chip_efuse_info_setup(rtwdev);
  1746. if (ret) {
  1747. rtw_err(rtwdev, "failed to setup chip efuse info\n");
  1748. goto err_out;
  1749. }
  1750. ret = rtw_chip_board_info_setup(rtwdev);
  1751. if (ret) {
  1752. rtw_err(rtwdev, "failed to setup chip board info\n");
  1753. goto err_out;
  1754. }
  1755. return 0;
  1756. err_out:
  1757. return ret;
  1758. }
  1759. EXPORT_SYMBOL(rtw_chip_info_setup);
  1760. static void rtw_stats_init(struct rtw_dev *rtwdev)
  1761. {
  1762. struct rtw_traffic_stats *stats = &rtwdev->stats;
  1763. struct rtw_dm_info *dm_info = &rtwdev->dm_info;
  1764. int i;
  1765. ewma_tp_init(&stats->tx_ewma_tp);
  1766. ewma_tp_init(&stats->rx_ewma_tp);
  1767. for (i = 0; i < RTW_EVM_NUM; i++)
  1768. ewma_evm_init(&dm_info->ewma_evm[i]);
  1769. for (i = 0; i < RTW_SNR_NUM; i++)
  1770. ewma_snr_init(&dm_info->ewma_snr[i]);
  1771. }
  1772. int rtw_core_init(struct rtw_dev *rtwdev)
  1773. {
  1774. const struct rtw_chip_info *chip = rtwdev->chip;
  1775. struct rtw_coex *coex = &rtwdev->coex;
  1776. int ret;
  1777. INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
  1778. INIT_LIST_HEAD(&rtwdev->txqs);
  1779. timer_setup(&rtwdev->tx_report.purge_timer,
  1780. rtw_tx_report_purge_timer, 0);
  1781. rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
  1782. if (!rtwdev->tx_wq) {
  1783. rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n");
  1784. return -ENOMEM;
  1785. }
  1786. INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
  1787. INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
  1788. INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
  1789. INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
  1790. INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
  1791. INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
  1792. INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
  1793. INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
  1794. rtw_coex_bt_multi_link_remain_work);
  1795. INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
  1796. INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
  1797. INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
  1798. INIT_WORK(&rtwdev->ips_work, rtw_ips_work);
  1799. INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
  1800. INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work);
  1801. INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
  1802. skb_queue_head_init(&rtwdev->c2h_queue);
  1803. skb_queue_head_init(&rtwdev->coex.queue);
  1804. skb_queue_head_init(&rtwdev->tx_report.queue);
  1805. spin_lock_init(&rtwdev->txq_lock);
  1806. spin_lock_init(&rtwdev->tx_report.q_lock);
  1807. mutex_init(&rtwdev->mutex);
  1808. mutex_init(&rtwdev->hal.tx_power_mutex);
  1809. init_waitqueue_head(&rtwdev->coex.wait);
  1810. init_completion(&rtwdev->lps_leave_check);
  1811. init_completion(&rtwdev->fw_scan_density);
  1812. rtwdev->sec.total_cam_num = 32;
  1813. rtwdev->hal.current_channel = 1;
  1814. rtwdev->dm_info.fix_rate = U8_MAX;
  1815. rtw_stats_init(rtwdev);
  1816. /* default rx filter setting */
  1817. rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
  1818. BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
  1819. BIT_AB | BIT_AM | BIT_APM;
  1820. ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
  1821. if (ret) {
  1822. rtw_warn(rtwdev, "no firmware loaded\n");
  1823. goto out;
  1824. }
  1825. if (chip->wow_fw_name) {
  1826. ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
  1827. if (ret) {
  1828. rtw_warn(rtwdev, "no wow firmware loaded\n");
  1829. wait_for_completion(&rtwdev->fw.completion);
  1830. if (rtwdev->fw.firmware)
  1831. release_firmware(rtwdev->fw.firmware);
  1832. goto out;
  1833. }
  1834. }
  1835. return 0;
  1836. out:
  1837. destroy_workqueue(rtwdev->tx_wq);
  1838. return ret;
  1839. }
  1840. EXPORT_SYMBOL(rtw_core_init);
  1841. void rtw_core_deinit(struct rtw_dev *rtwdev)
  1842. {
  1843. struct rtw_fw_state *fw = &rtwdev->fw;
  1844. struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
  1845. struct rtw_rsvd_page *rsvd_pkt, *tmp;
  1846. unsigned long flags;
  1847. rtw_wait_firmware_completion(rtwdev);
  1848. if (fw->firmware)
  1849. release_firmware(fw->firmware);
  1850. if (wow_fw->firmware)
  1851. release_firmware(wow_fw->firmware);
  1852. destroy_workqueue(rtwdev->tx_wq);
  1853. timer_delete_sync(&rtwdev->tx_report.purge_timer);
  1854. spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
  1855. skb_queue_purge(&rtwdev->tx_report.queue);
  1856. spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
  1857. skb_queue_purge(&rtwdev->coex.queue);
  1858. skb_queue_purge(&rtwdev->c2h_queue);
  1859. list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
  1860. build_list) {
  1861. list_del(&rsvd_pkt->build_list);
  1862. kfree(rsvd_pkt);
  1863. }
  1864. mutex_destroy(&rtwdev->mutex);
  1865. mutex_destroy(&rtwdev->hal.tx_power_mutex);
  1866. }
  1867. EXPORT_SYMBOL(rtw_core_deinit);
  1868. int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
  1869. {
  1870. struct rtw_hal *hal = &rtwdev->hal;
  1871. int max_tx_headroom = 0;
  1872. int ret;
  1873. max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
  1874. if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
  1875. max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN;
  1876. hw->extra_tx_headroom = max_tx_headroom;
  1877. hw->queues = IEEE80211_NUM_ACS;
  1878. hw->txq_data_size = sizeof(struct rtw_txq);
  1879. hw->sta_data_size = sizeof(struct rtw_sta_info);
  1880. hw->vif_data_size = sizeof(struct rtw_vif);
  1881. ieee80211_hw_set(hw, SIGNAL_DBM);
  1882. ieee80211_hw_set(hw, RX_INCLUDES_FCS);
  1883. ieee80211_hw_set(hw, AMPDU_AGGREGATION);
  1884. ieee80211_hw_set(hw, MFP_CAPABLE);
  1885. ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
  1886. ieee80211_hw_set(hw, SUPPORTS_PS);
  1887. ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
  1888. ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
  1889. if (rtwdev->chip->amsdu_in_ampdu)
  1890. ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
  1891. ieee80211_hw_set(hw, HAS_RATE_CONTROL);
  1892. ieee80211_hw_set(hw, TX_AMSDU);
  1893. ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
  1894. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
  1895. BIT(NL80211_IFTYPE_AP) |
  1896. BIT(NL80211_IFTYPE_ADHOC);
  1897. hw->wiphy->available_antennas_tx = hal->antenna_tx;
  1898. hw->wiphy->available_antennas_rx = hal->antenna_rx;
  1899. hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
  1900. WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
  1901. hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
  1902. hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
  1903. hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev);
  1904. if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C) {
  1905. hw->wiphy->iface_combinations = rtw_iface_combs;
  1906. hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs);
  1907. }
  1908. wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
  1909. wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
  1910. wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
  1911. #ifdef CONFIG_PM
  1912. hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
  1913. hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
  1914. #endif
  1915. rtw_set_supported_band(hw, rtwdev->chip);
  1916. SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
  1917. hw->wiphy->sar_capa = &rtw_sar_capa;
  1918. ret = rtw_regd_init(rtwdev);
  1919. if (ret) {
  1920. rtw_err(rtwdev, "failed to init regd\n");
  1921. return ret;
  1922. }
  1923. rtw_led_init(rtwdev);
  1924. ret = ieee80211_register_hw(hw);
  1925. if (ret) {
  1926. rtw_err(rtwdev, "failed to register hw\n");
  1927. goto led_deinit;
  1928. }
  1929. ret = rtw_regd_hint(rtwdev);
  1930. if (ret) {
  1931. rtw_err(rtwdev, "failed to hint regd\n");
  1932. goto led_deinit;
  1933. }
  1934. rtw_debugfs_init(rtwdev);
  1935. rtwdev->bf_info.bfer_mu_cnt = 0;
  1936. rtwdev->bf_info.bfer_su_cnt = 0;
  1937. return 0;
  1938. led_deinit:
  1939. rtw_led_deinit(rtwdev);
  1940. return ret;
  1941. }
  1942. EXPORT_SYMBOL(rtw_register_hw);
  1943. void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
  1944. {
  1945. ieee80211_unregister_hw(hw);
  1946. rtw_debugfs_deinit(rtwdev);
  1947. rtw_led_deinit(rtwdev);
  1948. }
  1949. EXPORT_SYMBOL(rtw_unregister_hw);
  1950. static
  1951. void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1,
  1952. const struct rtw_hw_reg *reg2, u8 nbytes)
  1953. {
  1954. u8 i;
  1955. for (i = 0; i < nbytes; i++) {
  1956. u8 v1 = rtw_read8(rtwdev, reg1->addr + i);
  1957. u8 v2 = rtw_read8(rtwdev, reg2->addr + i);
  1958. rtw_write8(rtwdev, reg1->addr + i, v2);
  1959. rtw_write8(rtwdev, reg2->addr + i, v1);
  1960. }
  1961. }
  1962. static
  1963. void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1,
  1964. const struct rtw_hw_reg *reg2)
  1965. {
  1966. u32 v1, v2;
  1967. v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask);
  1968. v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask);
  1969. rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1);
  1970. rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2);
  1971. }
  1972. struct rtw_iter_port_switch_data {
  1973. struct rtw_dev *rtwdev;
  1974. struct rtw_vif *rtwvif_ap;
  1975. };
  1976. static void rtw_port_switch_iter(void *data, struct ieee80211_vif *vif)
  1977. {
  1978. struct rtw_iter_port_switch_data *iter_data = data;
  1979. struct rtw_dev *rtwdev = iter_data->rtwdev;
  1980. struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv;
  1981. struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap;
  1982. const struct rtw_hw_reg *reg1, *reg2;
  1983. if (rtwvif_target->port != RTW_PORT_0)
  1984. return;
  1985. rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n",
  1986. rtwvif_ap->port, rtwvif_target->port);
  1987. /* Leave LPS so the value swapped are not in PS mode */
  1988. rtw_leave_lps(rtwdev);
  1989. reg1 = &rtwvif_ap->conf->net_type;
  1990. reg2 = &rtwvif_target->conf->net_type;
  1991. rtw_swap_reg_mask(rtwdev, reg1, reg2);
  1992. reg1 = &rtwvif_ap->conf->mac_addr;
  1993. reg2 = &rtwvif_target->conf->mac_addr;
  1994. rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN);
  1995. reg1 = &rtwvif_ap->conf->bssid;
  1996. reg2 = &rtwvif_target->conf->bssid;
  1997. rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN);
  1998. reg1 = &rtwvif_ap->conf->bcn_ctrl;
  1999. reg2 = &rtwvif_target->conf->bcn_ctrl;
  2000. rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1);
  2001. swap(rtwvif_target->port, rtwvif_ap->port);
  2002. swap(rtwvif_target->conf, rtwvif_ap->conf);
  2003. rtw_fw_default_port(rtwdev, rtwvif_target);
  2004. }
  2005. void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif)
  2006. {
  2007. struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
  2008. struct rtw_iter_port_switch_data iter_data;
  2009. if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0)
  2010. return;
  2011. iter_data.rtwdev = rtwdev;
  2012. iter_data.rtwvif_ap = rtwvif;
  2013. rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data);
  2014. }
  2015. static void rtw_check_sta_active_iter(void *data, struct ieee80211_vif *vif)
  2016. {
  2017. struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
  2018. bool *active = data;
  2019. if (*active)
  2020. return;
  2021. if (vif->type != NL80211_IFTYPE_STATION)
  2022. return;
  2023. if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid))
  2024. *active = true;
  2025. }
  2026. bool rtw_core_check_sta_active(struct rtw_dev *rtwdev)
  2027. {
  2028. bool sta_active = false;
  2029. rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active);
  2030. return rtwdev->ap_active || sta_active;
  2031. }
  2032. void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable)
  2033. {
  2034. if (!rtwdev->ap_active)
  2035. return;
  2036. if (enable) {
  2037. rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
  2038. rtw_write8_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
  2039. } else {
  2040. rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
  2041. rtw_write8_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
  2042. }
  2043. }
  2044. void rtw_set_ampdu_factor(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
  2045. struct ieee80211_bss_conf *bss_conf)
  2046. {
  2047. const struct rtw_chip_ops *ops = rtwdev->chip->ops;
  2048. struct ieee80211_sta *sta;
  2049. u8 factor = 0xff;
  2050. if (!ops->set_ampdu_factor)
  2051. return;
  2052. rcu_read_lock();
  2053. sta = ieee80211_find_sta(vif, bss_conf->bssid);
  2054. if (!sta) {
  2055. rcu_read_unlock();
  2056. rtw_warn(rtwdev, "%s: failed to find station %pM\n",
  2057. __func__, bss_conf->bssid);
  2058. return;
  2059. }
  2060. if (sta->deflink.vht_cap.vht_supported)
  2061. factor = u32_get_bits(sta->deflink.vht_cap.cap,
  2062. IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
  2063. else if (sta->deflink.ht_cap.ht_supported)
  2064. factor = sta->deflink.ht_cap.ampdu_factor;
  2065. rcu_read_unlock();
  2066. if (factor != 0xff)
  2067. ops->set_ampdu_factor(rtwdev, factor);
  2068. }
  2069. MODULE_AUTHOR("Realtek Corporation");
  2070. MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
  2071. MODULE_LICENSE("Dual BSD/GPL");