main.c 69 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  21. u32 queues, bool drop);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
  57. bool sw_pending)
  58. {
  59. bool pending = false;
  60. spin_lock_bh(&txq->axq_lock);
  61. if (txq->axq_depth) {
  62. pending = true;
  63. goto out;
  64. }
  65. if (!sw_pending)
  66. goto out;
  67. if (txq->mac80211_qnum >= 0) {
  68. struct ath_acq *acq;
  69. acq = &sc->cur_chan->acq[txq->mac80211_qnum];
  70. if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
  71. pending = true;
  72. }
  73. out:
  74. spin_unlock_bh(&txq->axq_lock);
  75. return pending;
  76. }
  77. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  78. {
  79. unsigned long flags;
  80. bool ret;
  81. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  82. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  83. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  84. return ret;
  85. }
  86. void ath_ps_full_sleep(struct timer_list *t)
  87. {
  88. struct ath_softc *sc = timer_container_of(sc, t, sleep_timer);
  89. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  90. unsigned long flags;
  91. bool reset;
  92. spin_lock_irqsave(&common->cc_lock, flags);
  93. ath_hw_cycle_counters_update(common);
  94. spin_unlock_irqrestore(&common->cc_lock, flags);
  95. ath9k_hw_setrxabort(sc->sc_ah, 1);
  96. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  97. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  98. }
  99. void ath9k_ps_wakeup(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. unsigned long flags;
  103. enum ath9k_power_mode power_mode;
  104. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  105. if (++sc->ps_usecount != 1)
  106. goto unlock;
  107. timer_delete_sync(&sc->sleep_timer);
  108. power_mode = sc->sc_ah->power_mode;
  109. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  110. /*
  111. * While the hardware is asleep, the cycle counters contain no
  112. * useful data. Better clear them now so that they don't mess up
  113. * survey data results.
  114. */
  115. if (power_mode != ATH9K_PM_AWAKE) {
  116. spin_lock(&common->cc_lock);
  117. ath_hw_cycle_counters_update(common);
  118. memset(&common->cc, 0, sizeof(common->cc));
  119. spin_unlock(&common->cc_lock);
  120. }
  121. unlock:
  122. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  123. }
  124. void ath9k_ps_restore(struct ath_softc *sc)
  125. {
  126. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  127. enum ath9k_power_mode mode;
  128. unsigned long flags;
  129. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  130. if (--sc->ps_usecount != 0)
  131. goto unlock;
  132. if (sc->ps_idle) {
  133. mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
  134. goto unlock;
  135. }
  136. if (sc->ps_enabled &&
  137. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  138. PS_WAIT_FOR_CAB |
  139. PS_WAIT_FOR_PSPOLL_DATA |
  140. PS_WAIT_FOR_TX_ACK |
  141. PS_WAIT_FOR_ANI))) {
  142. mode = ATH9K_PM_NETWORK_SLEEP;
  143. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  144. ath9k_btcoex_stop_gen_timer(sc);
  145. } else {
  146. goto unlock;
  147. }
  148. spin_lock(&common->cc_lock);
  149. ath_hw_cycle_counters_update(common);
  150. spin_unlock(&common->cc_lock);
  151. ath9k_hw_setpower(sc->sc_ah, mode);
  152. unlock:
  153. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  154. }
  155. static void __ath_cancel_work(struct ath_softc *sc)
  156. {
  157. cancel_work_sync(&sc->paprd_work);
  158. cancel_delayed_work_sync(&sc->hw_check_work);
  159. cancel_delayed_work_sync(&sc->hw_pll_work);
  160. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  161. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  162. cancel_work_sync(&sc->mci_work);
  163. #endif
  164. }
  165. void ath_cancel_work(struct ath_softc *sc)
  166. {
  167. __ath_cancel_work(sc);
  168. cancel_work_sync(&sc->hw_reset_work);
  169. }
  170. void ath_restart_work(struct ath_softc *sc)
  171. {
  172. ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
  173. msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
  174. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
  175. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  176. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  177. ath_start_ani(sc);
  178. }
  179. static bool ath_prepare_reset(struct ath_softc *sc)
  180. {
  181. struct ath_hw *ah = sc->sc_ah;
  182. bool ret = true;
  183. ieee80211_stop_queues(sc->hw);
  184. ath_stop_ani(sc);
  185. ath9k_hw_disable_interrupts(ah);
  186. if (AR_SREV_9300_20_OR_LATER(ah)) {
  187. ret &= ath_stoprecv(sc);
  188. ret &= ath_drain_all_txq(sc);
  189. } else {
  190. ret &= ath_drain_all_txq(sc);
  191. ret &= ath_stoprecv(sc);
  192. }
  193. return ret;
  194. }
  195. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  196. {
  197. struct ath_hw *ah = sc->sc_ah;
  198. struct ath_common *common = ath9k_hw_common(ah);
  199. unsigned long flags;
  200. ath9k_calculate_summary_state(sc, sc->cur_chan);
  201. ath_startrecv(sc);
  202. ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
  203. sc->cur_chan->txpower,
  204. &sc->cur_chan->cur_txpower);
  205. clear_bit(ATH_OP_HW_RESET, &common->op_flags);
  206. if (!sc->cur_chan->offchannel && start) {
  207. /* restore per chanctx TSF timer */
  208. if (sc->cur_chan->tsf_val) {
  209. u32 offset;
  210. offset = ath9k_hw_get_tsf_offset(sc->cur_chan->tsf_ts, 0);
  211. ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
  212. }
  213. if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
  214. goto work;
  215. if (ah->opmode == NL80211_IFTYPE_STATION &&
  216. test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
  217. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  218. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  219. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  220. } else {
  221. ath9k_set_beacon(sc);
  222. }
  223. work:
  224. ath_restart_work(sc);
  225. ath_txq_schedule_all(sc);
  226. }
  227. sc->gtt_cnt = 0;
  228. ath9k_hw_set_interrupts(ah);
  229. ath9k_hw_enable_interrupts(ah);
  230. ieee80211_wake_queues(sc->hw);
  231. ath9k_p2p_ps_timer(sc);
  232. return true;
  233. }
  234. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
  235. {
  236. struct ath_hw *ah = sc->sc_ah;
  237. struct ath_common *common = ath9k_hw_common(ah);
  238. struct ath9k_hw_cal_data *caldata = NULL;
  239. bool fastcc = true;
  240. int r;
  241. __ath_cancel_work(sc);
  242. disable_irq(sc->irq);
  243. tasklet_disable(&sc->intr_tq);
  244. tasklet_disable(&sc->bcon_tasklet);
  245. spin_lock_bh(&sc->sc_pcu_lock);
  246. if (!sc->cur_chan->offchannel) {
  247. fastcc = false;
  248. caldata = &sc->cur_chan->caldata;
  249. }
  250. if (!hchan) {
  251. fastcc = false;
  252. hchan = ah->curchan;
  253. }
  254. if (!hchan) {
  255. fastcc = false;
  256. hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
  257. }
  258. if (!ath_prepare_reset(sc))
  259. fastcc = false;
  260. if (ath9k_is_chanctx_enabled())
  261. fastcc = false;
  262. spin_lock_bh(&sc->chan_lock);
  263. sc->cur_chandef = sc->cur_chan->chandef;
  264. spin_unlock_bh(&sc->chan_lock);
  265. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  266. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  267. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  268. if (r) {
  269. ath_err(common,
  270. "Unable to reset channel, reset status %d\n", r);
  271. ath9k_hw_enable_interrupts(ah);
  272. ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
  273. goto out;
  274. }
  275. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  276. sc->cur_chan->offchannel)
  277. ath9k_mci_set_txpower(sc, true, false);
  278. if (!ath_complete_reset(sc, true))
  279. r = -EIO;
  280. out:
  281. enable_irq(sc->irq);
  282. spin_unlock_bh(&sc->sc_pcu_lock);
  283. tasklet_enable(&sc->bcon_tasklet);
  284. tasklet_enable(&sc->intr_tq);
  285. return r;
  286. }
  287. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  288. struct ieee80211_vif *vif)
  289. {
  290. struct ath_node *an;
  291. an = (struct ath_node *)sta->drv_priv;
  292. an->sc = sc;
  293. an->sta = sta;
  294. an->vif = vif;
  295. memset(&an->key_idx, 0, sizeof(an->key_idx));
  296. ath_tx_node_init(sc, an);
  297. ath_dynack_node_init(sc->sc_ah, an);
  298. }
  299. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  300. {
  301. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  302. ath_tx_node_cleanup(sc, an);
  303. ath_dynack_node_deinit(sc->sc_ah, an);
  304. }
  305. void ath9k_tasklet(struct tasklet_struct *t)
  306. {
  307. struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
  308. struct ath_hw *ah = sc->sc_ah;
  309. struct ath_common *common = ath9k_hw_common(ah);
  310. enum ath_reset_type type;
  311. unsigned long flags;
  312. u32 status;
  313. u32 rxmask;
  314. spin_lock_irqsave(&sc->intr_lock, flags);
  315. status = sc->intrstatus;
  316. sc->intrstatus = 0;
  317. spin_unlock_irqrestore(&sc->intr_lock, flags);
  318. ath9k_ps_wakeup(sc);
  319. spin_lock(&sc->sc_pcu_lock);
  320. if (status & ATH9K_INT_FATAL) {
  321. type = RESET_TYPE_FATAL_INT;
  322. ath9k_queue_reset(sc, type);
  323. ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
  324. goto out;
  325. }
  326. if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
  327. (status & ATH9K_INT_BB_WATCHDOG)) {
  328. spin_lock_irqsave(&common->cc_lock, flags);
  329. ath_hw_cycle_counters_update(common);
  330. ar9003_hw_bb_watchdog_dbg_info(ah);
  331. spin_unlock_irqrestore(&common->cc_lock, flags);
  332. if (ar9003_hw_bb_watchdog_check(ah)) {
  333. type = RESET_TYPE_BB_WATCHDOG;
  334. ath9k_queue_reset(sc, type);
  335. ath_dbg(common, RESET,
  336. "BB_WATCHDOG: Skipping interrupts\n");
  337. goto out;
  338. }
  339. }
  340. if (status & ATH9K_INT_GTT) {
  341. sc->gtt_cnt++;
  342. if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
  343. type = RESET_TYPE_TX_GTT;
  344. ath9k_queue_reset(sc, type);
  345. ath_dbg(common, RESET,
  346. "GTT: Skipping interrupts\n");
  347. goto out;
  348. }
  349. }
  350. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  351. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  352. /*
  353. * TSF sync does not look correct; remain awake to sync with
  354. * the next Beacon.
  355. */
  356. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  357. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  358. }
  359. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  360. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  361. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  362. ATH9K_INT_RXORN);
  363. else
  364. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  365. if (status & rxmask) {
  366. /* Check for high priority Rx first */
  367. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  368. (status & ATH9K_INT_RXHP))
  369. ath_rx_tasklet(sc, 0, true);
  370. ath_rx_tasklet(sc, 0, false);
  371. sc->rx_active_count++;
  372. }
  373. if (status & ATH9K_INT_TX) {
  374. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  375. /*
  376. * For EDMA chips, TX completion is enabled for the
  377. * beacon queue, so if a beacon has been transmitted
  378. * successfully after a GTT interrupt, the GTT counter
  379. * gets reset to zero here.
  380. */
  381. sc->gtt_cnt = 0;
  382. ath_tx_edma_tasklet(sc);
  383. } else {
  384. ath_tx_tasklet(sc);
  385. }
  386. wake_up(&sc->tx_wait);
  387. }
  388. if (status & ATH9K_INT_GENTIMER)
  389. ath_gen_timer_isr(sc->sc_ah);
  390. ath9k_btcoex_handle_interrupt(sc, status);
  391. /* re-enable hardware interrupt */
  392. ath9k_hw_resume_interrupts(ah);
  393. out:
  394. spin_unlock(&sc->sc_pcu_lock);
  395. ath9k_ps_restore(sc);
  396. }
  397. irqreturn_t ath_isr(int irq, void *dev)
  398. {
  399. #define SCHED_INTR ( \
  400. ATH9K_INT_FATAL | \
  401. ATH9K_INT_BB_WATCHDOG | \
  402. ATH9K_INT_RXORN | \
  403. ATH9K_INT_RXEOL | \
  404. ATH9K_INT_RX | \
  405. ATH9K_INT_RXLP | \
  406. ATH9K_INT_RXHP | \
  407. ATH9K_INT_TX | \
  408. ATH9K_INT_BMISS | \
  409. ATH9K_INT_CST | \
  410. ATH9K_INT_GTT | \
  411. ATH9K_INT_TSFOOR | \
  412. ATH9K_INT_GENTIMER | \
  413. ATH9K_INT_MCI)
  414. struct ath_softc *sc = dev;
  415. struct ath_hw *ah = sc->sc_ah;
  416. struct ath_common *common = ath9k_hw_common(ah);
  417. enum ath9k_int status;
  418. u32 sync_cause = 0;
  419. bool sched = false;
  420. /*
  421. * The hardware is not ready/present, don't
  422. * touch anything. Note this can happen early
  423. * on if the IRQ is shared.
  424. */
  425. if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
  426. return IRQ_NONE;
  427. /* shared irq, not for us */
  428. if (!ath9k_hw_intrpend(ah))
  429. return IRQ_NONE;
  430. /*
  431. * Figure out the reason(s) for the interrupt. Note
  432. * that the hal returns a pseudo-ISR that may include
  433. * bits we haven't explicitly enabled so we mask the
  434. * value to insure we only process bits we requested.
  435. */
  436. ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
  437. ath9k_debug_sync_cause(sc, sync_cause);
  438. status &= ah->imask; /* discard unasked-for bits */
  439. if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
  440. ath9k_hw_kill_interrupts(sc->sc_ah);
  441. return IRQ_HANDLED;
  442. }
  443. /*
  444. * If there are no status bits set, then this interrupt was not
  445. * for me (should have been caught above).
  446. */
  447. if (!status)
  448. return IRQ_NONE;
  449. /* Cache the status */
  450. spin_lock(&sc->intr_lock);
  451. sc->intrstatus |= status;
  452. spin_unlock(&sc->intr_lock);
  453. if (status & SCHED_INTR)
  454. sched = true;
  455. /*
  456. * If a FATAL interrupt is received, we have to reset the chip
  457. * immediately.
  458. */
  459. if (status & ATH9K_INT_FATAL)
  460. goto chip_reset;
  461. if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
  462. (status & ATH9K_INT_BB_WATCHDOG))
  463. goto chip_reset;
  464. if (status & ATH9K_INT_SWBA)
  465. tasklet_schedule(&sc->bcon_tasklet);
  466. if (status & ATH9K_INT_TXURN)
  467. ath9k_hw_updatetxtriglevel(ah, true);
  468. if (status & ATH9K_INT_RXEOL) {
  469. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  470. ath9k_hw_set_interrupts(ah);
  471. }
  472. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  473. if (status & ATH9K_INT_TIM_TIMER) {
  474. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  475. goto chip_reset;
  476. /* Clear RxAbort bit so that we can
  477. * receive frames */
  478. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  479. spin_lock(&sc->sc_pm_lock);
  480. ath9k_hw_setrxabort(sc->sc_ah, 0);
  481. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  482. spin_unlock(&sc->sc_pm_lock);
  483. }
  484. chip_reset:
  485. ath_debug_stat_interrupt(sc, status);
  486. if (sched) {
  487. /* turn off every interrupt */
  488. ath9k_hw_kill_interrupts(ah);
  489. tasklet_schedule(&sc->intr_tq);
  490. }
  491. return IRQ_HANDLED;
  492. #undef SCHED_INTR
  493. }
  494. /*
  495. * This function is called when a HW reset cannot be deferred
  496. * and has to be immediate.
  497. */
  498. int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
  499. {
  500. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  501. int r;
  502. ath9k_hw_kill_interrupts(sc->sc_ah);
  503. set_bit(ATH_OP_HW_RESET, &common->op_flags);
  504. ath9k_ps_wakeup(sc);
  505. r = ath_reset_internal(sc, hchan);
  506. ath9k_ps_restore(sc);
  507. return r;
  508. }
  509. /*
  510. * When a HW reset can be deferred, it is added to the
  511. * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
  512. * queueing.
  513. */
  514. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  515. {
  516. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  517. #ifdef CONFIG_ATH9K_DEBUGFS
  518. RESET_STAT_INC(sc, type);
  519. #endif
  520. ath9k_hw_kill_interrupts(sc->sc_ah);
  521. set_bit(ATH_OP_HW_RESET, &common->op_flags);
  522. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  523. }
  524. void ath_reset_work(struct work_struct *work)
  525. {
  526. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  527. ath9k_ps_wakeup(sc);
  528. ath_reset_internal(sc, NULL);
  529. ath9k_ps_restore(sc);
  530. }
  531. /**********************/
  532. /* mac80211 callbacks */
  533. /**********************/
  534. static int ath9k_start(struct ieee80211_hw *hw)
  535. {
  536. struct ath_softc *sc = hw->priv;
  537. struct ath_hw *ah = sc->sc_ah;
  538. struct ath_common *common = ath9k_hw_common(ah);
  539. struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
  540. struct ath_chanctx *ctx = sc->cur_chan;
  541. struct ath9k_channel *init_channel;
  542. int r;
  543. ath_dbg(common, CONFIG,
  544. "Starting driver with initial channel: %d MHz\n",
  545. curchan->center_freq);
  546. ath9k_ps_wakeup(sc);
  547. mutex_lock(&sc->mutex);
  548. init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
  549. sc->cur_chandef = hw->conf.chandef;
  550. /* Reset SERDES registers */
  551. ath9k_hw_configpcipowersave(ah, false);
  552. /*
  553. * The basic interface to setting the hardware in a good
  554. * state is ``reset''. On return the hardware is known to
  555. * be powered up and with interrupts disabled. This must
  556. * be followed by initialization of the appropriate bits
  557. * and then setup of the interrupt mask.
  558. */
  559. spin_lock_bh(&sc->sc_pcu_lock);
  560. atomic_set(&ah->intr_ref_cnt, -1);
  561. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  562. if (r) {
  563. ath_err(common,
  564. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  565. r, curchan->center_freq);
  566. ah->reset_power_on = false;
  567. }
  568. /* Setup our intr mask. */
  569. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  570. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  571. ATH9K_INT_GLOBAL;
  572. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  573. ah->imask |= ATH9K_INT_RXHP |
  574. ATH9K_INT_RXLP;
  575. else
  576. ah->imask |= ATH9K_INT_RX;
  577. if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
  578. ah->imask |= ATH9K_INT_BB_WATCHDOG;
  579. /*
  580. * Enable GTT interrupts only for AR9003/AR9004 chips
  581. * for now.
  582. */
  583. if (AR_SREV_9300_20_OR_LATER(ah))
  584. ah->imask |= ATH9K_INT_GTT;
  585. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  586. ah->imask |= ATH9K_INT_CST;
  587. ath_mci_enable(sc);
  588. clear_bit(ATH_OP_INVALID, &common->op_flags);
  589. sc->sc_ah->is_monitoring = false;
  590. if (!ath_complete_reset(sc, false))
  591. ah->reset_power_on = false;
  592. if (ah->led_pin >= 0) {
  593. ath9k_hw_set_gpio(ah, ah->led_pin,
  594. (ah->config.led_active_high) ? 1 : 0);
  595. ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
  596. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  597. }
  598. /*
  599. * Reset key cache to sane defaults (all entries cleared) instead of
  600. * semi-random values after suspend/resume.
  601. */
  602. ath9k_cmn_init_crypto(sc->sc_ah);
  603. ath9k_hw_reset_tsf(ah);
  604. spin_unlock_bh(&sc->sc_pcu_lock);
  605. ath9k_rng_start(sc);
  606. mutex_unlock(&sc->mutex);
  607. ath9k_ps_restore(sc);
  608. return 0;
  609. }
  610. static void ath9k_tx(struct ieee80211_hw *hw,
  611. struct ieee80211_tx_control *control,
  612. struct sk_buff *skb)
  613. {
  614. struct ath_softc *sc = hw->priv;
  615. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  616. struct ath_tx_control txctl;
  617. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  618. unsigned long flags;
  619. if (sc->ps_enabled) {
  620. /*
  621. * mac80211 does not set PM field for normal data frames, so we
  622. * need to update that based on the current PS mode.
  623. */
  624. if (ieee80211_is_data(hdr->frame_control) &&
  625. !ieee80211_is_nullfunc(hdr->frame_control) &&
  626. !ieee80211_has_pm(hdr->frame_control)) {
  627. ath_dbg(common, PS,
  628. "Add PM=1 for a TX frame while in PS mode\n");
  629. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  630. }
  631. }
  632. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  633. /*
  634. * We are using PS-Poll and mac80211 can request TX while in
  635. * power save mode. Need to wake up hardware for the TX to be
  636. * completed and if needed, also for RX of buffered frames.
  637. */
  638. ath9k_ps_wakeup(sc);
  639. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  640. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  641. ath9k_hw_setrxabort(sc->sc_ah, 0);
  642. if (ieee80211_is_pspoll(hdr->frame_control)) {
  643. ath_dbg(common, PS,
  644. "Sending PS-Poll to pick a buffered frame\n");
  645. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  646. } else {
  647. ath_dbg(common, PS, "Wake up to complete TX\n");
  648. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  649. }
  650. /*
  651. * The actual restore operation will happen only after
  652. * the ps_flags bit is cleared. We are just dropping
  653. * the ps_usecount here.
  654. */
  655. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  656. ath9k_ps_restore(sc);
  657. }
  658. /*
  659. * Cannot tx while the hardware is in full sleep, it first needs a full
  660. * chip reset to recover from that
  661. */
  662. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  663. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  664. goto exit;
  665. }
  666. memset(&txctl, 0, sizeof(struct ath_tx_control));
  667. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  668. txctl.sta = control->sta;
  669. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  670. if (ath_tx_start(hw, skb, &txctl) != 0) {
  671. ath_dbg(common, XMIT, "TX failed\n");
  672. TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
  673. goto exit;
  674. }
  675. return;
  676. exit:
  677. ieee80211_free_txskb(hw, skb);
  678. }
  679. static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
  680. {
  681. struct ath_buf *bf;
  682. struct ieee80211_tx_info *txinfo;
  683. struct ath_frame_info *fi;
  684. list_for_each_entry(bf, txq_list, list) {
  685. if (bf->bf_state.stale || !bf->bf_mpdu)
  686. continue;
  687. txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
  688. fi = (struct ath_frame_info *)&txinfo->status.status_driver_data[0];
  689. if (fi->keyix == keyix)
  690. return true;
  691. }
  692. return false;
  693. }
  694. static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
  695. {
  696. struct ath_hw *ah = sc->sc_ah;
  697. int i, j;
  698. struct ath_txq *txq;
  699. bool key_in_use = false;
  700. for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
  701. if (!ATH_TXQ_SETUP(sc, i))
  702. continue;
  703. txq = &sc->tx.txq[i];
  704. if (!txq->axq_depth)
  705. continue;
  706. if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
  707. continue;
  708. ath_txq_lock(sc, txq);
  709. key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
  710. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  711. int idx = txq->txq_tailidx;
  712. for (j = 0; !key_in_use &&
  713. !list_empty(&txq->txq_fifo[idx]) &&
  714. j < ATH_TXFIFO_DEPTH; j++) {
  715. key_in_use = ath9k_txq_list_has_key(
  716. &txq->txq_fifo[idx], keyix);
  717. INCR(idx, ATH_TXFIFO_DEPTH);
  718. }
  719. }
  720. ath_txq_unlock(sc, txq);
  721. }
  722. return key_in_use;
  723. }
  724. static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
  725. {
  726. struct ath_hw *ah = sc->sc_ah;
  727. struct ath_common *common = ath9k_hw_common(ah);
  728. if (!test_bit(keyix, ah->pending_del_keymap) ||
  729. ath9k_txq_has_key(sc, keyix))
  730. return;
  731. /* No more TXQ frames point to this key cache entry, so delete it. */
  732. clear_bit(keyix, ah->pending_del_keymap);
  733. ath_key_delete(common, keyix);
  734. }
  735. static void ath9k_stop(struct ieee80211_hw *hw, bool suspend)
  736. {
  737. struct ath_softc *sc = hw->priv;
  738. struct ath_hw *ah = sc->sc_ah;
  739. struct ath_common *common = ath9k_hw_common(ah);
  740. bool prev_idle;
  741. int i;
  742. ath9k_deinit_channel_context(sc);
  743. mutex_lock(&sc->mutex);
  744. ath9k_rng_stop(sc);
  745. ath_cancel_work(sc);
  746. if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
  747. ath_dbg(common, ANY, "Device not present\n");
  748. mutex_unlock(&sc->mutex);
  749. return;
  750. }
  751. /* Ensure HW is awake when we try to shut it down. */
  752. ath9k_ps_wakeup(sc);
  753. spin_lock_bh(&sc->sc_pcu_lock);
  754. /* prevent tasklets to enable interrupts once we disable them */
  755. ah->imask &= ~ATH9K_INT_GLOBAL;
  756. /* make sure h/w will not generate any interrupt
  757. * before setting the invalid flag. */
  758. ath9k_hw_disable_interrupts(ah);
  759. spin_unlock_bh(&sc->sc_pcu_lock);
  760. /* we can now sync irq and kill any running tasklets, since we already
  761. * disabled interrupts and not holding a spin lock */
  762. synchronize_irq(sc->irq);
  763. tasklet_kill(&sc->intr_tq);
  764. tasklet_kill(&sc->bcon_tasklet);
  765. prev_idle = sc->ps_idle;
  766. sc->ps_idle = true;
  767. spin_lock_bh(&sc->sc_pcu_lock);
  768. if (ah->led_pin >= 0) {
  769. ath9k_hw_set_gpio(ah, ah->led_pin,
  770. (ah->config.led_active_high) ? 0 : 1);
  771. ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
  772. }
  773. ath_prepare_reset(sc);
  774. if (sc->rx.frag) {
  775. dev_kfree_skb_any(sc->rx.frag);
  776. sc->rx.frag = NULL;
  777. }
  778. if (!ah->curchan)
  779. ah->curchan = ath9k_cmn_get_channel(hw, ah,
  780. &sc->cur_chan->chandef);
  781. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  782. set_bit(ATH_OP_INVALID, &common->op_flags);
  783. ath9k_hw_phy_disable(ah);
  784. ath9k_hw_configpcipowersave(ah, true);
  785. spin_unlock_bh(&sc->sc_pcu_lock);
  786. for (i = 0; i < ATH_KEYMAX; i++)
  787. ath9k_pending_key_del(sc, i);
  788. /* Clear key cache entries explicitly to get rid of any potentially
  789. * remaining keys.
  790. */
  791. ath9k_cmn_init_crypto(sc->sc_ah);
  792. ath9k_ps_restore(sc);
  793. sc->ps_idle = prev_idle;
  794. mutex_unlock(&sc->mutex);
  795. ath_dbg(common, CONFIG, "Driver halt\n");
  796. }
  797. static bool ath9k_uses_beacons(int type)
  798. {
  799. switch (type) {
  800. case NL80211_IFTYPE_AP:
  801. case NL80211_IFTYPE_ADHOC:
  802. case NL80211_IFTYPE_MESH_POINT:
  803. return true;
  804. default:
  805. return false;
  806. }
  807. }
  808. static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
  809. struct ieee80211_vif *vif)
  810. {
  811. /* Use the first (configured) interface, but preferring AP interfaces. */
  812. if (!iter_data->primary_beacon_vif) {
  813. iter_data->primary_beacon_vif = vif;
  814. } else {
  815. if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
  816. vif->type == NL80211_IFTYPE_AP)
  817. iter_data->primary_beacon_vif = vif;
  818. }
  819. iter_data->beacons = true;
  820. iter_data->nbcnvifs += 1;
  821. }
  822. static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
  823. u8 *mac, struct ieee80211_vif *vif)
  824. {
  825. struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
  826. int i;
  827. if (iter_data->has_hw_macaddr) {
  828. for (i = 0; i < ETH_ALEN; i++)
  829. iter_data->mask[i] &=
  830. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  831. } else {
  832. memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
  833. iter_data->has_hw_macaddr = true;
  834. }
  835. if (!vif->bss_conf.use_short_slot)
  836. iter_data->slottime = 20;
  837. switch (vif->type) {
  838. case NL80211_IFTYPE_AP:
  839. iter_data->naps++;
  840. if (vif->bss_conf.enable_beacon)
  841. ath9k_vif_iter_set_beacon(iter_data, vif);
  842. break;
  843. case NL80211_IFTYPE_STATION:
  844. iter_data->nstations++;
  845. if (avp->assoc && !iter_data->primary_sta)
  846. iter_data->primary_sta = vif;
  847. break;
  848. case NL80211_IFTYPE_OCB:
  849. iter_data->nocbs++;
  850. break;
  851. case NL80211_IFTYPE_ADHOC:
  852. iter_data->nadhocs++;
  853. if (vif->bss_conf.enable_beacon)
  854. ath9k_vif_iter_set_beacon(iter_data, vif);
  855. break;
  856. case NL80211_IFTYPE_MESH_POINT:
  857. iter_data->nmeshes++;
  858. if (vif->bss_conf.enable_beacon)
  859. ath9k_vif_iter_set_beacon(iter_data, vif);
  860. break;
  861. default:
  862. break;
  863. }
  864. }
  865. static void ath9k_update_bssid_mask(struct ath_softc *sc,
  866. struct ath_chanctx *ctx,
  867. struct ath9k_vif_iter_data *iter_data)
  868. {
  869. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  870. struct ath_vif *avp;
  871. int i;
  872. if (!ath9k_is_chanctx_enabled())
  873. return;
  874. list_for_each_entry(avp, &ctx->vifs, list) {
  875. if (ctx->nvifs_assigned != 1)
  876. continue;
  877. if (!iter_data->has_hw_macaddr)
  878. continue;
  879. ether_addr_copy(common->curbssid, avp->bssid);
  880. /* perm_addr will be used as the p2p device address. */
  881. for (i = 0; i < ETH_ALEN; i++)
  882. iter_data->mask[i] &=
  883. ~(iter_data->hw_macaddr[i] ^
  884. sc->hw->wiphy->perm_addr[i]);
  885. }
  886. }
  887. /* Called with sc->mutex held. */
  888. void ath9k_calculate_iter_data(struct ath_softc *sc,
  889. struct ath_chanctx *ctx,
  890. struct ath9k_vif_iter_data *iter_data)
  891. {
  892. struct ath_vif *avp;
  893. /*
  894. * The hardware will use primary station addr together with the
  895. * BSSID mask when matching addresses.
  896. */
  897. memset(iter_data, 0, sizeof(*iter_data));
  898. eth_broadcast_addr(iter_data->mask);
  899. iter_data->slottime = 9;
  900. list_for_each_entry(avp, &ctx->vifs, list)
  901. ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
  902. ath9k_update_bssid_mask(sc, ctx, iter_data);
  903. }
  904. static void ath9k_set_assoc_state(struct ath_softc *sc,
  905. struct ieee80211_vif *vif, bool changed)
  906. {
  907. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  908. struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
  909. unsigned long flags;
  910. set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  911. ether_addr_copy(common->curbssid, avp->bssid);
  912. common->curaid = avp->aid;
  913. ath9k_hw_write_associd(sc->sc_ah);
  914. if (changed) {
  915. common->last_rssi = ATH_RSSI_DUMMY_MARKER;
  916. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  917. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  918. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  919. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  920. }
  921. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  922. ath9k_mci_update_wlan_channels(sc, false);
  923. ath_dbg(common, CONFIG,
  924. "Primary Station interface: %pM, BSSID: %pM\n",
  925. vif->addr, common->curbssid);
  926. }
  927. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  928. static void ath9k_set_offchannel_state(struct ath_softc *sc)
  929. {
  930. struct ath_hw *ah = sc->sc_ah;
  931. struct ath_common *common = ath9k_hw_common(ah);
  932. struct ieee80211_vif *vif = NULL;
  933. ath9k_ps_wakeup(sc);
  934. if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
  935. vif = sc->offchannel.scan_vif;
  936. else
  937. vif = sc->offchannel.roc_vif;
  938. if (WARN_ON(!vif))
  939. goto exit;
  940. eth_zero_addr(common->curbssid);
  941. eth_broadcast_addr(common->bssidmask);
  942. memcpy(common->macaddr, vif->addr, ETH_ALEN);
  943. common->curaid = 0;
  944. ah->opmode = vif->type;
  945. ah->imask &= ~ATH9K_INT_SWBA;
  946. ah->imask &= ~ATH9K_INT_TSFOOR;
  947. ah->slottime = 9;
  948. ath_hw_setbssidmask(common);
  949. ath9k_hw_setopmode(ah);
  950. ath9k_hw_write_associd(sc->sc_ah);
  951. ath9k_hw_set_interrupts(ah);
  952. ath9k_hw_init_global_settings(ah);
  953. exit:
  954. ath9k_ps_restore(sc);
  955. }
  956. #endif
  957. /* Called with sc->mutex held. */
  958. void ath9k_calculate_summary_state(struct ath_softc *sc,
  959. struct ath_chanctx *ctx)
  960. {
  961. struct ath_hw *ah = sc->sc_ah;
  962. struct ath_common *common = ath9k_hw_common(ah);
  963. struct ath9k_vif_iter_data iter_data;
  964. ath_chanctx_check_active(sc, ctx);
  965. if (ctx != sc->cur_chan)
  966. return;
  967. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  968. if (ctx == &sc->offchannel.chan)
  969. return ath9k_set_offchannel_state(sc);
  970. #endif
  971. ath9k_ps_wakeup(sc);
  972. ath9k_calculate_iter_data(sc, ctx, &iter_data);
  973. if (iter_data.has_hw_macaddr)
  974. memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
  975. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  976. ath_hw_setbssidmask(common);
  977. if (iter_data.naps > 0) {
  978. ath9k_hw_set_tsfadjust(ah, true);
  979. ah->opmode = NL80211_IFTYPE_AP;
  980. } else {
  981. ath9k_hw_set_tsfadjust(ah, false);
  982. if (iter_data.beacons)
  983. ath9k_beacon_ensure_primary_slot(sc);
  984. if (iter_data.nmeshes)
  985. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  986. else if (iter_data.nocbs)
  987. ah->opmode = NL80211_IFTYPE_OCB;
  988. else if (iter_data.nadhocs)
  989. ah->opmode = NL80211_IFTYPE_ADHOC;
  990. else
  991. ah->opmode = NL80211_IFTYPE_STATION;
  992. }
  993. ath9k_hw_setopmode(ah);
  994. ctx->switch_after_beacon = false;
  995. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  996. ah->imask |= ATH9K_INT_TSFOOR;
  997. else {
  998. ah->imask &= ~ATH9K_INT_TSFOOR;
  999. if (iter_data.naps == 1 && iter_data.beacons)
  1000. ctx->switch_after_beacon = true;
  1001. }
  1002. if (ah->opmode == NL80211_IFTYPE_STATION) {
  1003. bool changed = (iter_data.primary_sta != ctx->primary_sta);
  1004. if (iter_data.primary_sta) {
  1005. iter_data.primary_beacon_vif = iter_data.primary_sta;
  1006. iter_data.beacons = true;
  1007. ath9k_set_assoc_state(sc, iter_data.primary_sta,
  1008. changed);
  1009. ctx->primary_sta = iter_data.primary_sta;
  1010. } else {
  1011. ctx->primary_sta = NULL;
  1012. eth_zero_addr(common->curbssid);
  1013. common->curaid = 0;
  1014. ath9k_hw_write_associd(sc->sc_ah);
  1015. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1016. ath9k_mci_update_wlan_channels(sc, true);
  1017. }
  1018. }
  1019. sc->nbcnvifs = iter_data.nbcnvifs;
  1020. ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
  1021. iter_data.beacons);
  1022. ath9k_hw_set_interrupts(ah);
  1023. if (ah->slottime != iter_data.slottime) {
  1024. ah->slottime = iter_data.slottime;
  1025. ath9k_hw_init_global_settings(ah);
  1026. }
  1027. if (iter_data.primary_sta)
  1028. set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  1029. else
  1030. clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  1031. ath_dbg(common, CONFIG,
  1032. "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
  1033. common->macaddr, common->curbssid, common->bssidmask);
  1034. ath9k_ps_restore(sc);
  1035. }
  1036. static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1037. {
  1038. int *power = data;
  1039. if (vif->bss_conf.txpower == INT_MIN)
  1040. return;
  1041. if (*power < vif->bss_conf.txpower)
  1042. *power = vif->bss_conf.txpower;
  1043. }
  1044. /* Called with sc->mutex held. */
  1045. void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
  1046. {
  1047. int power;
  1048. struct ath_hw *ah = sc->sc_ah;
  1049. struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
  1050. ath9k_ps_wakeup(sc);
  1051. if (ah->tpc_enabled) {
  1052. power = (vif) ? vif->bss_conf.txpower : -1;
  1053. ieee80211_iterate_active_interfaces_atomic(
  1054. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1055. ath9k_tpc_vif_iter, &power);
  1056. if (power == -1)
  1057. power = sc->hw->conf.power_level;
  1058. } else {
  1059. power = sc->hw->conf.power_level;
  1060. }
  1061. sc->cur_chan->txpower = 2 * power;
  1062. ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
  1063. sc->cur_chan->cur_txpower = reg->max_power_level;
  1064. ath9k_ps_restore(sc);
  1065. }
  1066. static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
  1067. struct ieee80211_vif *vif)
  1068. {
  1069. int i;
  1070. if (!ath9k_is_chanctx_enabled())
  1071. return;
  1072. for (i = 0; i < IEEE80211_NUM_ACS; i++)
  1073. vif->hw_queue[i] = i;
  1074. if (vif->type == NL80211_IFTYPE_AP ||
  1075. vif->type == NL80211_IFTYPE_MESH_POINT)
  1076. vif->cab_queue = hw->queues - 2;
  1077. else
  1078. vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
  1079. }
  1080. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1081. struct ieee80211_vif *vif)
  1082. {
  1083. struct ath_softc *sc = hw->priv;
  1084. struct ath_hw *ah = sc->sc_ah;
  1085. struct ath_common *common = ath9k_hw_common(ah);
  1086. struct ath_vif *avp = (void *)vif->drv_priv;
  1087. struct ath_node *an = &avp->mcast_node;
  1088. mutex_lock(&sc->mutex);
  1089. if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
  1090. if (sc->cur_chan->nvifs >= 1) {
  1091. mutex_unlock(&sc->mutex);
  1092. return -EOPNOTSUPP;
  1093. }
  1094. sc->tx99_vif = vif;
  1095. }
  1096. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  1097. sc->cur_chan->nvifs++;
  1098. if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
  1099. vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
  1100. if (ath9k_uses_beacons(vif->type))
  1101. ath9k_beacon_assign_slot(sc, vif);
  1102. avp->vif = vif;
  1103. if (!ath9k_is_chanctx_enabled()) {
  1104. avp->chanctx = sc->cur_chan;
  1105. list_add_tail(&avp->list, &avp->chanctx->vifs);
  1106. }
  1107. ath9k_calculate_summary_state(sc, avp->chanctx);
  1108. ath9k_assign_hw_queues(hw, vif);
  1109. ath9k_set_txpower(sc, vif);
  1110. an->sc = sc;
  1111. an->sta = NULL;
  1112. an->vif = vif;
  1113. an->no_ps_filter = true;
  1114. ath_tx_node_init(sc, an);
  1115. mutex_unlock(&sc->mutex);
  1116. return 0;
  1117. }
  1118. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1119. struct ieee80211_vif *vif,
  1120. enum nl80211_iftype new_type,
  1121. bool p2p)
  1122. {
  1123. struct ath_softc *sc = hw->priv;
  1124. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1125. struct ath_vif *avp = (void *)vif->drv_priv;
  1126. mutex_lock(&sc->mutex);
  1127. if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
  1128. mutex_unlock(&sc->mutex);
  1129. return -EOPNOTSUPP;
  1130. }
  1131. ath_dbg(common, CONFIG, "Change Interface\n");
  1132. if (ath9k_uses_beacons(vif->type))
  1133. ath9k_beacon_remove_slot(sc, vif);
  1134. vif->type = new_type;
  1135. vif->p2p = p2p;
  1136. if (ath9k_uses_beacons(vif->type))
  1137. ath9k_beacon_assign_slot(sc, vif);
  1138. ath9k_assign_hw_queues(hw, vif);
  1139. ath9k_calculate_summary_state(sc, avp->chanctx);
  1140. ath9k_set_txpower(sc, vif);
  1141. mutex_unlock(&sc->mutex);
  1142. return 0;
  1143. }
  1144. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1145. struct ieee80211_vif *vif)
  1146. {
  1147. struct ath_softc *sc = hw->priv;
  1148. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1149. struct ath_vif *avp = (void *)vif->drv_priv;
  1150. ath_dbg(common, CONFIG, "Detach Interface\n");
  1151. mutex_lock(&sc->mutex);
  1152. ath9k_p2p_remove_vif(sc, vif);
  1153. sc->cur_chan->nvifs--;
  1154. sc->tx99_vif = NULL;
  1155. if (!ath9k_is_chanctx_enabled())
  1156. list_del(&avp->list);
  1157. if (ath9k_uses_beacons(vif->type))
  1158. ath9k_beacon_remove_slot(sc, vif);
  1159. ath_tx_node_cleanup(sc, &avp->mcast_node);
  1160. ath9k_calculate_summary_state(sc, avp->chanctx);
  1161. ath9k_set_txpower(sc, NULL);
  1162. mutex_unlock(&sc->mutex);
  1163. }
  1164. static void ath9k_enable_ps(struct ath_softc *sc)
  1165. {
  1166. struct ath_hw *ah = sc->sc_ah;
  1167. struct ath_common *common = ath9k_hw_common(ah);
  1168. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1169. return;
  1170. sc->ps_enabled = true;
  1171. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1172. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1173. ah->imask |= ATH9K_INT_TIM_TIMER;
  1174. ath9k_hw_set_interrupts(ah);
  1175. }
  1176. ath9k_hw_setrxabort(ah, 1);
  1177. }
  1178. ath_dbg(common, PS, "PowerSave enabled\n");
  1179. }
  1180. static void ath9k_disable_ps(struct ath_softc *sc)
  1181. {
  1182. struct ath_hw *ah = sc->sc_ah;
  1183. struct ath_common *common = ath9k_hw_common(ah);
  1184. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1185. return;
  1186. sc->ps_enabled = false;
  1187. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1188. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1189. ath9k_hw_setrxabort(ah, 0);
  1190. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1191. PS_WAIT_FOR_CAB |
  1192. PS_WAIT_FOR_PSPOLL_DATA |
  1193. PS_WAIT_FOR_TX_ACK);
  1194. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1195. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1196. ath9k_hw_set_interrupts(ah);
  1197. }
  1198. }
  1199. ath_dbg(common, PS, "PowerSave disabled\n");
  1200. }
  1201. static int ath9k_config(struct ieee80211_hw *hw, int radio_idx, u32 changed)
  1202. {
  1203. struct ath_softc *sc = hw->priv;
  1204. struct ath_hw *ah = sc->sc_ah;
  1205. struct ath_common *common = ath9k_hw_common(ah);
  1206. struct ieee80211_conf *conf = &hw->conf;
  1207. struct ath_chanctx *ctx = sc->cur_chan;
  1208. ath9k_ps_wakeup(sc);
  1209. mutex_lock(&sc->mutex);
  1210. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1211. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1212. if (sc->ps_idle) {
  1213. ath_cancel_work(sc);
  1214. ath9k_stop_btcoex(sc);
  1215. } else {
  1216. ath9k_start_btcoex(sc);
  1217. /*
  1218. * The chip needs a reset to properly wake up from
  1219. * full sleep
  1220. */
  1221. ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
  1222. }
  1223. }
  1224. /*
  1225. * We just prepare to enable PS. We have to wait until our AP has
  1226. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1227. * those ACKs and end up retransmitting the same null data frames.
  1228. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1229. */
  1230. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1231. unsigned long flags;
  1232. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1233. if (conf->flags & IEEE80211_CONF_PS)
  1234. ath9k_enable_ps(sc);
  1235. else
  1236. ath9k_disable_ps(sc);
  1237. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1238. }
  1239. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1240. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1241. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  1242. sc->sc_ah->is_monitoring = true;
  1243. } else {
  1244. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  1245. sc->sc_ah->is_monitoring = false;
  1246. }
  1247. }
  1248. if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  1249. ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
  1250. ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
  1251. }
  1252. if (changed & IEEE80211_CONF_CHANGE_POWER)
  1253. ath9k_set_txpower(sc, NULL);
  1254. mutex_unlock(&sc->mutex);
  1255. ath9k_ps_restore(sc);
  1256. return 0;
  1257. }
  1258. #define SUPPORTED_FILTERS \
  1259. (FIF_ALLMULTI | \
  1260. FIF_CONTROL | \
  1261. FIF_PSPOLL | \
  1262. FIF_OTHER_BSS | \
  1263. FIF_BCN_PRBRESP_PROMISC | \
  1264. FIF_PROBE_REQ | \
  1265. FIF_MCAST_ACTION | \
  1266. FIF_FCSFAIL)
  1267. /* FIXME: sc->sc_full_reset ? */
  1268. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1269. unsigned int changed_flags,
  1270. unsigned int *total_flags,
  1271. u64 multicast)
  1272. {
  1273. struct ath_softc *sc = hw->priv;
  1274. struct ath_chanctx *ctx;
  1275. u32 rfilt;
  1276. *total_flags &= SUPPORTED_FILTERS;
  1277. spin_lock_bh(&sc->chan_lock);
  1278. ath_for_each_chanctx(sc, ctx)
  1279. ctx->rxfilter = *total_flags;
  1280. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  1281. sc->offchannel.chan.rxfilter = *total_flags;
  1282. #endif
  1283. spin_unlock_bh(&sc->chan_lock);
  1284. ath9k_ps_wakeup(sc);
  1285. rfilt = ath_calcrxfilter(sc);
  1286. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1287. ath9k_ps_restore(sc);
  1288. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1289. rfilt);
  1290. }
  1291. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1292. struct ieee80211_vif *vif,
  1293. struct ieee80211_sta *sta)
  1294. {
  1295. struct ath_softc *sc = hw->priv;
  1296. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1297. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1298. struct ieee80211_key_conf ps_key = { };
  1299. int key;
  1300. ath_node_attach(sc, sta, vif);
  1301. if (vif->type != NL80211_IFTYPE_AP &&
  1302. vif->type != NL80211_IFTYPE_AP_VLAN)
  1303. return 0;
  1304. key = ath_key_config(common, vif, sta, &ps_key);
  1305. if (key > 0) {
  1306. an->ps_key = key;
  1307. an->key_idx[0] = key;
  1308. }
  1309. return 0;
  1310. }
  1311. static void ath9k_del_ps_key(struct ath_softc *sc,
  1312. struct ieee80211_vif *vif,
  1313. struct ieee80211_sta *sta)
  1314. {
  1315. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1316. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1317. if (!an->ps_key)
  1318. return;
  1319. ath_key_delete(common, an->ps_key);
  1320. an->ps_key = 0;
  1321. an->key_idx[0] = 0;
  1322. }
  1323. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1324. struct ieee80211_vif *vif,
  1325. struct ieee80211_sta *sta)
  1326. {
  1327. struct ath_softc *sc = hw->priv;
  1328. ath9k_del_ps_key(sc, vif, sta);
  1329. ath_node_detach(sc, sta);
  1330. return 0;
  1331. }
  1332. static int ath9k_sta_state(struct ieee80211_hw *hw,
  1333. struct ieee80211_vif *vif,
  1334. struct ieee80211_sta *sta,
  1335. enum ieee80211_sta_state old_state,
  1336. enum ieee80211_sta_state new_state)
  1337. {
  1338. struct ath_softc *sc = hw->priv;
  1339. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1340. int ret = 0;
  1341. if (old_state == IEEE80211_STA_NOTEXIST &&
  1342. new_state == IEEE80211_STA_NONE) {
  1343. ret = ath9k_sta_add(hw, vif, sta);
  1344. ath_dbg(common, CONFIG,
  1345. "Add station: %pM\n", sta->addr);
  1346. } else if (old_state == IEEE80211_STA_NONE &&
  1347. new_state == IEEE80211_STA_NOTEXIST) {
  1348. ret = ath9k_sta_remove(hw, vif, sta);
  1349. ath_dbg(common, CONFIG,
  1350. "Remove station: %pM\n", sta->addr);
  1351. }
  1352. if (ath9k_is_chanctx_enabled()) {
  1353. if (vif->type == NL80211_IFTYPE_STATION) {
  1354. if (old_state == IEEE80211_STA_ASSOC &&
  1355. new_state == IEEE80211_STA_AUTHORIZED)
  1356. ath_chanctx_event(sc, vif,
  1357. ATH_CHANCTX_EVENT_AUTHORIZED);
  1358. }
  1359. }
  1360. return ret;
  1361. }
  1362. static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
  1363. struct ath_node *an,
  1364. bool set)
  1365. {
  1366. int i;
  1367. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1368. if (!an->key_idx[i])
  1369. continue;
  1370. ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
  1371. }
  1372. }
  1373. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1374. struct ieee80211_vif *vif,
  1375. enum sta_notify_cmd cmd,
  1376. struct ieee80211_sta *sta)
  1377. {
  1378. struct ath_softc *sc = hw->priv;
  1379. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1380. switch (cmd) {
  1381. case STA_NOTIFY_SLEEP:
  1382. an->sleeping = true;
  1383. ath_tx_aggr_sleep(sta, sc, an);
  1384. ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
  1385. break;
  1386. case STA_NOTIFY_AWAKE:
  1387. ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
  1388. an->sleeping = false;
  1389. ath_tx_aggr_wakeup(sc, an);
  1390. break;
  1391. }
  1392. }
  1393. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1394. struct ieee80211_vif *vif,
  1395. unsigned int link_id, u16 queue,
  1396. const struct ieee80211_tx_queue_params *params)
  1397. {
  1398. struct ath_softc *sc = hw->priv;
  1399. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1400. struct ath_txq *txq;
  1401. struct ath9k_tx_queue_info qi;
  1402. int ret = 0;
  1403. if (queue >= IEEE80211_NUM_ACS)
  1404. return 0;
  1405. txq = sc->tx.txq_map[queue];
  1406. ath9k_ps_wakeup(sc);
  1407. mutex_lock(&sc->mutex);
  1408. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1409. qi.tqi_aifs = params->aifs;
  1410. qi.tqi_cwmin = params->cw_min;
  1411. qi.tqi_cwmax = params->cw_max;
  1412. qi.tqi_burstTime = params->txop * 32;
  1413. ath_dbg(common, CONFIG,
  1414. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1415. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1416. params->cw_max, params->txop);
  1417. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1418. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1419. if (ret)
  1420. ath_err(common, "TXQ Update failed\n");
  1421. mutex_unlock(&sc->mutex);
  1422. ath9k_ps_restore(sc);
  1423. return ret;
  1424. }
  1425. static int ath9k_set_key(struct ieee80211_hw *hw,
  1426. enum set_key_cmd cmd,
  1427. struct ieee80211_vif *vif,
  1428. struct ieee80211_sta *sta,
  1429. struct ieee80211_key_conf *key)
  1430. {
  1431. struct ath_softc *sc = hw->priv;
  1432. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1433. struct ath_node *an = NULL;
  1434. int ret = 0, i;
  1435. if (ath9k_modparam_nohwcrypt)
  1436. return -ENOSPC;
  1437. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1438. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1439. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1440. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1441. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1442. /*
  1443. * For now, disable hw crypto for the RSN IBSS group keys. This
  1444. * could be optimized in the future to use a modified key cache
  1445. * design to support per-STA RX GTK, but until that gets
  1446. * implemented, use of software crypto for group addressed
  1447. * frames is a acceptable to allow RSN IBSS to be used.
  1448. */
  1449. return -EOPNOTSUPP;
  1450. }
  1451. /* There may be MPDUs queued for the outgoing PTK key. Flush queues to
  1452. * make sure these are not send unencrypted or with a wrong (new) key
  1453. */
  1454. if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
  1455. ieee80211_stop_queues(hw);
  1456. ath9k_flush(hw, vif, 0, true);
  1457. ieee80211_wake_queues(hw);
  1458. }
  1459. mutex_lock(&sc->mutex);
  1460. ath9k_ps_wakeup(sc);
  1461. ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
  1462. if (sta)
  1463. an = (struct ath_node *)sta->drv_priv;
  1464. /* Delete pending key cache entries if no more frames are pointing to
  1465. * them in TXQs.
  1466. */
  1467. for (i = 0; i < ATH_KEYMAX; i++)
  1468. ath9k_pending_key_del(sc, i);
  1469. switch (cmd) {
  1470. case SET_KEY:
  1471. if (sta)
  1472. ath9k_del_ps_key(sc, vif, sta);
  1473. key->hw_key_idx = 0;
  1474. ret = ath_key_config(common, vif, sta, key);
  1475. if (ret >= 0) {
  1476. key->hw_key_idx = ret;
  1477. /* push IV and Michael MIC generation to stack */
  1478. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1479. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1480. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1481. if (sc->sc_ah->sw_mgmt_crypto_tx &&
  1482. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1483. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1484. ret = 0;
  1485. }
  1486. if (an && key->hw_key_idx) {
  1487. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1488. if (an->key_idx[i])
  1489. continue;
  1490. an->key_idx[i] = key->hw_key_idx;
  1491. break;
  1492. }
  1493. WARN_ON(i == ARRAY_SIZE(an->key_idx));
  1494. }
  1495. break;
  1496. case DISABLE_KEY:
  1497. if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
  1498. /* Delay key cache entry deletion until there are no
  1499. * remaining TXQ frames pointing to this entry.
  1500. */
  1501. set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
  1502. ath_hw_keysetmac(common, key->hw_key_idx, NULL);
  1503. } else {
  1504. ath_key_delete(common, key->hw_key_idx);
  1505. }
  1506. if (an) {
  1507. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1508. if (an->key_idx[i] != key->hw_key_idx)
  1509. continue;
  1510. an->key_idx[i] = 0;
  1511. break;
  1512. }
  1513. }
  1514. key->hw_key_idx = 0;
  1515. break;
  1516. default:
  1517. ret = -EINVAL;
  1518. }
  1519. ath9k_ps_restore(sc);
  1520. mutex_unlock(&sc->mutex);
  1521. return ret;
  1522. }
  1523. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1524. struct ieee80211_vif *vif,
  1525. struct ieee80211_bss_conf *bss_conf,
  1526. u64 changed)
  1527. {
  1528. #define CHECK_ANI \
  1529. (BSS_CHANGED_ASSOC | \
  1530. BSS_CHANGED_IBSS | \
  1531. BSS_CHANGED_BEACON_ENABLED)
  1532. struct ath_softc *sc = hw->priv;
  1533. struct ath_hw *ah = sc->sc_ah;
  1534. struct ath_common *common = ath9k_hw_common(ah);
  1535. struct ath_vif *avp = (void *)vif->drv_priv;
  1536. int slottime;
  1537. ath9k_ps_wakeup(sc);
  1538. mutex_lock(&sc->mutex);
  1539. if (changed & BSS_CHANGED_ASSOC) {
  1540. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1541. bss_conf->bssid, vif->cfg.assoc);
  1542. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1543. avp->aid = vif->cfg.aid;
  1544. avp->assoc = vif->cfg.assoc;
  1545. ath9k_calculate_summary_state(sc, avp->chanctx);
  1546. }
  1547. if ((changed & BSS_CHANGED_IBSS) ||
  1548. (changed & BSS_CHANGED_OCB)) {
  1549. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1550. common->curaid = vif->cfg.aid;
  1551. ath9k_hw_write_associd(sc->sc_ah);
  1552. }
  1553. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1554. (changed & BSS_CHANGED_BEACON_INT) ||
  1555. (changed & BSS_CHANGED_BEACON_INFO)) {
  1556. ath9k_calculate_summary_state(sc, avp->chanctx);
  1557. }
  1558. if ((avp->chanctx == sc->cur_chan) &&
  1559. (changed & BSS_CHANGED_ERP_SLOT)) {
  1560. if (bss_conf->use_short_slot)
  1561. slottime = 9;
  1562. else
  1563. slottime = 20;
  1564. if (vif->type == NL80211_IFTYPE_AP) {
  1565. /*
  1566. * Defer update, so that connected stations can adjust
  1567. * their settings at the same time.
  1568. * See beacon.c for more details
  1569. */
  1570. sc->beacon.slottime = slottime;
  1571. sc->beacon.updateslot = UPDATE;
  1572. } else {
  1573. ah->slottime = slottime;
  1574. ath9k_hw_init_global_settings(ah);
  1575. }
  1576. }
  1577. if (changed & BSS_CHANGED_P2P_PS)
  1578. ath9k_p2p_bss_info_changed(sc, vif);
  1579. if (changed & CHECK_ANI)
  1580. ath_check_ani(sc);
  1581. if (changed & BSS_CHANGED_TXPOWER) {
  1582. ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
  1583. vif->addr, bss_conf->txpower, bss_conf->txpower_type);
  1584. ath9k_set_txpower(sc, vif);
  1585. }
  1586. mutex_unlock(&sc->mutex);
  1587. ath9k_ps_restore(sc);
  1588. #undef CHECK_ANI
  1589. }
  1590. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1591. {
  1592. struct ath_softc *sc = hw->priv;
  1593. struct ath_vif *avp = (void *)vif->drv_priv;
  1594. u64 tsf;
  1595. mutex_lock(&sc->mutex);
  1596. ath9k_ps_wakeup(sc);
  1597. /* Get current TSF either from HW or kernel time. */
  1598. if (sc->cur_chan == avp->chanctx) {
  1599. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1600. } else {
  1601. tsf = sc->cur_chan->tsf_val +
  1602. ath9k_hw_get_tsf_offset(sc->cur_chan->tsf_ts, 0);
  1603. }
  1604. tsf += le64_to_cpu(avp->tsf_adjust);
  1605. ath9k_ps_restore(sc);
  1606. mutex_unlock(&sc->mutex);
  1607. return tsf;
  1608. }
  1609. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1610. struct ieee80211_vif *vif,
  1611. u64 tsf)
  1612. {
  1613. struct ath_softc *sc = hw->priv;
  1614. struct ath_vif *avp = (void *)vif->drv_priv;
  1615. mutex_lock(&sc->mutex);
  1616. ath9k_ps_wakeup(sc);
  1617. tsf -= le64_to_cpu(avp->tsf_adjust);
  1618. avp->chanctx->tsf_ts = ktime_get_raw();
  1619. if (sc->cur_chan == avp->chanctx)
  1620. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1621. avp->chanctx->tsf_val = tsf;
  1622. ath9k_ps_restore(sc);
  1623. mutex_unlock(&sc->mutex);
  1624. }
  1625. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1626. {
  1627. struct ath_softc *sc = hw->priv;
  1628. struct ath_vif *avp = (void *)vif->drv_priv;
  1629. mutex_lock(&sc->mutex);
  1630. ath9k_ps_wakeup(sc);
  1631. avp->chanctx->tsf_ts = ktime_get_raw();
  1632. if (sc->cur_chan == avp->chanctx)
  1633. ath9k_hw_reset_tsf(sc->sc_ah);
  1634. avp->chanctx->tsf_val = 0;
  1635. ath9k_ps_restore(sc);
  1636. mutex_unlock(&sc->mutex);
  1637. }
  1638. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1639. struct ieee80211_vif *vif,
  1640. struct ieee80211_ampdu_params *params)
  1641. {
  1642. struct ath_softc *sc = hw->priv;
  1643. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1644. bool flush = false;
  1645. int ret = 0;
  1646. struct ieee80211_sta *sta = params->sta;
  1647. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  1648. enum ieee80211_ampdu_mlme_action action = params->action;
  1649. u16 tid = params->tid;
  1650. u16 *ssn = &params->ssn;
  1651. struct ath_atx_tid *atid;
  1652. mutex_lock(&sc->mutex);
  1653. switch (action) {
  1654. case IEEE80211_AMPDU_RX_START:
  1655. break;
  1656. case IEEE80211_AMPDU_RX_STOP:
  1657. break;
  1658. case IEEE80211_AMPDU_TX_START:
  1659. if (ath9k_is_chanctx_enabled()) {
  1660. if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
  1661. ret = -EBUSY;
  1662. break;
  1663. }
  1664. }
  1665. ath9k_ps_wakeup(sc);
  1666. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1667. if (!ret)
  1668. ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
  1669. ath9k_ps_restore(sc);
  1670. break;
  1671. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  1672. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  1673. flush = true;
  1674. fallthrough;
  1675. case IEEE80211_AMPDU_TX_STOP_CONT:
  1676. ath9k_ps_wakeup(sc);
  1677. ath_tx_aggr_stop(sc, sta, tid);
  1678. if (!flush)
  1679. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1680. ath9k_ps_restore(sc);
  1681. break;
  1682. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1683. atid = ath_node_to_tid(an, tid);
  1684. atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
  1685. sta->deflink.ht_cap.ampdu_factor;
  1686. break;
  1687. default:
  1688. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1689. }
  1690. mutex_unlock(&sc->mutex);
  1691. return ret;
  1692. }
  1693. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1694. struct survey_info *survey)
  1695. {
  1696. struct ath_softc *sc = hw->priv;
  1697. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1698. struct ieee80211_supported_band *sband;
  1699. struct ieee80211_channel *chan;
  1700. unsigned long flags;
  1701. int pos;
  1702. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1703. return -EOPNOTSUPP;
  1704. spin_lock_irqsave(&common->cc_lock, flags);
  1705. if (idx == 0)
  1706. ath_update_survey_stats(sc);
  1707. sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
  1708. if (sband && idx >= sband->n_channels) {
  1709. idx -= sband->n_channels;
  1710. sband = NULL;
  1711. }
  1712. if (!sband)
  1713. sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
  1714. if (!sband || idx >= sband->n_channels) {
  1715. spin_unlock_irqrestore(&common->cc_lock, flags);
  1716. return -ENOENT;
  1717. }
  1718. chan = &sband->channels[idx];
  1719. pos = chan->hw_value;
  1720. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1721. survey->channel = chan;
  1722. spin_unlock_irqrestore(&common->cc_lock, flags);
  1723. return 0;
  1724. }
  1725. static void ath9k_enable_dynack(struct ath_softc *sc)
  1726. {
  1727. #ifdef CONFIG_ATH9K_DYNACK
  1728. u32 rfilt;
  1729. struct ath_hw *ah = sc->sc_ah;
  1730. ath_dynack_reset(ah);
  1731. ah->dynack.enabled = true;
  1732. rfilt = ath_calcrxfilter(sc);
  1733. ath9k_hw_setrxfilter(ah, rfilt);
  1734. #endif
  1735. }
  1736. static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
  1737. int radio_idx,
  1738. s16 coverage_class)
  1739. {
  1740. struct ath_softc *sc = hw->priv;
  1741. struct ath_hw *ah = sc->sc_ah;
  1742. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1743. return;
  1744. mutex_lock(&sc->mutex);
  1745. if (coverage_class >= 0) {
  1746. ah->coverage_class = coverage_class;
  1747. if (ah->dynack.enabled) {
  1748. u32 rfilt;
  1749. ah->dynack.enabled = false;
  1750. rfilt = ath_calcrxfilter(sc);
  1751. ath9k_hw_setrxfilter(ah, rfilt);
  1752. }
  1753. ath9k_ps_wakeup(sc);
  1754. ath9k_hw_init_global_settings(ah);
  1755. ath9k_ps_restore(sc);
  1756. } else if (!ah->dynack.enabled) {
  1757. ath9k_enable_dynack(sc);
  1758. }
  1759. mutex_unlock(&sc->mutex);
  1760. }
  1761. static bool ath9k_has_tx_pending(struct ath_softc *sc,
  1762. bool sw_pending)
  1763. {
  1764. int i, npend = 0;
  1765. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1766. if (!ATH_TXQ_SETUP(sc, i))
  1767. continue;
  1768. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
  1769. sw_pending);
  1770. if (npend)
  1771. break;
  1772. }
  1773. return !!npend;
  1774. }
  1775. static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1776. u32 queues, bool drop)
  1777. {
  1778. struct ath_softc *sc = hw->priv;
  1779. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1780. if (ath9k_is_chanctx_enabled()) {
  1781. if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
  1782. goto flush;
  1783. /*
  1784. * If MCC is active, extend the flush timeout
  1785. * and wait for the HW/SW queues to become
  1786. * empty. This needs to be done outside the
  1787. * sc->mutex lock to allow the channel scheduler
  1788. * to switch channel contexts.
  1789. *
  1790. * The vif queues have been stopped in mac80211,
  1791. * so there won't be any incoming frames.
  1792. */
  1793. __ath9k_flush(hw, queues, drop, true, true);
  1794. return;
  1795. }
  1796. flush:
  1797. mutex_lock(&sc->mutex);
  1798. __ath9k_flush(hw, queues, drop, true, false);
  1799. mutex_unlock(&sc->mutex);
  1800. }
  1801. void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
  1802. bool sw_pending, bool timeout_override)
  1803. {
  1804. struct ath_softc *sc = hw->priv;
  1805. struct ath_hw *ah = sc->sc_ah;
  1806. struct ath_common *common = ath9k_hw_common(ah);
  1807. int timeout;
  1808. bool drain_txq;
  1809. cancel_delayed_work_sync(&sc->hw_check_work);
  1810. if (ah->ah_flags & AH_UNPLUGGED) {
  1811. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1812. return;
  1813. }
  1814. if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
  1815. ath_dbg(common, ANY, "Device not present\n");
  1816. return;
  1817. }
  1818. spin_lock_bh(&sc->chan_lock);
  1819. if (timeout_override)
  1820. timeout = HZ / 5;
  1821. else
  1822. timeout = sc->cur_chan->flush_timeout;
  1823. spin_unlock_bh(&sc->chan_lock);
  1824. ath_dbg(common, CHAN_CTX,
  1825. "Flush timeout: %d\n", jiffies_to_msecs(timeout));
  1826. if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
  1827. timeout) > 0)
  1828. drop = false;
  1829. if (drop) {
  1830. ath9k_ps_wakeup(sc);
  1831. spin_lock_bh(&sc->sc_pcu_lock);
  1832. drain_txq = ath_drain_all_txq(sc);
  1833. spin_unlock_bh(&sc->sc_pcu_lock);
  1834. if (!drain_txq)
  1835. ath_reset(sc, NULL);
  1836. ath9k_ps_restore(sc);
  1837. }
  1838. ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
  1839. msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
  1840. }
  1841. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1842. {
  1843. struct ath_softc *sc = hw->priv;
  1844. return ath9k_has_tx_pending(sc, true);
  1845. }
  1846. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1847. {
  1848. struct ath_softc *sc = hw->priv;
  1849. struct ath_hw *ah = sc->sc_ah;
  1850. struct ieee80211_vif *vif;
  1851. struct ath_vif *avp;
  1852. struct ath_buf *bf;
  1853. struct ath_tx_status ts;
  1854. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1855. int status;
  1856. vif = sc->beacon.bslot[0];
  1857. if (!vif)
  1858. return 0;
  1859. if (!vif->bss_conf.enable_beacon)
  1860. return 0;
  1861. avp = (void *)vif->drv_priv;
  1862. if (!sc->beacon.tx_processed && !edma) {
  1863. tasklet_disable(&sc->bcon_tasklet);
  1864. bf = avp->av_bcbuf;
  1865. if (!bf || !bf->bf_mpdu)
  1866. goto skip;
  1867. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1868. if (status == -EINPROGRESS)
  1869. goto skip;
  1870. sc->beacon.tx_processed = true;
  1871. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1872. skip:
  1873. tasklet_enable(&sc->bcon_tasklet);
  1874. }
  1875. return sc->beacon.tx_last;
  1876. }
  1877. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1878. struct ieee80211_low_level_stats *stats)
  1879. {
  1880. struct ath_softc *sc = hw->priv;
  1881. struct ath_hw *ah = sc->sc_ah;
  1882. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1883. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1884. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1885. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1886. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1887. return 0;
  1888. }
  1889. static u32 fill_chainmask(u32 cap, u32 new)
  1890. {
  1891. u32 filled = 0;
  1892. int i;
  1893. for (i = 0; cap && new; i++, cap >>= 1) {
  1894. if (!(cap & BIT(0)))
  1895. continue;
  1896. if (new & BIT(0))
  1897. filled |= BIT(i);
  1898. new >>= 1;
  1899. }
  1900. return filled;
  1901. }
  1902. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1903. {
  1904. if (AR_SREV_9300_20_OR_LATER(ah))
  1905. return true;
  1906. switch (val & 0x7) {
  1907. case 0x1:
  1908. case 0x3:
  1909. case 0x7:
  1910. return true;
  1911. case 0x2:
  1912. return (ah->caps.rx_chainmask == 1);
  1913. default:
  1914. return false;
  1915. }
  1916. }
  1917. static int ath9k_set_antenna(struct ieee80211_hw *hw, int radio_idx,
  1918. u32 tx_ant, u32 rx_ant)
  1919. {
  1920. struct ath_softc *sc = hw->priv;
  1921. struct ath_hw *ah = sc->sc_ah;
  1922. if (ah->caps.rx_chainmask != 1)
  1923. rx_ant |= tx_ant;
  1924. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1925. return -EINVAL;
  1926. sc->ant_rx = rx_ant;
  1927. sc->ant_tx = tx_ant;
  1928. if (ah->caps.rx_chainmask == 1)
  1929. return 0;
  1930. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1931. if (AR_SREV_9100(ah))
  1932. ah->rxchainmask = 0x7;
  1933. else
  1934. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1935. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1936. ath9k_cmn_reload_chainmask(ah);
  1937. return 0;
  1938. }
  1939. static int ath9k_get_antenna(struct ieee80211_hw *hw, int radio_idx,
  1940. u32 *tx_ant, u32 *rx_ant)
  1941. {
  1942. struct ath_softc *sc = hw->priv;
  1943. *tx_ant = sc->ant_tx;
  1944. *rx_ant = sc->ant_rx;
  1945. return 0;
  1946. }
  1947. static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
  1948. struct ieee80211_vif *vif,
  1949. const u8 *mac_addr)
  1950. {
  1951. struct ath_softc *sc = hw->priv;
  1952. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1953. struct cfg80211_chan_def *chandef = &sc->cur_chan->chandef;
  1954. struct ieee80211_channel *chan = chandef->chan;
  1955. int pos = chan->hw_value;
  1956. set_bit(ATH_OP_SCANNING, &common->op_flags);
  1957. /* Reset current survey */
  1958. if (!sc->cur_chan->offchannel) {
  1959. if (sc->cur_survey != &sc->survey[pos]) {
  1960. if (sc->cur_survey)
  1961. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1962. sc->cur_survey = &sc->survey[pos];
  1963. }
  1964. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1965. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1966. }
  1967. }
  1968. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
  1969. struct ieee80211_vif *vif)
  1970. {
  1971. struct ath_softc *sc = hw->priv;
  1972. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1973. clear_bit(ATH_OP_SCANNING, &common->op_flags);
  1974. }
  1975. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  1976. static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
  1977. {
  1978. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1979. if (sc->offchannel.roc_vif) {
  1980. ath_dbg(common, CHAN_CTX,
  1981. "%s: Aborting RoC\n", __func__);
  1982. timer_delete_sync(&sc->offchannel.timer);
  1983. if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
  1984. ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
  1985. }
  1986. if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
  1987. ath_dbg(common, CHAN_CTX,
  1988. "%s: Aborting HW scan\n", __func__);
  1989. timer_delete_sync(&sc->offchannel.timer);
  1990. ath_scan_complete(sc, true);
  1991. }
  1992. }
  1993. static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1994. struct ieee80211_scan_request *hw_req)
  1995. {
  1996. struct cfg80211_scan_request *req = &hw_req->req;
  1997. struct ath_softc *sc = hw->priv;
  1998. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1999. int ret = 0;
  2000. mutex_lock(&sc->mutex);
  2001. if (WARN_ON(sc->offchannel.scan_req)) {
  2002. ret = -EBUSY;
  2003. goto out;
  2004. }
  2005. ath9k_ps_wakeup(sc);
  2006. set_bit(ATH_OP_SCANNING, &common->op_flags);
  2007. sc->offchannel.scan_vif = vif;
  2008. sc->offchannel.scan_req = req;
  2009. sc->offchannel.scan_idx = 0;
  2010. ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
  2011. vif->addr);
  2012. if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
  2013. ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
  2014. ath_offchannel_next(sc);
  2015. }
  2016. out:
  2017. mutex_unlock(&sc->mutex);
  2018. return ret;
  2019. }
  2020. static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
  2021. struct ieee80211_vif *vif)
  2022. {
  2023. struct ath_softc *sc = hw->priv;
  2024. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2025. ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
  2026. mutex_lock(&sc->mutex);
  2027. timer_delete_sync(&sc->offchannel.timer);
  2028. ath_scan_complete(sc, true);
  2029. mutex_unlock(&sc->mutex);
  2030. }
  2031. static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
  2032. struct ieee80211_vif *vif,
  2033. struct ieee80211_channel *chan, int duration,
  2034. enum ieee80211_roc_type type)
  2035. {
  2036. struct ath_softc *sc = hw->priv;
  2037. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2038. int ret = 0;
  2039. mutex_lock(&sc->mutex);
  2040. if (WARN_ON(sc->offchannel.roc_vif)) {
  2041. ret = -EBUSY;
  2042. goto out;
  2043. }
  2044. ath9k_ps_wakeup(sc);
  2045. sc->offchannel.roc_vif = vif;
  2046. sc->offchannel.roc_chan = chan;
  2047. sc->offchannel.roc_duration = duration;
  2048. ath_dbg(common, CHAN_CTX,
  2049. "RoC request on vif: %pM, type: %d duration: %d\n",
  2050. vif->addr, type, duration);
  2051. if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
  2052. ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
  2053. ath_offchannel_next(sc);
  2054. }
  2055. out:
  2056. mutex_unlock(&sc->mutex);
  2057. return ret;
  2058. }
  2059. static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
  2060. struct ieee80211_vif *vif)
  2061. {
  2062. struct ath_softc *sc = hw->priv;
  2063. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2064. mutex_lock(&sc->mutex);
  2065. ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
  2066. timer_delete_sync(&sc->offchannel.timer);
  2067. if (sc->offchannel.roc_vif) {
  2068. if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
  2069. ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
  2070. }
  2071. mutex_unlock(&sc->mutex);
  2072. return 0;
  2073. }
  2074. static int ath9k_add_chanctx(struct ieee80211_hw *hw,
  2075. struct ieee80211_chanctx_conf *conf)
  2076. {
  2077. struct ath_softc *sc = hw->priv;
  2078. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2079. struct ath_chanctx *ctx, **ptr;
  2080. int pos;
  2081. mutex_lock(&sc->mutex);
  2082. ath_for_each_chanctx(sc, ctx) {
  2083. if (ctx->assigned)
  2084. continue;
  2085. ptr = (void *) conf->drv_priv;
  2086. *ptr = ctx;
  2087. ctx->assigned = true;
  2088. pos = ctx - &sc->chanctx[0];
  2089. ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
  2090. ath_dbg(common, CHAN_CTX,
  2091. "Add channel context: %d MHz\n",
  2092. conf->def.chan->center_freq);
  2093. ath_chanctx_set_channel(sc, ctx, &conf->def);
  2094. mutex_unlock(&sc->mutex);
  2095. return 0;
  2096. }
  2097. mutex_unlock(&sc->mutex);
  2098. return -ENOSPC;
  2099. }
  2100. static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
  2101. struct ieee80211_chanctx_conf *conf)
  2102. {
  2103. struct ath_softc *sc = hw->priv;
  2104. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2105. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2106. mutex_lock(&sc->mutex);
  2107. ath_dbg(common, CHAN_CTX,
  2108. "Remove channel context: %d MHz\n",
  2109. conf->def.chan->center_freq);
  2110. ctx->assigned = false;
  2111. ctx->hw_queue_base = 0;
  2112. ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
  2113. mutex_unlock(&sc->mutex);
  2114. }
  2115. static void ath9k_change_chanctx(struct ieee80211_hw *hw,
  2116. struct ieee80211_chanctx_conf *conf,
  2117. u32 changed)
  2118. {
  2119. struct ath_softc *sc = hw->priv;
  2120. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2121. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2122. mutex_lock(&sc->mutex);
  2123. ath_dbg(common, CHAN_CTX,
  2124. "Change channel context: %d MHz\n",
  2125. conf->def.chan->center_freq);
  2126. ath_chanctx_set_channel(sc, ctx, &conf->def);
  2127. mutex_unlock(&sc->mutex);
  2128. }
  2129. static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
  2130. struct ieee80211_vif *vif,
  2131. struct ieee80211_bss_conf *link_conf,
  2132. struct ieee80211_chanctx_conf *conf)
  2133. {
  2134. struct ath_softc *sc = hw->priv;
  2135. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2136. struct ath_vif *avp = (void *)vif->drv_priv;
  2137. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2138. int i;
  2139. ath9k_cancel_pending_offchannel(sc);
  2140. mutex_lock(&sc->mutex);
  2141. ath_dbg(common, CHAN_CTX,
  2142. "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
  2143. vif->addr, vif->type, vif->p2p,
  2144. conf->def.chan->center_freq);
  2145. avp->chanctx = ctx;
  2146. ctx->nvifs_assigned++;
  2147. list_add_tail(&avp->list, &ctx->vifs);
  2148. ath9k_calculate_summary_state(sc, ctx);
  2149. for (i = 0; i < IEEE80211_NUM_ACS; i++)
  2150. vif->hw_queue[i] = ctx->hw_queue_base + i;
  2151. mutex_unlock(&sc->mutex);
  2152. return 0;
  2153. }
  2154. static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
  2155. struct ieee80211_vif *vif,
  2156. struct ieee80211_bss_conf *link_conf,
  2157. struct ieee80211_chanctx_conf *conf)
  2158. {
  2159. struct ath_softc *sc = hw->priv;
  2160. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2161. struct ath_vif *avp = (void *)vif->drv_priv;
  2162. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2163. int ac;
  2164. ath9k_cancel_pending_offchannel(sc);
  2165. mutex_lock(&sc->mutex);
  2166. ath_dbg(common, CHAN_CTX,
  2167. "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
  2168. vif->addr, vif->type, vif->p2p,
  2169. conf->def.chan->center_freq);
  2170. avp->chanctx = NULL;
  2171. ctx->nvifs_assigned--;
  2172. list_del(&avp->list);
  2173. ath9k_calculate_summary_state(sc, ctx);
  2174. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
  2175. vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
  2176. mutex_unlock(&sc->mutex);
  2177. }
  2178. static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
  2179. struct ieee80211_vif *vif,
  2180. struct ieee80211_prep_tx_info *info)
  2181. {
  2182. struct ath_softc *sc = hw->priv;
  2183. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2184. struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
  2185. struct ath_beacon_config *cur_conf;
  2186. struct ath_chanctx *go_ctx;
  2187. unsigned long timeout;
  2188. bool changed = false;
  2189. u32 beacon_int;
  2190. if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
  2191. return;
  2192. if (!avp->chanctx)
  2193. return;
  2194. mutex_lock(&sc->mutex);
  2195. spin_lock_bh(&sc->chan_lock);
  2196. if (sc->next_chan || (sc->cur_chan != avp->chanctx))
  2197. changed = true;
  2198. spin_unlock_bh(&sc->chan_lock);
  2199. if (!changed)
  2200. goto out;
  2201. ath9k_cancel_pending_offchannel(sc);
  2202. go_ctx = ath_is_go_chanctx_present(sc);
  2203. if (go_ctx) {
  2204. /*
  2205. * Wait till the GO interface gets a chance
  2206. * to send out an NoA.
  2207. */
  2208. spin_lock_bh(&sc->chan_lock);
  2209. sc->sched.mgd_prepare_tx = true;
  2210. cur_conf = &go_ctx->beacon;
  2211. beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
  2212. spin_unlock_bh(&sc->chan_lock);
  2213. timeout = usecs_to_jiffies(beacon_int * 2);
  2214. init_completion(&sc->go_beacon);
  2215. mutex_unlock(&sc->mutex);
  2216. if (wait_for_completion_timeout(&sc->go_beacon,
  2217. timeout) == 0) {
  2218. ath_dbg(common, CHAN_CTX,
  2219. "Failed to send new NoA\n");
  2220. spin_lock_bh(&sc->chan_lock);
  2221. sc->sched.mgd_prepare_tx = false;
  2222. spin_unlock_bh(&sc->chan_lock);
  2223. }
  2224. mutex_lock(&sc->mutex);
  2225. }
  2226. ath_dbg(common, CHAN_CTX,
  2227. "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
  2228. __func__, vif->addr);
  2229. spin_lock_bh(&sc->chan_lock);
  2230. sc->next_chan = avp->chanctx;
  2231. sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
  2232. spin_unlock_bh(&sc->chan_lock);
  2233. ath_chanctx_set_next(sc, true);
  2234. out:
  2235. mutex_unlock(&sc->mutex);
  2236. }
  2237. void ath9k_fill_chanctx_ops(void)
  2238. {
  2239. if (!ath9k_is_chanctx_enabled())
  2240. return;
  2241. ath9k_ops.hw_scan = ath9k_hw_scan;
  2242. ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
  2243. ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
  2244. ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
  2245. ath9k_ops.add_chanctx = ath9k_add_chanctx;
  2246. ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
  2247. ath9k_ops.change_chanctx = ath9k_change_chanctx;
  2248. ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
  2249. ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
  2250. ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
  2251. }
  2252. #endif
  2253. static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2254. unsigned int link_id, int *dbm)
  2255. {
  2256. struct ath_softc *sc = hw->priv;
  2257. struct ath_vif *avp = (void *)vif->drv_priv;
  2258. mutex_lock(&sc->mutex);
  2259. if (avp->chanctx)
  2260. *dbm = avp->chanctx->cur_txpower;
  2261. else
  2262. *dbm = sc->cur_chan->cur_txpower;
  2263. mutex_unlock(&sc->mutex);
  2264. *dbm /= 2;
  2265. return 0;
  2266. }
  2267. struct ieee80211_ops ath9k_ops = {
  2268. .add_chanctx = ieee80211_emulate_add_chanctx,
  2269. .remove_chanctx = ieee80211_emulate_remove_chanctx,
  2270. .change_chanctx = ieee80211_emulate_change_chanctx,
  2271. .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx,
  2272. .tx = ath9k_tx,
  2273. .start = ath9k_start,
  2274. .stop = ath9k_stop,
  2275. .add_interface = ath9k_add_interface,
  2276. .change_interface = ath9k_change_interface,
  2277. .remove_interface = ath9k_remove_interface,
  2278. .config = ath9k_config,
  2279. .configure_filter = ath9k_configure_filter,
  2280. .sta_state = ath9k_sta_state,
  2281. .sta_notify = ath9k_sta_notify,
  2282. .conf_tx = ath9k_conf_tx,
  2283. .bss_info_changed = ath9k_bss_info_changed,
  2284. .set_key = ath9k_set_key,
  2285. .get_tsf = ath9k_get_tsf,
  2286. .set_tsf = ath9k_set_tsf,
  2287. .reset_tsf = ath9k_reset_tsf,
  2288. .ampdu_action = ath9k_ampdu_action,
  2289. .get_survey = ath9k_get_survey,
  2290. .rfkill_poll = ath9k_rfkill_poll_state,
  2291. .set_coverage_class = ath9k_set_coverage_class,
  2292. .flush = ath9k_flush,
  2293. .tx_frames_pending = ath9k_tx_frames_pending,
  2294. .tx_last_beacon = ath9k_tx_last_beacon,
  2295. .release_buffered_frames = ath9k_release_buffered_frames,
  2296. .get_stats = ath9k_get_stats,
  2297. .set_antenna = ath9k_set_antenna,
  2298. .get_antenna = ath9k_get_antenna,
  2299. #ifdef CONFIG_ATH9K_WOW
  2300. .suspend = ath9k_suspend,
  2301. .resume = ath9k_resume,
  2302. .set_wakeup = ath9k_set_wakeup,
  2303. #endif
  2304. #ifdef CONFIG_ATH9K_DEBUGFS
  2305. .get_et_sset_count = ath9k_get_et_sset_count,
  2306. .get_et_stats = ath9k_get_et_stats,
  2307. .get_et_strings = ath9k_get_et_strings,
  2308. #endif
  2309. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
  2310. .sta_add_debugfs = ath9k_sta_add_debugfs,
  2311. #endif
  2312. .sw_scan_start = ath9k_sw_scan_start,
  2313. .sw_scan_complete = ath9k_sw_scan_complete,
  2314. .get_txpower = ath9k_get_txpower,
  2315. .wake_tx_queue = ath9k_wake_tx_queue,
  2316. };