dynack.c 9.5 KB

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  1. /*
  2. * Copyright (c) 2014, Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/export.h>
  17. #include "ath9k.h"
  18. #include "hw.h"
  19. #include "dynack.h"
  20. #define COMPUTE_TO (5 * HZ)
  21. #define LATEACK_DELAY (10 * HZ)
  22. #define EWMA_LEVEL 96
  23. #define EWMA_DIV 128
  24. /**
  25. * ath_dynack_get_max_to - set max timeout according to channel width
  26. * @ah: ath hw
  27. *
  28. */
  29. static u32 ath_dynack_get_max_to(struct ath_hw *ah)
  30. {
  31. const struct ath9k_channel *chan = ah->curchan;
  32. if (!chan)
  33. return 300;
  34. if (IS_CHAN_HT40(chan))
  35. return 300;
  36. if (IS_CHAN_HALF_RATE(chan))
  37. return 750;
  38. if (IS_CHAN_QUARTER_RATE(chan))
  39. return 1500;
  40. return 600;
  41. }
  42. /*
  43. * ath_dynack_ewma - EWMA (Exponentially Weighted Moving Average) calculation
  44. */
  45. static inline int ath_dynack_ewma(int old, int new)
  46. {
  47. if (old > 0)
  48. return (new * (EWMA_DIV - EWMA_LEVEL) +
  49. old * EWMA_LEVEL) / EWMA_DIV;
  50. else
  51. return new;
  52. }
  53. /**
  54. * ath_dynack_get_sifs - get sifs time based on phy used
  55. * @ah: ath hw
  56. * @phy: phy used
  57. *
  58. */
  59. static inline u32 ath_dynack_get_sifs(struct ath_hw *ah, int phy)
  60. {
  61. u32 sifs = CCK_SIFS_TIME;
  62. if (phy == WLAN_RC_PHY_OFDM) {
  63. if (IS_CHAN_QUARTER_RATE(ah->curchan))
  64. sifs = OFDM_SIFS_TIME_QUARTER;
  65. else if (IS_CHAN_HALF_RATE(ah->curchan))
  66. sifs = OFDM_SIFS_TIME_HALF;
  67. else
  68. sifs = OFDM_SIFS_TIME;
  69. }
  70. return sifs;
  71. }
  72. /**
  73. * ath_dynack_bssidmask - filter out ACK frames based on BSSID mask
  74. * @ah: ath hw
  75. * @mac: receiver address
  76. */
  77. static inline bool ath_dynack_bssidmask(struct ath_hw *ah, const u8 *mac)
  78. {
  79. int i;
  80. struct ath_common *common = ath9k_hw_common(ah);
  81. for (i = 0; i < ETH_ALEN; i++) {
  82. if ((common->macaddr[i] & common->bssidmask[i]) !=
  83. (mac[i] & common->bssidmask[i]))
  84. return false;
  85. }
  86. return true;
  87. }
  88. /**
  89. * ath_dynack_set_timeout - configure timeouts/slottime registers
  90. * @ah: ath hw
  91. * @to: timeout value
  92. *
  93. */
  94. static void ath_dynack_set_timeout(struct ath_hw *ah, int to)
  95. {
  96. struct ath_common *common = ath9k_hw_common(ah);
  97. int slottime = (to - 3) / 2;
  98. ath_dbg(common, DYNACK, "ACK timeout %u slottime %u\n",
  99. to, slottime);
  100. ath9k_hw_setslottime(ah, slottime);
  101. ath9k_hw_set_ack_timeout(ah, to);
  102. ath9k_hw_set_cts_timeout(ah, to);
  103. }
  104. /**
  105. * ath_dynack_compute_ackto - compute ACK timeout as the maximum STA timeout
  106. * @ah: ath hw
  107. *
  108. * should be called while holding qlock
  109. */
  110. static void ath_dynack_compute_ackto(struct ath_hw *ah)
  111. {
  112. struct ath_dynack *da = &ah->dynack;
  113. struct ath_node *an;
  114. int to = 0;
  115. list_for_each_entry(an, &da->nodes, list)
  116. if (an->ackto > to)
  117. to = an->ackto;
  118. if (to && da->ackto != to) {
  119. ath_dynack_set_timeout(ah, to);
  120. da->ackto = to;
  121. }
  122. }
  123. /**
  124. * ath_dynack_compute_to - compute STA ACK timeout
  125. * @ah: ath hw
  126. *
  127. * should be called while holding qlock
  128. */
  129. static void ath_dynack_compute_to(struct ath_hw *ah)
  130. {
  131. struct ath_dynack *da = &ah->dynack;
  132. u32 ackto, ack_ts, max_to;
  133. struct ieee80211_sta *sta;
  134. struct ts_info *st_ts;
  135. struct ath_node *an;
  136. u8 *dst, *src;
  137. rcu_read_lock();
  138. max_to = ath_dynack_get_max_to(ah);
  139. while (da->st_rbf.h_rb != da->st_rbf.t_rb &&
  140. da->ack_rbf.h_rb != da->ack_rbf.t_rb) {
  141. ack_ts = da->ack_rbf.tstamp[da->ack_rbf.h_rb];
  142. st_ts = &da->st_rbf.ts[da->st_rbf.h_rb];
  143. dst = da->st_rbf.addr[da->st_rbf.h_rb].h_dest;
  144. src = da->st_rbf.addr[da->st_rbf.h_rb].h_src;
  145. ath_dbg(ath9k_hw_common(ah), DYNACK,
  146. "ack_ts %u st_ts %u st_dur %u [%u-%u]\n",
  147. ack_ts, st_ts->tstamp, st_ts->dur,
  148. da->ack_rbf.h_rb, da->st_rbf.h_rb);
  149. if (ack_ts > st_ts->tstamp + st_ts->dur) {
  150. ackto = ack_ts - st_ts->tstamp - st_ts->dur;
  151. if (ackto < max_to) {
  152. sta = ieee80211_find_sta_by_ifaddr(ah->hw, dst,
  153. src);
  154. if (sta) {
  155. an = (struct ath_node *)sta->drv_priv;
  156. an->ackto = ath_dynack_ewma(an->ackto,
  157. ackto);
  158. ath_dbg(ath9k_hw_common(ah), DYNACK,
  159. "%pM to %d [%u]\n", dst,
  160. an->ackto, ackto);
  161. if (time_is_before_jiffies(da->lto)) {
  162. ath_dynack_compute_ackto(ah);
  163. da->lto = jiffies + COMPUTE_TO;
  164. }
  165. }
  166. INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
  167. }
  168. INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
  169. } else {
  170. INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
  171. }
  172. }
  173. rcu_read_unlock();
  174. }
  175. /**
  176. * ath_dynack_sample_tx_ts - status timestamp sampling method
  177. * @ah: ath hw
  178. * @skb: socket buffer
  179. * @ts: tx status info
  180. * @sta: station pointer
  181. *
  182. */
  183. void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
  184. struct ath_tx_status *ts,
  185. struct ieee80211_sta *sta)
  186. {
  187. struct ieee80211_hdr *hdr;
  188. struct ath_dynack *da = &ah->dynack;
  189. struct ath_common *common = ath9k_hw_common(ah);
  190. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  191. u32 dur = ts->duration;
  192. u8 ridx;
  193. if (!da->enabled || (info->flags & IEEE80211_TX_CTL_NO_ACK))
  194. return;
  195. spin_lock_bh(&da->qlock);
  196. hdr = (struct ieee80211_hdr *)skb->data;
  197. /* late ACK */
  198. if (ts->ts_status & ATH9K_TXERR_XRETRY) {
  199. if (ieee80211_is_assoc_req(hdr->frame_control) ||
  200. ieee80211_is_assoc_resp(hdr->frame_control) ||
  201. ieee80211_is_auth(hdr->frame_control)) {
  202. u32 max_to = ath_dynack_get_max_to(ah);
  203. ath_dbg(common, DYNACK, "late ack\n");
  204. ath_dynack_set_timeout(ah, max_to);
  205. if (sta) {
  206. struct ath_node *an;
  207. an = (struct ath_node *)sta->drv_priv;
  208. an->ackto = -1;
  209. }
  210. da->lto = jiffies + LATEACK_DELAY;
  211. }
  212. spin_unlock_bh(&da->qlock);
  213. return;
  214. }
  215. ridx = ts->ts_rateindex;
  216. da->st_rbf.ts[da->st_rbf.t_rb].tstamp = ts->ts_tstamp;
  217. /* ether_addr_copy() gives a false warning on gcc-10 so use memcpy()
  218. * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97490
  219. */
  220. memcpy(da->st_rbf.addr[da->st_rbf.t_rb].h_dest, hdr->addr1, ETH_ALEN);
  221. memcpy(da->st_rbf.addr[da->st_rbf.t_rb].h_src, hdr->addr2, ETH_ALEN);
  222. if (!(info->status.rates[ridx].flags & IEEE80211_TX_RC_MCS)) {
  223. const struct ieee80211_rate *rate;
  224. struct ieee80211_tx_rate *rates = info->status.rates;
  225. u32 phy;
  226. rate = &common->sbands[info->band].bitrates[rates[ridx].idx];
  227. if (info->band == NL80211_BAND_2GHZ &&
  228. !(rate->flags & IEEE80211_RATE_ERP_G))
  229. phy = WLAN_RC_PHY_CCK;
  230. else
  231. phy = WLAN_RC_PHY_OFDM;
  232. dur -= ath_dynack_get_sifs(ah, phy);
  233. }
  234. da->st_rbf.ts[da->st_rbf.t_rb].dur = dur;
  235. INCR(da->st_rbf.t_rb, ATH_DYN_BUF);
  236. if (da->st_rbf.t_rb == da->st_rbf.h_rb)
  237. INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
  238. ath_dbg(common, DYNACK, "{%pM} tx sample %u [dur %u][h %u-t %u]\n",
  239. hdr->addr1, ts->ts_tstamp, dur, da->st_rbf.h_rb,
  240. da->st_rbf.t_rb);
  241. ath_dynack_compute_to(ah);
  242. spin_unlock_bh(&da->qlock);
  243. }
  244. EXPORT_SYMBOL(ath_dynack_sample_tx_ts);
  245. /**
  246. * ath_dynack_sample_ack_ts - ACK timestamp sampling method
  247. * @ah: ath hw
  248. * @skb: socket buffer
  249. * @ts: rx timestamp
  250. *
  251. */
  252. void ath_dynack_sample_ack_ts(struct ath_hw *ah, struct sk_buff *skb,
  253. u32 ts)
  254. {
  255. struct ath_dynack *da = &ah->dynack;
  256. struct ath_common *common = ath9k_hw_common(ah);
  257. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  258. if (!da->enabled || !ath_dynack_bssidmask(ah, hdr->addr1))
  259. return;
  260. spin_lock_bh(&da->qlock);
  261. da->ack_rbf.tstamp[da->ack_rbf.t_rb] = ts;
  262. INCR(da->ack_rbf.t_rb, ATH_DYN_BUF);
  263. if (da->ack_rbf.t_rb == da->ack_rbf.h_rb)
  264. INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
  265. ath_dbg(common, DYNACK, "rx sample %u [h %u-t %u]\n",
  266. ts, da->ack_rbf.h_rb, da->ack_rbf.t_rb);
  267. ath_dynack_compute_to(ah);
  268. spin_unlock_bh(&da->qlock);
  269. }
  270. EXPORT_SYMBOL(ath_dynack_sample_ack_ts);
  271. /**
  272. * ath_dynack_node_init - init ath_node related info
  273. * @ah: ath hw
  274. * @an: ath node
  275. *
  276. */
  277. void ath_dynack_node_init(struct ath_hw *ah, struct ath_node *an)
  278. {
  279. struct ath_dynack *da = &ah->dynack;
  280. an->ackto = da->ackto;
  281. spin_lock_bh(&da->qlock);
  282. list_add_tail(&an->list, &da->nodes);
  283. spin_unlock_bh(&da->qlock);
  284. }
  285. EXPORT_SYMBOL(ath_dynack_node_init);
  286. /**
  287. * ath_dynack_node_deinit - deinit ath_node related info
  288. * @ah: ath hw
  289. * @an: ath node
  290. *
  291. */
  292. void ath_dynack_node_deinit(struct ath_hw *ah, struct ath_node *an)
  293. {
  294. struct ath_dynack *da = &ah->dynack;
  295. spin_lock_bh(&da->qlock);
  296. list_del(&an->list);
  297. spin_unlock_bh(&da->qlock);
  298. }
  299. EXPORT_SYMBOL(ath_dynack_node_deinit);
  300. /**
  301. * ath_dynack_reset - reset dynack processing
  302. * @ah: ath hw
  303. *
  304. */
  305. void ath_dynack_reset(struct ath_hw *ah)
  306. {
  307. struct ath_dynack *da = &ah->dynack;
  308. struct ath_node *an;
  309. spin_lock_bh(&da->qlock);
  310. da->lto = jiffies + COMPUTE_TO;
  311. da->st_rbf.t_rb = 0;
  312. da->st_rbf.h_rb = 0;
  313. da->ack_rbf.t_rb = 0;
  314. da->ack_rbf.h_rb = 0;
  315. da->ackto = ath_dynack_get_max_to(ah);
  316. list_for_each_entry(an, &da->nodes, list)
  317. an->ackto = da->ackto;
  318. /* init acktimeout */
  319. ath_dynack_set_timeout(ah, da->ackto);
  320. spin_unlock_bh(&da->qlock);
  321. }
  322. EXPORT_SYMBOL(ath_dynack_reset);
  323. /**
  324. * ath_dynack_init - init dynack data structure
  325. * @ah: ath hw
  326. *
  327. */
  328. void ath_dynack_init(struct ath_hw *ah)
  329. {
  330. struct ath_dynack *da = &ah->dynack;
  331. memset(da, 0, sizeof(struct ath_dynack));
  332. spin_lock_init(&da->qlock);
  333. INIT_LIST_HEAD(&da->nodes);
  334. /* ackto = slottime + sifs + air delay */
  335. da->ackto = 9 + 16 + 64;
  336. ah->hw->wiphy->features |= NL80211_FEATURE_ACKTO_ESTIMATION;
  337. }