dbring.c 8.5 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause-Clear
  2. /*
  3. * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  5. */
  6. #include "core.h"
  7. #include "debug.h"
  8. #include "hal.h"
  9. static int ath12k_dbring_bufs_replenish(struct ath12k *ar,
  10. struct ath12k_dbring *ring,
  11. struct ath12k_dbring_element *buff,
  12. gfp_t gfp)
  13. {
  14. struct ath12k_base *ab = ar->ab;
  15. struct hal_srng *srng;
  16. dma_addr_t paddr;
  17. void *ptr_aligned, *ptr_unaligned, *desc;
  18. int ret;
  19. int buf_id;
  20. u32 cookie;
  21. srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
  22. lockdep_assert_held(&srng->lock);
  23. ath12k_hal_srng_access_begin(ab, srng);
  24. ptr_unaligned = buff->payload;
  25. ptr_aligned = PTR_ALIGN(ptr_unaligned, ring->buf_align);
  26. paddr = dma_map_single(ab->dev, ptr_aligned, ring->buf_sz,
  27. DMA_FROM_DEVICE);
  28. ret = dma_mapping_error(ab->dev, paddr);
  29. if (ret)
  30. goto err;
  31. spin_lock_bh(&ring->idr_lock);
  32. buf_id = idr_alloc(&ring->bufs_idr, buff, 0, ring->bufs_max, gfp);
  33. spin_unlock_bh(&ring->idr_lock);
  34. if (buf_id < 0) {
  35. ret = -ENOBUFS;
  36. goto err_dma_unmap;
  37. }
  38. desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
  39. if (!desc) {
  40. ret = -ENOENT;
  41. goto err_idr_remove;
  42. }
  43. buff->paddr = paddr;
  44. cookie = u32_encode_bits(ar->pdev_idx, DP_RXDMA_BUF_COOKIE_PDEV_ID) |
  45. u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID);
  46. ath12k_hal_rx_buf_addr_info_set(&ab->hal, desc, paddr, cookie, 0);
  47. ath12k_hal_srng_access_end(ab, srng);
  48. return 0;
  49. err_idr_remove:
  50. spin_lock_bh(&ring->idr_lock);
  51. idr_remove(&ring->bufs_idr, buf_id);
  52. spin_unlock_bh(&ring->idr_lock);
  53. err_dma_unmap:
  54. dma_unmap_single(ab->dev, paddr, ring->buf_sz,
  55. DMA_FROM_DEVICE);
  56. err:
  57. ath12k_hal_srng_access_end(ab, srng);
  58. return ret;
  59. }
  60. static int ath12k_dbring_fill_bufs(struct ath12k *ar,
  61. struct ath12k_dbring *ring,
  62. gfp_t gfp)
  63. {
  64. struct ath12k_dbring_element *buff;
  65. struct hal_srng *srng;
  66. struct ath12k_base *ab = ar->ab;
  67. int num_remain, req_entries, num_free;
  68. u32 align;
  69. int size, ret;
  70. srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
  71. spin_lock_bh(&srng->lock);
  72. num_free = ath12k_hal_srng_src_num_free(ab, srng, true);
  73. req_entries = min(num_free, ring->bufs_max);
  74. num_remain = req_entries;
  75. align = ring->buf_align;
  76. size = sizeof(*buff) + ring->buf_sz + align - 1;
  77. while (num_remain > 0) {
  78. buff = kzalloc(size, gfp);
  79. if (!buff)
  80. break;
  81. ret = ath12k_dbring_bufs_replenish(ar, ring, buff, gfp);
  82. if (ret) {
  83. ath12k_warn(ab, "failed to replenish db ring num_remain %d req_ent %d\n",
  84. num_remain, req_entries);
  85. kfree(buff);
  86. break;
  87. }
  88. num_remain--;
  89. }
  90. spin_unlock_bh(&srng->lock);
  91. return num_remain;
  92. }
  93. int ath12k_dbring_wmi_cfg_setup(struct ath12k *ar,
  94. struct ath12k_dbring *ring,
  95. enum wmi_direct_buffer_module id)
  96. {
  97. struct ath12k_wmi_pdev_dma_ring_cfg_arg arg = {};
  98. int ret;
  99. if (id >= WMI_DIRECT_BUF_MAX)
  100. return -EINVAL;
  101. arg.pdev_id = DP_SW2HW_MACID(ring->pdev_id);
  102. arg.module_id = id;
  103. arg.base_paddr_lo = lower_32_bits(ring->refill_srng.paddr);
  104. arg.base_paddr_hi = upper_32_bits(ring->refill_srng.paddr);
  105. arg.head_idx_paddr_lo = lower_32_bits(ring->hp_addr);
  106. arg.head_idx_paddr_hi = upper_32_bits(ring->hp_addr);
  107. arg.tail_idx_paddr_lo = lower_32_bits(ring->tp_addr);
  108. arg.tail_idx_paddr_hi = upper_32_bits(ring->tp_addr);
  109. arg.num_elems = ring->bufs_max;
  110. arg.buf_size = ring->buf_sz;
  111. arg.num_resp_per_event = ring->num_resp_per_event;
  112. arg.event_timeout_ms = ring->event_timeout_ms;
  113. ret = ath12k_wmi_pdev_dma_ring_cfg(ar, &arg);
  114. if (ret) {
  115. ath12k_warn(ar->ab, "failed to setup db ring cfg\n");
  116. return ret;
  117. }
  118. return 0;
  119. }
  120. int ath12k_dbring_set_cfg(struct ath12k *ar, struct ath12k_dbring *ring,
  121. u32 num_resp_per_event, u32 event_timeout_ms,
  122. int (*handler)(struct ath12k *,
  123. struct ath12k_dbring_data *))
  124. {
  125. if (WARN_ON(!ring))
  126. return -EINVAL;
  127. ring->num_resp_per_event = num_resp_per_event;
  128. ring->event_timeout_ms = event_timeout_ms;
  129. ring->handler = handler;
  130. return 0;
  131. }
  132. int ath12k_dbring_buf_setup(struct ath12k *ar,
  133. struct ath12k_dbring *ring,
  134. struct ath12k_dbring_cap *db_cap)
  135. {
  136. struct ath12k_base *ab = ar->ab;
  137. struct hal_srng *srng;
  138. int ret;
  139. srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
  140. ring->bufs_max = ring->refill_srng.size /
  141. ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_DIR_BUF);
  142. ring->buf_sz = db_cap->min_buf_sz;
  143. ring->buf_align = db_cap->min_buf_align;
  144. ring->pdev_id = db_cap->pdev_id;
  145. ring->hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng);
  146. ring->tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng);
  147. ret = ath12k_dbring_fill_bufs(ar, ring, GFP_KERNEL);
  148. return ret;
  149. }
  150. int ath12k_dbring_srng_setup(struct ath12k *ar, struct ath12k_dbring *ring,
  151. int ring_num, int num_entries)
  152. {
  153. int ret;
  154. ret = ath12k_dp_srng_setup(ar->ab, &ring->refill_srng, HAL_RXDMA_DIR_BUF,
  155. ring_num, ar->pdev_idx, num_entries);
  156. if (ret < 0) {
  157. ath12k_warn(ar->ab, "failed to setup srng: %d ring_id %d\n",
  158. ret, ring_num);
  159. goto err;
  160. }
  161. return 0;
  162. err:
  163. ath12k_dp_srng_cleanup(ar->ab, &ring->refill_srng);
  164. return ret;
  165. }
  166. int ath12k_dbring_get_cap(struct ath12k_base *ab,
  167. u8 pdev_idx,
  168. enum wmi_direct_buffer_module id,
  169. struct ath12k_dbring_cap *db_cap)
  170. {
  171. int i;
  172. if (!ab->num_db_cap || !ab->db_caps)
  173. return -ENOENT;
  174. if (id >= WMI_DIRECT_BUF_MAX)
  175. return -EINVAL;
  176. for (i = 0; i < ab->num_db_cap; i++) {
  177. if (pdev_idx == ab->db_caps[i].pdev_id &&
  178. id == ab->db_caps[i].id) {
  179. *db_cap = ab->db_caps[i];
  180. return 0;
  181. }
  182. }
  183. return -ENOENT;
  184. }
  185. int ath12k_dbring_buffer_release_event(struct ath12k_base *ab,
  186. struct ath12k_dbring_buf_release_event *ev)
  187. {
  188. struct ath12k_dbring *ring = NULL;
  189. struct hal_srng *srng;
  190. struct ath12k *ar;
  191. struct ath12k_dbring_element *buff;
  192. struct ath12k_dbring_data handler_data;
  193. struct ath12k_buffer_addr desc;
  194. u8 *vaddr_unalign;
  195. u32 num_entry, num_buff_reaped;
  196. u8 pdev_idx, rbm;
  197. u32 cookie;
  198. int buf_id;
  199. int size;
  200. dma_addr_t paddr;
  201. int ret = 0;
  202. pdev_idx = le32_to_cpu(ev->fixed.pdev_id);
  203. if (pdev_idx >= ab->num_radios) {
  204. ath12k_warn(ab, "Invalid pdev id %d\n", pdev_idx);
  205. return -EINVAL;
  206. }
  207. if (ev->fixed.num_buf_release_entry !=
  208. ev->fixed.num_meta_data_entry) {
  209. ath12k_warn(ab, "Buffer entry %d mismatch meta entry %d\n",
  210. ev->fixed.num_buf_release_entry,
  211. ev->fixed.num_meta_data_entry);
  212. return -EINVAL;
  213. }
  214. ar = ab->pdevs[pdev_idx].ar;
  215. rcu_read_lock();
  216. if (!rcu_dereference(ab->pdevs_active[pdev_idx])) {
  217. ret = -EINVAL;
  218. goto rcu_unlock;
  219. }
  220. switch (ev->fixed.module_id) {
  221. case WMI_DIRECT_BUF_SPECTRAL:
  222. break;
  223. default:
  224. ring = NULL;
  225. ath12k_warn(ab, "Recv dma buffer release ev on unsupp module %d\n",
  226. ev->fixed.module_id);
  227. break;
  228. }
  229. if (!ring) {
  230. ret = -EINVAL;
  231. goto rcu_unlock;
  232. }
  233. srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
  234. num_entry = le32_to_cpu(ev->fixed.num_buf_release_entry);
  235. size = sizeof(*buff) + ring->buf_sz + ring->buf_align - 1;
  236. num_buff_reaped = 0;
  237. spin_lock_bh(&srng->lock);
  238. while (num_buff_reaped < num_entry) {
  239. desc.info0 = ev->buf_entry[num_buff_reaped].paddr_lo;
  240. desc.info1 = ev->buf_entry[num_buff_reaped].paddr_hi;
  241. handler_data.meta = ev->meta_data[num_buff_reaped];
  242. num_buff_reaped++;
  243. ath12k_hal_rx_buf_addr_info_get(&ab->hal, &desc, &paddr, &cookie, &rbm);
  244. buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
  245. spin_lock_bh(&ring->idr_lock);
  246. buff = idr_find(&ring->bufs_idr, buf_id);
  247. if (!buff) {
  248. spin_unlock_bh(&ring->idr_lock);
  249. continue;
  250. }
  251. idr_remove(&ring->bufs_idr, buf_id);
  252. spin_unlock_bh(&ring->idr_lock);
  253. dma_unmap_single(ab->dev, buff->paddr, ring->buf_sz,
  254. DMA_FROM_DEVICE);
  255. if (ring->handler) {
  256. vaddr_unalign = buff->payload;
  257. handler_data.data = PTR_ALIGN(vaddr_unalign,
  258. ring->buf_align);
  259. handler_data.data_sz = ring->buf_sz;
  260. ring->handler(ar, &handler_data);
  261. }
  262. memset(buff, 0, size);
  263. ath12k_dbring_bufs_replenish(ar, ring, buff, GFP_ATOMIC);
  264. }
  265. spin_unlock_bh(&srng->lock);
  266. rcu_unlock:
  267. rcu_read_unlock();
  268. return ret;
  269. }
  270. void ath12k_dbring_srng_cleanup(struct ath12k *ar, struct ath12k_dbring *ring)
  271. {
  272. ath12k_dp_srng_cleanup(ar->ab, &ring->refill_srng);
  273. }
  274. void ath12k_dbring_buf_cleanup(struct ath12k *ar, struct ath12k_dbring *ring)
  275. {
  276. struct ath12k_dbring_element *buff;
  277. int buf_id;
  278. spin_lock_bh(&ring->idr_lock);
  279. idr_for_each_entry(&ring->bufs_idr, buff, buf_id) {
  280. idr_remove(&ring->bufs_idr, buf_id);
  281. dma_unmap_single(ar->ab->dev, buff->paddr,
  282. ring->buf_sz, DMA_FROM_DEVICE);
  283. kfree(buff);
  284. }
  285. idr_destroy(&ring->bufs_idr);
  286. spin_unlock_bh(&ring->idr_lock);
  287. }