dp_tx.c 37 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307
  1. // SPDX-License-Identifier: BSD-3-Clause-Clear
  2. /*
  3. * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  6. */
  7. #include "core.h"
  8. #include "dp_tx.h"
  9. #include "debug.h"
  10. #include "debugfs_sta.h"
  11. #include "hw.h"
  12. #include "peer.h"
  13. #include "mac.h"
  14. static enum hal_tcl_encap_type
  15. ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb)
  16. {
  17. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  18. struct ath11k_base *ab = arvif->ar->ab;
  19. if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
  20. return HAL_TCL_ENCAP_TYPE_RAW;
  21. if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)
  22. return HAL_TCL_ENCAP_TYPE_ETHERNET;
  23. return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
  24. }
  25. static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb)
  26. {
  27. struct ieee80211_hdr *hdr = (void *)skb->data;
  28. u8 *qos_ctl;
  29. if (!ieee80211_is_data_qos(hdr->frame_control))
  30. return;
  31. qos_ctl = ieee80211_get_qos_ctl(hdr);
  32. memmove(skb->data + IEEE80211_QOS_CTL_LEN,
  33. skb->data, (void *)qos_ctl - (void *)skb->data);
  34. skb_pull(skb, IEEE80211_QOS_CTL_LEN);
  35. hdr = (void *)skb->data;
  36. hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
  37. }
  38. static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb)
  39. {
  40. struct ieee80211_hdr *hdr = (void *)skb->data;
  41. struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb);
  42. if (cb->flags & ATH11K_SKB_HW_80211_ENCAP)
  43. return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
  44. else if (!ieee80211_is_data_qos(hdr->frame_control))
  45. return HAL_DESC_REO_NON_QOS_TID;
  46. else
  47. return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
  48. }
  49. enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher)
  50. {
  51. switch (cipher) {
  52. case WLAN_CIPHER_SUITE_WEP40:
  53. return HAL_ENCRYPT_TYPE_WEP_40;
  54. case WLAN_CIPHER_SUITE_WEP104:
  55. return HAL_ENCRYPT_TYPE_WEP_104;
  56. case WLAN_CIPHER_SUITE_TKIP:
  57. return HAL_ENCRYPT_TYPE_TKIP_MIC;
  58. case WLAN_CIPHER_SUITE_CCMP:
  59. return HAL_ENCRYPT_TYPE_CCMP_128;
  60. case WLAN_CIPHER_SUITE_CCMP_256:
  61. return HAL_ENCRYPT_TYPE_CCMP_256;
  62. case WLAN_CIPHER_SUITE_GCMP:
  63. return HAL_ENCRYPT_TYPE_GCMP_128;
  64. case WLAN_CIPHER_SUITE_GCMP_256:
  65. return HAL_ENCRYPT_TYPE_AES_GCMP_256;
  66. default:
  67. return HAL_ENCRYPT_TYPE_OPEN;
  68. }
  69. }
  70. int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif,
  71. struct ath11k_sta *arsta, struct sk_buff *skb)
  72. {
  73. struct ath11k_base *ab = ar->ab;
  74. struct ath11k_dp *dp = &ab->dp;
  75. struct hal_tx_info ti = {};
  76. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  77. struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb);
  78. struct hal_srng *tcl_ring;
  79. struct ieee80211_hdr *hdr = (void *)skb->data;
  80. struct dp_tx_ring *tx_ring;
  81. size_t num_tx_rings = ab->hw_params.hal_params->num_tx_rings;
  82. void *hal_tcl_desc;
  83. u8 pool_id;
  84. u8 hal_ring_id;
  85. int ret;
  86. u32 ring_selector = 0;
  87. u8 ring_map = 0;
  88. bool tcl_ring_retry;
  89. if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)))
  90. return -ESHUTDOWN;
  91. if (unlikely(!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
  92. !ieee80211_is_data(hdr->frame_control)))
  93. return -EOPNOTSUPP;
  94. pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1);
  95. ring_selector = ab->hw_params.hw_ops->get_ring_selector(skb);
  96. tcl_ring_sel:
  97. tcl_ring_retry = false;
  98. ti.ring_id = ring_selector % num_tx_rings;
  99. ti.rbm_id = ab->hw_params.hal_params->tcl2wbm_rbm_map[ti.ring_id].rbm_id;
  100. ring_map |= BIT(ti.ring_id);
  101. tx_ring = &dp->tx_ring[ti.ring_id];
  102. spin_lock_bh(&tx_ring->tx_idr_lock);
  103. ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0,
  104. DP_TX_IDR_SIZE - 1, GFP_ATOMIC);
  105. spin_unlock_bh(&tx_ring->tx_idr_lock);
  106. if (unlikely(ret < 0)) {
  107. if (ring_map == (BIT(num_tx_rings) - 1) ||
  108. !ab->hw_params.tcl_ring_retry) {
  109. atomic_inc(&ab->soc_stats.tx_err.misc_fail);
  110. return -ENOSPC;
  111. }
  112. /* Check if the next ring is available */
  113. ring_selector++;
  114. goto tcl_ring_sel;
  115. }
  116. ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) |
  117. FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) |
  118. FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id);
  119. ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb);
  120. if (ieee80211_has_a4(hdr->frame_control) &&
  121. is_multicast_ether_addr(hdr->addr3) && arsta &&
  122. arsta->use_4addr_set) {
  123. ti.meta_data_flags = arsta->tcl_metadata;
  124. ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1);
  125. } else {
  126. ti.meta_data_flags = arvif->tcl_metadata;
  127. }
  128. if (unlikely(ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW)) {
  129. if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) {
  130. ti.encrypt_type =
  131. ath11k_dp_tx_get_encrypt_type(skb_cb->cipher);
  132. if (ieee80211_has_protected(hdr->frame_control))
  133. skb_put(skb, IEEE80211_CCMP_MIC_LEN);
  134. } else {
  135. ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
  136. }
  137. }
  138. ti.addr_search_flags = arvif->hal_addr_search_flags;
  139. ti.search_type = arvif->search_type;
  140. ti.type = HAL_TCL_DESC_TYPE_BUFFER;
  141. ti.pkt_offset = 0;
  142. ti.lmac_id = ar->lmac_id;
  143. ti.bss_ast_hash = arvif->ast_hash;
  144. ti.bss_ast_idx = arvif->ast_idx;
  145. ti.dscp_tid_tbl_idx = 0;
  146. if (likely(skb->ip_summed == CHECKSUM_PARTIAL &&
  147. ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW)) {
  148. ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) |
  149. FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) |
  150. FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) |
  151. FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) |
  152. FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1);
  153. }
  154. if (ieee80211_vif_is_mesh(arvif->vif))
  155. ti.enable_mesh = true;
  156. ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1);
  157. ti.tid = ath11k_dp_tx_get_tid(skb);
  158. switch (ti.encap_type) {
  159. case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
  160. ath11k_dp_tx_encap_nwifi(skb);
  161. break;
  162. case HAL_TCL_ENCAP_TYPE_RAW:
  163. if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) {
  164. ret = -EINVAL;
  165. goto fail_remove_idr;
  166. }
  167. break;
  168. case HAL_TCL_ENCAP_TYPE_ETHERNET:
  169. /* no need to encap */
  170. break;
  171. case HAL_TCL_ENCAP_TYPE_802_3:
  172. default:
  173. /* TODO: Take care of other encap modes as well */
  174. ret = -EINVAL;
  175. atomic_inc(&ab->soc_stats.tx_err.misc_fail);
  176. goto fail_remove_idr;
  177. }
  178. ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
  179. if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) {
  180. atomic_inc(&ab->soc_stats.tx_err.misc_fail);
  181. ath11k_warn(ab, "failed to DMA map data Tx buffer\n");
  182. ret = -ENOMEM;
  183. goto fail_remove_idr;
  184. }
  185. ti.data_len = skb->len;
  186. skb_cb->paddr = ti.paddr;
  187. skb_cb->vif = arvif->vif;
  188. skb_cb->ar = ar;
  189. hal_ring_id = tx_ring->tcl_data_ring.ring_id;
  190. tcl_ring = &ab->hal.srng_list[hal_ring_id];
  191. spin_lock_bh(&tcl_ring->lock);
  192. ath11k_hal_srng_access_begin(ab, tcl_ring);
  193. hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring);
  194. if (unlikely(!hal_tcl_desc)) {
  195. /* NOTE: It is highly unlikely we'll be running out of tcl_ring
  196. * desc because the desc is directly enqueued onto hw queue.
  197. */
  198. ath11k_hal_srng_access_end(ab, tcl_ring);
  199. ab->soc_stats.tx_err.desc_na[ti.ring_id]++;
  200. spin_unlock_bh(&tcl_ring->lock);
  201. ret = -ENOMEM;
  202. /* Checking for available tcl descriptors in another ring in
  203. * case of failure due to full tcl ring now, is better than
  204. * checking this ring earlier for each pkt tx.
  205. * Restart ring selection if some rings are not checked yet.
  206. */
  207. if (unlikely(ring_map != (BIT(num_tx_rings)) - 1) &&
  208. ab->hw_params.tcl_ring_retry && num_tx_rings > 1) {
  209. tcl_ring_retry = true;
  210. ring_selector++;
  211. }
  212. goto fail_unmap_dma;
  213. }
  214. ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc +
  215. sizeof(struct hal_tlv_hdr), &ti);
  216. ath11k_hal_srng_access_end(ab, tcl_ring);
  217. ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]);
  218. spin_unlock_bh(&tcl_ring->lock);
  219. ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ",
  220. skb->data, skb->len);
  221. atomic_inc(&ar->dp.num_tx_pending);
  222. return 0;
  223. fail_unmap_dma:
  224. dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
  225. fail_remove_idr:
  226. spin_lock_bh(&tx_ring->tx_idr_lock);
  227. idr_remove(&tx_ring->txbuf_idr,
  228. FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id));
  229. spin_unlock_bh(&tx_ring->tx_idr_lock);
  230. if (tcl_ring_retry)
  231. goto tcl_ring_sel;
  232. return ret;
  233. }
  234. static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id,
  235. int msdu_id,
  236. struct dp_tx_ring *tx_ring)
  237. {
  238. struct ath11k *ar;
  239. struct sk_buff *msdu;
  240. struct ath11k_skb_cb *skb_cb;
  241. spin_lock(&tx_ring->tx_idr_lock);
  242. msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id);
  243. spin_unlock(&tx_ring->tx_idr_lock);
  244. if (unlikely(!msdu)) {
  245. ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
  246. msdu_id);
  247. return;
  248. }
  249. skb_cb = ATH11K_SKB_CB(msdu);
  250. dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
  251. dev_kfree_skb_any(msdu);
  252. ar = ab->pdevs[mac_id].ar;
  253. if (atomic_dec_and_test(&ar->dp.num_tx_pending))
  254. wake_up(&ar->dp.tx_empty_waitq);
  255. }
  256. static void
  257. ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab,
  258. struct dp_tx_ring *tx_ring,
  259. struct ath11k_dp_htt_wbm_tx_status *ts)
  260. {
  261. struct ieee80211_tx_status status = {};
  262. struct sk_buff *msdu;
  263. struct ieee80211_tx_info *info;
  264. struct ath11k_skb_cb *skb_cb;
  265. struct ath11k *ar;
  266. struct ath11k_peer *peer;
  267. spin_lock(&tx_ring->tx_idr_lock);
  268. msdu = idr_remove(&tx_ring->txbuf_idr, ts->msdu_id);
  269. spin_unlock(&tx_ring->tx_idr_lock);
  270. if (unlikely(!msdu)) {
  271. ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n",
  272. ts->msdu_id);
  273. return;
  274. }
  275. skb_cb = ATH11K_SKB_CB(msdu);
  276. info = IEEE80211_SKB_CB(msdu);
  277. ar = skb_cb->ar;
  278. if (atomic_dec_and_test(&ar->dp.num_tx_pending))
  279. wake_up(&ar->dp.tx_empty_waitq);
  280. dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
  281. if (!skb_cb->vif) {
  282. ieee80211_free_txskb(ar->hw, msdu);
  283. return;
  284. }
  285. memset(&info->status, 0, sizeof(info->status));
  286. if (ts->acked) {
  287. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  288. info->flags |= IEEE80211_TX_STAT_ACK;
  289. info->status.ack_signal = ts->ack_rssi;
  290. if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,
  291. ab->wmi_ab.svc_map))
  292. info->status.ack_signal += ATH11K_DEFAULT_NOISE_FLOOR;
  293. info->status.flags |=
  294. IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
  295. } else {
  296. info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
  297. }
  298. }
  299. spin_lock_bh(&ab->base_lock);
  300. peer = ath11k_peer_find_by_id(ab, ts->peer_id);
  301. if (!peer || !peer->sta) {
  302. ath11k_dbg(ab, ATH11K_DBG_DATA,
  303. "dp_tx: failed to find the peer with peer_id %d\n",
  304. ts->peer_id);
  305. spin_unlock_bh(&ab->base_lock);
  306. ieee80211_free_txskb(ar->hw, msdu);
  307. return;
  308. }
  309. spin_unlock_bh(&ab->base_lock);
  310. status.sta = peer->sta;
  311. status.info = info;
  312. status.skb = msdu;
  313. ieee80211_tx_status_ext(ar->hw, &status);
  314. }
  315. static void
  316. ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab,
  317. void *desc, u8 mac_id,
  318. u32 msdu_id, struct dp_tx_ring *tx_ring)
  319. {
  320. struct htt_tx_wbm_completion *status_desc;
  321. struct ath11k_dp_htt_wbm_tx_status ts = {};
  322. enum hal_wbm_htt_tx_comp_status wbm_status;
  323. status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET;
  324. wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS,
  325. status_desc->info0);
  326. switch (wbm_status) {
  327. case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
  328. case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
  329. case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
  330. ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
  331. ts.msdu_id = msdu_id;
  332. ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI,
  333. status_desc->info1);
  334. if (FIELD_GET(HTT_TX_WBM_COMP_INFO2_VALID, status_desc->info2))
  335. ts.peer_id = FIELD_GET(HTT_TX_WBM_COMP_INFO2_SW_PEER_ID,
  336. status_desc->info2);
  337. else
  338. ts.peer_id = HTT_INVALID_PEER_ID;
  339. ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts);
  340. break;
  341. case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
  342. case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
  343. ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring);
  344. break;
  345. case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
  346. /* This event is to be handled only when the driver decides to
  347. * use WDS offload functionality.
  348. */
  349. break;
  350. default:
  351. ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
  352. break;
  353. }
  354. }
  355. static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar,
  356. struct sk_buff *msdu,
  357. struct hal_tx_status *ts)
  358. {
  359. struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
  360. if (ts->try_cnt > 1) {
  361. peer_stats->retry_pkts += ts->try_cnt - 1;
  362. peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len;
  363. if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) {
  364. peer_stats->failed_pkts += 1;
  365. peer_stats->failed_bytes += msdu->len;
  366. }
  367. }
  368. }
  369. void ath11k_dp_tx_update_txcompl(struct ath11k *ar, struct hal_tx_status *ts)
  370. {
  371. struct ath11k_base *ab = ar->ab;
  372. struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
  373. enum hal_tx_rate_stats_pkt_type pkt_type;
  374. enum hal_tx_rate_stats_sgi sgi;
  375. enum hal_tx_rate_stats_bw bw;
  376. struct ath11k_peer *peer;
  377. struct ath11k_sta *arsta;
  378. struct ieee80211_sta *sta;
  379. u16 rate, ru_tones;
  380. u8 mcs, rate_idx = 0, ofdma;
  381. int ret;
  382. spin_lock_bh(&ab->base_lock);
  383. peer = ath11k_peer_find_by_id(ab, ts->peer_id);
  384. if (!peer || !peer->sta) {
  385. ath11k_dbg(ab, ATH11K_DBG_DP_TX,
  386. "failed to find the peer by id %u\n", ts->peer_id);
  387. goto err_out;
  388. }
  389. sta = peer->sta;
  390. arsta = ath11k_sta_to_arsta(sta);
  391. memset(&arsta->txrate, 0, sizeof(arsta->txrate));
  392. pkt_type = FIELD_GET(HAL_TX_RATE_STATS_INFO0_PKT_TYPE,
  393. ts->rate_stats);
  394. mcs = FIELD_GET(HAL_TX_RATE_STATS_INFO0_MCS,
  395. ts->rate_stats);
  396. sgi = FIELD_GET(HAL_TX_RATE_STATS_INFO0_SGI,
  397. ts->rate_stats);
  398. bw = FIELD_GET(HAL_TX_RATE_STATS_INFO0_BW, ts->rate_stats);
  399. ru_tones = FIELD_GET(HAL_TX_RATE_STATS_INFO0_TONES_IN_RU, ts->rate_stats);
  400. ofdma = FIELD_GET(HAL_TX_RATE_STATS_INFO0_OFDMA_TX, ts->rate_stats);
  401. /* This is to prefer choose the real NSS value arsta->last_txrate.nss,
  402. * if it is invalid, then choose the NSS value while assoc.
  403. */
  404. if (arsta->last_txrate.nss)
  405. arsta->txrate.nss = arsta->last_txrate.nss;
  406. else
  407. arsta->txrate.nss = arsta->peer_nss;
  408. if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11A ||
  409. pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11B) {
  410. ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
  411. pkt_type,
  412. &rate_idx,
  413. &rate);
  414. if (ret < 0)
  415. goto err_out;
  416. arsta->txrate.legacy = rate;
  417. } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11N) {
  418. if (mcs > 7) {
  419. ath11k_warn(ab, "Invalid HT mcs index %d\n", mcs);
  420. goto err_out;
  421. }
  422. if (arsta->txrate.nss != 0)
  423. arsta->txrate.mcs = mcs + 8 * (arsta->txrate.nss - 1);
  424. arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
  425. if (sgi)
  426. arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
  427. } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AC) {
  428. if (mcs > 9) {
  429. ath11k_warn(ab, "Invalid VHT mcs index %d\n", mcs);
  430. goto err_out;
  431. }
  432. arsta->txrate.mcs = mcs;
  433. arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
  434. if (sgi)
  435. arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
  436. } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) {
  437. if (mcs > 11) {
  438. ath11k_warn(ab, "Invalid HE mcs index %d\n", mcs);
  439. goto err_out;
  440. }
  441. arsta->txrate.mcs = mcs;
  442. arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
  443. arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
  444. }
  445. arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
  446. if (ofdma && pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) {
  447. arsta->txrate.bw = RATE_INFO_BW_HE_RU;
  448. arsta->txrate.he_ru_alloc =
  449. ath11k_mac_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
  450. }
  451. if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
  452. ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
  453. err_out:
  454. spin_unlock_bh(&ab->base_lock);
  455. }
  456. static void ath11k_dp_tx_complete_msdu(struct ath11k *ar,
  457. struct sk_buff *msdu,
  458. struct hal_tx_status *ts)
  459. {
  460. struct ieee80211_tx_status status = {};
  461. struct ieee80211_rate_status status_rate = {};
  462. struct ath11k_base *ab = ar->ab;
  463. struct ieee80211_tx_info *info;
  464. struct ath11k_skb_cb *skb_cb;
  465. struct ath11k_peer *peer;
  466. struct ath11k_sta *arsta;
  467. struct rate_info rate;
  468. if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
  469. /* Must not happen */
  470. return;
  471. }
  472. skb_cb = ATH11K_SKB_CB(msdu);
  473. dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
  474. if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) {
  475. ieee80211_free_txskb(ar->hw, msdu);
  476. return;
  477. }
  478. if (unlikely(!skb_cb->vif)) {
  479. ieee80211_free_txskb(ar->hw, msdu);
  480. return;
  481. }
  482. info = IEEE80211_SKB_CB(msdu);
  483. memset(&info->status, 0, sizeof(info->status));
  484. /* skip tx rate update from ieee80211_status*/
  485. info->status.rates[0].idx = -1;
  486. if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED &&
  487. !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  488. info->flags |= IEEE80211_TX_STAT_ACK;
  489. info->status.ack_signal = ts->ack_rssi;
  490. if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,
  491. ab->wmi_ab.svc_map))
  492. info->status.ack_signal += ATH11K_DEFAULT_NOISE_FLOOR;
  493. info->status.flags |= IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
  494. }
  495. if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX &&
  496. (info->flags & IEEE80211_TX_CTL_NO_ACK))
  497. info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
  498. if (unlikely(ath11k_debugfs_is_extd_tx_stats_enabled(ar)) ||
  499. ab->hw_params.single_pdev_only) {
  500. if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) {
  501. if (ar->last_ppdu_id == 0) {
  502. ar->last_ppdu_id = ts->ppdu_id;
  503. } else if (ar->last_ppdu_id == ts->ppdu_id ||
  504. ar->cached_ppdu_id == ar->last_ppdu_id) {
  505. ar->cached_ppdu_id = ar->last_ppdu_id;
  506. ar->cached_stats.is_ampdu = true;
  507. ath11k_dp_tx_update_txcompl(ar, ts);
  508. memset(&ar->cached_stats, 0,
  509. sizeof(struct ath11k_per_peer_tx_stats));
  510. } else {
  511. ar->cached_stats.is_ampdu = false;
  512. ath11k_dp_tx_update_txcompl(ar, ts);
  513. memset(&ar->cached_stats, 0,
  514. sizeof(struct ath11k_per_peer_tx_stats));
  515. }
  516. ar->last_ppdu_id = ts->ppdu_id;
  517. }
  518. ath11k_dp_tx_cache_peer_stats(ar, msdu, ts);
  519. }
  520. spin_lock_bh(&ab->base_lock);
  521. peer = ath11k_peer_find_by_id(ab, ts->peer_id);
  522. if (!peer || !peer->sta) {
  523. ath11k_dbg(ab, ATH11K_DBG_DATA,
  524. "dp_tx: failed to find the peer with peer_id %d\n",
  525. ts->peer_id);
  526. spin_unlock_bh(&ab->base_lock);
  527. ieee80211_free_txskb(ar->hw, msdu);
  528. return;
  529. }
  530. arsta = ath11k_sta_to_arsta(peer->sta);
  531. status.sta = peer->sta;
  532. status.skb = msdu;
  533. status.info = info;
  534. rate = arsta->last_txrate;
  535. status_rate.rate_idx = rate;
  536. status_rate.try_count = 1;
  537. status.rates = &status_rate;
  538. status.n_rates = 1;
  539. spin_unlock_bh(&ab->base_lock);
  540. ieee80211_tx_status_ext(ar->hw, &status);
  541. }
  542. static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab,
  543. struct hal_wbm_release_ring *desc,
  544. struct hal_tx_status *ts)
  545. {
  546. ts->buf_rel_source =
  547. FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0);
  548. if (unlikely(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
  549. ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM))
  550. return;
  551. if (unlikely(ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW))
  552. return;
  553. ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON,
  554. desc->info0);
  555. ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER,
  556. desc->info1);
  557. ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT,
  558. desc->info1);
  559. ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI,
  560. desc->info2);
  561. if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU)
  562. ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU;
  563. ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3);
  564. ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3);
  565. if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID)
  566. ts->rate_stats = desc->rate_stats.info0;
  567. else
  568. ts->rate_stats = 0;
  569. }
  570. void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id)
  571. {
  572. struct ath11k *ar;
  573. struct ath11k_dp *dp = &ab->dp;
  574. int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
  575. struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
  576. struct sk_buff *msdu;
  577. struct hal_tx_status ts = {};
  578. struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
  579. u32 *desc;
  580. u32 msdu_id;
  581. u8 mac_id;
  582. spin_lock_bh(&status_ring->lock);
  583. ath11k_hal_srng_access_begin(ab, status_ring);
  584. while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) !=
  585. tx_ring->tx_status_tail) &&
  586. (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) {
  587. memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
  588. desc, sizeof(struct hal_wbm_release_ring));
  589. tx_ring->tx_status_head =
  590. ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head);
  591. }
  592. if (unlikely((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) &&
  593. (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) ==
  594. tx_ring->tx_status_tail))) {
  595. /* TODO: Process pending tx_status messages when kfifo_is_full() */
  596. ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
  597. }
  598. ath11k_hal_srng_access_end(ab, status_ring);
  599. spin_unlock_bh(&status_ring->lock);
  600. while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
  601. struct hal_wbm_release_ring *tx_status;
  602. u32 desc_id;
  603. tx_ring->tx_status_tail =
  604. ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
  605. tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
  606. ath11k_dp_tx_status_parse(ab, tx_status, &ts);
  607. desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
  608. tx_status->buf_addr_info.info1);
  609. mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id);
  610. msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id);
  611. if (unlikely(ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) {
  612. ath11k_dp_tx_process_htt_tx_complete(ab,
  613. (void *)tx_status,
  614. mac_id, msdu_id,
  615. tx_ring);
  616. continue;
  617. }
  618. spin_lock(&tx_ring->tx_idr_lock);
  619. msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id);
  620. if (unlikely(!msdu)) {
  621. ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
  622. msdu_id);
  623. spin_unlock(&tx_ring->tx_idr_lock);
  624. continue;
  625. }
  626. spin_unlock(&tx_ring->tx_idr_lock);
  627. ar = ab->pdevs[mac_id].ar;
  628. if (atomic_dec_and_test(&ar->dp.num_tx_pending))
  629. wake_up(&ar->dp.tx_empty_waitq);
  630. ath11k_dp_tx_complete_msdu(ar, msdu, &ts);
  631. }
  632. }
  633. int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid,
  634. enum hal_reo_cmd_type type,
  635. struct ath11k_hal_reo_cmd *cmd,
  636. void (*cb)(struct ath11k_dp *, void *,
  637. enum hal_reo_cmd_status))
  638. {
  639. struct ath11k_dp *dp = &ab->dp;
  640. struct dp_reo_cmd *dp_cmd;
  641. struct hal_srng *cmd_ring;
  642. int cmd_num;
  643. if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
  644. return -ESHUTDOWN;
  645. cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
  646. cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
  647. /* cmd_num should start from 1, during failure return the error code */
  648. if (cmd_num < 0)
  649. return cmd_num;
  650. /* reo cmd ring descriptors has cmd_num starting from 1 */
  651. if (cmd_num == 0)
  652. return -EINVAL;
  653. if (!cb)
  654. return 0;
  655. /* Can this be optimized so that we keep the pending command list only
  656. * for tid delete command to free up the resource on the command status
  657. * indication?
  658. */
  659. dp_cmd = kzalloc_obj(*dp_cmd, GFP_ATOMIC);
  660. if (!dp_cmd)
  661. return -ENOMEM;
  662. memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid));
  663. dp_cmd->cmd_num = cmd_num;
  664. dp_cmd->handler = cb;
  665. spin_lock_bh(&dp->reo_cmd_lock);
  666. list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
  667. spin_unlock_bh(&dp->reo_cmd_lock);
  668. return 0;
  669. }
  670. static int
  671. ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab,
  672. int mac_id, u32 ring_id,
  673. enum hal_ring_type ring_type,
  674. enum htt_srng_ring_type *htt_ring_type,
  675. enum htt_srng_ring_id *htt_ring_id)
  676. {
  677. int lmac_ring_id_offset = 0;
  678. int ret = 0;
  679. switch (ring_type) {
  680. case HAL_RXDMA_BUF:
  681. lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC;
  682. /* for QCA6390, host fills rx buffer to fw and fw fills to
  683. * rxbuf ring for each rxdma
  684. */
  685. if (!ab->hw_params.rx_mac_buf_ring) {
  686. if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF +
  687. lmac_ring_id_offset) ||
  688. ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF +
  689. lmac_ring_id_offset))) {
  690. ret = -EINVAL;
  691. }
  692. *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
  693. *htt_ring_type = HTT_SW_TO_HW_RING;
  694. } else {
  695. if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) {
  696. *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
  697. *htt_ring_type = HTT_SW_TO_SW_RING;
  698. } else {
  699. *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
  700. *htt_ring_type = HTT_SW_TO_HW_RING;
  701. }
  702. }
  703. break;
  704. case HAL_RXDMA_DST:
  705. *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
  706. *htt_ring_type = HTT_HW_TO_SW_RING;
  707. break;
  708. case HAL_RXDMA_MONITOR_BUF:
  709. *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;
  710. *htt_ring_type = HTT_SW_TO_HW_RING;
  711. break;
  712. case HAL_RXDMA_MONITOR_STATUS:
  713. *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
  714. *htt_ring_type = HTT_SW_TO_HW_RING;
  715. break;
  716. case HAL_RXDMA_MONITOR_DST:
  717. *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;
  718. *htt_ring_type = HTT_HW_TO_SW_RING;
  719. break;
  720. case HAL_RXDMA_MONITOR_DESC:
  721. *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
  722. *htt_ring_type = HTT_SW_TO_HW_RING;
  723. break;
  724. default:
  725. ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
  726. ret = -EINVAL;
  727. }
  728. return ret;
  729. }
  730. int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
  731. int mac_id, enum hal_ring_type ring_type)
  732. {
  733. struct htt_srng_setup_cmd *cmd;
  734. struct hal_srng *srng = &ab->hal.srng_list[ring_id];
  735. struct hal_srng_params params;
  736. struct sk_buff *skb;
  737. u32 ring_entry_sz;
  738. int len = sizeof(*cmd);
  739. dma_addr_t hp_addr, tp_addr;
  740. enum htt_srng_ring_type htt_ring_type;
  741. enum htt_srng_ring_id htt_ring_id;
  742. int ret;
  743. skb = ath11k_htc_alloc_skb(ab, len);
  744. if (!skb)
  745. return -ENOMEM;
  746. memset(&params, 0, sizeof(params));
  747. ath11k_hal_srng_get_params(ab, srng, &params);
  748. hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng);
  749. tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng);
  750. ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
  751. ring_type, &htt_ring_type,
  752. &htt_ring_id);
  753. if (ret)
  754. goto err_free;
  755. skb_put(skb, len);
  756. cmd = (struct htt_srng_setup_cmd *)skb->data;
  757. cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE,
  758. HTT_H2T_MSG_TYPE_SRING_SETUP);
  759. if (htt_ring_type == HTT_SW_TO_HW_RING ||
  760. htt_ring_type == HTT_HW_TO_SW_RING)
  761. cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
  762. DP_SW2HW_MACID(mac_id));
  763. else
  764. cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
  765. mac_id);
  766. cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE,
  767. htt_ring_type);
  768. cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id);
  769. cmd->ring_base_addr_lo = params.ring_base_paddr &
  770. HAL_ADDR_LSB_REG_MASK;
  771. cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >>
  772. HAL_ADDR_MSB_REG_SHIFT;
  773. ret = ath11k_hal_srng_get_entrysize(ab, ring_type);
  774. if (ret < 0)
  775. goto err_free;
  776. ring_entry_sz = ret;
  777. ring_entry_sz >>= 2;
  778. cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE,
  779. ring_entry_sz);
  780. cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE,
  781. params.num_entries * ring_entry_sz);
  782. cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP,
  783. !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
  784. cmd->info1 |= FIELD_PREP(
  785. HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP,
  786. !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
  787. cmd->info1 |= FIELD_PREP(
  788. HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP,
  789. !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP));
  790. if (htt_ring_type == HTT_SW_TO_HW_RING)
  791. cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS;
  792. cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK;
  793. cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >>
  794. HAL_ADDR_MSB_REG_SHIFT;
  795. cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK;
  796. cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >>
  797. HAL_ADDR_MSB_REG_SHIFT;
  798. cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr);
  799. cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr);
  800. cmd->msi_data = params.msi_data;
  801. cmd->intr_info = FIELD_PREP(
  802. HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH,
  803. params.intr_batch_cntr_thres_entries * ring_entry_sz);
  804. cmd->intr_info |= FIELD_PREP(
  805. HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH,
  806. params.intr_timer_thres_us >> 3);
  807. cmd->info2 = 0;
  808. if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
  809. cmd->info2 = FIELD_PREP(
  810. HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH,
  811. params.low_threshold);
  812. }
  813. ath11k_dbg(ab, ATH11K_DBG_DP_TX,
  814. "htt srng setup msi_addr_lo 0x%x msi_addr_hi 0x%x msi_data 0x%x ring_id %d ring_type %d intr_info 0x%x flags 0x%x\n",
  815. cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
  816. cmd->msi_data, ring_id, ring_type, cmd->intr_info, cmd->info2);
  817. ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
  818. if (ret)
  819. goto err_free;
  820. return 0;
  821. err_free:
  822. dev_kfree_skb_any(skb);
  823. return ret;
  824. }
  825. #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
  826. int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab)
  827. {
  828. struct ath11k_dp *dp = &ab->dp;
  829. struct sk_buff *skb;
  830. struct htt_ver_req_cmd *cmd;
  831. int len = sizeof(*cmd);
  832. int ret;
  833. init_completion(&dp->htt_tgt_version_received);
  834. skb = ath11k_htc_alloc_skb(ab, len);
  835. if (!skb)
  836. return -ENOMEM;
  837. skb_put(skb, len);
  838. cmd = (struct htt_ver_req_cmd *)skb->data;
  839. cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID,
  840. HTT_H2T_MSG_TYPE_VERSION_REQ);
  841. ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
  842. if (ret) {
  843. dev_kfree_skb_any(skb);
  844. return ret;
  845. }
  846. ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
  847. HTT_TARGET_VERSION_TIMEOUT_HZ);
  848. if (ret == 0) {
  849. ath11k_warn(ab, "htt target version request timed out\n");
  850. return -ETIMEDOUT;
  851. }
  852. if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
  853. ath11k_err(ab, "unsupported htt major version %d supported version is %d\n",
  854. dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
  855. return -EOPNOTSUPP;
  856. }
  857. return 0;
  858. }
  859. int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask)
  860. {
  861. struct ath11k_base *ab = ar->ab;
  862. struct ath11k_dp *dp = &ab->dp;
  863. struct sk_buff *skb;
  864. struct htt_ppdu_stats_cfg_cmd *cmd;
  865. int len = sizeof(*cmd);
  866. u8 pdev_mask;
  867. int ret;
  868. int i;
  869. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  870. skb = ath11k_htc_alloc_skb(ab, len);
  871. if (!skb)
  872. return -ENOMEM;
  873. skb_put(skb, len);
  874. cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
  875. cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE,
  876. HTT_H2T_MSG_TYPE_PPDU_STATS_CFG);
  877. pdev_mask = 1 << (ar->pdev_idx + i);
  878. cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask);
  879. cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask);
  880. ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
  881. if (ret) {
  882. dev_kfree_skb_any(skb);
  883. return ret;
  884. }
  885. }
  886. return 0;
  887. }
  888. int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id,
  889. int mac_id, enum hal_ring_type ring_type,
  890. int rx_buf_size,
  891. struct htt_rx_ring_tlv_filter *tlv_filter)
  892. {
  893. struct htt_rx_ring_selection_cfg_cmd *cmd;
  894. struct hal_srng *srng = &ab->hal.srng_list[ring_id];
  895. struct hal_srng_params params;
  896. struct sk_buff *skb;
  897. int len = sizeof(*cmd);
  898. enum htt_srng_ring_type htt_ring_type;
  899. enum htt_srng_ring_id htt_ring_id;
  900. int ret;
  901. skb = ath11k_htc_alloc_skb(ab, len);
  902. if (!skb)
  903. return -ENOMEM;
  904. memset(&params, 0, sizeof(params));
  905. ath11k_hal_srng_get_params(ab, srng, &params);
  906. ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
  907. ring_type, &htt_ring_type,
  908. &htt_ring_id);
  909. if (ret)
  910. goto err_free;
  911. skb_put(skb, len);
  912. cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
  913. cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE,
  914. HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG);
  915. if (htt_ring_type == HTT_SW_TO_HW_RING ||
  916. htt_ring_type == HTT_HW_TO_SW_RING)
  917. cmd->info0 |=
  918. FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
  919. DP_SW2HW_MACID(mac_id));
  920. else
  921. cmd->info0 |=
  922. FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
  923. mac_id);
  924. cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID,
  925. htt_ring_id);
  926. cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS,
  927. !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
  928. cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS,
  929. !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
  930. cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE,
  931. rx_buf_size);
  932. cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0;
  933. cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1;
  934. cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2;
  935. cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3;
  936. cmd->rx_filter_tlv = tlv_filter->rx_filter;
  937. ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
  938. if (ret)
  939. goto err_free;
  940. return 0;
  941. err_free:
  942. dev_kfree_skb_any(skb);
  943. return ret;
  944. }
  945. int
  946. ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type,
  947. struct htt_ext_stats_cfg_params *cfg_params,
  948. u64 cookie)
  949. {
  950. struct ath11k_base *ab = ar->ab;
  951. struct ath11k_dp *dp = &ab->dp;
  952. struct sk_buff *skb;
  953. struct htt_ext_stats_cfg_cmd *cmd;
  954. u32 pdev_id;
  955. int len = sizeof(*cmd);
  956. int ret;
  957. skb = ath11k_htc_alloc_skb(ab, len);
  958. if (!skb)
  959. return -ENOMEM;
  960. skb_put(skb, len);
  961. cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
  962. memset(cmd, 0, sizeof(*cmd));
  963. cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
  964. if (ab->hw_params.single_pdev_only)
  965. pdev_id = ath11k_mac_get_target_pdev_id(ar);
  966. else
  967. pdev_id = ar->pdev->pdev_id;
  968. cmd->hdr.pdev_mask = 1 << pdev_id;
  969. cmd->hdr.stats_type = type;
  970. cmd->cfg_param0 = cfg_params->cfg0;
  971. cmd->cfg_param1 = cfg_params->cfg1;
  972. cmd->cfg_param2 = cfg_params->cfg2;
  973. cmd->cfg_param3 = cfg_params->cfg3;
  974. cmd->cookie_lsb = lower_32_bits(cookie);
  975. cmd->cookie_msb = upper_32_bits(cookie);
  976. ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
  977. if (ret) {
  978. ath11k_warn(ab, "failed to send htt type stats request: %d",
  979. ret);
  980. dev_kfree_skb_any(skb);
  981. return ret;
  982. }
  983. return 0;
  984. }
  985. int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset)
  986. {
  987. struct ath11k_pdev_dp *dp = &ar->dp;
  988. struct ath11k_base *ab = ar->ab;
  989. struct htt_rx_ring_tlv_filter tlv_filter = {};
  990. int ret = 0, ring_id = 0, i;
  991. if (ab->hw_params.full_monitor_mode) {
  992. ret = ath11k_dp_tx_htt_rx_full_mon_setup(ab,
  993. dp->mac_id, !reset);
  994. if (ret < 0) {
  995. ath11k_err(ab, "failed to setup full monitor %d\n", ret);
  996. return ret;
  997. }
  998. }
  999. ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
  1000. if (!reset) {
  1001. tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
  1002. tlv_filter.pkt_filter_flags0 =
  1003. HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
  1004. HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
  1005. tlv_filter.pkt_filter_flags1 =
  1006. HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
  1007. HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
  1008. tlv_filter.pkt_filter_flags2 =
  1009. HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
  1010. HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
  1011. tlv_filter.pkt_filter_flags3 =
  1012. HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
  1013. HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
  1014. HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
  1015. HTT_RX_MON_MO_DATA_FILTER_FLASG3;
  1016. }
  1017. if (ab->hw_params.rxdma1_enable) {
  1018. ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id,
  1019. HAL_RXDMA_MONITOR_BUF,
  1020. DP_RXDMA_REFILL_RING_SIZE,
  1021. &tlv_filter);
  1022. } else if (!reset) {
  1023. /* set in monitor mode only */
  1024. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  1025. ring_id = dp->rx_mac_buf_ring[i].ring_id;
  1026. ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
  1027. dp->mac_id + i,
  1028. HAL_RXDMA_BUF,
  1029. 1024,
  1030. &tlv_filter);
  1031. }
  1032. }
  1033. if (ret)
  1034. return ret;
  1035. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  1036. ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
  1037. if (!reset) {
  1038. tlv_filter.rx_filter =
  1039. HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING;
  1040. } else {
  1041. tlv_filter = ath11k_mac_mon_status_filter_default;
  1042. if (ath11k_debugfs_is_extd_rx_stats_enabled(ar))
  1043. tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar);
  1044. }
  1045. ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id,
  1046. dp->mac_id + i,
  1047. HAL_RXDMA_MONITOR_STATUS,
  1048. DP_RXDMA_REFILL_RING_SIZE,
  1049. &tlv_filter);
  1050. }
  1051. if (!ar->ab->hw_params.rxdma1_enable)
  1052. mod_timer(&ar->ab->mon_reap_timer, jiffies +
  1053. msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
  1054. return ret;
  1055. }
  1056. int ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base *ab, int mac_id,
  1057. bool config)
  1058. {
  1059. struct htt_rx_full_monitor_mode_cfg_cmd *cmd;
  1060. struct sk_buff *skb;
  1061. int ret, len = sizeof(*cmd);
  1062. skb = ath11k_htc_alloc_skb(ab, len);
  1063. if (!skb)
  1064. return -ENOMEM;
  1065. skb_put(skb, len);
  1066. cmd = (struct htt_rx_full_monitor_mode_cfg_cmd *)skb->data;
  1067. memset(cmd, 0, sizeof(*cmd));
  1068. cmd->info0 = FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE,
  1069. HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE);
  1070. cmd->info0 |= FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID, mac_id);
  1071. cmd->cfg = HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE |
  1072. FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING,
  1073. HTT_RX_MON_RING_SW);
  1074. if (config) {
  1075. cmd->cfg |= HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END |
  1076. HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END;
  1077. }
  1078. ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
  1079. if (ret)
  1080. goto err_free;
  1081. return 0;
  1082. err_free:
  1083. dev_kfree_skb_any(skb);
  1084. return ret;
  1085. }