smsc75xx.c 57 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /***************************************************************************
  3. *
  4. * Copyright (C) 2007-2010 SMSC
  5. *
  6. *****************************************************************************/
  7. #include <linux/module.h>
  8. #include <linux/kmod.h>
  9. #include <linux/netdevice.h>
  10. #include <linux/etherdevice.h>
  11. #include <linux/ethtool.h>
  12. #include <linux/mii.h>
  13. #include <linux/usb.h>
  14. #include <linux/bitrev.h>
  15. #include <linux/crc16.h>
  16. #include <linux/crc32.h>
  17. #include <linux/usb/usbnet.h>
  18. #include <linux/slab.h>
  19. #include <linux/of_net.h>
  20. #include "smsc75xx.h"
  21. #define SMSC_CHIPNAME "smsc75xx"
  22. #define HS_USB_PKT_SIZE (512)
  23. #define FS_USB_PKT_SIZE (64)
  24. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  25. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  26. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  27. #define MAX_SINGLE_PACKET_SIZE (9000)
  28. #define LAN75XX_EEPROM_MAGIC (0x7500)
  29. #define EEPROM_MAC_OFFSET (0x01)
  30. #define DEFAULT_TX_CSUM_ENABLE (true)
  31. #define DEFAULT_RX_CSUM_ENABLE (true)
  32. #define SMSC75XX_INTERNAL_PHY_ID (1)
  33. #define SMSC75XX_TX_OVERHEAD (8)
  34. #define MAX_RX_FIFO_SIZE (20 * 1024)
  35. #define MAX_TX_FIFO_SIZE (12 * 1024)
  36. #define USB_VENDOR_ID_SMSC (0x0424)
  37. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  38. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  39. #define RXW_PADDING 2
  40. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  41. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  42. #define SUSPEND_SUSPEND0 (0x01)
  43. #define SUSPEND_SUSPEND1 (0x02)
  44. #define SUSPEND_SUSPEND2 (0x04)
  45. #define SUSPEND_SUSPEND3 (0x08)
  46. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  47. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  48. struct smsc75xx_priv {
  49. struct usbnet *dev;
  50. u32 rfe_ctl;
  51. u32 wolopts;
  52. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  53. struct mutex dataport_mutex;
  54. spinlock_t rfe_ctl_lock;
  55. struct work_struct set_multicast;
  56. u8 suspend_flags;
  57. };
  58. static bool turbo_mode = true;
  59. module_param(turbo_mode, bool, 0644);
  60. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  61. static int smsc75xx_link_ok_nopm(struct usbnet *dev);
  62. static int smsc75xx_phy_gig_workaround(struct usbnet *dev);
  63. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  64. u32 *data, int in_pm)
  65. {
  66. u32 buf;
  67. int ret;
  68. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  69. BUG_ON(!dev);
  70. if (!in_pm)
  71. fn = usbnet_read_cmd;
  72. else
  73. fn = usbnet_read_cmd_nopm;
  74. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  75. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  76. 0, index, &buf, 4);
  77. if (unlikely(ret < 4)) {
  78. ret = ret < 0 ? ret : -ENODATA;
  79. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  80. index, ret);
  81. return ret;
  82. }
  83. le32_to_cpus(&buf);
  84. *data = buf;
  85. return ret;
  86. }
  87. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  88. u32 data, int in_pm)
  89. {
  90. u32 buf;
  91. int ret;
  92. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  93. BUG_ON(!dev);
  94. if (!in_pm)
  95. fn = usbnet_write_cmd;
  96. else
  97. fn = usbnet_write_cmd_nopm;
  98. buf = data;
  99. cpu_to_le32s(&buf);
  100. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  101. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  102. 0, index, &buf, 4);
  103. if (unlikely(ret < 0))
  104. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  105. index, ret);
  106. return ret;
  107. }
  108. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  109. u32 *data)
  110. {
  111. return __smsc75xx_read_reg(dev, index, data, 1);
  112. }
  113. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  114. u32 data)
  115. {
  116. return __smsc75xx_write_reg(dev, index, data, 1);
  117. }
  118. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  119. u32 *data)
  120. {
  121. return __smsc75xx_read_reg(dev, index, data, 0);
  122. }
  123. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  124. u32 data)
  125. {
  126. return __smsc75xx_write_reg(dev, index, data, 0);
  127. }
  128. /* Loop until the read is completed with timeout
  129. * called with phy_mutex held */
  130. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  131. int in_pm)
  132. {
  133. unsigned long start_time = jiffies;
  134. u32 val;
  135. int ret;
  136. do {
  137. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  138. if (ret < 0) {
  139. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  140. return ret;
  141. }
  142. if (!(val & MII_ACCESS_BUSY))
  143. return 0;
  144. } while (!time_after(jiffies, start_time + HZ));
  145. return -EIO;
  146. }
  147. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  148. int in_pm)
  149. {
  150. struct usbnet *dev = netdev_priv(netdev);
  151. u32 val, addr;
  152. int ret;
  153. mutex_lock(&dev->phy_mutex);
  154. /* confirm MII not busy */
  155. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  156. if (ret < 0) {
  157. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  158. goto done;
  159. }
  160. /* set the address, index & direction (read from PHY) */
  161. phy_id &= dev->mii.phy_id_mask;
  162. idx &= dev->mii.reg_num_mask;
  163. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  164. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  165. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  166. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  167. if (ret < 0) {
  168. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  169. goto done;
  170. }
  171. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  172. if (ret < 0) {
  173. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  174. goto done;
  175. }
  176. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  177. if (ret < 0) {
  178. netdev_warn(dev->net, "Error reading MII_DATA\n");
  179. goto done;
  180. }
  181. ret = (u16)(val & 0xFFFF);
  182. done:
  183. mutex_unlock(&dev->phy_mutex);
  184. return ret;
  185. }
  186. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  187. int idx, int regval, int in_pm)
  188. {
  189. struct usbnet *dev = netdev_priv(netdev);
  190. u32 val, addr;
  191. int ret;
  192. mutex_lock(&dev->phy_mutex);
  193. /* confirm MII not busy */
  194. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  195. if (ret < 0) {
  196. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  197. goto done;
  198. }
  199. val = regval;
  200. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  201. if (ret < 0) {
  202. netdev_warn(dev->net, "Error writing MII_DATA\n");
  203. goto done;
  204. }
  205. /* set the address, index & direction (write to PHY) */
  206. phy_id &= dev->mii.phy_id_mask;
  207. idx &= dev->mii.reg_num_mask;
  208. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  209. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  210. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  211. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  212. if (ret < 0) {
  213. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  214. goto done;
  215. }
  216. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  217. if (ret < 0) {
  218. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  219. goto done;
  220. }
  221. done:
  222. mutex_unlock(&dev->phy_mutex);
  223. }
  224. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  225. int idx)
  226. {
  227. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  228. }
  229. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  230. int idx, int regval)
  231. {
  232. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  233. }
  234. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  235. {
  236. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  237. }
  238. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  239. int regval)
  240. {
  241. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  242. }
  243. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  244. {
  245. unsigned long start_time = jiffies;
  246. u32 val;
  247. int ret;
  248. do {
  249. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  250. if (ret < 0) {
  251. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  252. return ret;
  253. }
  254. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  255. break;
  256. udelay(40);
  257. } while (!time_after(jiffies, start_time + HZ));
  258. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  259. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  260. return -EIO;
  261. }
  262. return 0;
  263. }
  264. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  265. {
  266. unsigned long start_time = jiffies;
  267. u32 val;
  268. int ret;
  269. do {
  270. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  271. if (ret < 0) {
  272. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  273. return ret;
  274. }
  275. if (!(val & E2P_CMD_BUSY))
  276. return 0;
  277. udelay(40);
  278. } while (!time_after(jiffies, start_time + HZ));
  279. netdev_warn(dev->net, "EEPROM is busy\n");
  280. return -EIO;
  281. }
  282. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  283. u8 *data)
  284. {
  285. u32 val;
  286. int i, ret;
  287. BUG_ON(!dev);
  288. BUG_ON(!data);
  289. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  290. if (ret)
  291. return ret;
  292. for (i = 0; i < length; i++) {
  293. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  294. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  295. if (ret < 0) {
  296. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  297. return ret;
  298. }
  299. ret = smsc75xx_wait_eeprom(dev);
  300. if (ret < 0)
  301. return ret;
  302. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  303. if (ret < 0) {
  304. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  305. return ret;
  306. }
  307. data[i] = val & 0xFF;
  308. offset++;
  309. }
  310. return 0;
  311. }
  312. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  313. u8 *data)
  314. {
  315. u32 val;
  316. int i, ret;
  317. BUG_ON(!dev);
  318. BUG_ON(!data);
  319. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  320. if (ret)
  321. return ret;
  322. /* Issue write/erase enable command */
  323. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  324. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  325. if (ret < 0) {
  326. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  327. return ret;
  328. }
  329. ret = smsc75xx_wait_eeprom(dev);
  330. if (ret < 0)
  331. return ret;
  332. for (i = 0; i < length; i++) {
  333. /* Fill data register */
  334. val = data[i];
  335. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  336. if (ret < 0) {
  337. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  338. return ret;
  339. }
  340. /* Send "write" command */
  341. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  342. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  343. if (ret < 0) {
  344. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  345. return ret;
  346. }
  347. ret = smsc75xx_wait_eeprom(dev);
  348. if (ret < 0)
  349. return ret;
  350. offset++;
  351. }
  352. return 0;
  353. }
  354. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  355. {
  356. int i, ret;
  357. for (i = 0; i < 100; i++) {
  358. u32 dp_sel;
  359. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  360. if (ret < 0) {
  361. netdev_warn(dev->net, "Error reading DP_SEL\n");
  362. return ret;
  363. }
  364. if (dp_sel & DP_SEL_DPRDY)
  365. return 0;
  366. udelay(40);
  367. }
  368. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  369. return -EIO;
  370. }
  371. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  372. u32 length, u32 *buf)
  373. {
  374. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  375. u32 dp_sel;
  376. int i, ret;
  377. mutex_lock(&pdata->dataport_mutex);
  378. ret = smsc75xx_dataport_wait_not_busy(dev);
  379. if (ret < 0) {
  380. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  381. goto done;
  382. }
  383. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  384. if (ret < 0) {
  385. netdev_warn(dev->net, "Error reading DP_SEL\n");
  386. goto done;
  387. }
  388. dp_sel &= ~DP_SEL_RSEL;
  389. dp_sel |= ram_select;
  390. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  391. if (ret < 0) {
  392. netdev_warn(dev->net, "Error writing DP_SEL\n");
  393. goto done;
  394. }
  395. for (i = 0; i < length; i++) {
  396. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  397. if (ret < 0) {
  398. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  399. goto done;
  400. }
  401. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  402. if (ret < 0) {
  403. netdev_warn(dev->net, "Error writing DP_DATA\n");
  404. goto done;
  405. }
  406. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  407. if (ret < 0) {
  408. netdev_warn(dev->net, "Error writing DP_CMD\n");
  409. goto done;
  410. }
  411. ret = smsc75xx_dataport_wait_not_busy(dev);
  412. if (ret < 0) {
  413. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  414. goto done;
  415. }
  416. }
  417. done:
  418. mutex_unlock(&pdata->dataport_mutex);
  419. return ret;
  420. }
  421. /* returns hash bit number for given MAC address */
  422. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  423. {
  424. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  425. }
  426. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  427. {
  428. struct smsc75xx_priv *pdata =
  429. container_of(param, struct smsc75xx_priv, set_multicast);
  430. struct usbnet *dev = pdata->dev;
  431. int ret;
  432. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  433. pdata->rfe_ctl);
  434. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  435. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  436. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  437. if (ret < 0)
  438. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  439. }
  440. static void smsc75xx_set_multicast(struct net_device *netdev)
  441. {
  442. struct usbnet *dev = netdev_priv(netdev);
  443. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  444. unsigned long flags;
  445. int i;
  446. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  447. pdata->rfe_ctl &=
  448. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  449. pdata->rfe_ctl |= RFE_CTL_AB;
  450. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  451. pdata->multicast_hash_table[i] = 0;
  452. if (dev->net->flags & IFF_PROMISC) {
  453. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  454. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  455. } else if (dev->net->flags & IFF_ALLMULTI) {
  456. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  457. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  458. } else if (!netdev_mc_empty(dev->net)) {
  459. struct netdev_hw_addr *ha;
  460. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  461. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  462. netdev_for_each_mc_addr(ha, netdev) {
  463. u32 bitnum = smsc75xx_hash(ha->addr);
  464. pdata->multicast_hash_table[bitnum / 32] |=
  465. (1 << (bitnum % 32));
  466. }
  467. } else {
  468. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  469. pdata->rfe_ctl |= RFE_CTL_DPF;
  470. }
  471. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  472. /* defer register writes to a sleepable context */
  473. schedule_work(&pdata->set_multicast);
  474. }
  475. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  476. u16 lcladv, u16 rmtadv)
  477. {
  478. u32 flow = 0, fct_flow = 0;
  479. int ret;
  480. if (duplex == DUPLEX_FULL) {
  481. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  482. if (cap & FLOW_CTRL_TX) {
  483. flow = (FLOW_TX_FCEN | 0xFFFF);
  484. /* set fct_flow thresholds to 20% and 80% */
  485. fct_flow = (8 << 8) | 32;
  486. }
  487. if (cap & FLOW_CTRL_RX)
  488. flow |= FLOW_RX_FCEN;
  489. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  490. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  491. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  492. } else {
  493. netif_dbg(dev, link, dev->net, "half duplex\n");
  494. }
  495. ret = smsc75xx_write_reg(dev, FLOW, flow);
  496. if (ret < 0) {
  497. netdev_warn(dev->net, "Error writing FLOW\n");
  498. return ret;
  499. }
  500. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  501. if (ret < 0) {
  502. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  503. return ret;
  504. }
  505. return 0;
  506. }
  507. static int smsc75xx_link_reset(struct usbnet *dev)
  508. {
  509. struct mii_if_info *mii = &dev->mii;
  510. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  511. u16 lcladv, rmtadv;
  512. int ret;
  513. /* write to clear phy interrupt status */
  514. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  515. PHY_INT_SRC_CLEAR_ALL);
  516. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  517. if (ret < 0) {
  518. netdev_warn(dev->net, "Error writing INT_STS\n");
  519. return ret;
  520. }
  521. mii_check_media(mii, 1, 1);
  522. mii_ethtool_gset(&dev->mii, &ecmd);
  523. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  524. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  525. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  526. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  527. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  528. }
  529. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  530. {
  531. u32 intdata;
  532. if (urb->actual_length != 4) {
  533. netdev_warn(dev->net, "unexpected urb length %d\n",
  534. urb->actual_length);
  535. return;
  536. }
  537. intdata = get_unaligned_le32(urb->transfer_buffer);
  538. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  539. if (intdata & INT_ENP_PHY_INT)
  540. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  541. else
  542. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  543. intdata);
  544. }
  545. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  546. {
  547. return MAX_EEPROM_SIZE;
  548. }
  549. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  550. struct ethtool_eeprom *ee, u8 *data)
  551. {
  552. struct usbnet *dev = netdev_priv(netdev);
  553. ee->magic = LAN75XX_EEPROM_MAGIC;
  554. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  555. }
  556. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  557. struct ethtool_eeprom *ee, u8 *data)
  558. {
  559. struct usbnet *dev = netdev_priv(netdev);
  560. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  561. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  562. ee->magic);
  563. return -EINVAL;
  564. }
  565. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  566. }
  567. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  568. struct ethtool_wolinfo *wolinfo)
  569. {
  570. struct usbnet *dev = netdev_priv(net);
  571. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  572. wolinfo->supported = SUPPORTED_WAKE;
  573. wolinfo->wolopts = pdata->wolopts;
  574. }
  575. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  576. struct ethtool_wolinfo *wolinfo)
  577. {
  578. struct usbnet *dev = netdev_priv(net);
  579. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  580. int ret;
  581. if (wolinfo->wolopts & ~SUPPORTED_WAKE)
  582. return -EINVAL;
  583. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  584. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  585. if (ret < 0)
  586. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  587. return ret;
  588. }
  589. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  590. .get_link = usbnet_get_link,
  591. .nway_reset = usbnet_nway_reset,
  592. .get_drvinfo = usbnet_get_drvinfo,
  593. .get_msglevel = usbnet_get_msglevel,
  594. .set_msglevel = usbnet_set_msglevel,
  595. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  596. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  597. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  598. .get_wol = smsc75xx_ethtool_get_wol,
  599. .set_wol = smsc75xx_ethtool_set_wol,
  600. .get_link_ksettings = usbnet_get_link_ksettings_mii,
  601. .set_link_ksettings = usbnet_set_link_ksettings_mii,
  602. };
  603. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  604. {
  605. if (!netif_running(netdev))
  606. return -EINVAL;
  607. return usbnet_mii_ioctl(netdev, rq, cmd);
  608. }
  609. static void smsc75xx_init_mac_address(struct usbnet *dev)
  610. {
  611. u8 addr[ETH_ALEN];
  612. /* maybe the boot loader passed the MAC address in devicetree */
  613. if (!platform_get_ethdev_address(&dev->udev->dev, dev->net)) {
  614. if (is_valid_ether_addr(dev->net->dev_addr)) {
  615. /* device tree values are valid so use them */
  616. netif_dbg(dev, ifup, dev->net, "MAC address read from the device tree\n");
  617. return;
  618. }
  619. }
  620. /* try reading mac address from EEPROM */
  621. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, addr) == 0) {
  622. eth_hw_addr_set(dev->net, addr);
  623. if (is_valid_ether_addr(dev->net->dev_addr)) {
  624. /* eeprom values are valid so use them */
  625. netif_dbg(dev, ifup, dev->net,
  626. "MAC address read from EEPROM\n");
  627. return;
  628. }
  629. }
  630. /* no useful static MAC address found. generate a random one */
  631. eth_hw_addr_random(dev->net);
  632. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  633. }
  634. static int smsc75xx_set_mac_address(struct usbnet *dev)
  635. {
  636. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  637. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  638. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  639. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  640. if (ret < 0) {
  641. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  642. return ret;
  643. }
  644. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  645. if (ret < 0) {
  646. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  647. return ret;
  648. }
  649. addr_hi |= ADDR_FILTX_FB_VALID;
  650. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  651. if (ret < 0) {
  652. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  653. return ret;
  654. }
  655. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  656. if (ret < 0)
  657. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  658. return ret;
  659. }
  660. static int smsc75xx_phy_initialize(struct usbnet *dev)
  661. {
  662. int bmcr, ret, timeout = 0;
  663. /* Initialize MII structure */
  664. dev->mii.dev = dev->net;
  665. dev->mii.mdio_read = smsc75xx_mdio_read;
  666. dev->mii.mdio_write = smsc75xx_mdio_write;
  667. dev->mii.phy_id_mask = 0x1f;
  668. dev->mii.reg_num_mask = 0x1f;
  669. dev->mii.supports_gmii = 1;
  670. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  671. /* reset phy and wait for reset to complete */
  672. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  673. do {
  674. msleep(10);
  675. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  676. if (bmcr < 0) {
  677. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  678. return bmcr;
  679. }
  680. timeout++;
  681. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  682. if (timeout >= 100) {
  683. netdev_warn(dev->net, "timeout on PHY Reset\n");
  684. return -EIO;
  685. }
  686. /* phy workaround for gig link */
  687. smsc75xx_phy_gig_workaround(dev);
  688. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  689. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  690. ADVERTISE_PAUSE_ASYM);
  691. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  692. ADVERTISE_1000FULL);
  693. /* read and write to clear phy interrupt status */
  694. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  695. if (ret < 0) {
  696. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  697. return ret;
  698. }
  699. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  700. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  701. PHY_INT_MASK_DEFAULT);
  702. mii_nway_restart(&dev->mii);
  703. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  704. return 0;
  705. }
  706. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  707. {
  708. int ret = 0;
  709. u32 buf;
  710. bool rxenabled;
  711. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  712. if (ret < 0) {
  713. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  714. return ret;
  715. }
  716. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  717. if (rxenabled) {
  718. buf &= ~MAC_RX_RXEN;
  719. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  720. if (ret < 0) {
  721. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  722. return ret;
  723. }
  724. }
  725. /* add 4 to size for FCS */
  726. buf &= ~MAC_RX_MAX_SIZE;
  727. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  728. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  729. if (ret < 0) {
  730. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  731. return ret;
  732. }
  733. if (rxenabled) {
  734. buf |= MAC_RX_RXEN;
  735. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  736. if (ret < 0) {
  737. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  738. return ret;
  739. }
  740. }
  741. return 0;
  742. }
  743. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  744. {
  745. struct usbnet *dev = netdev_priv(netdev);
  746. int ret;
  747. ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
  748. if (ret < 0) {
  749. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  750. return ret;
  751. }
  752. return usbnet_change_mtu(netdev, new_mtu);
  753. }
  754. /* Enable or disable Rx checksum offload engine */
  755. static int smsc75xx_set_features(struct net_device *netdev,
  756. netdev_features_t features)
  757. {
  758. struct usbnet *dev = netdev_priv(netdev);
  759. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  760. unsigned long flags;
  761. int ret;
  762. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  763. if (features & NETIF_F_RXCSUM)
  764. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  765. else
  766. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  767. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  768. /* it's racing here! */
  769. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  770. if (ret < 0) {
  771. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  772. return ret;
  773. }
  774. return 0;
  775. }
  776. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  777. {
  778. int timeout = 0;
  779. do {
  780. u32 buf;
  781. int ret;
  782. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  783. if (ret < 0) {
  784. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  785. return ret;
  786. }
  787. if (buf & PMT_CTL_DEV_RDY)
  788. return 0;
  789. msleep(10);
  790. timeout++;
  791. } while (timeout < 100);
  792. netdev_warn(dev->net, "timeout waiting for device ready\n");
  793. return -EIO;
  794. }
  795. static int smsc75xx_phy_gig_workaround(struct usbnet *dev)
  796. {
  797. struct mii_if_info *mii = &dev->mii;
  798. int ret = 0, timeout = 0;
  799. u32 buf, link_up = 0;
  800. /* Set the phy in Gig loopback */
  801. smsc75xx_mdio_write(dev->net, mii->phy_id, MII_BMCR, 0x4040);
  802. /* Wait for the link up */
  803. do {
  804. link_up = smsc75xx_link_ok_nopm(dev);
  805. usleep_range(10000, 20000);
  806. timeout++;
  807. } while ((!link_up) && (timeout < 1000));
  808. if (timeout >= 1000) {
  809. netdev_warn(dev->net, "Timeout waiting for PHY link up\n");
  810. return -EIO;
  811. }
  812. /* phy reset */
  813. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  814. if (ret < 0) {
  815. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  816. return ret;
  817. }
  818. buf |= PMT_CTL_PHY_RST;
  819. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  820. if (ret < 0) {
  821. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  822. return ret;
  823. }
  824. timeout = 0;
  825. do {
  826. usleep_range(10000, 20000);
  827. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  828. if (ret < 0) {
  829. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n",
  830. ret);
  831. return ret;
  832. }
  833. timeout++;
  834. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  835. if (timeout >= 100) {
  836. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  837. return -EIO;
  838. }
  839. return 0;
  840. }
  841. static int smsc75xx_reset(struct usbnet *dev)
  842. {
  843. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  844. u32 buf;
  845. int ret = 0, timeout;
  846. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  847. ret = smsc75xx_wait_ready(dev, 0);
  848. if (ret < 0) {
  849. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  850. return ret;
  851. }
  852. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  853. if (ret < 0) {
  854. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  855. return ret;
  856. }
  857. buf |= HW_CFG_LRST;
  858. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  859. if (ret < 0) {
  860. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  861. return ret;
  862. }
  863. timeout = 0;
  864. do {
  865. msleep(10);
  866. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  867. if (ret < 0) {
  868. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  869. return ret;
  870. }
  871. timeout++;
  872. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  873. if (timeout >= 100) {
  874. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  875. return -EIO;
  876. }
  877. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  878. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  879. if (ret < 0) {
  880. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  881. return ret;
  882. }
  883. buf |= PMT_CTL_PHY_RST;
  884. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  885. if (ret < 0) {
  886. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  887. return ret;
  888. }
  889. timeout = 0;
  890. do {
  891. msleep(10);
  892. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  893. if (ret < 0) {
  894. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  895. return ret;
  896. }
  897. timeout++;
  898. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  899. if (timeout >= 100) {
  900. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  901. return -EIO;
  902. }
  903. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  904. ret = smsc75xx_set_mac_address(dev);
  905. if (ret < 0) {
  906. netdev_warn(dev->net, "Failed to set mac address\n");
  907. return ret;
  908. }
  909. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  910. dev->net->dev_addr);
  911. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  912. if (ret < 0) {
  913. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  914. return ret;
  915. }
  916. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  917. buf);
  918. buf |= HW_CFG_BIR;
  919. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  920. if (ret < 0) {
  921. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  922. return ret;
  923. }
  924. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  925. if (ret < 0) {
  926. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  927. return ret;
  928. }
  929. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  930. buf);
  931. if (!turbo_mode) {
  932. buf = 0;
  933. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  934. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  935. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  936. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  937. } else {
  938. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  939. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  940. }
  941. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  942. (ulong)dev->rx_urb_size);
  943. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  944. if (ret < 0) {
  945. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  946. return ret;
  947. }
  948. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  949. if (ret < 0) {
  950. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  951. return ret;
  952. }
  953. netif_dbg(dev, ifup, dev->net,
  954. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  955. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  956. if (ret < 0) {
  957. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  958. return ret;
  959. }
  960. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  961. if (ret < 0) {
  962. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  963. return ret;
  964. }
  965. netif_dbg(dev, ifup, dev->net,
  966. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  967. if (turbo_mode) {
  968. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  969. if (ret < 0) {
  970. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  971. return ret;
  972. }
  973. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  974. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  975. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  976. if (ret < 0) {
  977. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  978. return ret;
  979. }
  980. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  981. if (ret < 0) {
  982. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  983. return ret;
  984. }
  985. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  986. }
  987. /* set FIFO sizes */
  988. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  989. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  990. if (ret < 0) {
  991. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  992. return ret;
  993. }
  994. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  995. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  996. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  997. if (ret < 0) {
  998. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  999. return ret;
  1000. }
  1001. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  1002. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  1003. if (ret < 0) {
  1004. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  1005. return ret;
  1006. }
  1007. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  1008. if (ret < 0) {
  1009. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  1010. return ret;
  1011. }
  1012. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  1013. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  1014. if (ret < 0) {
  1015. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  1016. return ret;
  1017. }
  1018. /* only set default GPIO/LED settings if no EEPROM is detected */
  1019. if (!(buf & E2P_CMD_LOADED)) {
  1020. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  1021. if (ret < 0) {
  1022. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  1023. return ret;
  1024. }
  1025. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  1026. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  1027. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  1028. if (ret < 0) {
  1029. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  1030. return ret;
  1031. }
  1032. }
  1033. ret = smsc75xx_write_reg(dev, FLOW, 0);
  1034. if (ret < 0) {
  1035. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  1036. return ret;
  1037. }
  1038. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  1039. if (ret < 0) {
  1040. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  1041. return ret;
  1042. }
  1043. /* Don't need rfe_ctl_lock during initialisation */
  1044. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1045. if (ret < 0) {
  1046. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1047. return ret;
  1048. }
  1049. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1050. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1051. if (ret < 0) {
  1052. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1053. return ret;
  1054. }
  1055. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1056. if (ret < 0) {
  1057. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1058. return ret;
  1059. }
  1060. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1061. pdata->rfe_ctl);
  1062. /* Enable or disable checksum offload engines */
  1063. smsc75xx_set_features(dev->net, dev->net->features);
  1064. smsc75xx_set_multicast(dev->net);
  1065. ret = smsc75xx_phy_initialize(dev);
  1066. if (ret < 0) {
  1067. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1068. return ret;
  1069. }
  1070. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1071. if (ret < 0) {
  1072. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1073. return ret;
  1074. }
  1075. /* enable PHY interrupts */
  1076. buf |= INT_ENP_PHY_INT;
  1077. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1078. if (ret < 0) {
  1079. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1080. return ret;
  1081. }
  1082. /* allow mac to detect speed and duplex from phy */
  1083. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1084. if (ret < 0) {
  1085. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1086. return ret;
  1087. }
  1088. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1089. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1090. if (ret < 0) {
  1091. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1092. return ret;
  1093. }
  1094. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1095. if (ret < 0) {
  1096. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1097. return ret;
  1098. }
  1099. buf |= MAC_TX_TXEN;
  1100. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1101. if (ret < 0) {
  1102. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1103. return ret;
  1104. }
  1105. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1106. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1107. if (ret < 0) {
  1108. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1109. return ret;
  1110. }
  1111. buf |= FCT_TX_CTL_EN;
  1112. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1113. if (ret < 0) {
  1114. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1115. return ret;
  1116. }
  1117. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1118. ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
  1119. if (ret < 0) {
  1120. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1121. return ret;
  1122. }
  1123. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1124. if (ret < 0) {
  1125. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1126. return ret;
  1127. }
  1128. buf |= MAC_RX_RXEN;
  1129. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1130. if (ret < 0) {
  1131. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1132. return ret;
  1133. }
  1134. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1135. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1136. if (ret < 0) {
  1137. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1138. return ret;
  1139. }
  1140. buf |= FCT_RX_CTL_EN;
  1141. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1142. if (ret < 0) {
  1143. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1144. return ret;
  1145. }
  1146. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1147. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1148. return 0;
  1149. }
  1150. static const struct net_device_ops smsc75xx_netdev_ops = {
  1151. .ndo_open = usbnet_open,
  1152. .ndo_stop = usbnet_stop,
  1153. .ndo_start_xmit = usbnet_start_xmit,
  1154. .ndo_tx_timeout = usbnet_tx_timeout,
  1155. .ndo_get_stats64 = dev_get_tstats64,
  1156. .ndo_change_mtu = smsc75xx_change_mtu,
  1157. .ndo_set_mac_address = eth_mac_addr,
  1158. .ndo_validate_addr = eth_validate_addr,
  1159. .ndo_eth_ioctl = smsc75xx_ioctl,
  1160. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1161. .ndo_set_features = smsc75xx_set_features,
  1162. };
  1163. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1164. {
  1165. struct smsc75xx_priv *pdata = NULL;
  1166. int ret;
  1167. ret = usbnet_get_endpoints(dev, intf);
  1168. if (ret < 0) {
  1169. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1170. return ret;
  1171. }
  1172. dev->data[0] = (unsigned long) kzalloc_obj(struct smsc75xx_priv);
  1173. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1174. if (!pdata)
  1175. return -ENOMEM;
  1176. pdata->dev = dev;
  1177. spin_lock_init(&pdata->rfe_ctl_lock);
  1178. mutex_init(&pdata->dataport_mutex);
  1179. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1180. if (DEFAULT_TX_CSUM_ENABLE)
  1181. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1182. if (DEFAULT_RX_CSUM_ENABLE)
  1183. dev->net->features |= NETIF_F_RXCSUM;
  1184. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1185. NETIF_F_RXCSUM;
  1186. ret = smsc75xx_wait_ready(dev, 0);
  1187. if (ret < 0) {
  1188. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1189. goto free_pdata;
  1190. }
  1191. smsc75xx_init_mac_address(dev);
  1192. /* Init all registers */
  1193. ret = smsc75xx_reset(dev);
  1194. if (ret < 0) {
  1195. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1196. goto cancel_work;
  1197. }
  1198. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1199. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1200. dev->net->flags |= IFF_MULTICAST;
  1201. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1202. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1203. dev->net->max_mtu = MAX_SINGLE_PACKET_SIZE;
  1204. return 0;
  1205. cancel_work:
  1206. cancel_work_sync(&pdata->set_multicast);
  1207. free_pdata:
  1208. kfree(pdata);
  1209. dev->data[0] = 0;
  1210. return ret;
  1211. }
  1212. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1213. {
  1214. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1215. if (pdata) {
  1216. cancel_work_sync(&pdata->set_multicast);
  1217. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1218. kfree(pdata);
  1219. dev->data[0] = 0;
  1220. }
  1221. }
  1222. static u16 smsc_crc(const u8 *buffer, size_t len)
  1223. {
  1224. return bitrev16(crc16(0xFFFF, buffer, len));
  1225. }
  1226. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1227. u32 wuf_mask1)
  1228. {
  1229. int cfg_base = WUF_CFGX + filter * 4;
  1230. int mask_base = WUF_MASKX + filter * 16;
  1231. int ret;
  1232. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1233. if (ret < 0) {
  1234. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1235. return ret;
  1236. }
  1237. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1238. if (ret < 0) {
  1239. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1240. return ret;
  1241. }
  1242. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1243. if (ret < 0) {
  1244. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1245. return ret;
  1246. }
  1247. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1248. if (ret < 0) {
  1249. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1250. return ret;
  1251. }
  1252. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1253. if (ret < 0) {
  1254. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1255. return ret;
  1256. }
  1257. return 0;
  1258. }
  1259. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1260. {
  1261. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1262. u32 val;
  1263. int ret;
  1264. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1265. if (ret < 0) {
  1266. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1267. return ret;
  1268. }
  1269. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1270. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1271. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1272. if (ret < 0) {
  1273. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1274. return ret;
  1275. }
  1276. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1277. return 0;
  1278. }
  1279. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1280. {
  1281. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1282. u32 val;
  1283. int ret;
  1284. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1285. if (ret < 0) {
  1286. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1287. return ret;
  1288. }
  1289. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1290. val |= PMT_CTL_SUS_MODE_1;
  1291. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1292. if (ret < 0) {
  1293. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1294. return ret;
  1295. }
  1296. /* clear wol status, enable energy detection */
  1297. val &= ~PMT_CTL_WUPS;
  1298. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1299. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1300. if (ret < 0) {
  1301. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1302. return ret;
  1303. }
  1304. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1305. return 0;
  1306. }
  1307. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1308. {
  1309. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1310. u32 val;
  1311. int ret;
  1312. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1313. if (ret < 0) {
  1314. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1315. return ret;
  1316. }
  1317. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1318. val |= PMT_CTL_SUS_MODE_2;
  1319. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1320. if (ret < 0) {
  1321. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1322. return ret;
  1323. }
  1324. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1325. return 0;
  1326. }
  1327. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1328. {
  1329. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1330. u32 val;
  1331. int ret;
  1332. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1333. if (ret < 0) {
  1334. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1335. return ret;
  1336. }
  1337. if (val & FCT_RX_CTL_RXUSED) {
  1338. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1339. return -EBUSY;
  1340. }
  1341. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1342. if (ret < 0) {
  1343. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1344. return ret;
  1345. }
  1346. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1347. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1348. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1349. if (ret < 0) {
  1350. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1351. return ret;
  1352. }
  1353. /* clear wol status */
  1354. val &= ~PMT_CTL_WUPS;
  1355. val |= PMT_CTL_WUPS_WOL;
  1356. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1357. if (ret < 0) {
  1358. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1359. return ret;
  1360. }
  1361. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1362. return 0;
  1363. }
  1364. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1365. {
  1366. struct mii_if_info *mii = &dev->mii;
  1367. int ret;
  1368. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1369. /* read to clear */
  1370. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1371. if (ret < 0) {
  1372. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1373. return ret;
  1374. }
  1375. /* enable interrupt source */
  1376. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1377. if (ret < 0) {
  1378. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1379. return ret;
  1380. }
  1381. ret |= mask;
  1382. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1383. return 0;
  1384. }
  1385. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1386. {
  1387. struct mii_if_info *mii = &dev->mii;
  1388. int ret;
  1389. /* first, a dummy read, needed to latch some MII phys */
  1390. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1391. if (ret < 0) {
  1392. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1393. return ret;
  1394. }
  1395. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1396. if (ret < 0) {
  1397. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1398. return ret;
  1399. }
  1400. return !!(ret & BMSR_LSTATUS);
  1401. }
  1402. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1403. {
  1404. int ret;
  1405. if (!netif_running(dev->net)) {
  1406. /* interface is ifconfig down so fully power down hw */
  1407. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1408. return smsc75xx_enter_suspend2(dev);
  1409. }
  1410. if (!link_up) {
  1411. /* link is down so enter EDPD mode */
  1412. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1413. /* enable PHY wakeup events for if cable is attached */
  1414. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1415. PHY_INT_MASK_ANEG_COMP);
  1416. if (ret < 0) {
  1417. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1418. return ret;
  1419. }
  1420. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1421. return smsc75xx_enter_suspend1(dev);
  1422. }
  1423. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1424. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1425. PHY_INT_MASK_LINK_DOWN);
  1426. if (ret < 0) {
  1427. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1428. return ret;
  1429. }
  1430. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1431. return smsc75xx_enter_suspend3(dev);
  1432. }
  1433. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1434. {
  1435. struct usbnet *dev = usb_get_intfdata(intf);
  1436. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1437. u32 val, link_up;
  1438. int ret;
  1439. ret = usbnet_suspend(intf, message);
  1440. if (ret < 0) {
  1441. netdev_warn(dev->net, "usbnet_suspend error\n");
  1442. return ret;
  1443. }
  1444. if (pdata->suspend_flags) {
  1445. netdev_warn(dev->net, "error during last resume\n");
  1446. pdata->suspend_flags = 0;
  1447. }
  1448. /* determine if link is up using only _nopm functions */
  1449. link_up = smsc75xx_link_ok_nopm(dev);
  1450. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1451. ret = smsc75xx_autosuspend(dev, link_up);
  1452. goto done;
  1453. }
  1454. /* if we get this far we're not autosuspending */
  1455. /* if no wol options set, or if link is down and we're not waking on
  1456. * PHY activity, enter lowest power SUSPEND2 mode
  1457. */
  1458. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1459. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1460. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1461. /* disable energy detect (link up) & wake up events */
  1462. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1463. if (ret < 0) {
  1464. netdev_warn(dev->net, "Error reading WUCSR\n");
  1465. goto done;
  1466. }
  1467. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1468. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1469. if (ret < 0) {
  1470. netdev_warn(dev->net, "Error writing WUCSR\n");
  1471. goto done;
  1472. }
  1473. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1474. if (ret < 0) {
  1475. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1476. goto done;
  1477. }
  1478. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1479. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1480. if (ret < 0) {
  1481. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1482. goto done;
  1483. }
  1484. ret = smsc75xx_enter_suspend2(dev);
  1485. goto done;
  1486. }
  1487. if (pdata->wolopts & WAKE_PHY) {
  1488. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1489. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1490. if (ret < 0) {
  1491. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1492. goto done;
  1493. }
  1494. /* if link is down then configure EDPD and enter SUSPEND1,
  1495. * otherwise enter SUSPEND0 below
  1496. */
  1497. if (!link_up) {
  1498. struct mii_if_info *mii = &dev->mii;
  1499. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1500. /* enable energy detect power-down mode */
  1501. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1502. PHY_MODE_CTRL_STS);
  1503. if (ret < 0) {
  1504. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1505. goto done;
  1506. }
  1507. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1508. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1509. PHY_MODE_CTRL_STS, ret);
  1510. /* enter SUSPEND1 mode */
  1511. ret = smsc75xx_enter_suspend1(dev);
  1512. goto done;
  1513. }
  1514. }
  1515. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1516. int i, filter = 0;
  1517. /* disable all filters */
  1518. for (i = 0; i < WUF_NUM; i++) {
  1519. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1520. if (ret < 0) {
  1521. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1522. goto done;
  1523. }
  1524. }
  1525. if (pdata->wolopts & WAKE_MCAST) {
  1526. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1527. netdev_info(dev->net, "enabling multicast detection\n");
  1528. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1529. | smsc_crc(mcast, 3);
  1530. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1531. if (ret < 0) {
  1532. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1533. goto done;
  1534. }
  1535. }
  1536. if (pdata->wolopts & WAKE_ARP) {
  1537. const u8 arp[] = {0x08, 0x06};
  1538. netdev_info(dev->net, "enabling ARP detection\n");
  1539. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1540. | smsc_crc(arp, 2);
  1541. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1542. if (ret < 0) {
  1543. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1544. goto done;
  1545. }
  1546. }
  1547. /* clear any pending pattern match packet status */
  1548. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1549. if (ret < 0) {
  1550. netdev_warn(dev->net, "Error reading WUCSR\n");
  1551. goto done;
  1552. }
  1553. val |= WUCSR_WUFR;
  1554. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1555. if (ret < 0) {
  1556. netdev_warn(dev->net, "Error writing WUCSR\n");
  1557. goto done;
  1558. }
  1559. netdev_info(dev->net, "enabling packet match detection\n");
  1560. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1561. if (ret < 0) {
  1562. netdev_warn(dev->net, "Error reading WUCSR\n");
  1563. goto done;
  1564. }
  1565. val |= WUCSR_WUEN;
  1566. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1567. if (ret < 0) {
  1568. netdev_warn(dev->net, "Error writing WUCSR\n");
  1569. goto done;
  1570. }
  1571. } else {
  1572. netdev_info(dev->net, "disabling packet match detection\n");
  1573. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1574. if (ret < 0) {
  1575. netdev_warn(dev->net, "Error reading WUCSR\n");
  1576. goto done;
  1577. }
  1578. val &= ~WUCSR_WUEN;
  1579. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1580. if (ret < 0) {
  1581. netdev_warn(dev->net, "Error writing WUCSR\n");
  1582. goto done;
  1583. }
  1584. }
  1585. /* disable magic, bcast & unicast wakeup sources */
  1586. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1587. if (ret < 0) {
  1588. netdev_warn(dev->net, "Error reading WUCSR\n");
  1589. goto done;
  1590. }
  1591. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1592. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1593. if (ret < 0) {
  1594. netdev_warn(dev->net, "Error writing WUCSR\n");
  1595. goto done;
  1596. }
  1597. if (pdata->wolopts & WAKE_PHY) {
  1598. netdev_info(dev->net, "enabling PHY wakeup\n");
  1599. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1600. if (ret < 0) {
  1601. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1602. goto done;
  1603. }
  1604. /* clear wol status, enable energy detection */
  1605. val &= ~PMT_CTL_WUPS;
  1606. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1607. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1608. if (ret < 0) {
  1609. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1610. goto done;
  1611. }
  1612. }
  1613. if (pdata->wolopts & WAKE_MAGIC) {
  1614. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1615. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1616. if (ret < 0) {
  1617. netdev_warn(dev->net, "Error reading WUCSR\n");
  1618. goto done;
  1619. }
  1620. /* clear any pending magic packet status */
  1621. val |= WUCSR_MPR | WUCSR_MPEN;
  1622. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1623. if (ret < 0) {
  1624. netdev_warn(dev->net, "Error writing WUCSR\n");
  1625. goto done;
  1626. }
  1627. }
  1628. if (pdata->wolopts & WAKE_BCAST) {
  1629. netdev_info(dev->net, "enabling broadcast detection\n");
  1630. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1631. if (ret < 0) {
  1632. netdev_warn(dev->net, "Error reading WUCSR\n");
  1633. goto done;
  1634. }
  1635. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1636. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1637. if (ret < 0) {
  1638. netdev_warn(dev->net, "Error writing WUCSR\n");
  1639. goto done;
  1640. }
  1641. }
  1642. if (pdata->wolopts & WAKE_UCAST) {
  1643. netdev_info(dev->net, "enabling unicast detection\n");
  1644. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1645. if (ret < 0) {
  1646. netdev_warn(dev->net, "Error reading WUCSR\n");
  1647. goto done;
  1648. }
  1649. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1650. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1651. if (ret < 0) {
  1652. netdev_warn(dev->net, "Error writing WUCSR\n");
  1653. goto done;
  1654. }
  1655. }
  1656. /* enable receiver to enable frame reception */
  1657. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1658. if (ret < 0) {
  1659. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1660. goto done;
  1661. }
  1662. val |= MAC_RX_RXEN;
  1663. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1664. if (ret < 0) {
  1665. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1666. goto done;
  1667. }
  1668. /* some wol options are enabled, so enter SUSPEND0 */
  1669. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1670. ret = smsc75xx_enter_suspend0(dev);
  1671. done:
  1672. /*
  1673. * TODO: resume() might need to handle the suspend failure
  1674. * in system sleep
  1675. */
  1676. if (ret && PMSG_IS_AUTO(message))
  1677. usbnet_resume(intf);
  1678. return ret;
  1679. }
  1680. static int smsc75xx_resume(struct usb_interface *intf)
  1681. {
  1682. struct usbnet *dev = usb_get_intfdata(intf);
  1683. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1684. u8 suspend_flags = pdata->suspend_flags;
  1685. int ret;
  1686. u32 val;
  1687. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1688. /* do this first to ensure it's cleared even in error case */
  1689. pdata->suspend_flags = 0;
  1690. if (suspend_flags & SUSPEND_ALLMODES) {
  1691. /* Disable wakeup sources */
  1692. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1693. if (ret < 0) {
  1694. netdev_warn(dev->net, "Error reading WUCSR\n");
  1695. return ret;
  1696. }
  1697. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1698. | WUCSR_BCST_EN);
  1699. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1700. if (ret < 0) {
  1701. netdev_warn(dev->net, "Error writing WUCSR\n");
  1702. return ret;
  1703. }
  1704. /* clear wake-up status */
  1705. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1706. if (ret < 0) {
  1707. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1708. return ret;
  1709. }
  1710. val &= ~PMT_CTL_WOL_EN;
  1711. val |= PMT_CTL_WUPS;
  1712. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1713. if (ret < 0) {
  1714. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1715. return ret;
  1716. }
  1717. }
  1718. if (suspend_flags & SUSPEND_SUSPEND2) {
  1719. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1720. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1721. if (ret < 0) {
  1722. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1723. return ret;
  1724. }
  1725. val |= PMT_CTL_PHY_PWRUP;
  1726. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1727. if (ret < 0) {
  1728. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1729. return ret;
  1730. }
  1731. }
  1732. ret = smsc75xx_wait_ready(dev, 1);
  1733. if (ret < 0) {
  1734. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1735. return ret;
  1736. }
  1737. return usbnet_resume(intf);
  1738. }
  1739. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1740. u32 rx_cmd_a, u32 rx_cmd_b)
  1741. {
  1742. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1743. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1744. skb->ip_summed = CHECKSUM_NONE;
  1745. } else {
  1746. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1747. skb->ip_summed = CHECKSUM_COMPLETE;
  1748. }
  1749. }
  1750. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1751. {
  1752. /* This check is no longer done by usbnet */
  1753. if (skb->len < dev->net->hard_header_len)
  1754. return 0;
  1755. while (skb->len > 0) {
  1756. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1757. struct sk_buff *ax_skb;
  1758. unsigned char *packet;
  1759. rx_cmd_a = get_unaligned_le32(skb->data);
  1760. skb_pull(skb, 4);
  1761. rx_cmd_b = get_unaligned_le32(skb->data);
  1762. skb_pull(skb, 4 + RXW_PADDING);
  1763. packet = skb->data;
  1764. /* get the packet length */
  1765. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1766. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1767. if (unlikely(size > skb->len)) {
  1768. netif_dbg(dev, rx_err, dev->net,
  1769. "size err rx_cmd_a=0x%08x\n",
  1770. rx_cmd_a);
  1771. return 0;
  1772. }
  1773. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1774. netif_dbg(dev, rx_err, dev->net,
  1775. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1776. dev->net->stats.rx_errors++;
  1777. dev->net->stats.rx_dropped++;
  1778. if (rx_cmd_a & RX_CMD_A_FCS)
  1779. dev->net->stats.rx_crc_errors++;
  1780. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1781. dev->net->stats.rx_frame_errors++;
  1782. } else {
  1783. /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
  1784. if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
  1785. netif_dbg(dev, rx_err, dev->net,
  1786. "size err rx_cmd_a=0x%08x\n",
  1787. rx_cmd_a);
  1788. return 0;
  1789. }
  1790. /* last frame in this batch */
  1791. if (skb->len == size) {
  1792. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1793. rx_cmd_b);
  1794. skb_trim(skb, skb->len - 4); /* remove fcs */
  1795. return 1;
  1796. }
  1797. /* Use "size - 4" to remove fcs */
  1798. ax_skb = netdev_alloc_skb_ip_align(dev->net, size - 4);
  1799. if (unlikely(!ax_skb)) {
  1800. netdev_warn(dev->net, "Error allocating skb\n");
  1801. return 0;
  1802. }
  1803. skb_put(ax_skb, size - 4);
  1804. memcpy(ax_skb->data, packet, size - 4);
  1805. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1806. rx_cmd_b);
  1807. usbnet_skb_return(dev, ax_skb);
  1808. }
  1809. skb_pull(skb, size);
  1810. /* padding bytes before the next frame starts */
  1811. if (skb->len)
  1812. skb_pull(skb, align_count);
  1813. }
  1814. return 1;
  1815. }
  1816. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1817. struct sk_buff *skb, gfp_t flags)
  1818. {
  1819. u32 tx_cmd_a, tx_cmd_b;
  1820. void *ptr;
  1821. if (skb_cow_head(skb, SMSC75XX_TX_OVERHEAD)) {
  1822. dev_kfree_skb_any(skb);
  1823. return NULL;
  1824. }
  1825. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1826. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1827. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1828. if (skb_is_gso(skb)) {
  1829. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1830. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1831. tx_cmd_a |= TX_CMD_A_LSO;
  1832. } else {
  1833. tx_cmd_b = 0;
  1834. }
  1835. ptr = skb_push(skb, 8);
  1836. put_unaligned_le32(tx_cmd_a, ptr);
  1837. put_unaligned_le32(tx_cmd_b, ptr + 4);
  1838. return skb;
  1839. }
  1840. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1841. {
  1842. dev->intf->needs_remote_wakeup = on;
  1843. return 0;
  1844. }
  1845. static const struct driver_info smsc75xx_info = {
  1846. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1847. .bind = smsc75xx_bind,
  1848. .unbind = smsc75xx_unbind,
  1849. .link_reset = smsc75xx_link_reset,
  1850. .reset = smsc75xx_reset,
  1851. .rx_fixup = smsc75xx_rx_fixup,
  1852. .tx_fixup = smsc75xx_tx_fixup,
  1853. .status = smsc75xx_status,
  1854. .manage_power = smsc75xx_manage_power,
  1855. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1856. };
  1857. static const struct usb_device_id products[] = {
  1858. {
  1859. /* SMSC7500 USB Gigabit Ethernet Device */
  1860. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1861. .driver_info = (unsigned long) &smsc75xx_info,
  1862. },
  1863. {
  1864. /* SMSC7500 USB Gigabit Ethernet Device */
  1865. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1866. .driver_info = (unsigned long) &smsc75xx_info,
  1867. },
  1868. { }, /* END */
  1869. };
  1870. MODULE_DEVICE_TABLE(usb, products);
  1871. static struct usb_driver smsc75xx_driver = {
  1872. .name = SMSC_CHIPNAME,
  1873. .id_table = products,
  1874. .probe = usbnet_probe,
  1875. .suspend = smsc75xx_suspend,
  1876. .resume = smsc75xx_resume,
  1877. .reset_resume = smsc75xx_resume,
  1878. .disconnect = usbnet_disconnect,
  1879. .disable_hub_initiated_lpm = 1,
  1880. .supports_autosuspend = 1,
  1881. };
  1882. module_usb_driver(smsc75xx_driver);
  1883. MODULE_AUTHOR("Nancy Lin");
  1884. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1885. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1886. MODULE_LICENSE("GPL");