mdio-ipq8064.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Qualcomm IPQ8064 MDIO interface driver
  3. *
  4. * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
  5. * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_mdio.h>
  11. #include <linux/of_address.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/regmap.h>
  14. /* MII address register definitions */
  15. #define MII_ADDR_REG_ADDR 0x10
  16. #define MII_BUSY BIT(0)
  17. #define MII_WRITE BIT(1)
  18. #define MII_CLKRANGE(x) ((x) << 2)
  19. #define MII_CLKRANGE_60_100M MII_CLKRANGE(0)
  20. #define MII_CLKRANGE_100_150M MII_CLKRANGE(1)
  21. #define MII_CLKRANGE_20_35M MII_CLKRANGE(2)
  22. #define MII_CLKRANGE_35_60M MII_CLKRANGE(3)
  23. #define MII_CLKRANGE_150_250M MII_CLKRANGE(4)
  24. #define MII_CLKRANGE_250_300M MII_CLKRANGE(5)
  25. #define MII_CLKRANGE_MASK GENMASK(4, 2)
  26. #define MII_REG_SHIFT 6
  27. #define MII_REG_MASK GENMASK(10, 6)
  28. #define MII_ADDR_SHIFT 11
  29. #define MII_ADDR_MASK GENMASK(15, 11)
  30. #define MII_DATA_REG_ADDR 0x14
  31. #define MII_MDIO_DELAY_USEC (1000)
  32. #define MII_MDIO_RETRY_MSEC (10)
  33. struct ipq8064_mdio {
  34. struct regmap *base; /* NSS_GMAC0_BASE */
  35. };
  36. static int
  37. ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
  38. {
  39. u32 busy;
  40. return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
  41. !(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
  42. MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
  43. }
  44. static int
  45. ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
  46. {
  47. u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
  48. struct ipq8064_mdio *priv = bus->priv;
  49. u32 ret_val;
  50. int err;
  51. miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
  52. ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
  53. regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
  54. usleep_range(10, 13);
  55. err = ipq8064_mdio_wait_busy(priv);
  56. if (err)
  57. return err;
  58. regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
  59. return (int)ret_val;
  60. }
  61. static int
  62. ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
  63. {
  64. u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
  65. struct ipq8064_mdio *priv = bus->priv;
  66. regmap_write(priv->base, MII_DATA_REG_ADDR, data);
  67. miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
  68. ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
  69. regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
  70. /* For the specific reg 31 extra time is needed or the next
  71. * read will produce garbage data.
  72. */
  73. if (reg_offset == 31)
  74. usleep_range(30, 43);
  75. else
  76. usleep_range(10, 13);
  77. return ipq8064_mdio_wait_busy(priv);
  78. }
  79. static const struct regmap_config ipq8064_mdio_regmap_config = {
  80. .reg_bits = 32,
  81. .reg_stride = 4,
  82. .val_bits = 32,
  83. .can_multi_write = false,
  84. /* the mdio lock is used by any user of this mdio driver */
  85. .disable_locking = true,
  86. .cache_type = REGCACHE_NONE,
  87. };
  88. static int
  89. ipq8064_mdio_probe(struct platform_device *pdev)
  90. {
  91. struct device_node *np = pdev->dev.of_node;
  92. struct ipq8064_mdio *priv;
  93. struct resource res;
  94. struct mii_bus *bus;
  95. void __iomem *base;
  96. int ret;
  97. if (of_address_to_resource(np, 0, &res))
  98. return -ENOMEM;
  99. base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
  100. if (!base)
  101. return -ENOMEM;
  102. bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
  103. if (!bus)
  104. return -ENOMEM;
  105. bus->name = "ipq8064_mdio_bus";
  106. bus->read = ipq8064_mdio_read;
  107. bus->write = ipq8064_mdio_write;
  108. snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
  109. bus->parent = &pdev->dev;
  110. priv = bus->priv;
  111. priv->base = devm_regmap_init_mmio(&pdev->dev, base,
  112. &ipq8064_mdio_regmap_config);
  113. if (IS_ERR(priv->base))
  114. return PTR_ERR(priv->base);
  115. ret = of_mdiobus_register(bus, np);
  116. if (ret)
  117. return ret;
  118. platform_set_drvdata(pdev, bus);
  119. return 0;
  120. }
  121. static void ipq8064_mdio_remove(struct platform_device *pdev)
  122. {
  123. struct mii_bus *bus = platform_get_drvdata(pdev);
  124. mdiobus_unregister(bus);
  125. }
  126. static const struct of_device_id ipq8064_mdio_dt_ids[] = {
  127. { .compatible = "qcom,ipq8064-mdio" },
  128. { }
  129. };
  130. MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
  131. static struct platform_driver ipq8064_mdio_driver = {
  132. .probe = ipq8064_mdio_probe,
  133. .remove = ipq8064_mdio_remove,
  134. .driver = {
  135. .name = "ipq8064-mdio",
  136. .of_match_table = ipq8064_mdio_dt_ids,
  137. },
  138. };
  139. module_platform_driver(ipq8064_mdio_driver);
  140. MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
  141. MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
  142. MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
  143. MODULE_LICENSE("GPL");