mdio-aspeed.c 5.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Copyright (C) 2019 IBM Corp. */
  3. #include <linux/bitfield.h>
  4. #include <linux/delay.h>
  5. #include <linux/reset.h>
  6. #include <linux/iopoll.h>
  7. #include <linux/mdio.h>
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/of_mdio.h>
  11. #include <linux/phy.h>
  12. #include <linux/platform_device.h>
  13. #define DRV_NAME "mdio-aspeed"
  14. #define ASPEED_MDIO_CTRL 0x0
  15. #define ASPEED_MDIO_CTRL_FIRE BIT(31)
  16. #define ASPEED_MDIO_CTRL_ST BIT(28)
  17. #define ASPEED_MDIO_CTRL_ST_C45 0
  18. #define ASPEED_MDIO_CTRL_ST_C22 1
  19. #define ASPEED_MDIO_CTRL_OP GENMASK(27, 26)
  20. #define MDIO_C22_OP_WRITE 0b01
  21. #define MDIO_C22_OP_READ 0b10
  22. #define MDIO_C45_OP_ADDR 0b00
  23. #define MDIO_C45_OP_WRITE 0b01
  24. #define MDIO_C45_OP_PREAD 0b10
  25. #define MDIO_C45_OP_READ 0b11
  26. #define ASPEED_MDIO_CTRL_PHYAD GENMASK(25, 21)
  27. #define ASPEED_MDIO_CTRL_REGAD GENMASK(20, 16)
  28. #define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)
  29. #define ASPEED_MDIO_DATA 0x4
  30. #define ASPEED_MDIO_DATA_MDC_THRES GENMASK(31, 24)
  31. #define ASPEED_MDIO_DATA_MDIO_EDGE BIT(23)
  32. #define ASPEED_MDIO_DATA_MDIO_LATCH GENMASK(22, 20)
  33. #define ASPEED_MDIO_DATA_IDLE BIT(16)
  34. #define ASPEED_MDIO_DATA_MIIRDATA GENMASK(15, 0)
  35. #define ASPEED_MDIO_INTERVAL_US 100
  36. #define ASPEED_MDIO_TIMEOUT_US (ASPEED_MDIO_INTERVAL_US * 10)
  37. struct aspeed_mdio {
  38. void __iomem *base;
  39. struct reset_control *reset;
  40. };
  41. static int aspeed_mdio_op(struct mii_bus *bus, u8 st, u8 op, u8 phyad, u8 regad,
  42. u16 data)
  43. {
  44. struct aspeed_mdio *ctx = bus->priv;
  45. u32 ctrl;
  46. dev_dbg(&bus->dev, "%s: st: %u op: %u, phyad: %u, regad: %u, data: %u\n",
  47. __func__, st, op, phyad, regad, data);
  48. ctrl = ASPEED_MDIO_CTRL_FIRE
  49. | FIELD_PREP(ASPEED_MDIO_CTRL_ST, st)
  50. | FIELD_PREP(ASPEED_MDIO_CTRL_OP, op)
  51. | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, phyad)
  52. | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, regad)
  53. | FIELD_PREP(ASPEED_MDIO_DATA_MIIRDATA, data);
  54. iowrite32(ctrl, ctx->base + ASPEED_MDIO_CTRL);
  55. /* Workaround for read-after-write issue.
  56. * The controller may return stale data if a read follows immediately
  57. * after a write. A dummy read forces the hardware to update its
  58. * internal state, ensuring that the next real read returns correct data.
  59. */
  60. ioread32(ctx->base + ASPEED_MDIO_CTRL);
  61. return readl_poll_timeout(ctx->base + ASPEED_MDIO_CTRL, ctrl,
  62. !(ctrl & ASPEED_MDIO_CTRL_FIRE),
  63. ASPEED_MDIO_INTERVAL_US,
  64. ASPEED_MDIO_TIMEOUT_US);
  65. }
  66. static int aspeed_mdio_get_data(struct mii_bus *bus)
  67. {
  68. struct aspeed_mdio *ctx = bus->priv;
  69. u32 data;
  70. int rc;
  71. rc = readl_poll_timeout(ctx->base + ASPEED_MDIO_DATA, data,
  72. data & ASPEED_MDIO_DATA_IDLE,
  73. ASPEED_MDIO_INTERVAL_US,
  74. ASPEED_MDIO_TIMEOUT_US);
  75. if (rc < 0)
  76. return rc;
  77. return FIELD_GET(ASPEED_MDIO_DATA_MIIRDATA, data);
  78. }
  79. static int aspeed_mdio_read_c22(struct mii_bus *bus, int addr, int regnum)
  80. {
  81. int rc;
  82. rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C22, MDIO_C22_OP_READ,
  83. addr, regnum, 0);
  84. if (rc < 0)
  85. return rc;
  86. return aspeed_mdio_get_data(bus);
  87. }
  88. static int aspeed_mdio_write_c22(struct mii_bus *bus, int addr, int regnum,
  89. u16 val)
  90. {
  91. return aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C22, MDIO_C22_OP_WRITE,
  92. addr, regnum, val);
  93. }
  94. static int aspeed_mdio_read_c45(struct mii_bus *bus, int addr, int devad,
  95. int regnum)
  96. {
  97. int rc;
  98. rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_ADDR,
  99. addr, devad, regnum);
  100. if (rc < 0)
  101. return rc;
  102. rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_READ,
  103. addr, devad, 0);
  104. if (rc < 0)
  105. return rc;
  106. return aspeed_mdio_get_data(bus);
  107. }
  108. static int aspeed_mdio_write_c45(struct mii_bus *bus, int addr, int devad,
  109. int regnum, u16 val)
  110. {
  111. int rc;
  112. rc = aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_ADDR,
  113. addr, devad, regnum);
  114. if (rc < 0)
  115. return rc;
  116. return aspeed_mdio_op(bus, ASPEED_MDIO_CTRL_ST_C45, MDIO_C45_OP_WRITE,
  117. addr, devad, val);
  118. }
  119. static int aspeed_mdio_probe(struct platform_device *pdev)
  120. {
  121. struct aspeed_mdio *ctx;
  122. struct mii_bus *bus;
  123. int rc;
  124. bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*ctx));
  125. if (!bus)
  126. return -ENOMEM;
  127. ctx = bus->priv;
  128. ctx->base = devm_platform_ioremap_resource(pdev, 0);
  129. if (IS_ERR(ctx->base))
  130. return PTR_ERR(ctx->base);
  131. ctx->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
  132. if (IS_ERR(ctx->reset))
  133. return PTR_ERR(ctx->reset);
  134. reset_control_deassert(ctx->reset);
  135. bus->name = DRV_NAME;
  136. snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id);
  137. bus->parent = &pdev->dev;
  138. bus->read = aspeed_mdio_read_c22;
  139. bus->write = aspeed_mdio_write_c22;
  140. bus->read_c45 = aspeed_mdio_read_c45;
  141. bus->write_c45 = aspeed_mdio_write_c45;
  142. rc = of_mdiobus_register(bus, pdev->dev.of_node);
  143. if (rc) {
  144. dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
  145. reset_control_assert(ctx->reset);
  146. return rc;
  147. }
  148. platform_set_drvdata(pdev, bus);
  149. return 0;
  150. }
  151. static void aspeed_mdio_remove(struct platform_device *pdev)
  152. {
  153. struct mii_bus *bus = (struct mii_bus *)platform_get_drvdata(pdev);
  154. struct aspeed_mdio *ctx = bus->priv;
  155. reset_control_assert(ctx->reset);
  156. mdiobus_unregister(bus);
  157. }
  158. static const struct of_device_id aspeed_mdio_of_match[] = {
  159. { .compatible = "aspeed,ast2600-mdio", },
  160. { },
  161. };
  162. MODULE_DEVICE_TABLE(of, aspeed_mdio_of_match);
  163. static struct platform_driver aspeed_mdio_driver = {
  164. .driver = {
  165. .name = DRV_NAME,
  166. .of_match_table = aspeed_mdio_of_match,
  167. },
  168. .probe = aspeed_mdio_probe,
  169. .remove = aspeed_mdio_remove,
  170. };
  171. module_platform_driver(aspeed_mdio_driver);
  172. MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
  173. MODULE_LICENSE("GPL");
  174. MODULE_DESCRIPTION("ASPEED MDIO bus controller");