rx_common.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /****************************************************************************
  3. * Driver for Solarflare network controllers and boards
  4. * Copyright 2018 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include "net_driver.h"
  11. #include <linux/module.h>
  12. #include <linux/iommu.h>
  13. #include <net/rps.h>
  14. #include "efx.h"
  15. #include "nic.h"
  16. #include "rx_common.h"
  17. /* This is the percentage fill level below which new RX descriptors
  18. * will be added to the RX descriptor ring.
  19. */
  20. static unsigned int rx_refill_threshold;
  21. module_param(rx_refill_threshold, uint, 0444);
  22. MODULE_PARM_DESC(rx_refill_threshold,
  23. "RX descriptor ring refill threshold (%)");
  24. /* RX maximum head room required.
  25. *
  26. * This must be at least 1 to prevent overflow, plus one packet-worth
  27. * to allow pipelined receives.
  28. */
  29. #define EFX_RXD_HEAD_ROOM (1 + EFX_RX_MAX_FRAGS)
  30. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  31. struct efx_rx_buffer *rx_buf);
  32. /* Check the RX page recycle ring for a page that can be reused. */
  33. static struct page *efx_reuse_page(struct efx_rx_queue *rx_queue)
  34. {
  35. struct efx_nic *efx = rx_queue->efx;
  36. struct efx_rx_page_state *state;
  37. unsigned int index;
  38. struct page *page;
  39. if (unlikely(!rx_queue->page_ring))
  40. return NULL;
  41. index = rx_queue->page_remove & rx_queue->page_ptr_mask;
  42. page = rx_queue->page_ring[index];
  43. if (page == NULL)
  44. return NULL;
  45. rx_queue->page_ring[index] = NULL;
  46. /* page_remove cannot exceed page_add. */
  47. if (rx_queue->page_remove != rx_queue->page_add)
  48. ++rx_queue->page_remove;
  49. /* If page_count is 1 then we hold the only reference to this page. */
  50. if (page_count(page) == 1) {
  51. ++rx_queue->page_recycle_count;
  52. return page;
  53. } else {
  54. state = page_address(page);
  55. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  56. PAGE_SIZE << efx->rx_buffer_order,
  57. DMA_FROM_DEVICE);
  58. put_page(page);
  59. ++rx_queue->page_recycle_failed;
  60. }
  61. return NULL;
  62. }
  63. /* Attempt to recycle the page if there is an RX recycle ring; the page can
  64. * only be added if this is the final RX buffer, to prevent pages being used in
  65. * the descriptor ring and appearing in the recycle ring simultaneously.
  66. */
  67. static void efx_recycle_rx_page(struct efx_channel *channel,
  68. struct efx_rx_buffer *rx_buf)
  69. {
  70. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  71. struct efx_nic *efx = rx_queue->efx;
  72. struct page *page = rx_buf->page;
  73. unsigned int index;
  74. /* Only recycle the page after processing the final buffer. */
  75. if (!(rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE))
  76. return;
  77. index = rx_queue->page_add & rx_queue->page_ptr_mask;
  78. if (rx_queue->page_ring[index] == NULL) {
  79. unsigned int read_index = rx_queue->page_remove &
  80. rx_queue->page_ptr_mask;
  81. /* The next slot in the recycle ring is available, but
  82. * increment page_remove if the read pointer currently
  83. * points here.
  84. */
  85. if (read_index == index)
  86. ++rx_queue->page_remove;
  87. rx_queue->page_ring[index] = page;
  88. ++rx_queue->page_add;
  89. return;
  90. }
  91. ++rx_queue->page_recycle_full;
  92. efx_unmap_rx_buffer(efx, rx_buf);
  93. put_page(rx_buf->page);
  94. }
  95. /* Recycle the pages that are used by buffers that have just been received. */
  96. void efx_siena_recycle_rx_pages(struct efx_channel *channel,
  97. struct efx_rx_buffer *rx_buf,
  98. unsigned int n_frags)
  99. {
  100. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  101. if (unlikely(!rx_queue->page_ring))
  102. return;
  103. do {
  104. efx_recycle_rx_page(channel, rx_buf);
  105. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  106. } while (--n_frags);
  107. }
  108. void efx_siena_discard_rx_packet(struct efx_channel *channel,
  109. struct efx_rx_buffer *rx_buf,
  110. unsigned int n_frags)
  111. {
  112. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  113. efx_siena_recycle_rx_pages(channel, rx_buf, n_frags);
  114. efx_siena_free_rx_buffers(rx_queue, rx_buf, n_frags);
  115. }
  116. static void efx_init_rx_recycle_ring(struct efx_rx_queue *rx_queue)
  117. {
  118. unsigned int bufs_in_recycle_ring, page_ring_size;
  119. struct efx_nic *efx = rx_queue->efx;
  120. bufs_in_recycle_ring = efx_rx_recycle_ring_size(efx);
  121. page_ring_size = roundup_pow_of_two(bufs_in_recycle_ring /
  122. efx->rx_bufs_per_page);
  123. rx_queue->page_ring = kzalloc_objs(*rx_queue->page_ring, page_ring_size);
  124. if (!rx_queue->page_ring)
  125. rx_queue->page_ptr_mask = 0;
  126. else
  127. rx_queue->page_ptr_mask = page_ring_size - 1;
  128. }
  129. static void efx_fini_rx_recycle_ring(struct efx_rx_queue *rx_queue)
  130. {
  131. struct efx_nic *efx = rx_queue->efx;
  132. int i;
  133. if (unlikely(!rx_queue->page_ring))
  134. return;
  135. /* Unmap and release the pages in the recycle ring. Remove the ring. */
  136. for (i = 0; i <= rx_queue->page_ptr_mask; i++) {
  137. struct page *page = rx_queue->page_ring[i];
  138. struct efx_rx_page_state *state;
  139. if (page == NULL)
  140. continue;
  141. state = page_address(page);
  142. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  143. PAGE_SIZE << efx->rx_buffer_order,
  144. DMA_FROM_DEVICE);
  145. put_page(page);
  146. }
  147. kfree(rx_queue->page_ring);
  148. rx_queue->page_ring = NULL;
  149. }
  150. static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
  151. struct efx_rx_buffer *rx_buf)
  152. {
  153. /* Release the page reference we hold for the buffer. */
  154. if (rx_buf->page)
  155. put_page(rx_buf->page);
  156. /* If this is the last buffer in a page, unmap and free it. */
  157. if (rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE) {
  158. efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
  159. efx_siena_free_rx_buffers(rx_queue, rx_buf, 1);
  160. }
  161. rx_buf->page = NULL;
  162. }
  163. int efx_siena_probe_rx_queue(struct efx_rx_queue *rx_queue)
  164. {
  165. struct efx_nic *efx = rx_queue->efx;
  166. unsigned int entries;
  167. int rc;
  168. /* Create the smallest power-of-two aligned ring */
  169. entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
  170. EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  171. rx_queue->ptr_mask = entries - 1;
  172. netif_dbg(efx, probe, efx->net_dev,
  173. "creating RX queue %d size %#x mask %#x\n",
  174. efx_rx_queue_index(rx_queue), efx->rxq_entries,
  175. rx_queue->ptr_mask);
  176. /* Allocate RX buffers */
  177. rx_queue->buffer = kzalloc_objs(*rx_queue->buffer, entries);
  178. if (!rx_queue->buffer)
  179. return -ENOMEM;
  180. rc = efx_nic_probe_rx(rx_queue);
  181. if (rc) {
  182. kfree(rx_queue->buffer);
  183. rx_queue->buffer = NULL;
  184. }
  185. return rc;
  186. }
  187. void efx_siena_init_rx_queue(struct efx_rx_queue *rx_queue)
  188. {
  189. unsigned int max_fill, trigger, max_trigger;
  190. struct efx_nic *efx = rx_queue->efx;
  191. int rc = 0;
  192. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  193. "initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
  194. /* Initialise ptr fields */
  195. rx_queue->added_count = 0;
  196. rx_queue->notified_count = 0;
  197. rx_queue->removed_count = 0;
  198. rx_queue->min_fill = -1U;
  199. efx_init_rx_recycle_ring(rx_queue);
  200. rx_queue->page_remove = 0;
  201. rx_queue->page_add = rx_queue->page_ptr_mask + 1;
  202. rx_queue->page_recycle_count = 0;
  203. rx_queue->page_recycle_failed = 0;
  204. rx_queue->page_recycle_full = 0;
  205. /* Initialise limit fields */
  206. max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
  207. max_trigger =
  208. max_fill - efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  209. if (rx_refill_threshold != 0) {
  210. trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
  211. if (trigger > max_trigger)
  212. trigger = max_trigger;
  213. } else {
  214. trigger = max_trigger;
  215. }
  216. rx_queue->max_fill = max_fill;
  217. rx_queue->fast_fill_trigger = trigger;
  218. rx_queue->refill_enabled = true;
  219. /* Initialise XDP queue information */
  220. rc = xdp_rxq_info_reg(&rx_queue->xdp_rxq_info, efx->net_dev,
  221. rx_queue->core_index, 0);
  222. if (rc) {
  223. netif_err(efx, rx_err, efx->net_dev,
  224. "Failure to initialise XDP queue information rc=%d\n",
  225. rc);
  226. efx->xdp_rxq_info_failed = true;
  227. }
  228. /* Set up RX descriptor ring */
  229. efx_nic_init_rx(rx_queue);
  230. }
  231. void efx_siena_fini_rx_queue(struct efx_rx_queue *rx_queue)
  232. {
  233. struct efx_rx_buffer *rx_buf;
  234. int i;
  235. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  236. "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
  237. timer_delete_sync(&rx_queue->slow_fill);
  238. /* Release RX buffers from the current read ptr to the write ptr */
  239. if (rx_queue->buffer) {
  240. for (i = rx_queue->removed_count; i < rx_queue->added_count;
  241. i++) {
  242. unsigned int index = i & rx_queue->ptr_mask;
  243. rx_buf = efx_rx_buffer(rx_queue, index);
  244. efx_fini_rx_buffer(rx_queue, rx_buf);
  245. }
  246. }
  247. efx_fini_rx_recycle_ring(rx_queue);
  248. if (xdp_rxq_info_is_reg(&rx_queue->xdp_rxq_info))
  249. xdp_rxq_info_unreg(&rx_queue->xdp_rxq_info);
  250. }
  251. void efx_siena_remove_rx_queue(struct efx_rx_queue *rx_queue)
  252. {
  253. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  254. "destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
  255. efx_nic_remove_rx(rx_queue);
  256. kfree(rx_queue->buffer);
  257. rx_queue->buffer = NULL;
  258. }
  259. /* Unmap a DMA-mapped page. This function is only called for the final RX
  260. * buffer in a page.
  261. */
  262. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  263. struct efx_rx_buffer *rx_buf)
  264. {
  265. struct page *page = rx_buf->page;
  266. if (page) {
  267. struct efx_rx_page_state *state = page_address(page);
  268. dma_unmap_page(&efx->pci_dev->dev,
  269. state->dma_addr,
  270. PAGE_SIZE << efx->rx_buffer_order,
  271. DMA_FROM_DEVICE);
  272. }
  273. }
  274. void efx_siena_free_rx_buffers(struct efx_rx_queue *rx_queue,
  275. struct efx_rx_buffer *rx_buf,
  276. unsigned int num_bufs)
  277. {
  278. do {
  279. if (rx_buf->page) {
  280. put_page(rx_buf->page);
  281. rx_buf->page = NULL;
  282. }
  283. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  284. } while (--num_bufs);
  285. }
  286. void efx_siena_rx_slow_fill(struct timer_list *t)
  287. {
  288. struct efx_rx_queue *rx_queue = timer_container_of(rx_queue, t,
  289. slow_fill);
  290. /* Post an event to cause NAPI to run and refill the queue */
  291. efx_nic_generate_fill_event(rx_queue);
  292. ++rx_queue->slow_fill_count;
  293. }
  294. static void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
  295. {
  296. mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(10));
  297. }
  298. /* efx_init_rx_buffers - create EFX_RX_BATCH page-based RX buffers
  299. *
  300. * @rx_queue: Efx RX queue
  301. *
  302. * This allocates a batch of pages, maps them for DMA, and populates
  303. * struct efx_rx_buffers for each one. Return a negative error code or
  304. * 0 on success. If a single page can be used for multiple buffers,
  305. * then the page will either be inserted fully, or not at all.
  306. */
  307. static int efx_init_rx_buffers(struct efx_rx_queue *rx_queue, bool atomic)
  308. {
  309. unsigned int page_offset, index, count;
  310. struct efx_nic *efx = rx_queue->efx;
  311. struct efx_rx_page_state *state;
  312. struct efx_rx_buffer *rx_buf;
  313. dma_addr_t dma_addr;
  314. struct page *page;
  315. count = 0;
  316. do {
  317. page = efx_reuse_page(rx_queue);
  318. if (page == NULL) {
  319. page = alloc_pages(__GFP_COMP |
  320. (atomic ? GFP_ATOMIC : GFP_KERNEL),
  321. efx->rx_buffer_order);
  322. if (unlikely(page == NULL))
  323. return -ENOMEM;
  324. dma_addr =
  325. dma_map_page(&efx->pci_dev->dev, page, 0,
  326. PAGE_SIZE << efx->rx_buffer_order,
  327. DMA_FROM_DEVICE);
  328. if (unlikely(dma_mapping_error(&efx->pci_dev->dev,
  329. dma_addr))) {
  330. __free_pages(page, efx->rx_buffer_order);
  331. return -EIO;
  332. }
  333. state = page_address(page);
  334. state->dma_addr = dma_addr;
  335. } else {
  336. state = page_address(page);
  337. dma_addr = state->dma_addr;
  338. }
  339. dma_addr += sizeof(struct efx_rx_page_state);
  340. page_offset = sizeof(struct efx_rx_page_state);
  341. do {
  342. index = rx_queue->added_count & rx_queue->ptr_mask;
  343. rx_buf = efx_rx_buffer(rx_queue, index);
  344. rx_buf->dma_addr = dma_addr + efx->rx_ip_align +
  345. EFX_XDP_HEADROOM;
  346. rx_buf->page = page;
  347. rx_buf->page_offset = page_offset + efx->rx_ip_align +
  348. EFX_XDP_HEADROOM;
  349. rx_buf->len = efx->rx_dma_len;
  350. rx_buf->flags = 0;
  351. ++rx_queue->added_count;
  352. get_page(page);
  353. dma_addr += efx->rx_page_buf_step;
  354. page_offset += efx->rx_page_buf_step;
  355. } while (page_offset + efx->rx_page_buf_step <= PAGE_SIZE);
  356. rx_buf->flags = EFX_RX_BUF_LAST_IN_PAGE;
  357. } while (++count < efx->rx_pages_per_batch);
  358. return 0;
  359. }
  360. void efx_siena_rx_config_page_split(struct efx_nic *efx)
  361. {
  362. efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + efx->rx_ip_align +
  363. EFX_XDP_HEADROOM + EFX_XDP_TAILROOM,
  364. EFX_RX_BUF_ALIGNMENT);
  365. efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
  366. ((PAGE_SIZE - sizeof(struct efx_rx_page_state)) /
  367. efx->rx_page_buf_step);
  368. efx->rx_buffer_truesize = (PAGE_SIZE << efx->rx_buffer_order) /
  369. efx->rx_bufs_per_page;
  370. efx->rx_pages_per_batch = DIV_ROUND_UP(EFX_RX_PREFERRED_BATCH,
  371. efx->rx_bufs_per_page);
  372. }
  373. /* efx_siena_fast_push_rx_descriptors - push new RX descriptors quickly
  374. * @rx_queue: RX descriptor queue
  375. *
  376. * This will aim to fill the RX descriptor queue up to
  377. * @rx_queue->@max_fill. If there is insufficient atomic
  378. * memory to do so, a slow fill will be scheduled.
  379. *
  380. * The caller must provide serialisation (none is used here). In practise,
  381. * this means this function must run from the NAPI handler, or be called
  382. * when NAPI is disabled.
  383. */
  384. void efx_siena_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue,
  385. bool atomic)
  386. {
  387. struct efx_nic *efx = rx_queue->efx;
  388. unsigned int fill_level, batch_size;
  389. int space, rc = 0;
  390. if (!rx_queue->refill_enabled)
  391. return;
  392. /* Calculate current fill level, and exit if we don't need to fill */
  393. fill_level = (rx_queue->added_count - rx_queue->removed_count);
  394. EFX_WARN_ON_ONCE_PARANOID(fill_level > rx_queue->efx->rxq_entries);
  395. if (fill_level >= rx_queue->fast_fill_trigger)
  396. goto out;
  397. /* Record minimum fill level */
  398. if (unlikely(fill_level < rx_queue->min_fill)) {
  399. if (fill_level)
  400. rx_queue->min_fill = fill_level;
  401. }
  402. batch_size = efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  403. space = rx_queue->max_fill - fill_level;
  404. EFX_WARN_ON_ONCE_PARANOID(space < batch_size);
  405. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  406. "RX queue %d fast-filling descriptor ring from"
  407. " level %d to level %d\n",
  408. efx_rx_queue_index(rx_queue), fill_level,
  409. rx_queue->max_fill);
  410. do {
  411. rc = efx_init_rx_buffers(rx_queue, atomic);
  412. if (unlikely(rc)) {
  413. /* Ensure that we don't leave the rx queue empty */
  414. efx_schedule_slow_fill(rx_queue);
  415. goto out;
  416. }
  417. } while ((space -= batch_size) >= batch_size);
  418. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  419. "RX queue %d fast-filled descriptor ring "
  420. "to level %d\n", efx_rx_queue_index(rx_queue),
  421. rx_queue->added_count - rx_queue->removed_count);
  422. out:
  423. if (rx_queue->notified_count != rx_queue->added_count)
  424. efx_nic_notify_rx_desc(rx_queue);
  425. }
  426. /* Pass a received packet up through GRO. GRO can handle pages
  427. * regardless of checksum state and skbs with a good checksum.
  428. */
  429. void
  430. efx_siena_rx_packet_gro(struct efx_channel *channel,
  431. struct efx_rx_buffer *rx_buf,
  432. unsigned int n_frags, u8 *eh, __wsum csum)
  433. {
  434. struct napi_struct *napi = &channel->napi_str;
  435. struct efx_nic *efx = channel->efx;
  436. struct sk_buff *skb;
  437. skb = napi_get_frags(napi);
  438. if (unlikely(!skb)) {
  439. struct efx_rx_queue *rx_queue;
  440. rx_queue = efx_channel_get_rx_queue(channel);
  441. efx_siena_free_rx_buffers(rx_queue, rx_buf, n_frags);
  442. return;
  443. }
  444. if (efx->net_dev->features & NETIF_F_RXHASH)
  445. skb_set_hash(skb, efx_rx_buf_hash(efx, eh),
  446. PKT_HASH_TYPE_L3);
  447. if (csum) {
  448. skb->csum = csum;
  449. skb->ip_summed = CHECKSUM_COMPLETE;
  450. } else {
  451. skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ?
  452. CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
  453. }
  454. skb->csum_level = !!(rx_buf->flags & EFX_RX_PKT_CSUM_LEVEL);
  455. for (;;) {
  456. skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
  457. rx_buf->page, rx_buf->page_offset,
  458. rx_buf->len);
  459. rx_buf->page = NULL;
  460. skb->len += rx_buf->len;
  461. if (skb_shinfo(skb)->nr_frags == n_frags)
  462. break;
  463. rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
  464. }
  465. skb->data_len = skb->len;
  466. skb->truesize += n_frags * efx->rx_buffer_truesize;
  467. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  468. napi_gro_frags(napi);
  469. }
  470. void efx_siena_set_default_rx_indir_table(struct efx_nic *efx,
  471. struct efx_rss_context *ctx)
  472. {
  473. size_t i;
  474. for (i = 0; i < ARRAY_SIZE(ctx->rx_indir_table); i++)
  475. ctx->rx_indir_table[i] =
  476. ethtool_rxfh_indir_default(i, efx->rss_spread);
  477. }
  478. /**
  479. * efx_siena_filter_is_mc_recipient - test whether spec is a multicast recipient
  480. * @spec: Specification to test
  481. *
  482. * Return: %true if the specification is a non-drop RX filter that
  483. * matches a local MAC address I/G bit value of 1 or matches a local
  484. * IPv4 or IPv6 address value in the respective multicast address
  485. * range. Otherwise %false.
  486. */
  487. bool efx_siena_filter_is_mc_recipient(const struct efx_filter_spec *spec)
  488. {
  489. if (!(spec->flags & EFX_FILTER_FLAG_RX) ||
  490. spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP)
  491. return false;
  492. if (spec->match_flags &
  493. (EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_LOC_MAC_IG) &&
  494. is_multicast_ether_addr(spec->loc_mac))
  495. return true;
  496. if ((spec->match_flags &
  497. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
  498. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
  499. if (spec->ether_type == htons(ETH_P_IP) &&
  500. ipv4_is_multicast(spec->loc_host[0]))
  501. return true;
  502. if (spec->ether_type == htons(ETH_P_IPV6) &&
  503. ((const u8 *)spec->loc_host)[0] == 0xff)
  504. return true;
  505. }
  506. return false;
  507. }
  508. bool efx_siena_filter_spec_equal(const struct efx_filter_spec *left,
  509. const struct efx_filter_spec *right)
  510. {
  511. if ((left->match_flags ^ right->match_flags) |
  512. ((left->flags ^ right->flags) &
  513. (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
  514. return false;
  515. return memcmp(&left->outer_vid, &right->outer_vid,
  516. sizeof(struct efx_filter_spec) -
  517. offsetof(struct efx_filter_spec, outer_vid)) == 0;
  518. }
  519. u32 efx_siena_filter_spec_hash(const struct efx_filter_spec *spec)
  520. {
  521. BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
  522. return jhash2((const u32 *)&spec->outer_vid,
  523. (sizeof(struct efx_filter_spec) -
  524. offsetof(struct efx_filter_spec, outer_vid)) / 4,
  525. 0);
  526. }
  527. #ifdef CONFIG_RFS_ACCEL
  528. bool efx_siena_rps_check_rule(struct efx_arfs_rule *rule,
  529. unsigned int filter_idx, bool *force)
  530. {
  531. if (rule->filter_id == EFX_ARFS_FILTER_ID_PENDING) {
  532. /* ARFS is currently updating this entry, leave it */
  533. return false;
  534. }
  535. if (rule->filter_id == EFX_ARFS_FILTER_ID_ERROR) {
  536. /* ARFS tried and failed to update this, so it's probably out
  537. * of date. Remove the filter and the ARFS rule entry.
  538. */
  539. rule->filter_id = EFX_ARFS_FILTER_ID_REMOVING;
  540. *force = true;
  541. return true;
  542. } else if (WARN_ON(rule->filter_id != filter_idx)) { /* can't happen */
  543. /* ARFS has moved on, so old filter is not needed. Since we did
  544. * not mark the rule with EFX_ARFS_FILTER_ID_REMOVING, it will
  545. * not be removed by efx_siena_rps_hash_del() subsequently.
  546. */
  547. *force = true;
  548. return true;
  549. }
  550. /* Remove it iff ARFS wants to. */
  551. return true;
  552. }
  553. static
  554. struct hlist_head *efx_rps_hash_bucket(struct efx_nic *efx,
  555. const struct efx_filter_spec *spec)
  556. {
  557. u32 hash = efx_siena_filter_spec_hash(spec);
  558. lockdep_assert_held(&efx->rps_hash_lock);
  559. if (!efx->rps_hash_table)
  560. return NULL;
  561. return &efx->rps_hash_table[hash % EFX_ARFS_HASH_TABLE_SIZE];
  562. }
  563. struct efx_arfs_rule *efx_siena_rps_hash_find(struct efx_nic *efx,
  564. const struct efx_filter_spec *spec)
  565. {
  566. struct efx_arfs_rule *rule;
  567. struct hlist_head *head;
  568. struct hlist_node *node;
  569. head = efx_rps_hash_bucket(efx, spec);
  570. if (!head)
  571. return NULL;
  572. hlist_for_each(node, head) {
  573. rule = container_of(node, struct efx_arfs_rule, node);
  574. if (efx_siena_filter_spec_equal(spec, &rule->spec))
  575. return rule;
  576. }
  577. return NULL;
  578. }
  579. static struct efx_arfs_rule *efx_rps_hash_add(struct efx_nic *efx,
  580. const struct efx_filter_spec *spec,
  581. bool *new)
  582. {
  583. struct efx_arfs_rule *rule;
  584. struct hlist_head *head;
  585. struct hlist_node *node;
  586. head = efx_rps_hash_bucket(efx, spec);
  587. if (!head)
  588. return NULL;
  589. hlist_for_each(node, head) {
  590. rule = container_of(node, struct efx_arfs_rule, node);
  591. if (efx_siena_filter_spec_equal(spec, &rule->spec)) {
  592. *new = false;
  593. return rule;
  594. }
  595. }
  596. rule = kmalloc_obj(*rule, GFP_ATOMIC);
  597. *new = true;
  598. if (rule) {
  599. memcpy(&rule->spec, spec, sizeof(rule->spec));
  600. hlist_add_head(&rule->node, head);
  601. }
  602. return rule;
  603. }
  604. void efx_siena_rps_hash_del(struct efx_nic *efx,
  605. const struct efx_filter_spec *spec)
  606. {
  607. struct efx_arfs_rule *rule;
  608. struct hlist_head *head;
  609. struct hlist_node *node;
  610. head = efx_rps_hash_bucket(efx, spec);
  611. if (WARN_ON(!head))
  612. return;
  613. hlist_for_each(node, head) {
  614. rule = container_of(node, struct efx_arfs_rule, node);
  615. if (efx_siena_filter_spec_equal(spec, &rule->spec)) {
  616. /* Someone already reused the entry. We know that if
  617. * this check doesn't fire (i.e. filter_id == REMOVING)
  618. * then the REMOVING mark was put there by our caller,
  619. * because caller is holding a lock on filter table and
  620. * only holders of that lock set REMOVING.
  621. */
  622. if (rule->filter_id != EFX_ARFS_FILTER_ID_REMOVING)
  623. return;
  624. hlist_del(node);
  625. kfree(rule);
  626. return;
  627. }
  628. }
  629. /* We didn't find it. */
  630. WARN_ON(1);
  631. }
  632. #endif
  633. int efx_siena_probe_filters(struct efx_nic *efx)
  634. {
  635. int rc;
  636. mutex_lock(&efx->mac_lock);
  637. down_write(&efx->filter_sem);
  638. rc = efx->type->filter_table_probe(efx);
  639. if (rc)
  640. goto out_unlock;
  641. #ifdef CONFIG_RFS_ACCEL
  642. if (efx->type->offload_features & NETIF_F_NTUPLE) {
  643. struct efx_channel *channel;
  644. int i, success = 1;
  645. efx_for_each_channel(channel, efx) {
  646. channel->rps_flow_id =
  647. kcalloc(efx->type->max_rx_ip_filters,
  648. sizeof(*channel->rps_flow_id),
  649. GFP_KERNEL);
  650. if (!channel->rps_flow_id)
  651. success = 0;
  652. else
  653. for (i = 0;
  654. i < efx->type->max_rx_ip_filters;
  655. ++i)
  656. channel->rps_flow_id[i] =
  657. RPS_FLOW_ID_INVALID;
  658. channel->rfs_expire_index = 0;
  659. channel->rfs_filter_count = 0;
  660. }
  661. if (!success) {
  662. efx_for_each_channel(channel, efx)
  663. kfree(channel->rps_flow_id);
  664. efx->type->filter_table_remove(efx);
  665. rc = -ENOMEM;
  666. goto out_unlock;
  667. }
  668. }
  669. #endif
  670. out_unlock:
  671. up_write(&efx->filter_sem);
  672. mutex_unlock(&efx->mac_lock);
  673. return rc;
  674. }
  675. void efx_siena_remove_filters(struct efx_nic *efx)
  676. {
  677. #ifdef CONFIG_RFS_ACCEL
  678. struct efx_channel *channel;
  679. efx_for_each_channel(channel, efx) {
  680. cancel_delayed_work_sync(&channel->filter_work);
  681. kfree(channel->rps_flow_id);
  682. channel->rps_flow_id = NULL;
  683. }
  684. #endif
  685. down_write(&efx->filter_sem);
  686. efx->type->filter_table_remove(efx);
  687. up_write(&efx->filter_sem);
  688. }
  689. #ifdef CONFIG_RFS_ACCEL
  690. static void efx_filter_rfs_work(struct work_struct *data)
  691. {
  692. struct efx_async_filter_insertion *req = container_of(data, struct efx_async_filter_insertion,
  693. work);
  694. struct efx_nic *efx = netdev_priv(req->net_dev);
  695. struct efx_channel *channel = efx_get_channel(efx, req->rxq_index);
  696. int slot_idx = req - efx->rps_slot;
  697. struct efx_arfs_rule *rule;
  698. u16 arfs_id = 0;
  699. int rc;
  700. rc = efx->type->filter_insert(efx, &req->spec, true);
  701. if (rc >= 0)
  702. /* Discard 'priority' part of EF10+ filter ID (mcdi_filters) */
  703. rc %= efx->type->max_rx_ip_filters;
  704. if (efx->rps_hash_table) {
  705. spin_lock_bh(&efx->rps_hash_lock);
  706. rule = efx_siena_rps_hash_find(efx, &req->spec);
  707. /* The rule might have already gone, if someone else's request
  708. * for the same spec was already worked and then expired before
  709. * we got around to our work. In that case we have nothing
  710. * tying us to an arfs_id, meaning that as soon as the filter
  711. * is considered for expiry it will be removed.
  712. */
  713. if (rule) {
  714. if (rc < 0)
  715. rule->filter_id = EFX_ARFS_FILTER_ID_ERROR;
  716. else
  717. rule->filter_id = rc;
  718. arfs_id = rule->arfs_id;
  719. }
  720. spin_unlock_bh(&efx->rps_hash_lock);
  721. }
  722. if (rc >= 0) {
  723. /* Remember this so we can check whether to expire the filter
  724. * later.
  725. */
  726. mutex_lock(&efx->rps_mutex);
  727. if (channel->rps_flow_id[rc] == RPS_FLOW_ID_INVALID)
  728. channel->rfs_filter_count++;
  729. channel->rps_flow_id[rc] = req->flow_id;
  730. mutex_unlock(&efx->rps_mutex);
  731. if (req->spec.ether_type == htons(ETH_P_IP))
  732. netif_info(efx, rx_status, efx->net_dev,
  733. "steering %s %pI4:%u:%pI4:%u to queue %u [flow %u filter %d id %u]\n",
  734. (req->spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  735. req->spec.rem_host, ntohs(req->spec.rem_port),
  736. req->spec.loc_host, ntohs(req->spec.loc_port),
  737. req->rxq_index, req->flow_id, rc, arfs_id);
  738. else
  739. netif_info(efx, rx_status, efx->net_dev,
  740. "steering %s [%pI6]:%u:[%pI6]:%u to queue %u [flow %u filter %d id %u]\n",
  741. (req->spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  742. req->spec.rem_host, ntohs(req->spec.rem_port),
  743. req->spec.loc_host, ntohs(req->spec.loc_port),
  744. req->rxq_index, req->flow_id, rc, arfs_id);
  745. channel->n_rfs_succeeded++;
  746. } else {
  747. if (req->spec.ether_type == htons(ETH_P_IP))
  748. netif_dbg(efx, rx_status, efx->net_dev,
  749. "failed to steer %s %pI4:%u:%pI4:%u to queue %u [flow %u rc %d id %u]\n",
  750. (req->spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  751. req->spec.rem_host, ntohs(req->spec.rem_port),
  752. req->spec.loc_host, ntohs(req->spec.loc_port),
  753. req->rxq_index, req->flow_id, rc, arfs_id);
  754. else
  755. netif_dbg(efx, rx_status, efx->net_dev,
  756. "failed to steer %s [%pI6]:%u:[%pI6]:%u to queue %u [flow %u rc %d id %u]\n",
  757. (req->spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  758. req->spec.rem_host, ntohs(req->spec.rem_port),
  759. req->spec.loc_host, ntohs(req->spec.loc_port),
  760. req->rxq_index, req->flow_id, rc, arfs_id);
  761. channel->n_rfs_failed++;
  762. /* We're overloading the NIC's filter tables, so let's do a
  763. * chunk of extra expiry work.
  764. */
  765. __efx_siena_filter_rfs_expire(channel,
  766. min(channel->rfs_filter_count,
  767. 100u));
  768. }
  769. /* Release references */
  770. clear_bit(slot_idx, &efx->rps_slot_map);
  771. netdev_put(req->net_dev, &req->net_dev_tracker);
  772. }
  773. int efx_siena_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
  774. u16 rxq_index, u32 flow_id)
  775. {
  776. struct efx_nic *efx = netdev_priv(net_dev);
  777. struct efx_async_filter_insertion *req;
  778. struct efx_arfs_rule *rule;
  779. struct flow_keys fk;
  780. int slot_idx;
  781. bool new;
  782. int rc;
  783. /* find a free slot */
  784. for (slot_idx = 0; slot_idx < EFX_RPS_MAX_IN_FLIGHT; slot_idx++)
  785. if (!test_and_set_bit(slot_idx, &efx->rps_slot_map))
  786. break;
  787. if (slot_idx >= EFX_RPS_MAX_IN_FLIGHT)
  788. return -EBUSY;
  789. if (flow_id == RPS_FLOW_ID_INVALID) {
  790. rc = -EINVAL;
  791. goto out_clear;
  792. }
  793. if (!skb_flow_dissect_flow_keys(skb, &fk, 0)) {
  794. rc = -EPROTONOSUPPORT;
  795. goto out_clear;
  796. }
  797. if (fk.basic.n_proto != htons(ETH_P_IP) && fk.basic.n_proto != htons(ETH_P_IPV6)) {
  798. rc = -EPROTONOSUPPORT;
  799. goto out_clear;
  800. }
  801. if (fk.control.flags & FLOW_DIS_IS_FRAGMENT) {
  802. rc = -EPROTONOSUPPORT;
  803. goto out_clear;
  804. }
  805. req = efx->rps_slot + slot_idx;
  806. efx_filter_init_rx(&req->spec, EFX_FILTER_PRI_HINT,
  807. efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0,
  808. rxq_index);
  809. req->spec.match_flags =
  810. EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
  811. EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
  812. EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
  813. req->spec.ether_type = fk.basic.n_proto;
  814. req->spec.ip_proto = fk.basic.ip_proto;
  815. if (fk.basic.n_proto == htons(ETH_P_IP)) {
  816. req->spec.rem_host[0] = fk.addrs.v4addrs.src;
  817. req->spec.loc_host[0] = fk.addrs.v4addrs.dst;
  818. } else {
  819. memcpy(req->spec.rem_host, &fk.addrs.v6addrs.src,
  820. sizeof(struct in6_addr));
  821. memcpy(req->spec.loc_host, &fk.addrs.v6addrs.dst,
  822. sizeof(struct in6_addr));
  823. }
  824. req->spec.rem_port = fk.ports.src;
  825. req->spec.loc_port = fk.ports.dst;
  826. if (efx->rps_hash_table) {
  827. /* Add it to ARFS hash table */
  828. spin_lock(&efx->rps_hash_lock);
  829. rule = efx_rps_hash_add(efx, &req->spec, &new);
  830. if (!rule) {
  831. rc = -ENOMEM;
  832. goto out_unlock;
  833. }
  834. if (new)
  835. rule->arfs_id = efx->rps_next_id++ % RPS_NO_FILTER;
  836. rc = rule->arfs_id;
  837. /* Skip if existing or pending filter already does the right thing */
  838. if (!new && rule->rxq_index == rxq_index &&
  839. rule->filter_id >= EFX_ARFS_FILTER_ID_PENDING)
  840. goto out_unlock;
  841. rule->rxq_index = rxq_index;
  842. rule->filter_id = EFX_ARFS_FILTER_ID_PENDING;
  843. spin_unlock(&efx->rps_hash_lock);
  844. } else {
  845. /* Without an ARFS hash table, we just use arfs_id 0 for all
  846. * filters. This means if multiple flows hash to the same
  847. * flow_id, all but the most recently touched will be eligible
  848. * for expiry.
  849. */
  850. rc = 0;
  851. }
  852. /* Queue the request */
  853. req->net_dev = net_dev;
  854. netdev_hold(req->net_dev, &req->net_dev_tracker, GFP_ATOMIC);
  855. INIT_WORK(&req->work, efx_filter_rfs_work);
  856. req->rxq_index = rxq_index;
  857. req->flow_id = flow_id;
  858. schedule_work(&req->work);
  859. return rc;
  860. out_unlock:
  861. spin_unlock(&efx->rps_hash_lock);
  862. out_clear:
  863. clear_bit(slot_idx, &efx->rps_slot_map);
  864. return rc;
  865. }
  866. bool __efx_siena_filter_rfs_expire(struct efx_channel *channel,
  867. unsigned int quota)
  868. {
  869. bool (*expire_one)(struct efx_nic *efx, u32 flow_id, unsigned int index);
  870. struct efx_nic *efx = channel->efx;
  871. unsigned int index, size, start;
  872. u32 flow_id;
  873. if (!mutex_trylock(&efx->rps_mutex))
  874. return false;
  875. expire_one = efx->type->filter_rfs_expire_one;
  876. index = channel->rfs_expire_index;
  877. start = index;
  878. size = efx->type->max_rx_ip_filters;
  879. while (quota) {
  880. flow_id = channel->rps_flow_id[index];
  881. if (flow_id != RPS_FLOW_ID_INVALID) {
  882. quota--;
  883. if (expire_one(efx, flow_id, index)) {
  884. netif_info(efx, rx_status, efx->net_dev,
  885. "expired filter %d [channel %u flow %u]\n",
  886. index, channel->channel, flow_id);
  887. channel->rps_flow_id[index] = RPS_FLOW_ID_INVALID;
  888. channel->rfs_filter_count--;
  889. }
  890. }
  891. if (++index == size)
  892. index = 0;
  893. /* If we were called with a quota that exceeds the total number
  894. * of filters in the table (which shouldn't happen, but could
  895. * if two callers race), ensure that we don't loop forever -
  896. * stop when we've examined every row of the table.
  897. */
  898. if (index == start)
  899. break;
  900. }
  901. channel->rfs_expire_index = index;
  902. mutex_unlock(&efx->rps_mutex);
  903. return true;
  904. }
  905. #endif /* CONFIG_RFS_ACCEL */