qca_spi.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
  2. /*
  3. * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
  4. * Copyright (c) 2014, I2SE GmbH
  5. */
  6. /* This module implements the Qualcomm Atheros SPI protocol for
  7. * kernel-based SPI device; it is essentially an Ethernet-to-SPI
  8. * serial converter;
  9. */
  10. #include <linux/errno.h>
  11. #include <linux/etherdevice.h>
  12. #include <linux/if_arp.h>
  13. #include <linux/if_ether.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/jiffies.h>
  17. #include <linux/kernel.h>
  18. #include <linux/kthread.h>
  19. #include <linux/module.h>
  20. #include <linux/moduleparam.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/of.h>
  23. #include <linux/of_net.h>
  24. #include <linux/sched.h>
  25. #include <linux/skbuff.h>
  26. #include <linux/spi/spi.h>
  27. #include <linux/types.h>
  28. #include "qca_7k.h"
  29. #include "qca_7k_common.h"
  30. #include "qca_debug.h"
  31. #include "qca_spi.h"
  32. #define MAX_DMA_BURST_LEN 5000
  33. #define SPI_INTR 0
  34. #define SPI_RESET 1
  35. /* Modules parameters */
  36. #define QCASPI_CLK_SPEED_MIN 1000000
  37. #define QCASPI_CLK_SPEED_MAX 16000000
  38. #define QCASPI_CLK_SPEED 8000000
  39. static int qcaspi_clkspeed;
  40. module_param(qcaspi_clkspeed, int, 0);
  41. MODULE_PARM_DESC(qcaspi_clkspeed, "SPI bus clock speed (Hz). Use 1000000-16000000.");
  42. #define QCASPI_BURST_LEN_MIN 1
  43. #define QCASPI_BURST_LEN_MAX MAX_DMA_BURST_LEN
  44. static int qcaspi_burst_len = MAX_DMA_BURST_LEN;
  45. module_param(qcaspi_burst_len, int, 0);
  46. MODULE_PARM_DESC(qcaspi_burst_len, "Number of data bytes per burst. Use 1-5000.");
  47. #define QCASPI_PLUGGABLE_MIN 0
  48. #define QCASPI_PLUGGABLE_MAX 1
  49. static int qcaspi_pluggable = QCASPI_PLUGGABLE_MAX;
  50. module_param(qcaspi_pluggable, int, 0);
  51. MODULE_PARM_DESC(qcaspi_pluggable, "Pluggable SPI connection (yes/no).");
  52. #define QCASPI_WRITE_VERIFY_MIN 0
  53. #define QCASPI_WRITE_VERIFY_MAX 3
  54. static int wr_verify = QCASPI_WRITE_VERIFY_MIN;
  55. module_param(wr_verify, int, 0);
  56. MODULE_PARM_DESC(wr_verify, "SPI register write verify trails. Use 0-3.");
  57. #define QCASPI_TX_TIMEOUT (1 * HZ)
  58. #define QCASPI_QCA7K_REBOOT_TIME_MS 1000
  59. static void
  60. start_spi_intr_handling(struct qcaspi *qca, u16 *intr_cause)
  61. {
  62. *intr_cause = 0;
  63. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0, wr_verify);
  64. qcaspi_read_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
  65. netdev_dbg(qca->net_dev, "interrupts: 0x%04x\n", *intr_cause);
  66. }
  67. static void
  68. end_spi_intr_handling(struct qcaspi *qca, u16 intr_cause)
  69. {
  70. u16 intr_enable = (SPI_INT_CPU_ON |
  71. SPI_INT_PKT_AVLBL |
  72. SPI_INT_RDBUF_ERR |
  73. SPI_INT_WRBUF_ERR);
  74. qcaspi_write_register(qca, SPI_REG_INTR_CAUSE, intr_cause, 0);
  75. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, intr_enable, wr_verify);
  76. netdev_dbg(qca->net_dev, "acking int: 0x%04x\n", intr_cause);
  77. }
  78. static u32
  79. qcaspi_write_burst(struct qcaspi *qca, u8 *src, u32 len)
  80. {
  81. __be16 cmd;
  82. struct spi_message msg;
  83. struct spi_transfer transfer[2];
  84. int ret;
  85. memset(&transfer, 0, sizeof(transfer));
  86. spi_message_init(&msg);
  87. cmd = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  88. transfer[0].tx_buf = &cmd;
  89. transfer[0].len = QCASPI_CMD_LEN;
  90. transfer[1].tx_buf = src;
  91. transfer[1].len = len;
  92. spi_message_add_tail(&transfer[0], &msg);
  93. spi_message_add_tail(&transfer[1], &msg);
  94. ret = spi_sync(qca->spi_dev, &msg);
  95. if (ret || (msg.actual_length != QCASPI_CMD_LEN + len)) {
  96. qcaspi_spi_error(qca);
  97. return 0;
  98. }
  99. return len;
  100. }
  101. static u32
  102. qcaspi_write_legacy(struct qcaspi *qca, u8 *src, u32 len)
  103. {
  104. struct spi_message msg;
  105. struct spi_transfer transfer;
  106. int ret;
  107. memset(&transfer, 0, sizeof(transfer));
  108. spi_message_init(&msg);
  109. transfer.tx_buf = src;
  110. transfer.len = len;
  111. spi_message_add_tail(&transfer, &msg);
  112. ret = spi_sync(qca->spi_dev, &msg);
  113. if (ret || (msg.actual_length != len)) {
  114. qcaspi_spi_error(qca);
  115. return 0;
  116. }
  117. return len;
  118. }
  119. static u32
  120. qcaspi_read_burst(struct qcaspi *qca, u8 *dst, u32 len)
  121. {
  122. struct spi_message msg;
  123. __be16 cmd;
  124. struct spi_transfer transfer[2];
  125. int ret;
  126. memset(&transfer, 0, sizeof(transfer));
  127. spi_message_init(&msg);
  128. cmd = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  129. transfer[0].tx_buf = &cmd;
  130. transfer[0].len = QCASPI_CMD_LEN;
  131. transfer[1].rx_buf = dst;
  132. transfer[1].len = len;
  133. spi_message_add_tail(&transfer[0], &msg);
  134. spi_message_add_tail(&transfer[1], &msg);
  135. ret = spi_sync(qca->spi_dev, &msg);
  136. if (ret || (msg.actual_length != QCASPI_CMD_LEN + len)) {
  137. qcaspi_spi_error(qca);
  138. return 0;
  139. }
  140. return len;
  141. }
  142. static u32
  143. qcaspi_read_legacy(struct qcaspi *qca, u8 *dst, u32 len)
  144. {
  145. struct spi_message msg;
  146. struct spi_transfer transfer;
  147. int ret;
  148. memset(&transfer, 0, sizeof(transfer));
  149. spi_message_init(&msg);
  150. transfer.rx_buf = dst;
  151. transfer.len = len;
  152. spi_message_add_tail(&transfer, &msg);
  153. ret = spi_sync(qca->spi_dev, &msg);
  154. if (ret || (msg.actual_length != len)) {
  155. qcaspi_spi_error(qca);
  156. return 0;
  157. }
  158. return len;
  159. }
  160. static int
  161. qcaspi_tx_cmd(struct qcaspi *qca, u16 cmd)
  162. {
  163. __be16 tx_data;
  164. struct spi_message msg;
  165. struct spi_transfer transfer;
  166. int ret;
  167. memset(&transfer, 0, sizeof(transfer));
  168. spi_message_init(&msg);
  169. tx_data = cpu_to_be16(cmd);
  170. transfer.len = sizeof(cmd);
  171. transfer.tx_buf = &tx_data;
  172. spi_message_add_tail(&transfer, &msg);
  173. ret = spi_sync(qca->spi_dev, &msg);
  174. if (!ret)
  175. ret = msg.status;
  176. if (ret)
  177. qcaspi_spi_error(qca);
  178. return ret;
  179. }
  180. static int
  181. qcaspi_tx_frame(struct qcaspi *qca, struct sk_buff *skb)
  182. {
  183. u32 count;
  184. u32 written;
  185. u32 offset;
  186. u32 len;
  187. len = skb->len;
  188. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, len, wr_verify);
  189. if (qca->legacy_mode)
  190. qcaspi_tx_cmd(qca, QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  191. offset = 0;
  192. while (len) {
  193. count = len;
  194. if (count > qca->burst_len)
  195. count = qca->burst_len;
  196. if (qca->legacy_mode) {
  197. written = qcaspi_write_legacy(qca,
  198. skb->data + offset,
  199. count);
  200. } else {
  201. written = qcaspi_write_burst(qca,
  202. skb->data + offset,
  203. count);
  204. }
  205. if (written != count)
  206. return -1;
  207. offset += count;
  208. len -= count;
  209. }
  210. return 0;
  211. }
  212. static int
  213. qcaspi_transmit(struct qcaspi *qca)
  214. {
  215. struct net_device_stats *n_stats = &qca->net_dev->stats;
  216. u16 available = 0;
  217. u32 pkt_len;
  218. u16 new_head;
  219. u16 packets = 0;
  220. if (qca->txr.skb[qca->txr.head] == NULL)
  221. return 0;
  222. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA, &available);
  223. if (available > QCASPI_HW_BUF_LEN) {
  224. /* This could only happen by interferences on the SPI line.
  225. * So retry later ...
  226. */
  227. qca->stats.buf_avail_err++;
  228. return -1;
  229. }
  230. while (qca->txr.skb[qca->txr.head]) {
  231. pkt_len = qca->txr.skb[qca->txr.head]->len + QCASPI_HW_PKT_LEN;
  232. if (available < pkt_len) {
  233. if (packets == 0)
  234. qca->stats.write_buf_miss++;
  235. break;
  236. }
  237. if (qcaspi_tx_frame(qca, qca->txr.skb[qca->txr.head]) == -1) {
  238. qca->stats.write_err++;
  239. return -1;
  240. }
  241. packets++;
  242. n_stats->tx_packets++;
  243. n_stats->tx_bytes += qca->txr.skb[qca->txr.head]->len;
  244. available -= pkt_len;
  245. /* remove the skb from the queue */
  246. /* XXX After inconsistent lock states netif_tx_lock()
  247. * has been replaced by netif_tx_lock_bh() and so on.
  248. */
  249. netif_tx_lock_bh(qca->net_dev);
  250. dev_kfree_skb(qca->txr.skb[qca->txr.head]);
  251. qca->txr.skb[qca->txr.head] = NULL;
  252. qca->txr.size -= pkt_len;
  253. new_head = qca->txr.head + 1;
  254. if (new_head >= qca->txr.count)
  255. new_head = 0;
  256. qca->txr.head = new_head;
  257. if (netif_queue_stopped(qca->net_dev))
  258. netif_wake_queue(qca->net_dev);
  259. netif_tx_unlock_bh(qca->net_dev);
  260. }
  261. return 0;
  262. }
  263. static int
  264. qcaspi_receive(struct qcaspi *qca)
  265. {
  266. struct net_device *net_dev = qca->net_dev;
  267. struct net_device_stats *n_stats = &net_dev->stats;
  268. u16 available = 0;
  269. u32 bytes_read;
  270. u8 *cp;
  271. /* Allocate rx SKB if we don't have one available. */
  272. if (!qca->rx_skb) {
  273. qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
  274. net_dev->mtu +
  275. VLAN_ETH_HLEN);
  276. if (!qca->rx_skb) {
  277. netdev_dbg(net_dev, "out of RX resources\n");
  278. qca->stats.out_of_mem++;
  279. return -1;
  280. }
  281. }
  282. /* Read the packet size. */
  283. qcaspi_read_register(qca, SPI_REG_RDBUF_BYTE_AVA, &available);
  284. netdev_dbg(net_dev, "qcaspi_receive: SPI_REG_RDBUF_BYTE_AVA: Value: %04x\n",
  285. available);
  286. if (available > QCASPI_HW_BUF_LEN + QCASPI_HW_PKT_LEN) {
  287. /* This could only happen by interferences on the SPI line.
  288. * So retry later ...
  289. */
  290. qca->stats.buf_avail_err++;
  291. return -1;
  292. } else if (available == 0) {
  293. netdev_dbg(net_dev, "qcaspi_receive called without any data being available!\n");
  294. return -1;
  295. }
  296. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, available, wr_verify);
  297. if (qca->legacy_mode)
  298. qcaspi_tx_cmd(qca, QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  299. while (available) {
  300. u32 count = available;
  301. if (count > qca->burst_len)
  302. count = qca->burst_len;
  303. if (qca->legacy_mode) {
  304. bytes_read = qcaspi_read_legacy(qca, qca->rx_buffer,
  305. count);
  306. } else {
  307. bytes_read = qcaspi_read_burst(qca, qca->rx_buffer,
  308. count);
  309. }
  310. netdev_dbg(net_dev, "available: %d, byte read: %d\n",
  311. available, bytes_read);
  312. if (bytes_read) {
  313. available -= bytes_read;
  314. } else {
  315. qca->stats.read_err++;
  316. return -1;
  317. }
  318. cp = qca->rx_buffer;
  319. while ((bytes_read--) && (qca->rx_skb)) {
  320. s32 retcode;
  321. retcode = qcafrm_fsm_decode(&qca->frm_handle,
  322. qca->rx_skb->data,
  323. skb_tailroom(qca->rx_skb),
  324. *cp);
  325. cp++;
  326. switch (retcode) {
  327. case QCAFRM_GATHER:
  328. case QCAFRM_NOHEAD:
  329. break;
  330. case QCAFRM_NOTAIL:
  331. netdev_dbg(net_dev, "no RX tail\n");
  332. n_stats->rx_errors++;
  333. n_stats->rx_dropped++;
  334. break;
  335. case QCAFRM_INVLEN:
  336. netdev_dbg(net_dev, "invalid RX length\n");
  337. n_stats->rx_errors++;
  338. n_stats->rx_dropped++;
  339. break;
  340. default:
  341. qca->rx_skb->dev = qca->net_dev;
  342. n_stats->rx_packets++;
  343. n_stats->rx_bytes += retcode;
  344. skb_put(qca->rx_skb, retcode);
  345. qca->rx_skb->protocol = eth_type_trans(
  346. qca->rx_skb, qca->rx_skb->dev);
  347. skb_checksum_none_assert(qca->rx_skb);
  348. netif_rx(qca->rx_skb);
  349. qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
  350. net_dev->mtu + VLAN_ETH_HLEN);
  351. if (!qca->rx_skb) {
  352. netdev_dbg(net_dev, "out of RX resources\n");
  353. n_stats->rx_errors++;
  354. qca->stats.out_of_mem++;
  355. break;
  356. }
  357. }
  358. }
  359. }
  360. return 0;
  361. }
  362. /* Check that tx ring stores only so much bytes
  363. * that fit into the internal QCA buffer.
  364. */
  365. static int
  366. qcaspi_tx_ring_has_space(struct tx_ring *txr)
  367. {
  368. if (txr->skb[txr->tail])
  369. return 0;
  370. return (txr->size + QCAFRM_MAX_LEN < QCASPI_HW_BUF_LEN) ? 1 : 0;
  371. }
  372. /* Flush the tx ring. This function is only safe to
  373. * call from the qcaspi_spi_thread.
  374. */
  375. static void
  376. qcaspi_flush_tx_ring(struct qcaspi *qca)
  377. {
  378. int i;
  379. /* XXX After inconsistent lock states netif_tx_lock()
  380. * has been replaced by netif_tx_lock_bh() and so on.
  381. */
  382. netif_tx_lock_bh(qca->net_dev);
  383. for (i = 0; i < QCASPI_TX_RING_MAX_LEN; i++) {
  384. if (qca->txr.skb[i]) {
  385. dev_kfree_skb(qca->txr.skb[i]);
  386. qca->txr.skb[i] = NULL;
  387. qca->net_dev->stats.tx_dropped++;
  388. }
  389. }
  390. qca->txr.tail = 0;
  391. qca->txr.head = 0;
  392. qca->txr.size = 0;
  393. netif_tx_unlock_bh(qca->net_dev);
  394. }
  395. static void
  396. qcaspi_qca7k_sync(struct qcaspi *qca, int event)
  397. {
  398. u16 signature = 0;
  399. u16 spi_config;
  400. u16 wrbuf_space = 0;
  401. if (event == QCASPI_EVENT_CPUON) {
  402. /* Read signature twice, if not valid
  403. * go back to unknown state.
  404. */
  405. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  406. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  407. if (signature != QCASPI_GOOD_SIGNATURE) {
  408. if (qca->sync == QCASPI_SYNC_READY)
  409. qca->stats.bad_signature++;
  410. set_bit(SPI_RESET, &qca->flags);
  411. netdev_dbg(qca->net_dev, "sync: got CPU on, but signature was invalid, restart\n");
  412. return;
  413. } else {
  414. /* ensure that the WRBUF is empty */
  415. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA,
  416. &wrbuf_space);
  417. if (wrbuf_space != QCASPI_HW_BUF_LEN) {
  418. netdev_dbg(qca->net_dev, "sync: got CPU on, but wrbuf not empty. reset!\n");
  419. qca->sync = QCASPI_SYNC_UNKNOWN;
  420. qca->stats.buf_avail_err++;
  421. } else {
  422. netdev_dbg(qca->net_dev, "sync: got CPU on, now in sync\n");
  423. qca->sync = QCASPI_SYNC_READY;
  424. return;
  425. }
  426. }
  427. } else {
  428. /* Handle reset only on QCASPI_EVENT_UPDATE */
  429. if (test_and_clear_bit(SPI_RESET, &qca->flags))
  430. qca->sync = QCASPI_SYNC_UNKNOWN;
  431. }
  432. switch (qca->sync) {
  433. case QCASPI_SYNC_READY:
  434. /* Check signature twice, if not valid go to unknown state. */
  435. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  436. if (signature != QCASPI_GOOD_SIGNATURE)
  437. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  438. if (signature != QCASPI_GOOD_SIGNATURE) {
  439. set_bit(SPI_RESET, &qca->flags);
  440. qca->stats.bad_signature++;
  441. netdev_dbg(qca->net_dev, "sync: bad signature, restart\n");
  442. /* don't reset right away */
  443. return;
  444. }
  445. break;
  446. case QCASPI_SYNC_UNKNOWN:
  447. /* Read signature, if not valid stay in unknown state */
  448. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  449. if (signature != QCASPI_GOOD_SIGNATURE) {
  450. netdev_dbg(qca->net_dev, "sync: could not read signature to reset device, retry.\n");
  451. return;
  452. }
  453. /* TODO: use GPIO to reset QCA7000 in legacy mode*/
  454. netdev_dbg(qca->net_dev, "sync: resetting device.\n");
  455. qcaspi_read_register(qca, SPI_REG_SPI_CONFIG, &spi_config);
  456. spi_config |= QCASPI_SLAVE_RESET_BIT;
  457. qcaspi_write_register(qca, SPI_REG_SPI_CONFIG, spi_config, 0);
  458. qca->sync = QCASPI_SYNC_RESET;
  459. qca->stats.trig_reset++;
  460. qca->reset_count = 0;
  461. break;
  462. case QCASPI_SYNC_RESET:
  463. qca->reset_count++;
  464. netdev_dbg(qca->net_dev, "sync: waiting for CPU on, count %u.\n",
  465. qca->reset_count);
  466. if (qca->reset_count >= QCASPI_RESET_TIMEOUT) {
  467. /* reset did not seem to take place, try again */
  468. set_bit(SPI_RESET, &qca->flags);
  469. qca->stats.reset_timeout++;
  470. netdev_dbg(qca->net_dev, "sync: reset timeout, restarting process.\n");
  471. }
  472. break;
  473. }
  474. }
  475. static int
  476. qcaspi_spi_thread(void *data)
  477. {
  478. struct qcaspi *qca = data;
  479. u16 intr_cause = 0;
  480. netdev_info(qca->net_dev, "SPI thread created\n");
  481. while (!kthread_should_stop()) {
  482. set_current_state(TASK_INTERRUPTIBLE);
  483. if (kthread_should_park()) {
  484. netif_tx_disable(qca->net_dev);
  485. netif_carrier_off(qca->net_dev);
  486. qcaspi_flush_tx_ring(qca);
  487. kthread_parkme();
  488. if (qca->sync == QCASPI_SYNC_READY) {
  489. netif_carrier_on(qca->net_dev);
  490. netif_wake_queue(qca->net_dev);
  491. }
  492. continue;
  493. }
  494. if (!qca->flags &&
  495. !qca->txr.skb[qca->txr.head])
  496. schedule();
  497. set_current_state(TASK_RUNNING);
  498. netdev_dbg(qca->net_dev, "have work to do. int: %lu, tx_skb: %p\n",
  499. qca->flags,
  500. qca->txr.skb[qca->txr.head]);
  501. qcaspi_qca7k_sync(qca, QCASPI_EVENT_UPDATE);
  502. if (qca->sync != QCASPI_SYNC_READY) {
  503. netdev_dbg(qca->net_dev, "sync: not ready %u, turn off carrier and flush\n",
  504. (unsigned int)qca->sync);
  505. netif_stop_queue(qca->net_dev);
  506. netif_carrier_off(qca->net_dev);
  507. qcaspi_flush_tx_ring(qca);
  508. msleep(QCASPI_QCA7K_REBOOT_TIME_MS);
  509. }
  510. if (test_and_clear_bit(SPI_INTR, &qca->flags)) {
  511. start_spi_intr_handling(qca, &intr_cause);
  512. if (intr_cause & SPI_INT_CPU_ON) {
  513. qcaspi_qca7k_sync(qca, QCASPI_EVENT_CPUON);
  514. /* Frame decoding in progress */
  515. if (qca->frm_handle.state != qca->frm_handle.init)
  516. qca->net_dev->stats.rx_dropped++;
  517. qcafrm_fsm_init_spi(&qca->frm_handle);
  518. qca->stats.device_reset++;
  519. /* not synced. */
  520. if (qca->sync != QCASPI_SYNC_READY)
  521. continue;
  522. netif_wake_queue(qca->net_dev);
  523. netif_carrier_on(qca->net_dev);
  524. }
  525. if (intr_cause & SPI_INT_RDBUF_ERR) {
  526. /* restart sync */
  527. netdev_dbg(qca->net_dev, "===> rdbuf error!\n");
  528. qca->stats.read_buf_err++;
  529. set_bit(SPI_RESET, &qca->flags);
  530. continue;
  531. }
  532. if (intr_cause & SPI_INT_WRBUF_ERR) {
  533. /* restart sync */
  534. netdev_dbg(qca->net_dev, "===> wrbuf error!\n");
  535. qca->stats.write_buf_err++;
  536. set_bit(SPI_RESET, &qca->flags);
  537. continue;
  538. }
  539. /* can only handle other interrupts
  540. * if sync has occurred
  541. */
  542. if (qca->sync == QCASPI_SYNC_READY) {
  543. if (intr_cause & SPI_INT_PKT_AVLBL)
  544. qcaspi_receive(qca);
  545. }
  546. end_spi_intr_handling(qca, intr_cause);
  547. }
  548. if (qca->sync == QCASPI_SYNC_READY)
  549. qcaspi_transmit(qca);
  550. }
  551. set_current_state(TASK_RUNNING);
  552. netdev_info(qca->net_dev, "SPI thread exit\n");
  553. return 0;
  554. }
  555. static irqreturn_t
  556. qcaspi_intr_handler(int irq, void *data)
  557. {
  558. struct qcaspi *qca = data;
  559. set_bit(SPI_INTR, &qca->flags);
  560. if (qca->spi_thread)
  561. wake_up_process(qca->spi_thread);
  562. return IRQ_HANDLED;
  563. }
  564. static int
  565. qcaspi_netdev_open(struct net_device *dev)
  566. {
  567. struct qcaspi *qca = netdev_priv(dev);
  568. struct task_struct *thread;
  569. if (!qca)
  570. return -EINVAL;
  571. set_bit(SPI_INTR, &qca->flags);
  572. qca->sync = QCASPI_SYNC_UNKNOWN;
  573. qcafrm_fsm_init_spi(&qca->frm_handle);
  574. thread = kthread_run((void *)qcaspi_spi_thread,
  575. qca, "%s", dev->name);
  576. if (IS_ERR(thread)) {
  577. netdev_err(dev, "%s: unable to start kernel thread.\n",
  578. QCASPI_DRV_NAME);
  579. return PTR_ERR(thread);
  580. }
  581. qca->spi_thread = thread;
  582. enable_irq(qca->spi_dev->irq);
  583. /* SPI thread takes care of TX queue */
  584. return 0;
  585. }
  586. static int
  587. qcaspi_netdev_close(struct net_device *dev)
  588. {
  589. struct qcaspi *qca = netdev_priv(dev);
  590. netif_stop_queue(dev);
  591. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0, wr_verify);
  592. disable_irq(qca->spi_dev->irq);
  593. if (qca->spi_thread) {
  594. kthread_stop(qca->spi_thread);
  595. qca->spi_thread = NULL;
  596. }
  597. qcaspi_flush_tx_ring(qca);
  598. return 0;
  599. }
  600. static netdev_tx_t
  601. qcaspi_netdev_xmit(struct sk_buff *skb, struct net_device *dev)
  602. {
  603. u32 frame_len;
  604. u8 *ptmp;
  605. struct qcaspi *qca = netdev_priv(dev);
  606. u16 new_tail;
  607. struct sk_buff *tskb;
  608. u8 pad_len = 0;
  609. if (skb->len < QCAFRM_MIN_LEN)
  610. pad_len = QCAFRM_MIN_LEN - skb->len;
  611. if (qca->txr.skb[qca->txr.tail]) {
  612. netdev_warn(qca->net_dev, "queue was unexpectedly full!\n");
  613. netif_stop_queue(qca->net_dev);
  614. qca->stats.ring_full++;
  615. return NETDEV_TX_BUSY;
  616. }
  617. if ((skb_headroom(skb) < QCAFRM_HEADER_LEN) ||
  618. (skb_tailroom(skb) < QCAFRM_FOOTER_LEN + pad_len)) {
  619. tskb = skb_copy_expand(skb, QCAFRM_HEADER_LEN,
  620. QCAFRM_FOOTER_LEN + pad_len, GFP_ATOMIC);
  621. if (!tskb) {
  622. qca->stats.out_of_mem++;
  623. return NETDEV_TX_BUSY;
  624. }
  625. dev_kfree_skb(skb);
  626. skb = tskb;
  627. }
  628. frame_len = skb->len + pad_len;
  629. ptmp = skb_push(skb, QCAFRM_HEADER_LEN);
  630. qcafrm_create_header(ptmp, frame_len);
  631. if (pad_len) {
  632. ptmp = skb_put_zero(skb, pad_len);
  633. }
  634. ptmp = skb_put(skb, QCAFRM_FOOTER_LEN);
  635. qcafrm_create_footer(ptmp);
  636. netdev_dbg(qca->net_dev, "Tx-ing packet: Size: 0x%08x\n",
  637. skb->len);
  638. qca->txr.size += skb->len + QCASPI_HW_PKT_LEN;
  639. new_tail = qca->txr.tail + 1;
  640. if (new_tail >= qca->txr.count)
  641. new_tail = 0;
  642. qca->txr.skb[qca->txr.tail] = skb;
  643. qca->txr.tail = new_tail;
  644. if (!qcaspi_tx_ring_has_space(&qca->txr)) {
  645. netif_stop_queue(qca->net_dev);
  646. qca->stats.ring_full++;
  647. }
  648. netif_trans_update(dev);
  649. if (qca->spi_thread)
  650. wake_up_process(qca->spi_thread);
  651. return NETDEV_TX_OK;
  652. }
  653. static void
  654. qcaspi_netdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
  655. {
  656. struct qcaspi *qca = netdev_priv(dev);
  657. netdev_info(qca->net_dev, "Transmit timeout at %ld, latency %ld\n",
  658. jiffies, jiffies - dev_trans_start(dev));
  659. qca->net_dev->stats.tx_errors++;
  660. /* Trigger tx queue flush and QCA7000 reset */
  661. set_bit(SPI_RESET, &qca->flags);
  662. if (qca->spi_thread)
  663. wake_up_process(qca->spi_thread);
  664. }
  665. static int
  666. qcaspi_netdev_init(struct net_device *dev)
  667. {
  668. struct qcaspi *qca = netdev_priv(dev);
  669. dev->mtu = QCAFRM_MAX_MTU;
  670. dev->type = ARPHRD_ETHER;
  671. qca->burst_len = qcaspi_burst_len;
  672. qca->spi_thread = NULL;
  673. qca->buffer_size = (QCAFRM_MAX_MTU + VLAN_ETH_HLEN + QCAFRM_HEADER_LEN +
  674. QCAFRM_FOOTER_LEN + QCASPI_HW_PKT_LEN) * QCASPI_RX_MAX_FRAMES;
  675. memset(&qca->stats, 0, sizeof(struct qcaspi_stats));
  676. qca->rx_buffer = kmalloc(qca->buffer_size, GFP_KERNEL);
  677. if (!qca->rx_buffer)
  678. return -ENOBUFS;
  679. qca->rx_skb = netdev_alloc_skb_ip_align(dev, qca->net_dev->mtu +
  680. VLAN_ETH_HLEN);
  681. if (!qca->rx_skb) {
  682. kfree(qca->rx_buffer);
  683. netdev_info(qca->net_dev, "Failed to allocate RX sk_buff.\n");
  684. return -ENOBUFS;
  685. }
  686. return 0;
  687. }
  688. static void
  689. qcaspi_netdev_uninit(struct net_device *dev)
  690. {
  691. struct qcaspi *qca = netdev_priv(dev);
  692. kfree(qca->rx_buffer);
  693. qca->buffer_size = 0;
  694. dev_kfree_skb(qca->rx_skb);
  695. }
  696. static const struct net_device_ops qcaspi_netdev_ops = {
  697. .ndo_init = qcaspi_netdev_init,
  698. .ndo_uninit = qcaspi_netdev_uninit,
  699. .ndo_open = qcaspi_netdev_open,
  700. .ndo_stop = qcaspi_netdev_close,
  701. .ndo_start_xmit = qcaspi_netdev_xmit,
  702. .ndo_set_mac_address = eth_mac_addr,
  703. .ndo_tx_timeout = qcaspi_netdev_tx_timeout,
  704. .ndo_validate_addr = eth_validate_addr,
  705. };
  706. static void
  707. qcaspi_netdev_setup(struct net_device *dev)
  708. {
  709. struct qcaspi *qca = NULL;
  710. dev->netdev_ops = &qcaspi_netdev_ops;
  711. qcaspi_set_ethtool_ops(dev);
  712. dev->watchdog_timeo = QCASPI_TX_TIMEOUT;
  713. dev->priv_flags &= ~IFF_TX_SKB_SHARING;
  714. dev->needed_tailroom = ALIGN(QCAFRM_FOOTER_LEN + QCAFRM_MIN_LEN, 4);
  715. dev->needed_headroom = ALIGN(QCAFRM_HEADER_LEN, 4);
  716. dev->tx_queue_len = 100;
  717. /* MTU range: 46 - 1500 */
  718. dev->min_mtu = QCAFRM_MIN_MTU;
  719. dev->max_mtu = QCAFRM_MAX_MTU;
  720. qca = netdev_priv(dev);
  721. memset(qca, 0, sizeof(struct qcaspi));
  722. memset(&qca->txr, 0, sizeof(qca->txr));
  723. qca->txr.count = QCASPI_TX_RING_MAX_LEN;
  724. }
  725. static const struct of_device_id qca_spi_of_match[] = {
  726. { .compatible = "qca,qca7000" },
  727. { /* sentinel */ }
  728. };
  729. MODULE_DEVICE_TABLE(of, qca_spi_of_match);
  730. static int
  731. qca_spi_probe(struct spi_device *spi)
  732. {
  733. struct qcaspi *qca = NULL;
  734. struct net_device *qcaspi_devs = NULL;
  735. u8 legacy_mode = 0;
  736. u16 signature;
  737. int ret;
  738. if (!spi->dev.of_node) {
  739. dev_err(&spi->dev, "Missing device tree\n");
  740. return -EINVAL;
  741. }
  742. legacy_mode = of_property_read_bool(spi->dev.of_node,
  743. "qca,legacy-mode");
  744. if (qcaspi_clkspeed)
  745. spi->max_speed_hz = qcaspi_clkspeed;
  746. else if (!spi->max_speed_hz)
  747. spi->max_speed_hz = QCASPI_CLK_SPEED;
  748. if (spi->max_speed_hz < QCASPI_CLK_SPEED_MIN ||
  749. spi->max_speed_hz > QCASPI_CLK_SPEED_MAX) {
  750. dev_err(&spi->dev, "Invalid clkspeed: %u\n",
  751. spi->max_speed_hz);
  752. return -EINVAL;
  753. }
  754. if ((qcaspi_burst_len < QCASPI_BURST_LEN_MIN) ||
  755. (qcaspi_burst_len > QCASPI_BURST_LEN_MAX)) {
  756. dev_err(&spi->dev, "Invalid burst len: %d\n",
  757. qcaspi_burst_len);
  758. return -EINVAL;
  759. }
  760. if ((qcaspi_pluggable < QCASPI_PLUGGABLE_MIN) ||
  761. (qcaspi_pluggable > QCASPI_PLUGGABLE_MAX)) {
  762. dev_err(&spi->dev, "Invalid pluggable: %d\n",
  763. qcaspi_pluggable);
  764. return -EINVAL;
  765. }
  766. if (wr_verify < QCASPI_WRITE_VERIFY_MIN ||
  767. wr_verify > QCASPI_WRITE_VERIFY_MAX) {
  768. dev_err(&spi->dev, "Invalid write verify: %d\n",
  769. wr_verify);
  770. return -EINVAL;
  771. }
  772. dev_info(&spi->dev, "ver=%s, clkspeed=%u, burst_len=%d, pluggable=%d\n",
  773. QCASPI_DRV_VERSION,
  774. spi->max_speed_hz,
  775. qcaspi_burst_len,
  776. qcaspi_pluggable);
  777. spi->mode = SPI_MODE_3;
  778. if (spi_setup(spi) < 0) {
  779. dev_err(&spi->dev, "Unable to setup SPI device\n");
  780. return -EFAULT;
  781. }
  782. qcaspi_devs = alloc_etherdev(sizeof(struct qcaspi));
  783. if (!qcaspi_devs)
  784. return -ENOMEM;
  785. qcaspi_netdev_setup(qcaspi_devs);
  786. SET_NETDEV_DEV(qcaspi_devs, &spi->dev);
  787. qca = netdev_priv(qcaspi_devs);
  788. if (!qca) {
  789. free_netdev(qcaspi_devs);
  790. dev_err(&spi->dev, "Fail to retrieve private structure\n");
  791. return -ENOMEM;
  792. }
  793. qca->net_dev = qcaspi_devs;
  794. qca->spi_dev = spi;
  795. qca->legacy_mode = legacy_mode;
  796. spi_set_drvdata(spi, qcaspi_devs);
  797. ret = devm_request_irq(&spi->dev, spi->irq, qcaspi_intr_handler,
  798. IRQF_NO_AUTOEN, qca->net_dev->name, qca);
  799. if (ret) {
  800. dev_err(&spi->dev, "Unable to get IRQ %d (irqval=%d).\n",
  801. spi->irq, ret);
  802. free_netdev(qcaspi_devs);
  803. return ret;
  804. }
  805. ret = of_get_ethdev_address(spi->dev.of_node, qca->net_dev);
  806. if (ret) {
  807. eth_hw_addr_random(qca->net_dev);
  808. dev_info(&spi->dev, "Using random MAC address: %pM\n",
  809. qca->net_dev->dev_addr);
  810. }
  811. netif_carrier_off(qca->net_dev);
  812. if (!qcaspi_pluggable) {
  813. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  814. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  815. if (signature != QCASPI_GOOD_SIGNATURE) {
  816. dev_err(&spi->dev, "Invalid signature (expected 0x%04x, read 0x%04x)\n",
  817. QCASPI_GOOD_SIGNATURE, signature);
  818. free_netdev(qcaspi_devs);
  819. return -EFAULT;
  820. }
  821. }
  822. if (register_netdev(qcaspi_devs)) {
  823. dev_err(&spi->dev, "Unable to register net device %s\n",
  824. qcaspi_devs->name);
  825. free_netdev(qcaspi_devs);
  826. return -EFAULT;
  827. }
  828. qcaspi_init_device_debugfs(qca);
  829. return 0;
  830. }
  831. static void
  832. qca_spi_remove(struct spi_device *spi)
  833. {
  834. struct net_device *qcaspi_devs = spi_get_drvdata(spi);
  835. struct qcaspi *qca = netdev_priv(qcaspi_devs);
  836. qcaspi_remove_device_debugfs(qca);
  837. unregister_netdev(qcaspi_devs);
  838. free_netdev(qcaspi_devs);
  839. }
  840. static const struct spi_device_id qca_spi_id[] = {
  841. { "qca7000", 0 },
  842. { /* sentinel */ }
  843. };
  844. MODULE_DEVICE_TABLE(spi, qca_spi_id);
  845. static struct spi_driver qca_spi_driver = {
  846. .driver = {
  847. .name = QCASPI_DRV_NAME,
  848. .of_match_table = qca_spi_of_match,
  849. },
  850. .id_table = qca_spi_id,
  851. .probe = qca_spi_probe,
  852. .remove = qca_spi_remove,
  853. };
  854. module_spi_driver(qca_spi_driver);
  855. MODULE_DESCRIPTION("Qualcomm Atheros QCA7000 SPI Driver");
  856. MODULE_AUTHOR("Qualcomm Atheros Communications");
  857. MODULE_AUTHOR("Stefan Wahren <wahrenst@gmx.net>");
  858. MODULE_LICENSE("Dual BSD/GPL");
  859. MODULE_VERSION(QCASPI_DRV_VERSION);