mtk_wed.h 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */
  3. #ifndef __MTK_WED_PRIV_H
  4. #define __MTK_WED_PRIV_H
  5. #include <linux/soc/mediatek/mtk_wed.h>
  6. #include <linux/debugfs.h>
  7. #include <linux/regmap.h>
  8. #include <linux/netdevice.h>
  9. #include "mtk_wed_regs.h"
  10. struct mtk_eth;
  11. struct mtk_wed_wo;
  12. struct mtk_wed_soc_data {
  13. struct {
  14. u32 tx_bm_tkid;
  15. u32 wpdma_rx_ring[MTK_WED_RX_QUEUES];
  16. u32 reset_idx_tx_mask;
  17. u32 reset_idx_rx_mask;
  18. } regmap;
  19. u32 tx_ring_desc_size;
  20. u32 wdma_desc_size;
  21. };
  22. struct mtk_wed_amsdu {
  23. void *txd;
  24. dma_addr_t txd_phy;
  25. };
  26. struct mtk_wed_hw {
  27. const struct mtk_wed_soc_data *soc;
  28. struct device_node *node;
  29. struct mtk_eth *eth;
  30. struct regmap *regs;
  31. struct regmap *hifsys;
  32. struct device *dev;
  33. void __iomem *wdma;
  34. phys_addr_t wdma_phy;
  35. struct regmap *mirror;
  36. struct dentry *debugfs_dir;
  37. struct mtk_wed_device *wed_dev;
  38. struct mtk_wed_wo *wed_wo;
  39. struct mtk_wed_amsdu *wed_amsdu;
  40. u32 pcie_base;
  41. u32 debugfs_reg;
  42. u32 num_flows;
  43. u8 version;
  44. char dirname[5];
  45. int irq;
  46. int index;
  47. };
  48. struct mtk_wdma_info {
  49. u8 wdma_idx;
  50. u8 queue;
  51. u16 wcid;
  52. u8 bss;
  53. u8 amsdu;
  54. };
  55. #ifdef CONFIG_NET_MEDIATEK_SOC_WED
  56. static inline bool mtk_wed_is_v1(struct mtk_wed_hw *hw)
  57. {
  58. return hw->version == 1;
  59. }
  60. static inline bool mtk_wed_is_v2(struct mtk_wed_hw *hw)
  61. {
  62. return hw->version == 2;
  63. }
  64. static inline bool mtk_wed_is_v3(struct mtk_wed_hw *hw)
  65. {
  66. return hw->version == 3;
  67. }
  68. static inline bool mtk_wed_is_v3_or_greater(struct mtk_wed_hw *hw)
  69. {
  70. return hw->version > 2;
  71. }
  72. static inline void
  73. wed_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
  74. {
  75. regmap_write(dev->hw->regs, reg, val);
  76. }
  77. static inline u32
  78. wed_r32(struct mtk_wed_device *dev, u32 reg)
  79. {
  80. unsigned int val;
  81. regmap_read(dev->hw->regs, reg, &val);
  82. return val;
  83. }
  84. static inline void
  85. wdma_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
  86. {
  87. writel(val, dev->hw->wdma + reg);
  88. }
  89. static inline u32
  90. wdma_r32(struct mtk_wed_device *dev, u32 reg)
  91. {
  92. return readl(dev->hw->wdma + reg);
  93. }
  94. static inline u32
  95. wpdma_tx_r32(struct mtk_wed_device *dev, int ring, u32 reg)
  96. {
  97. if (!dev->tx_ring[ring].wpdma)
  98. return 0;
  99. return readl(dev->tx_ring[ring].wpdma + reg);
  100. }
  101. static inline void
  102. wpdma_tx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)
  103. {
  104. if (!dev->tx_ring[ring].wpdma)
  105. return;
  106. writel(val, dev->tx_ring[ring].wpdma + reg);
  107. }
  108. static inline u32
  109. wpdma_rx_r32(struct mtk_wed_device *dev, int ring, u32 reg)
  110. {
  111. if (!dev->rx_ring[ring].wpdma)
  112. return 0;
  113. return readl(dev->rx_ring[ring].wpdma + reg);
  114. }
  115. static inline void
  116. wpdma_rx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)
  117. {
  118. if (!dev->rx_ring[ring].wpdma)
  119. return;
  120. writel(val, dev->rx_ring[ring].wpdma + reg);
  121. }
  122. static inline u32
  123. wpdma_txfree_r32(struct mtk_wed_device *dev, u32 reg)
  124. {
  125. if (!dev->txfree_ring.wpdma)
  126. return 0;
  127. return readl(dev->txfree_ring.wpdma + reg);
  128. }
  129. static inline void
  130. wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
  131. {
  132. if (!dev->txfree_ring.wpdma)
  133. return;
  134. writel(val, dev->txfree_ring.wpdma + reg);
  135. }
  136. static inline u32 mtk_wed_get_pcie_base(struct mtk_wed_device *dev)
  137. {
  138. if (!mtk_wed_is_v3_or_greater(dev->hw))
  139. return MTK_WED_PCIE_BASE;
  140. switch (dev->hw->index) {
  141. case 1:
  142. return MTK_WED_PCIE_BASE1;
  143. case 2:
  144. return MTK_WED_PCIE_BASE2;
  145. default:
  146. return MTK_WED_PCIE_BASE0;
  147. }
  148. }
  149. void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
  150. void __iomem *wdma, phys_addr_t wdma_phy,
  151. int index);
  152. void mtk_wed_exit(void);
  153. int mtk_wed_flow_add(int index);
  154. void mtk_wed_flow_remove(int index);
  155. void mtk_wed_fe_reset(void);
  156. void mtk_wed_fe_reset_complete(void);
  157. #else
  158. static inline void
  159. mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
  160. void __iomem *wdma, phys_addr_t wdma_phy,
  161. int index)
  162. {
  163. }
  164. static inline void
  165. mtk_wed_exit(void)
  166. {
  167. }
  168. static inline int mtk_wed_flow_add(int index)
  169. {
  170. return -EINVAL;
  171. }
  172. static inline void mtk_wed_flow_remove(int index)
  173. {
  174. }
  175. static inline void mtk_wed_fe_reset(void)
  176. {
  177. }
  178. static inline void mtk_wed_fe_reset_complete(void)
  179. {
  180. }
  181. #endif
  182. #ifdef CONFIG_DEBUG_FS
  183. void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw);
  184. #else
  185. static inline void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)
  186. {
  187. }
  188. #endif
  189. #endif