dl2k.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  3. /*
  4. Copyright (c) 2001, 2002 by D-Link Corporation
  5. Written by Edward Peng.<edward_peng@dlink.com.tw>
  6. Created 03-May-2001, base on Linux' sundance.c.
  7. */
  8. #include "dl2k.h"
  9. #include <linux/dma-mapping.h>
  10. #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
  11. #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
  12. #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
  13. #define dr32(reg) ioread32(ioaddr + (reg))
  14. #define dr16(reg) ioread16(ioaddr + (reg))
  15. #define dr8(reg) ioread8(ioaddr + (reg))
  16. #define MAX_UNITS 8
  17. static int mtu[MAX_UNITS];
  18. static int vlan[MAX_UNITS];
  19. static int jumbo[MAX_UNITS];
  20. static char *media[MAX_UNITS];
  21. static int tx_flow=-1;
  22. static int rx_flow=-1;
  23. static int copy_thresh;
  24. static int rx_coalesce=10; /* Rx frame count each interrupt */
  25. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  26. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  27. MODULE_AUTHOR ("Edward Peng");
  28. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  29. MODULE_LICENSE("GPL");
  30. module_param_array(mtu, int, NULL, 0);
  31. module_param_array(media, charp, NULL, 0);
  32. module_param_array(vlan, int, NULL, 0);
  33. module_param_array(jumbo, int, NULL, 0);
  34. module_param(tx_flow, int, 0);
  35. module_param(rx_flow, int, 0);
  36. module_param(copy_thresh, int, 0);
  37. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  38. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 640ns increments */
  39. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  40. /* Enable the default interrupts */
  41. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  42. UpdateStats | LinkEvent)
  43. static void dl2k_enable_int(struct netdev_private *np)
  44. {
  45. void __iomem *ioaddr = np->ioaddr;
  46. dw16(IntEnable, DEFAULT_INTR);
  47. }
  48. static const int max_intrloop = 50;
  49. static const int multicast_filter_limit = 0x40;
  50. static int rio_open (struct net_device *dev);
  51. static void rio_timer (struct timer_list *t);
  52. static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue);
  53. static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
  54. static irqreturn_t rio_interrupt (int irq, void *dev_instance);
  55. static void rio_free_tx (struct net_device *dev, int irq);
  56. static void tx_error (struct net_device *dev, int tx_status);
  57. static int receive_packet (struct net_device *dev);
  58. static void rio_error (struct net_device *dev, int int_status);
  59. static void set_multicast (struct net_device *dev);
  60. static struct net_device_stats *get_stats (struct net_device *dev);
  61. static int clear_stats (struct net_device *dev);
  62. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  63. static int rio_close (struct net_device *dev);
  64. static int find_miiphy (struct net_device *dev);
  65. static int parse_eeprom (struct net_device *dev);
  66. static int read_eeprom (struct netdev_private *, int eep_addr);
  67. static int mii_wait_link (struct net_device *dev, int wait);
  68. static int mii_set_media (struct net_device *dev);
  69. static int mii_get_media (struct net_device *dev);
  70. static int mii_set_media_pcs (struct net_device *dev);
  71. static int mii_get_media_pcs (struct net_device *dev);
  72. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  73. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  74. u16 data);
  75. static const struct ethtool_ops ethtool_ops;
  76. static const struct net_device_ops netdev_ops = {
  77. .ndo_open = rio_open,
  78. .ndo_start_xmit = start_xmit,
  79. .ndo_stop = rio_close,
  80. .ndo_get_stats = get_stats,
  81. .ndo_validate_addr = eth_validate_addr,
  82. .ndo_set_mac_address = eth_mac_addr,
  83. .ndo_set_rx_mode = set_multicast,
  84. .ndo_eth_ioctl = rio_ioctl,
  85. .ndo_tx_timeout = rio_tx_timeout,
  86. };
  87. static bool is_support_rmon_mmio(struct pci_dev *pdev)
  88. {
  89. return pdev->vendor == PCI_VENDOR_ID_DLINK &&
  90. pdev->device == 0x4000 &&
  91. pdev->revision == 0x0c;
  92. }
  93. static int
  94. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  95. {
  96. struct net_device *dev;
  97. struct netdev_private *np;
  98. static int card_idx;
  99. int chip_idx = ent->driver_data;
  100. int err, irq;
  101. void __iomem *ioaddr;
  102. void *ring_space;
  103. dma_addr_t ring_dma;
  104. err = pci_enable_device (pdev);
  105. if (err)
  106. return err;
  107. irq = pdev->irq;
  108. err = pci_request_regions (pdev, "dl2k");
  109. if (err)
  110. goto err_out_disable;
  111. pci_set_master (pdev);
  112. err = -ENOMEM;
  113. dev = alloc_etherdev (sizeof (*np));
  114. if (!dev)
  115. goto err_out_res;
  116. SET_NETDEV_DEV(dev, &pdev->dev);
  117. np = netdev_priv(dev);
  118. if (is_support_rmon_mmio(pdev))
  119. np->rmon_enable = true;
  120. /* IO registers range. */
  121. ioaddr = pci_iomap(pdev, 0, 0);
  122. if (!ioaddr)
  123. goto err_out_dev;
  124. np->eeprom_addr = ioaddr;
  125. if (np->rmon_enable) {
  126. /* MM registers range. */
  127. ioaddr = pci_iomap(pdev, 1, 0);
  128. if (!ioaddr)
  129. goto err_out_iounmap;
  130. }
  131. np->ioaddr = ioaddr;
  132. np->chip_id = chip_idx;
  133. np->pdev = pdev;
  134. spin_lock_init(&np->stats_lock);
  135. spin_lock_init (&np->tx_lock);
  136. spin_lock_init (&np->rx_lock);
  137. /* Parse manual configuration */
  138. np->an_enable = 1;
  139. np->tx_coalesce = 1;
  140. if (card_idx < MAX_UNITS) {
  141. if (media[card_idx] != NULL) {
  142. np->an_enable = 0;
  143. if (strcmp (media[card_idx], "auto") == 0 ||
  144. strcmp (media[card_idx], "autosense") == 0 ||
  145. strcmp (media[card_idx], "0") == 0 ) {
  146. np->an_enable = 2;
  147. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  148. strcmp (media[card_idx], "4") == 0) {
  149. np->speed = 100;
  150. np->full_duplex = 1;
  151. } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
  152. strcmp (media[card_idx], "3") == 0) {
  153. np->speed = 100;
  154. np->full_duplex = 0;
  155. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  156. strcmp (media[card_idx], "2") == 0) {
  157. np->speed = 10;
  158. np->full_duplex = 1;
  159. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  160. strcmp (media[card_idx], "1") == 0) {
  161. np->speed = 10;
  162. np->full_duplex = 0;
  163. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  164. strcmp (media[card_idx], "6") == 0) {
  165. np->speed=1000;
  166. np->full_duplex=1;
  167. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  168. strcmp (media[card_idx], "5") == 0) {
  169. np->speed = 1000;
  170. np->full_duplex = 0;
  171. } else {
  172. np->an_enable = 1;
  173. }
  174. }
  175. if (jumbo[card_idx] != 0) {
  176. np->jumbo = 1;
  177. dev->mtu = MAX_JUMBO;
  178. } else {
  179. np->jumbo = 0;
  180. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  181. dev->mtu = mtu[card_idx];
  182. }
  183. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  184. vlan[card_idx] : 0;
  185. if (rx_coalesce > 0 && rx_timeout > 0) {
  186. np->rx_coalesce = rx_coalesce;
  187. np->rx_timeout = rx_timeout;
  188. np->coalesce = 1;
  189. }
  190. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  191. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  192. if (tx_coalesce < 1)
  193. tx_coalesce = 1;
  194. else if (tx_coalesce > TX_RING_SIZE-1)
  195. tx_coalesce = TX_RING_SIZE - 1;
  196. }
  197. dev->netdev_ops = &netdev_ops;
  198. dev->watchdog_timeo = TX_TIMEOUT;
  199. dev->ethtool_ops = &ethtool_ops;
  200. #if 0
  201. dev->features = NETIF_F_IP_CSUM;
  202. #endif
  203. /* MTU range: 68 - 1536 or 8000 */
  204. dev->min_mtu = ETH_MIN_MTU;
  205. dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
  206. pci_set_drvdata (pdev, dev);
  207. ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
  208. GFP_KERNEL);
  209. if (!ring_space)
  210. goto err_out_iounmap;
  211. np->tx_ring = ring_space;
  212. np->tx_ring_dma = ring_dma;
  213. ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
  214. GFP_KERNEL);
  215. if (!ring_space)
  216. goto err_out_unmap_tx;
  217. np->rx_ring = ring_space;
  218. np->rx_ring_dma = ring_dma;
  219. /* Parse eeprom data */
  220. parse_eeprom (dev);
  221. /* Find PHY address */
  222. err = find_miiphy (dev);
  223. if (err)
  224. goto err_out_unmap_rx;
  225. /* Fiber device? */
  226. np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
  227. np->link_status = 0;
  228. /* Set media and reset PHY */
  229. if (np->phy_media) {
  230. /* default Auto-Negotiation for fiber devices */
  231. if (np->an_enable == 2) {
  232. np->an_enable = 1;
  233. }
  234. } else {
  235. /* Auto-Negotiation is mandatory for 1000BASE-T,
  236. IEEE 802.3ab Annex 28D page 14 */
  237. if (np->speed == 1000)
  238. np->an_enable = 1;
  239. }
  240. err = register_netdev (dev);
  241. if (err)
  242. goto err_out_unmap_rx;
  243. card_idx++;
  244. netdev_info(dev, "%s, %pM, IRQ %d", np->name, dev->dev_addr, irq);
  245. if (tx_coalesce > 1)
  246. netdev_dbg(dev, "tx_coalesce:\t%d packets", tx_coalesce);
  247. if (np->coalesce) {
  248. netdev_dbg(dev, "rx_coalesce:\t%d packets", np->rx_coalesce);
  249. netdev_dbg(dev, "rx_timeout: \t%d ns", np->rx_timeout * 640);
  250. }
  251. if (np->vlan)
  252. netdev_dbg(dev, "vlan(id):\t%d", np->vlan);
  253. return 0;
  254. err_out_unmap_rx:
  255. dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
  256. np->rx_ring_dma);
  257. err_out_unmap_tx:
  258. dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
  259. np->tx_ring_dma);
  260. err_out_iounmap:
  261. if (np->rmon_enable)
  262. pci_iounmap(pdev, np->ioaddr);
  263. pci_iounmap(pdev, np->eeprom_addr);
  264. err_out_dev:
  265. free_netdev (dev);
  266. err_out_res:
  267. pci_release_regions (pdev);
  268. err_out_disable:
  269. pci_disable_device (pdev);
  270. return err;
  271. }
  272. static int
  273. find_miiphy (struct net_device *dev)
  274. {
  275. struct netdev_private *np = netdev_priv(dev);
  276. int i, phy_found = 0;
  277. np->phy_addr = 1;
  278. for (i = 31; i >= 0; i--) {
  279. int mii_status = mii_read (dev, i, 1);
  280. if (mii_status != 0xffff && mii_status != 0x0000) {
  281. np->phy_addr = i;
  282. phy_found++;
  283. }
  284. }
  285. if (!phy_found) {
  286. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  287. return -ENODEV;
  288. }
  289. return 0;
  290. }
  291. static int
  292. parse_eeprom (struct net_device *dev)
  293. {
  294. struct netdev_private *np = netdev_priv(dev);
  295. void __iomem *ioaddr = np->ioaddr;
  296. int i, j;
  297. u8 sromdata[256];
  298. u8 *psib;
  299. u32 crc;
  300. PSROM_t psrom = (PSROM_t) sromdata;
  301. int cid, next;
  302. for (i = 0; i < 128; i++)
  303. ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
  304. if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
  305. /* Check CRC */
  306. crc = ~ether_crc_le (256 - 4, sromdata);
  307. if (psrom->crc != cpu_to_le32(crc)) {
  308. printk (KERN_ERR "%s: EEPROM data CRC error.\n",
  309. dev->name);
  310. return -1;
  311. }
  312. }
  313. /* Set MAC address */
  314. eth_hw_addr_set(dev, psrom->mac_addr);
  315. if (np->chip_id == CHIP_IP1000A) {
  316. np->led_mode = le16_to_cpu(psrom->led_mode);
  317. return 0;
  318. }
  319. if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
  320. return 0;
  321. }
  322. /* Parse Software Information Block */
  323. i = 0x30;
  324. psib = (u8 *) sromdata;
  325. do {
  326. cid = psib[i++];
  327. next = psib[i++];
  328. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  329. printk (KERN_ERR "Cell data error\n");
  330. return -1;
  331. }
  332. switch (cid) {
  333. case 0: /* Format version */
  334. break;
  335. case 1: /* End of cell */
  336. return 0;
  337. case 2: /* Duplex Polarity */
  338. np->duplex_polarity = psib[i];
  339. dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
  340. break;
  341. case 3: /* Wake Polarity */
  342. np->wake_polarity = psib[i];
  343. break;
  344. case 9: /* Adapter description */
  345. j = (next - i > 255) ? 255 : next - i;
  346. memcpy (np->name, &(psib[i]), j);
  347. break;
  348. case 4:
  349. case 5:
  350. case 6:
  351. case 7:
  352. case 8: /* Reversed */
  353. break;
  354. default: /* Unknown cell */
  355. return -1;
  356. }
  357. i = next;
  358. } while (1);
  359. return 0;
  360. }
  361. static void rio_set_led_mode(struct net_device *dev)
  362. {
  363. struct netdev_private *np = netdev_priv(dev);
  364. void __iomem *ioaddr = np->ioaddr;
  365. u32 mode;
  366. if (np->chip_id != CHIP_IP1000A)
  367. return;
  368. mode = dr32(ASICCtrl);
  369. mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
  370. if (np->led_mode & 0x01)
  371. mode |= IPG_AC_LED_MODE;
  372. if (np->led_mode & 0x02)
  373. mode |= IPG_AC_LED_MODE_BIT_1;
  374. if (np->led_mode & 0x08)
  375. mode |= IPG_AC_LED_SPEED;
  376. dw32(ASICCtrl, mode);
  377. }
  378. static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
  379. {
  380. return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
  381. }
  382. static void free_list(struct net_device *dev)
  383. {
  384. struct netdev_private *np = netdev_priv(dev);
  385. struct sk_buff *skb;
  386. int i;
  387. /* Free all the skbuffs in the queue. */
  388. for (i = 0; i < RX_RING_SIZE; i++) {
  389. skb = np->rx_skbuff[i];
  390. if (skb) {
  391. dma_unmap_single(&np->pdev->dev,
  392. desc_to_dma(&np->rx_ring[i]),
  393. skb->len, DMA_FROM_DEVICE);
  394. dev_kfree_skb(skb);
  395. np->rx_skbuff[i] = NULL;
  396. }
  397. np->rx_ring[i].status = 0;
  398. np->rx_ring[i].fraginfo = 0;
  399. }
  400. for (i = 0; i < TX_RING_SIZE; i++) {
  401. skb = np->tx_skbuff[i];
  402. if (skb) {
  403. dma_unmap_single(&np->pdev->dev,
  404. desc_to_dma(&np->tx_ring[i]),
  405. skb->len, DMA_TO_DEVICE);
  406. dev_kfree_skb(skb);
  407. np->tx_skbuff[i] = NULL;
  408. }
  409. }
  410. }
  411. static void rio_reset_ring(struct netdev_private *np)
  412. {
  413. int i;
  414. np->cur_rx = 0;
  415. np->cur_tx = 0;
  416. np->old_rx = 0;
  417. np->old_tx = 0;
  418. for (i = 0; i < TX_RING_SIZE; i++)
  419. np->tx_ring[i].status = cpu_to_le64(TFDDone);
  420. for (i = 0; i < RX_RING_SIZE; i++)
  421. np->rx_ring[i].status = 0;
  422. }
  423. /* allocate and initialize Tx and Rx descriptors */
  424. static int alloc_list(struct net_device *dev)
  425. {
  426. struct netdev_private *np = netdev_priv(dev);
  427. int i;
  428. rio_reset_ring(np);
  429. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  430. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  431. for (i = 0; i < TX_RING_SIZE; i++) {
  432. np->tx_skbuff[i] = NULL;
  433. np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
  434. ((i + 1) % TX_RING_SIZE) *
  435. sizeof(struct netdev_desc));
  436. }
  437. /* Initialize Rx descriptors & allocate buffers */
  438. for (i = 0; i < RX_RING_SIZE; i++) {
  439. /* Allocated fixed size of skbuff */
  440. struct sk_buff *skb;
  441. dma_addr_t addr;
  442. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  443. np->rx_skbuff[i] = skb;
  444. if (!skb)
  445. goto err_free_list;
  446. addr = dma_map_single(&np->pdev->dev, skb->data,
  447. np->rx_buf_sz, DMA_FROM_DEVICE);
  448. if (dma_mapping_error(&np->pdev->dev, addr))
  449. goto err_kfree_skb;
  450. np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
  451. ((i + 1) % RX_RING_SIZE) *
  452. sizeof(struct netdev_desc));
  453. /* Rubicon now supports 40 bits of addressing space. */
  454. np->rx_ring[i].fraginfo = cpu_to_le64(addr);
  455. np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
  456. }
  457. return 0;
  458. err_kfree_skb:
  459. dev_kfree_skb(np->rx_skbuff[i]);
  460. np->rx_skbuff[i] = NULL;
  461. err_free_list:
  462. free_list(dev);
  463. return -ENOMEM;
  464. }
  465. static void rio_hw_init(struct net_device *dev)
  466. {
  467. struct netdev_private *np = netdev_priv(dev);
  468. void __iomem *ioaddr = np->ioaddr;
  469. int i;
  470. u16 macctrl;
  471. /* Reset all logic functions */
  472. dw16(ASICCtrl + 2,
  473. GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
  474. mdelay(10);
  475. rio_set_led_mode(dev);
  476. /* DebugCtrl bit 4, 5, 9 must set */
  477. dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
  478. if (np->chip_id == CHIP_IP1000A &&
  479. (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
  480. /* PHY magic taken from ipg driver, undocumented registers */
  481. mii_write(dev, np->phy_addr, 31, 0x0001);
  482. mii_write(dev, np->phy_addr, 27, 0x01e0);
  483. mii_write(dev, np->phy_addr, 31, 0x0002);
  484. mii_write(dev, np->phy_addr, 27, 0xeb8e);
  485. mii_write(dev, np->phy_addr, 31, 0x0000);
  486. mii_write(dev, np->phy_addr, 30, 0x005e);
  487. /* advertise 1000BASE-T half & full duplex, prefer MASTER */
  488. mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
  489. }
  490. if (np->phy_media)
  491. mii_set_media_pcs(dev);
  492. else
  493. mii_set_media(dev);
  494. /* Jumbo frame */
  495. if (np->jumbo != 0)
  496. dw16(MaxFrameSize, MAX_JUMBO+14);
  497. /* Set RFDListPtr */
  498. dw32(RFDListPtr0, np->rx_ring_dma);
  499. dw32(RFDListPtr1, 0);
  500. /* Set station address */
  501. /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
  502. * too. However, it doesn't work on IP1000A so we use 16-bit access.
  503. */
  504. for (i = 0; i < 3; i++)
  505. dw16(StationAddr0 + 2 * i, get_unaligned_le16(&dev->dev_addr[2 * i]));
  506. set_multicast (dev);
  507. if (np->coalesce) {
  508. dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
  509. }
  510. /* Set RIO to poll every N*320nsec. */
  511. dw8(RxDMAPollPeriod, 0x20);
  512. dw8(TxDMAPollPeriod, 0xff);
  513. dw8(RxDMABurstThresh, 0x30);
  514. dw8(RxDMAUrgentThresh, 0x30);
  515. if (!np->rmon_enable)
  516. dw32(RmonStatMask, 0x0007ffff);
  517. /* clear statistics */
  518. clear_stats (dev);
  519. /* VLAN supported */
  520. if (np->vlan) {
  521. /* priority field in RxDMAIntCtrl */
  522. dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
  523. /* VLANId */
  524. dw16(VLANId, np->vlan);
  525. /* Length/Type should be 0x8100 */
  526. dw32(VLANTag, 0x8100 << 16 | np->vlan);
  527. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  528. VLAN information tagged by TFC' VID, CFI fields. */
  529. dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
  530. }
  531. /* Start Tx/Rx */
  532. dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
  533. macctrl = 0;
  534. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  535. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  536. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  537. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  538. dw16(MACCtrl, macctrl);
  539. }
  540. static void rio_hw_stop(struct net_device *dev)
  541. {
  542. struct netdev_private *np = netdev_priv(dev);
  543. void __iomem *ioaddr = np->ioaddr;
  544. /* Disable interrupts */
  545. dw16(IntEnable, 0);
  546. /* Stop Tx and Rx logics */
  547. dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
  548. }
  549. static int rio_open(struct net_device *dev)
  550. {
  551. struct netdev_private *np = netdev_priv(dev);
  552. const int irq = np->pdev->irq;
  553. int i;
  554. i = alloc_list(dev);
  555. if (i)
  556. return i;
  557. rio_hw_init(dev);
  558. i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
  559. if (i) {
  560. rio_hw_stop(dev);
  561. free_list(dev);
  562. return i;
  563. }
  564. timer_setup(&np->timer, rio_timer, 0);
  565. np->timer.expires = jiffies + 1 * HZ;
  566. add_timer(&np->timer);
  567. netif_start_queue (dev);
  568. dl2k_enable_int(np);
  569. return 0;
  570. }
  571. static void
  572. rio_timer (struct timer_list *t)
  573. {
  574. struct netdev_private *np = timer_container_of(np, t, timer);
  575. struct net_device *dev = pci_get_drvdata(np->pdev);
  576. unsigned int entry;
  577. int next_tick = 1*HZ;
  578. unsigned long flags;
  579. spin_lock_irqsave(&np->rx_lock, flags);
  580. /* Recover rx ring exhausted error */
  581. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  582. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  583. /* Re-allocate skbuffs to fill the descriptor ring */
  584. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  585. struct sk_buff *skb;
  586. entry = np->old_rx % RX_RING_SIZE;
  587. /* Dropped packets don't need to re-allocate */
  588. if (np->rx_skbuff[entry] == NULL) {
  589. skb = netdev_alloc_skb_ip_align(dev,
  590. np->rx_buf_sz);
  591. if (skb == NULL) {
  592. np->rx_ring[entry].fraginfo = 0;
  593. printk (KERN_INFO
  594. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  595. dev->name, entry);
  596. break;
  597. }
  598. np->rx_skbuff[entry] = skb;
  599. np->rx_ring[entry].fraginfo =
  600. cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
  601. np->rx_buf_sz, DMA_FROM_DEVICE));
  602. }
  603. np->rx_ring[entry].fraginfo |=
  604. cpu_to_le64((u64)np->rx_buf_sz << 48);
  605. np->rx_ring[entry].status = 0;
  606. } /* end for */
  607. } /* end if */
  608. spin_unlock_irqrestore (&np->rx_lock, flags);
  609. np->timer.expires = jiffies + next_tick;
  610. add_timer(&np->timer);
  611. }
  612. static void
  613. rio_tx_timeout (struct net_device *dev, unsigned int txqueue)
  614. {
  615. struct netdev_private *np = netdev_priv(dev);
  616. void __iomem *ioaddr = np->ioaddr;
  617. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  618. dev->name, dr32(TxStatus));
  619. rio_free_tx(dev, 0);
  620. dev->if_port = 0;
  621. netif_trans_update(dev); /* prevent tx timeout */
  622. }
  623. static netdev_tx_t
  624. start_xmit (struct sk_buff *skb, struct net_device *dev)
  625. {
  626. struct netdev_private *np = netdev_priv(dev);
  627. void __iomem *ioaddr = np->ioaddr;
  628. struct netdev_desc *txdesc;
  629. unsigned entry;
  630. u64 tfc_vlan_tag = 0;
  631. if (np->link_status == 0) { /* Link Down */
  632. dev_kfree_skb_any(skb);
  633. return NETDEV_TX_OK;
  634. }
  635. entry = np->cur_tx % TX_RING_SIZE;
  636. np->tx_skbuff[entry] = skb;
  637. txdesc = &np->tx_ring[entry];
  638. #if 0
  639. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  640. txdesc->status |=
  641. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  642. IPChecksumEnable);
  643. }
  644. #endif
  645. if (np->vlan) {
  646. tfc_vlan_tag = VLANTagInsert |
  647. ((u64)np->vlan << 32) |
  648. ((u64)skb->priority << 45);
  649. }
  650. txdesc->fraginfo = cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
  651. skb->len, DMA_TO_DEVICE));
  652. txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
  653. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  654. * Work around: Always use 1 descriptor in 10Mbps mode */
  655. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  656. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  657. WordAlignDisable |
  658. TxDMAIndicate |
  659. (1 << FragCountShift));
  660. else
  661. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  662. WordAlignDisable |
  663. (1 << FragCountShift));
  664. /* TxDMAPollNow */
  665. dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
  666. /* Schedule ISR */
  667. dw32(CountDown, 10000);
  668. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  669. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  670. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  671. /* do nothing */
  672. } else if (!netif_queue_stopped(dev)) {
  673. netif_stop_queue (dev);
  674. }
  675. /* The first TFDListPtr */
  676. if (!dr32(TFDListPtr0)) {
  677. dw32(TFDListPtr0, np->tx_ring_dma +
  678. entry * sizeof (struct netdev_desc));
  679. dw32(TFDListPtr1, 0);
  680. }
  681. return NETDEV_TX_OK;
  682. }
  683. static irqreturn_t
  684. rio_interrupt (int irq, void *dev_instance)
  685. {
  686. struct net_device *dev = dev_instance;
  687. struct netdev_private *np = netdev_priv(dev);
  688. void __iomem *ioaddr = np->ioaddr;
  689. unsigned int_status;
  690. int cnt = max_intrloop;
  691. int handled = 0;
  692. while (1) {
  693. int_status = dr16(IntStatus);
  694. dw16(IntStatus, int_status);
  695. int_status &= DEFAULT_INTR;
  696. if (int_status == 0 || --cnt < 0)
  697. break;
  698. handled = 1;
  699. /* Processing received packets */
  700. if (int_status & RxDMAComplete)
  701. receive_packet (dev);
  702. /* TxDMAComplete interrupt */
  703. if ((int_status & (TxDMAComplete|IntRequested))) {
  704. int tx_status;
  705. tx_status = dr32(TxStatus);
  706. if (tx_status & 0x01)
  707. tx_error (dev, tx_status);
  708. /* Free used tx skbuffs */
  709. rio_free_tx (dev, 1);
  710. }
  711. /* Handle uncommon events */
  712. if (int_status &
  713. (HostError | LinkEvent | UpdateStats))
  714. rio_error (dev, int_status);
  715. }
  716. if (np->cur_tx != np->old_tx)
  717. dw32(CountDown, 100);
  718. return IRQ_RETVAL(handled);
  719. }
  720. static void
  721. rio_free_tx (struct net_device *dev, int irq)
  722. {
  723. struct netdev_private *np = netdev_priv(dev);
  724. int entry = np->old_tx % TX_RING_SIZE;
  725. unsigned long flag = 0;
  726. if (irq)
  727. spin_lock(&np->tx_lock);
  728. else
  729. spin_lock_irqsave(&np->tx_lock, flag);
  730. /* Free used tx skbuffs */
  731. while (entry != np->cur_tx) {
  732. struct sk_buff *skb;
  733. if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
  734. break;
  735. skb = np->tx_skbuff[entry];
  736. dma_unmap_single(&np->pdev->dev,
  737. desc_to_dma(&np->tx_ring[entry]), skb->len,
  738. DMA_TO_DEVICE);
  739. if (irq)
  740. dev_consume_skb_irq(skb);
  741. else
  742. dev_kfree_skb(skb);
  743. np->tx_skbuff[entry] = NULL;
  744. entry = (entry + 1) % TX_RING_SIZE;
  745. }
  746. if (irq)
  747. spin_unlock(&np->tx_lock);
  748. else
  749. spin_unlock_irqrestore(&np->tx_lock, flag);
  750. np->old_tx = entry;
  751. /* If the ring is no longer full, clear tx_full and
  752. call netif_wake_queue() */
  753. if (netif_queue_stopped(dev) &&
  754. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  755. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  756. netif_wake_queue (dev);
  757. }
  758. }
  759. static void
  760. tx_error (struct net_device *dev, int tx_status)
  761. {
  762. struct netdev_private *np = netdev_priv(dev);
  763. void __iomem *ioaddr = np->ioaddr;
  764. int frame_id;
  765. int i;
  766. frame_id = (tx_status & 0xffff0000);
  767. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  768. dev->name, tx_status, frame_id);
  769. /* Transmit Underrun */
  770. if (tx_status & 0x10) {
  771. dev->stats.tx_fifo_errors++;
  772. dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
  773. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  774. dw16(ASICCtrl + 2,
  775. TxReset | DMAReset | FIFOReset | NetworkReset);
  776. /* Wait for ResetBusy bit clear */
  777. for (i = 50; i > 0; i--) {
  778. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  779. break;
  780. mdelay (1);
  781. }
  782. rio_set_led_mode(dev);
  783. rio_free_tx (dev, 1);
  784. /* Reset TFDListPtr */
  785. dw32(TFDListPtr0, np->tx_ring_dma +
  786. np->old_tx * sizeof (struct netdev_desc));
  787. dw32(TFDListPtr1, 0);
  788. /* Let TxStartThresh stay default value */
  789. }
  790. /* Late Collision */
  791. if (tx_status & 0x04) {
  792. dev->stats.tx_fifo_errors++;
  793. /* TxReset and clear FIFO */
  794. dw16(ASICCtrl + 2, TxReset | FIFOReset);
  795. /* Wait reset done */
  796. for (i = 50; i > 0; i--) {
  797. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  798. break;
  799. mdelay (1);
  800. }
  801. rio_set_led_mode(dev);
  802. /* Let TxStartThresh stay default value */
  803. }
  804. spin_lock(&np->stats_lock);
  805. /* Maximum Collisions */
  806. if (tx_status & 0x08)
  807. dev->stats.collisions++;
  808. dev->stats.tx_errors++;
  809. spin_unlock(&np->stats_lock);
  810. /* Restart the Tx */
  811. dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
  812. }
  813. static int
  814. receive_packet (struct net_device *dev)
  815. {
  816. struct netdev_private *np = netdev_priv(dev);
  817. int entry = np->cur_rx % RX_RING_SIZE;
  818. int cnt = 30;
  819. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  820. while (1) {
  821. struct netdev_desc *desc = &np->rx_ring[entry];
  822. int pkt_len;
  823. u64 frame_status;
  824. if (!(desc->status & cpu_to_le64(RFDDone)) ||
  825. !(desc->status & cpu_to_le64(FrameStart)) ||
  826. !(desc->status & cpu_to_le64(FrameEnd)))
  827. break;
  828. /* Chip omits the CRC. */
  829. frame_status = le64_to_cpu(desc->status);
  830. pkt_len = frame_status & 0xffff;
  831. if (--cnt < 0)
  832. break;
  833. /* Update rx error statistics, drop packet. */
  834. if (frame_status & RFS_Errors) {
  835. dev->stats.rx_errors++;
  836. if (frame_status & (RxRuntFrame | RxLengthError))
  837. dev->stats.rx_length_errors++;
  838. if (frame_status & RxFCSError)
  839. dev->stats.rx_crc_errors++;
  840. if (frame_status & RxAlignmentError && np->speed != 1000)
  841. dev->stats.rx_frame_errors++;
  842. if (frame_status & RxFIFOOverrun)
  843. dev->stats.rx_fifo_errors++;
  844. } else {
  845. struct sk_buff *skb;
  846. skb = NULL;
  847. /* Small skbuffs for short packets */
  848. if (pkt_len <= copy_thresh)
  849. skb = netdev_alloc_skb_ip_align(dev, pkt_len);
  850. if (!skb) {
  851. dma_unmap_single(&np->pdev->dev,
  852. desc_to_dma(desc),
  853. np->rx_buf_sz,
  854. DMA_FROM_DEVICE);
  855. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  856. np->rx_skbuff[entry] = NULL;
  857. } else {
  858. dma_sync_single_for_cpu(&np->pdev->dev,
  859. desc_to_dma(desc),
  860. np->rx_buf_sz,
  861. DMA_FROM_DEVICE);
  862. skb_copy_to_linear_data (skb,
  863. np->rx_skbuff[entry]->data,
  864. pkt_len);
  865. skb_put (skb, pkt_len);
  866. dma_sync_single_for_device(&np->pdev->dev,
  867. desc_to_dma(desc),
  868. np->rx_buf_sz,
  869. DMA_FROM_DEVICE);
  870. }
  871. skb->protocol = eth_type_trans (skb, dev);
  872. #if 0
  873. /* Checksum done by hw, but csum value unavailable. */
  874. if (np->pdev->pci_rev_id >= 0x0c &&
  875. !(frame_status & (TCPError | UDPError | IPError))) {
  876. skb->ip_summed = CHECKSUM_UNNECESSARY;
  877. }
  878. #endif
  879. netif_rx (skb);
  880. }
  881. entry = (entry + 1) % RX_RING_SIZE;
  882. }
  883. spin_lock(&np->rx_lock);
  884. np->cur_rx = entry;
  885. /* Re-allocate skbuffs to fill the descriptor ring */
  886. entry = np->old_rx;
  887. while (entry != np->cur_rx) {
  888. struct sk_buff *skb;
  889. /* Dropped packets don't need to re-allocate */
  890. if (np->rx_skbuff[entry] == NULL) {
  891. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  892. if (skb == NULL) {
  893. np->rx_ring[entry].fraginfo = 0;
  894. printk (KERN_INFO
  895. "%s: receive_packet: "
  896. "Unable to re-allocate Rx skbuff.#%d\n",
  897. dev->name, entry);
  898. break;
  899. }
  900. np->rx_skbuff[entry] = skb;
  901. np->rx_ring[entry].fraginfo =
  902. cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
  903. np->rx_buf_sz, DMA_FROM_DEVICE));
  904. }
  905. np->rx_ring[entry].fraginfo |=
  906. cpu_to_le64((u64)np->rx_buf_sz << 48);
  907. np->rx_ring[entry].status = 0;
  908. entry = (entry + 1) % RX_RING_SIZE;
  909. }
  910. np->old_rx = entry;
  911. spin_unlock(&np->rx_lock);
  912. return 0;
  913. }
  914. static void
  915. rio_error (struct net_device *dev, int int_status)
  916. {
  917. struct netdev_private *np = netdev_priv(dev);
  918. void __iomem *ioaddr = np->ioaddr;
  919. u16 macctrl;
  920. /* Link change event */
  921. if (int_status & LinkEvent) {
  922. if (mii_wait_link (dev, 10) == 0) {
  923. printk (KERN_INFO "%s: Link up\n", dev->name);
  924. if (np->phy_media)
  925. mii_get_media_pcs (dev);
  926. else
  927. mii_get_media (dev);
  928. if (np->speed == 1000)
  929. np->tx_coalesce = tx_coalesce;
  930. else
  931. np->tx_coalesce = 1;
  932. macctrl = 0;
  933. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  934. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  935. macctrl |= (np->tx_flow) ?
  936. TxFlowControlEnable : 0;
  937. macctrl |= (np->rx_flow) ?
  938. RxFlowControlEnable : 0;
  939. dw16(MACCtrl, macctrl);
  940. np->link_status = 1;
  941. netif_carrier_on(dev);
  942. } else {
  943. printk (KERN_INFO "%s: Link off\n", dev->name);
  944. np->link_status = 0;
  945. netif_carrier_off(dev);
  946. }
  947. }
  948. /* UpdateStats statistics registers */
  949. if (int_status & UpdateStats) {
  950. get_stats (dev);
  951. }
  952. /* PCI Error, a catastrophic error related to the bus interface
  953. occurs, set GlobalReset and HostReset to reset. */
  954. if (int_status & HostError) {
  955. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  956. dev->name, int_status);
  957. dw16(ASICCtrl + 2, GlobalReset | HostReset);
  958. mdelay (500);
  959. rio_set_led_mode(dev);
  960. }
  961. }
  962. static struct net_device_stats *
  963. get_stats (struct net_device *dev)
  964. {
  965. struct netdev_private *np = netdev_priv(dev);
  966. void __iomem *ioaddr = np->ioaddr;
  967. unsigned int stat_reg;
  968. unsigned long flags;
  969. spin_lock_irqsave(&np->stats_lock, flags);
  970. /* All statistics registers need to be acknowledged,
  971. else statistic overflow could cause problems */
  972. dev->stats.rx_packets += dr32(FramesRcvOk);
  973. dev->stats.tx_packets += dr32(FramesXmtOk);
  974. dev->stats.rx_bytes += dr32(OctetRcvOk);
  975. dev->stats.tx_bytes += dr32(OctetXmtOk);
  976. dev->stats.multicast += dr32(McstFramesRcvdOk);
  977. dev->stats.collisions += dr32(SingleColFrames)
  978. + dr32(MultiColFrames);
  979. /* detailed tx errors */
  980. stat_reg = dr16(FramesAbortXSColls);
  981. dev->stats.tx_aborted_errors += stat_reg;
  982. dev->stats.tx_errors += stat_reg;
  983. stat_reg = dr16(CarrierSenseErrors);
  984. dev->stats.tx_carrier_errors += stat_reg;
  985. dev->stats.tx_errors += stat_reg;
  986. /* Clear all other statistic register. */
  987. dr32(McstOctetXmtOk);
  988. dr16(BcstFramesXmtdOk);
  989. dr32(McstFramesXmtdOk);
  990. dr16(BcstFramesRcvdOk);
  991. dr16(MacControlFramesRcvd);
  992. dr16(FrameTooLongErrors);
  993. dr16(InRangeLengthErrors);
  994. dr16(FramesCheckSeqErrors);
  995. dr16(FramesLostRxErrors);
  996. dr32(McstOctetXmtOk);
  997. dr32(BcstOctetXmtOk);
  998. dr32(McstFramesXmtdOk);
  999. dr32(FramesWDeferredXmt);
  1000. dr32(LateCollisions);
  1001. dr16(BcstFramesXmtdOk);
  1002. dr16(MacControlFramesXmtd);
  1003. dr16(FramesWEXDeferal);
  1004. if (np->rmon_enable)
  1005. for (int i = 0x100; i <= 0x150; i += 4)
  1006. dr32(i);
  1007. dr16(TxJumboFrames);
  1008. dr16(RxJumboFrames);
  1009. dr16(TCPCheckSumErrors);
  1010. dr16(UDPCheckSumErrors);
  1011. dr16(IPCheckSumErrors);
  1012. spin_unlock_irqrestore(&np->stats_lock, flags);
  1013. return &dev->stats;
  1014. }
  1015. static int
  1016. clear_stats (struct net_device *dev)
  1017. {
  1018. struct netdev_private *np = netdev_priv(dev);
  1019. void __iomem *ioaddr = np->ioaddr;
  1020. /* All statistics registers need to be acknowledged,
  1021. else statistic overflow could cause problems */
  1022. dr32(FramesRcvOk);
  1023. dr32(FramesXmtOk);
  1024. dr32(OctetRcvOk);
  1025. dr32(OctetXmtOk);
  1026. dr32(McstFramesRcvdOk);
  1027. dr32(SingleColFrames);
  1028. dr32(MultiColFrames);
  1029. dr32(LateCollisions);
  1030. /* detailed rx errors */
  1031. dr16(FrameTooLongErrors);
  1032. dr16(InRangeLengthErrors);
  1033. dr16(FramesCheckSeqErrors);
  1034. dr16(FramesLostRxErrors);
  1035. /* detailed tx errors */
  1036. dr16(FramesAbortXSColls);
  1037. dr16(CarrierSenseErrors);
  1038. /* Clear all other statistic register. */
  1039. dr32(McstOctetXmtOk);
  1040. dr16(BcstFramesXmtdOk);
  1041. dr32(McstFramesXmtdOk);
  1042. dr16(BcstFramesRcvdOk);
  1043. dr16(MacControlFramesRcvd);
  1044. dr32(McstOctetXmtOk);
  1045. dr32(BcstOctetXmtOk);
  1046. dr32(McstFramesXmtdOk);
  1047. dr32(FramesWDeferredXmt);
  1048. dr16(BcstFramesXmtdOk);
  1049. dr16(MacControlFramesXmtd);
  1050. dr16(FramesWEXDeferal);
  1051. if (np->rmon_enable)
  1052. for (int i = 0x100; i <= 0x150; i += 4)
  1053. dr32(i);
  1054. dr16(TxJumboFrames);
  1055. dr16(RxJumboFrames);
  1056. dr16(TCPCheckSumErrors);
  1057. dr16(UDPCheckSumErrors);
  1058. dr16(IPCheckSumErrors);
  1059. return 0;
  1060. }
  1061. static void
  1062. set_multicast (struct net_device *dev)
  1063. {
  1064. struct netdev_private *np = netdev_priv(dev);
  1065. void __iomem *ioaddr = np->ioaddr;
  1066. u32 hash_table[2];
  1067. u16 rx_mode = 0;
  1068. hash_table[0] = hash_table[1] = 0;
  1069. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  1070. hash_table[1] |= 0x02000000;
  1071. if (dev->flags & IFF_PROMISC) {
  1072. /* Receive all frames promiscuously. */
  1073. rx_mode = ReceiveAllFrames;
  1074. } else if ((dev->flags & IFF_ALLMULTI) ||
  1075. (netdev_mc_count(dev) > multicast_filter_limit)) {
  1076. /* Receive broadcast and multicast frames */
  1077. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1078. } else if (!netdev_mc_empty(dev)) {
  1079. struct netdev_hw_addr *ha;
  1080. /* Receive broadcast frames and multicast frames filtering
  1081. by Hashtable */
  1082. rx_mode =
  1083. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1084. netdev_for_each_mc_addr(ha, dev) {
  1085. int bit, index = 0;
  1086. int crc = ether_crc_le(ETH_ALEN, ha->addr);
  1087. /* The inverted high significant 6 bits of CRC are
  1088. used as an index to hashtable */
  1089. for (bit = 0; bit < 6; bit++)
  1090. if (crc & (1 << (31 - bit)))
  1091. index |= (1 << bit);
  1092. hash_table[index / 32] |= (1 << (index % 32));
  1093. }
  1094. } else {
  1095. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1096. }
  1097. if (np->vlan) {
  1098. /* ReceiveVLANMatch field in ReceiveMode */
  1099. rx_mode |= ReceiveVLANMatch;
  1100. }
  1101. dw32(HashTable0, hash_table[0]);
  1102. dw32(HashTable1, hash_table[1]);
  1103. dw16(ReceiveMode, rx_mode);
  1104. }
  1105. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1106. {
  1107. struct netdev_private *np = netdev_priv(dev);
  1108. strscpy(info->driver, "dl2k", sizeof(info->driver));
  1109. strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
  1110. }
  1111. static int rio_get_link_ksettings(struct net_device *dev,
  1112. struct ethtool_link_ksettings *cmd)
  1113. {
  1114. struct netdev_private *np = netdev_priv(dev);
  1115. u32 supported, advertising;
  1116. if (np->phy_media) {
  1117. /* fiber device */
  1118. supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1119. advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1120. cmd->base.port = PORT_FIBRE;
  1121. } else {
  1122. /* copper device */
  1123. supported = SUPPORTED_10baseT_Half |
  1124. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1125. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1126. SUPPORTED_Autoneg | SUPPORTED_MII;
  1127. advertising = ADVERTISED_10baseT_Half |
  1128. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1129. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full |
  1130. ADVERTISED_Autoneg | ADVERTISED_MII;
  1131. cmd->base.port = PORT_MII;
  1132. }
  1133. if (np->link_status) {
  1134. cmd->base.speed = np->speed;
  1135. cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1136. } else {
  1137. cmd->base.speed = SPEED_UNKNOWN;
  1138. cmd->base.duplex = DUPLEX_UNKNOWN;
  1139. }
  1140. if (np->an_enable)
  1141. cmd->base.autoneg = AUTONEG_ENABLE;
  1142. else
  1143. cmd->base.autoneg = AUTONEG_DISABLE;
  1144. cmd->base.phy_address = np->phy_addr;
  1145. ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
  1146. supported);
  1147. ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
  1148. advertising);
  1149. return 0;
  1150. }
  1151. static int rio_set_link_ksettings(struct net_device *dev,
  1152. const struct ethtool_link_ksettings *cmd)
  1153. {
  1154. struct netdev_private *np = netdev_priv(dev);
  1155. u32 speed = cmd->base.speed;
  1156. u8 duplex = cmd->base.duplex;
  1157. netif_carrier_off(dev);
  1158. if (cmd->base.autoneg == AUTONEG_ENABLE) {
  1159. if (np->an_enable) {
  1160. return 0;
  1161. } else {
  1162. np->an_enable = 1;
  1163. mii_set_media(dev);
  1164. return 0;
  1165. }
  1166. } else {
  1167. np->an_enable = 0;
  1168. if (np->speed == 1000) {
  1169. speed = SPEED_100;
  1170. duplex = DUPLEX_FULL;
  1171. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1172. }
  1173. switch (speed) {
  1174. case SPEED_10:
  1175. np->speed = 10;
  1176. np->full_duplex = (duplex == DUPLEX_FULL);
  1177. break;
  1178. case SPEED_100:
  1179. np->speed = 100;
  1180. np->full_duplex = (duplex == DUPLEX_FULL);
  1181. break;
  1182. case SPEED_1000: /* not supported */
  1183. default:
  1184. return -EINVAL;
  1185. }
  1186. mii_set_media(dev);
  1187. }
  1188. return 0;
  1189. }
  1190. static u32 rio_get_link(struct net_device *dev)
  1191. {
  1192. struct netdev_private *np = netdev_priv(dev);
  1193. return np->link_status;
  1194. }
  1195. static const struct ethtool_ops ethtool_ops = {
  1196. .get_drvinfo = rio_get_drvinfo,
  1197. .get_link = rio_get_link,
  1198. .get_link_ksettings = rio_get_link_ksettings,
  1199. .set_link_ksettings = rio_set_link_ksettings,
  1200. };
  1201. static int
  1202. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1203. {
  1204. int phy_addr;
  1205. struct netdev_private *np = netdev_priv(dev);
  1206. struct mii_ioctl_data *miidata = if_mii(rq);
  1207. phy_addr = np->phy_addr;
  1208. switch (cmd) {
  1209. case SIOCGMIIPHY:
  1210. miidata->phy_id = phy_addr;
  1211. break;
  1212. case SIOCGMIIREG:
  1213. miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
  1214. break;
  1215. case SIOCSMIIREG:
  1216. if (!capable(CAP_NET_ADMIN))
  1217. return -EPERM;
  1218. mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
  1219. break;
  1220. default:
  1221. return -EOPNOTSUPP;
  1222. }
  1223. return 0;
  1224. }
  1225. #define EEP_READ 0x0200
  1226. #define EEP_BUSY 0x8000
  1227. /* Read the EEPROM word */
  1228. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1229. static int read_eeprom(struct netdev_private *np, int eep_addr)
  1230. {
  1231. void __iomem *ioaddr = np->eeprom_addr;
  1232. int i = 1000;
  1233. dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
  1234. while (i-- > 0) {
  1235. if (!(dr16(EepromCtrl) & EEP_BUSY))
  1236. return dr16(EepromData);
  1237. }
  1238. return 0;
  1239. }
  1240. enum phy_ctrl_bits {
  1241. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1242. MII_DUPLEX = 0x08,
  1243. };
  1244. #define mii_delay() dr8(PhyCtrl)
  1245. static void
  1246. mii_sendbit (struct net_device *dev, u32 data)
  1247. {
  1248. struct netdev_private *np = netdev_priv(dev);
  1249. void __iomem *ioaddr = np->ioaddr;
  1250. data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
  1251. dw8(PhyCtrl, data);
  1252. mii_delay ();
  1253. dw8(PhyCtrl, data | MII_CLK);
  1254. mii_delay ();
  1255. }
  1256. static int
  1257. mii_getbit (struct net_device *dev)
  1258. {
  1259. struct netdev_private *np = netdev_priv(dev);
  1260. void __iomem *ioaddr = np->ioaddr;
  1261. u8 data;
  1262. data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
  1263. dw8(PhyCtrl, data);
  1264. mii_delay ();
  1265. dw8(PhyCtrl, data | MII_CLK);
  1266. mii_delay ();
  1267. return (dr8(PhyCtrl) >> 1) & 1;
  1268. }
  1269. static void
  1270. mii_send_bits (struct net_device *dev, u32 data, int len)
  1271. {
  1272. int i;
  1273. for (i = len - 1; i >= 0; i--) {
  1274. mii_sendbit (dev, data & (1 << i));
  1275. }
  1276. }
  1277. static int
  1278. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1279. {
  1280. u32 cmd;
  1281. int i;
  1282. u32 retval = 0;
  1283. /* Preamble */
  1284. mii_send_bits (dev, 0xffffffff, 32);
  1285. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1286. /* ST,OP = 0110'b for read operation */
  1287. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1288. mii_send_bits (dev, cmd, 14);
  1289. /* Turnaround */
  1290. if (mii_getbit (dev))
  1291. goto err_out;
  1292. /* Read data */
  1293. for (i = 0; i < 16; i++) {
  1294. retval |= mii_getbit (dev);
  1295. retval <<= 1;
  1296. }
  1297. /* End cycle */
  1298. mii_getbit (dev);
  1299. return (retval >> 1) & 0xffff;
  1300. err_out:
  1301. return 0;
  1302. }
  1303. static int
  1304. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1305. {
  1306. u32 cmd;
  1307. /* Preamble */
  1308. mii_send_bits (dev, 0xffffffff, 32);
  1309. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1310. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1311. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1312. mii_send_bits (dev, cmd, 32);
  1313. /* End cycle */
  1314. mii_getbit (dev);
  1315. return 0;
  1316. }
  1317. static int
  1318. mii_wait_link (struct net_device *dev, int wait)
  1319. {
  1320. __u16 bmsr;
  1321. int phy_addr;
  1322. struct netdev_private *np;
  1323. np = netdev_priv(dev);
  1324. phy_addr = np->phy_addr;
  1325. do {
  1326. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1327. if (bmsr & BMSR_LSTATUS)
  1328. return 0;
  1329. mdelay (1);
  1330. } while (--wait > 0);
  1331. return -1;
  1332. }
  1333. static int
  1334. mii_get_media (struct net_device *dev)
  1335. {
  1336. __u16 negotiate;
  1337. __u16 bmsr;
  1338. __u16 mscr;
  1339. __u16 mssr;
  1340. int phy_addr;
  1341. struct netdev_private *np;
  1342. np = netdev_priv(dev);
  1343. phy_addr = np->phy_addr;
  1344. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1345. if (np->an_enable) {
  1346. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1347. /* Auto-Negotiation not completed */
  1348. return -1;
  1349. }
  1350. negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1351. mii_read (dev, phy_addr, MII_LPA);
  1352. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1353. mssr = mii_read (dev, phy_addr, MII_STAT1000);
  1354. if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
  1355. np->speed = 1000;
  1356. np->full_duplex = 1;
  1357. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1358. } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
  1359. np->speed = 1000;
  1360. np->full_duplex = 0;
  1361. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1362. } else if (negotiate & ADVERTISE_100FULL) {
  1363. np->speed = 100;
  1364. np->full_duplex = 1;
  1365. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1366. } else if (negotiate & ADVERTISE_100HALF) {
  1367. np->speed = 100;
  1368. np->full_duplex = 0;
  1369. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1370. } else if (negotiate & ADVERTISE_10FULL) {
  1371. np->speed = 10;
  1372. np->full_duplex = 1;
  1373. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1374. } else if (negotiate & ADVERTISE_10HALF) {
  1375. np->speed = 10;
  1376. np->full_duplex = 0;
  1377. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1378. }
  1379. if (negotiate & ADVERTISE_PAUSE_CAP) {
  1380. np->tx_flow &= 1;
  1381. np->rx_flow &= 1;
  1382. } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
  1383. np->tx_flow = 0;
  1384. np->rx_flow &= 1;
  1385. }
  1386. /* else tx_flow, rx_flow = user select */
  1387. } else {
  1388. __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1389. switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
  1390. case BMCR_SPEED1000:
  1391. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1392. break;
  1393. case BMCR_SPEED100:
  1394. printk (KERN_INFO "Operating at 100 Mbps, ");
  1395. break;
  1396. case 0:
  1397. printk (KERN_INFO "Operating at 10 Mbps, ");
  1398. }
  1399. if (bmcr & BMCR_FULLDPLX) {
  1400. printk (KERN_CONT "Full duplex\n");
  1401. } else {
  1402. printk (KERN_CONT "Half duplex\n");
  1403. }
  1404. }
  1405. if (np->tx_flow)
  1406. printk(KERN_INFO "Enable Tx Flow Control\n");
  1407. else
  1408. printk(KERN_INFO "Disable Tx Flow Control\n");
  1409. if (np->rx_flow)
  1410. printk(KERN_INFO "Enable Rx Flow Control\n");
  1411. else
  1412. printk(KERN_INFO "Disable Rx Flow Control\n");
  1413. return 0;
  1414. }
  1415. static int
  1416. mii_set_media (struct net_device *dev)
  1417. {
  1418. __u16 pscr;
  1419. __u16 bmcr;
  1420. __u16 bmsr;
  1421. __u16 anar;
  1422. int phy_addr;
  1423. struct netdev_private *np;
  1424. np = netdev_priv(dev);
  1425. phy_addr = np->phy_addr;
  1426. /* Does user set speed? */
  1427. if (np->an_enable) {
  1428. /* Advertise capabilities */
  1429. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1430. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1431. ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
  1432. ADVERTISE_100HALF | ADVERTISE_10HALF |
  1433. ADVERTISE_100BASE4);
  1434. if (bmsr & BMSR_100FULL)
  1435. anar |= ADVERTISE_100FULL;
  1436. if (bmsr & BMSR_100HALF)
  1437. anar |= ADVERTISE_100HALF;
  1438. if (bmsr & BMSR_100BASE4)
  1439. anar |= ADVERTISE_100BASE4;
  1440. if (bmsr & BMSR_10FULL)
  1441. anar |= ADVERTISE_10FULL;
  1442. if (bmsr & BMSR_10HALF)
  1443. anar |= ADVERTISE_10HALF;
  1444. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1445. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1446. /* Enable Auto crossover */
  1447. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1448. pscr |= 3 << 5; /* 11'b */
  1449. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1450. /* Soft reset PHY */
  1451. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1452. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1453. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1454. mdelay(1);
  1455. } else {
  1456. /* Force speed setting */
  1457. /* 1) Disable Auto crossover */
  1458. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1459. pscr &= ~(3 << 5);
  1460. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1461. /* 2) PHY Reset */
  1462. bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1463. bmcr |= BMCR_RESET;
  1464. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1465. /* 3) Power Down */
  1466. bmcr = 0x1940; /* must be 0x1940 */
  1467. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1468. mdelay (100); /* wait a certain time */
  1469. /* 4) Advertise nothing */
  1470. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1471. /* 5) Set media and Power Up */
  1472. bmcr = BMCR_PDOWN;
  1473. if (np->speed == 100) {
  1474. bmcr |= BMCR_SPEED100;
  1475. printk (KERN_INFO "Manual 100 Mbps, ");
  1476. } else if (np->speed == 10) {
  1477. printk (KERN_INFO "Manual 10 Mbps, ");
  1478. }
  1479. if (np->full_duplex) {
  1480. bmcr |= BMCR_FULLDPLX;
  1481. printk (KERN_CONT "Full duplex\n");
  1482. } else {
  1483. printk (KERN_CONT "Half duplex\n");
  1484. }
  1485. #if 0
  1486. /* Set 1000BaseT Master/Slave setting */
  1487. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1488. mscr |= MII_MSCR_CFG_ENABLE;
  1489. mscr &= ~MII_MSCR_CFG_VALUE = 0;
  1490. #endif
  1491. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1492. mdelay(10);
  1493. }
  1494. return 0;
  1495. }
  1496. static int
  1497. mii_get_media_pcs (struct net_device *dev)
  1498. {
  1499. __u16 negotiate;
  1500. __u16 bmsr;
  1501. int phy_addr;
  1502. struct netdev_private *np;
  1503. np = netdev_priv(dev);
  1504. phy_addr = np->phy_addr;
  1505. bmsr = mii_read (dev, phy_addr, PCS_BMSR);
  1506. if (np->an_enable) {
  1507. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1508. /* Auto-Negotiation not completed */
  1509. return -1;
  1510. }
  1511. negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
  1512. mii_read (dev, phy_addr, PCS_ANLPAR);
  1513. np->speed = 1000;
  1514. if (negotiate & PCS_ANAR_FULL_DUPLEX) {
  1515. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1516. np->full_duplex = 1;
  1517. } else {
  1518. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1519. np->full_duplex = 0;
  1520. }
  1521. if (negotiate & PCS_ANAR_PAUSE) {
  1522. np->tx_flow &= 1;
  1523. np->rx_flow &= 1;
  1524. } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
  1525. np->tx_flow = 0;
  1526. np->rx_flow &= 1;
  1527. }
  1528. /* else tx_flow, rx_flow = user select */
  1529. } else {
  1530. __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
  1531. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1532. if (bmcr & BMCR_FULLDPLX) {
  1533. printk (KERN_CONT "Full duplex\n");
  1534. } else {
  1535. printk (KERN_CONT "Half duplex\n");
  1536. }
  1537. }
  1538. if (np->tx_flow)
  1539. printk(KERN_INFO "Enable Tx Flow Control\n");
  1540. else
  1541. printk(KERN_INFO "Disable Tx Flow Control\n");
  1542. if (np->rx_flow)
  1543. printk(KERN_INFO "Enable Rx Flow Control\n");
  1544. else
  1545. printk(KERN_INFO "Disable Rx Flow Control\n");
  1546. return 0;
  1547. }
  1548. static int
  1549. mii_set_media_pcs (struct net_device *dev)
  1550. {
  1551. __u16 bmcr;
  1552. __u16 esr;
  1553. __u16 anar;
  1554. int phy_addr;
  1555. struct netdev_private *np;
  1556. np = netdev_priv(dev);
  1557. phy_addr = np->phy_addr;
  1558. /* Auto-Negotiation? */
  1559. if (np->an_enable) {
  1560. /* Advertise capabilities */
  1561. esr = mii_read (dev, phy_addr, PCS_ESR);
  1562. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1563. ~PCS_ANAR_HALF_DUPLEX &
  1564. ~PCS_ANAR_FULL_DUPLEX;
  1565. if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
  1566. anar |= PCS_ANAR_HALF_DUPLEX;
  1567. if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
  1568. anar |= PCS_ANAR_FULL_DUPLEX;
  1569. anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
  1570. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1571. /* Soft reset PHY */
  1572. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1573. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1574. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1575. mdelay(1);
  1576. } else {
  1577. /* Force speed setting */
  1578. /* PHY Reset */
  1579. bmcr = BMCR_RESET;
  1580. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1581. mdelay(10);
  1582. if (np->full_duplex) {
  1583. bmcr = BMCR_FULLDPLX;
  1584. printk (KERN_INFO "Manual full duplex\n");
  1585. } else {
  1586. bmcr = 0;
  1587. printk (KERN_INFO "Manual half duplex\n");
  1588. }
  1589. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1590. mdelay(10);
  1591. /* Advertise nothing */
  1592. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1593. }
  1594. return 0;
  1595. }
  1596. static int
  1597. rio_close (struct net_device *dev)
  1598. {
  1599. struct netdev_private *np = netdev_priv(dev);
  1600. struct pci_dev *pdev = np->pdev;
  1601. netif_stop_queue (dev);
  1602. rio_hw_stop(dev);
  1603. free_irq(pdev->irq, dev);
  1604. timer_delete_sync(&np->timer);
  1605. free_list(dev);
  1606. return 0;
  1607. }
  1608. static void
  1609. rio_remove1 (struct pci_dev *pdev)
  1610. {
  1611. struct net_device *dev = pci_get_drvdata (pdev);
  1612. if (dev) {
  1613. struct netdev_private *np = netdev_priv(dev);
  1614. unregister_netdev (dev);
  1615. dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
  1616. np->rx_ring_dma);
  1617. dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
  1618. np->tx_ring_dma);
  1619. if (np->rmon_enable)
  1620. pci_iounmap(pdev, np->ioaddr);
  1621. pci_iounmap(pdev, np->eeprom_addr);
  1622. free_netdev (dev);
  1623. pci_release_regions (pdev);
  1624. pci_disable_device (pdev);
  1625. }
  1626. }
  1627. #ifdef CONFIG_PM_SLEEP
  1628. static int rio_suspend(struct device *device)
  1629. {
  1630. struct net_device *dev = dev_get_drvdata(device);
  1631. struct netdev_private *np = netdev_priv(dev);
  1632. if (!netif_running(dev))
  1633. return 0;
  1634. netif_device_detach(dev);
  1635. timer_delete_sync(&np->timer);
  1636. rio_hw_stop(dev);
  1637. return 0;
  1638. }
  1639. static int rio_resume(struct device *device)
  1640. {
  1641. struct net_device *dev = dev_get_drvdata(device);
  1642. struct netdev_private *np = netdev_priv(dev);
  1643. if (!netif_running(dev))
  1644. return 0;
  1645. rio_reset_ring(np);
  1646. rio_hw_init(dev);
  1647. np->timer.expires = jiffies + 1 * HZ;
  1648. add_timer(&np->timer);
  1649. netif_device_attach(dev);
  1650. dl2k_enable_int(np);
  1651. return 0;
  1652. }
  1653. static DEFINE_SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
  1654. #define RIO_PM_OPS (&rio_pm_ops)
  1655. #else
  1656. #define RIO_PM_OPS NULL
  1657. #endif /* CONFIG_PM_SLEEP */
  1658. static struct pci_driver rio_driver = {
  1659. .name = "dl2k",
  1660. .id_table = rio_pci_tbl,
  1661. .probe = rio_probe1,
  1662. .remove = rio_remove1,
  1663. .driver.pm = RIO_PM_OPS,
  1664. };
  1665. module_pci_driver(rio_driver);
  1666. /* Read Documentation/networking/device_drivers/ethernet/dlink/dl2k.rst. */