lio_main.c 116 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349
  1. /**********************************************************************
  2. * Author: Cavium, Inc.
  3. *
  4. * Contact: support@cavium.com
  5. * Please include "LiquidIO" in the subject.
  6. *
  7. * Copyright (c) 2003-2016 Cavium, Inc.
  8. *
  9. * This file is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License, Version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful, but
  14. * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16. * NONINFRINGEMENT. See the GNU General Public License for more details.
  17. ***********************************************************************/
  18. #include <linux/module.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/pci.h>
  21. #include <linux/firmware.h>
  22. #include <net/vxlan.h>
  23. #include <linux/kthread.h>
  24. #include "liquidio_common.h"
  25. #include "octeon_droq.h"
  26. #include "octeon_iq.h"
  27. #include "response_manager.h"
  28. #include "octeon_device.h"
  29. #include "octeon_nic.h"
  30. #include "octeon_main.h"
  31. #include "octeon_network.h"
  32. #include "cn66xx_regs.h"
  33. #include "cn66xx_device.h"
  34. #include "cn68xx_device.h"
  35. #include "cn23xx_pf_device.h"
  36. #include "liquidio_image.h"
  37. #include "lio_vf_rep.h"
  38. MODULE_AUTHOR("Cavium Networks, <support@cavium.com>");
  39. MODULE_DESCRIPTION("Cavium LiquidIO Intelligent Server Adapter Driver");
  40. MODULE_LICENSE("GPL");
  41. MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210SV_NAME
  42. "_" LIO_FW_NAME_TYPE_NIC LIO_FW_NAME_SUFFIX);
  43. MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_210NV_NAME
  44. "_" LIO_FW_NAME_TYPE_NIC LIO_FW_NAME_SUFFIX);
  45. MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_410NV_NAME
  46. "_" LIO_FW_NAME_TYPE_NIC LIO_FW_NAME_SUFFIX);
  47. MODULE_FIRMWARE(LIO_FW_DIR LIO_FW_BASE_NAME LIO_23XX_NAME
  48. "_" LIO_FW_NAME_TYPE_NIC LIO_FW_NAME_SUFFIX);
  49. static int ddr_timeout = 10000;
  50. module_param(ddr_timeout, int, 0644);
  51. MODULE_PARM_DESC(ddr_timeout,
  52. "Number of milliseconds to wait for DDR initialization. 0 waits for ddr_timeout to be set to non-zero value before starting to check");
  53. #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  54. static int debug = -1;
  55. module_param(debug, int, 0644);
  56. MODULE_PARM_DESC(debug, "NETIF_MSG debug bits");
  57. static char fw_type[LIO_MAX_FW_TYPE_LEN] = LIO_FW_NAME_TYPE_AUTO;
  58. module_param_string(fw_type, fw_type, sizeof(fw_type), 0444);
  59. MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded (default is \"auto\"), which uses firmware in flash, if present, else loads \"nic\".");
  60. static u32 console_bitmask;
  61. module_param(console_bitmask, int, 0644);
  62. MODULE_PARM_DESC(console_bitmask,
  63. "Bitmask indicating which consoles have debug output redirected to syslog.");
  64. /**
  65. * octeon_console_debug_enabled - determines if a given console has debug enabled.
  66. * @console: console to check
  67. * Return: 1 = enabled. 0 otherwise
  68. */
  69. static int octeon_console_debug_enabled(u32 console)
  70. {
  71. return (console_bitmask >> (console)) & 0x1;
  72. }
  73. /* Polling interval for determining when NIC application is alive */
  74. #define LIQUIDIO_STARTER_POLL_INTERVAL_MS 100
  75. /* runtime link query interval */
  76. #define LIQUIDIO_LINK_QUERY_INTERVAL_MS 1000
  77. /* update localtime to octeon firmware every 60 seconds.
  78. * make firmware to use same time reference, so that it will be easy to
  79. * correlate firmware logged events/errors with host events, for debugging.
  80. */
  81. #define LIO_SYNC_OCTEON_TIME_INTERVAL_MS 60000
  82. /* time to wait for possible in-flight requests in milliseconds */
  83. #define WAIT_INFLIGHT_REQUEST msecs_to_jiffies(1000)
  84. struct oct_timestamp_resp {
  85. u64 rh;
  86. u64 timestamp;
  87. u64 status;
  88. };
  89. #define OCT_TIMESTAMP_RESP_SIZE (sizeof(struct oct_timestamp_resp))
  90. union tx_info {
  91. u64 u64;
  92. struct {
  93. #ifdef __BIG_ENDIAN_BITFIELD
  94. u16 gso_size;
  95. u16 gso_segs;
  96. u32 reserved;
  97. #else
  98. u32 reserved;
  99. u16 gso_segs;
  100. u16 gso_size;
  101. #endif
  102. } s;
  103. };
  104. /* Octeon device properties to be used by the NIC module.
  105. * Each octeon device in the system will be represented
  106. * by this structure in the NIC module.
  107. */
  108. #define OCTNIC_GSO_MAX_HEADER_SIZE 128
  109. #define OCTNIC_GSO_MAX_SIZE \
  110. (CN23XX_DEFAULT_INPUT_JABBER - OCTNIC_GSO_MAX_HEADER_SIZE)
  111. struct handshake {
  112. struct completion init;
  113. struct completion started;
  114. struct pci_dev *pci_dev;
  115. int init_ok;
  116. int started_ok;
  117. };
  118. #ifdef CONFIG_PCI_IOV
  119. static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs);
  120. #endif
  121. static int octeon_dbg_console_print(struct octeon_device *oct, u32 console_num,
  122. char *prefix, char *suffix);
  123. static int octeon_device_init(struct octeon_device *);
  124. static int liquidio_stop(struct net_device *netdev);
  125. static void liquidio_remove(struct pci_dev *pdev);
  126. static int liquidio_probe(struct pci_dev *pdev,
  127. const struct pci_device_id *ent);
  128. static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx,
  129. int linkstate);
  130. static struct handshake handshake[MAX_OCTEON_DEVICES];
  131. static struct completion first_stage;
  132. static void octeon_droq_bh(struct tasklet_struct *t)
  133. {
  134. int q_no;
  135. int reschedule = 0;
  136. struct octeon_device_priv *oct_priv = from_tasklet(oct_priv, t,
  137. droq_tasklet);
  138. struct octeon_device *oct = oct_priv->dev;
  139. for (q_no = 0; q_no < MAX_OCTEON_OUTPUT_QUEUES(oct); q_no++) {
  140. if (!(oct->io_qmask.oq & BIT_ULL(q_no)))
  141. continue;
  142. reschedule |= octeon_droq_process_packets(oct, oct->droq[q_no],
  143. MAX_PACKET_BUDGET);
  144. lio_enable_irq(oct->droq[q_no], NULL);
  145. if (OCTEON_CN23XX_PF(oct) && oct->msix_on) {
  146. /* set time and cnt interrupt thresholds for this DROQ
  147. * for NAPI
  148. */
  149. int adjusted_q_no = q_no + oct->sriov_info.pf_srn;
  150. octeon_write_csr64(
  151. oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(adjusted_q_no),
  152. 0x5700000040ULL);
  153. octeon_write_csr64(
  154. oct, CN23XX_SLI_OQ_PKTS_SENT(adjusted_q_no), 0);
  155. }
  156. }
  157. if (reschedule)
  158. tasklet_schedule(&oct_priv->droq_tasklet);
  159. }
  160. static int lio_wait_for_oq_pkts(struct octeon_device *oct)
  161. {
  162. struct octeon_device_priv *oct_priv = oct->priv;
  163. int retry = 100, pkt_cnt = 0, pending_pkts = 0;
  164. int i;
  165. do {
  166. pending_pkts = 0;
  167. for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
  168. if (!(oct->io_qmask.oq & BIT_ULL(i)))
  169. continue;
  170. pkt_cnt += octeon_droq_check_hw_for_pkts(oct->droq[i]);
  171. }
  172. if (pkt_cnt > 0) {
  173. pending_pkts += pkt_cnt;
  174. tasklet_schedule(&oct_priv->droq_tasklet);
  175. }
  176. pkt_cnt = 0;
  177. schedule_timeout_uninterruptible(1);
  178. } while (retry-- && pending_pkts);
  179. return pkt_cnt;
  180. }
  181. /**
  182. * force_io_queues_off - Forces all IO queues off on a given device
  183. * @oct: Pointer to Octeon device
  184. */
  185. static void force_io_queues_off(struct octeon_device *oct)
  186. {
  187. if ((oct->chip_id == OCTEON_CN66XX) ||
  188. (oct->chip_id == OCTEON_CN68XX)) {
  189. /* Reset the Enable bits for Input Queues. */
  190. octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
  191. /* Reset the Enable bits for Output Queues. */
  192. octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
  193. }
  194. }
  195. /**
  196. * pcierror_quiesce_device - Cause device to go quiet so it can be safely removed/reset/etc
  197. * @oct: Pointer to Octeon device
  198. */
  199. static inline void pcierror_quiesce_device(struct octeon_device *oct)
  200. {
  201. int i;
  202. /* Disable the input and output queues now. No more packets will
  203. * arrive from Octeon, but we should wait for all packet processing
  204. * to finish.
  205. */
  206. force_io_queues_off(oct);
  207. /* To allow for in-flight requests */
  208. schedule_timeout_uninterruptible(WAIT_INFLIGHT_REQUEST);
  209. if (wait_for_pending_requests(oct))
  210. dev_err(&oct->pci_dev->dev, "There were pending requests\n");
  211. /* Force all requests waiting to be fetched by OCTEON to complete. */
  212. for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
  213. struct octeon_instr_queue *iq;
  214. if (!(oct->io_qmask.iq & BIT_ULL(i)))
  215. continue;
  216. iq = oct->instr_queue[i];
  217. if (atomic_read(&iq->instr_pending)) {
  218. spin_lock_bh(&iq->lock);
  219. iq->fill_cnt = 0;
  220. iq->octeon_read_index = iq->host_write_index;
  221. iq->stats.instr_processed +=
  222. atomic_read(&iq->instr_pending);
  223. lio_process_iq_request_list(oct, iq, 0);
  224. spin_unlock_bh(&iq->lock);
  225. }
  226. }
  227. /* Force all pending ordered list requests to time out. */
  228. lio_process_ordered_list(oct, 1);
  229. /* We do not need to wait for output queue packets to be processed. */
  230. }
  231. /**
  232. * cleanup_aer_uncorrect_error_status - Cleanup PCI AER uncorrectable error status
  233. * @dev: Pointer to PCI device
  234. */
  235. static void cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
  236. {
  237. int pos = 0x100;
  238. u32 status, mask;
  239. pr_info("%s :\n", __func__);
  240. pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
  241. pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
  242. if (dev->error_state == pci_channel_io_normal)
  243. status &= ~mask; /* Clear corresponding nonfatal bits */
  244. else
  245. status &= mask; /* Clear corresponding fatal bits */
  246. pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
  247. }
  248. /**
  249. * stop_pci_io - Stop all PCI IO to a given device
  250. * @oct: Pointer to Octeon device
  251. */
  252. static void stop_pci_io(struct octeon_device *oct)
  253. {
  254. /* No more instructions will be forwarded. */
  255. atomic_set(&oct->status, OCT_DEV_IN_RESET);
  256. pci_disable_device(oct->pci_dev);
  257. /* Disable interrupts */
  258. oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
  259. pcierror_quiesce_device(oct);
  260. /* Release the interrupt line */
  261. free_irq(oct->pci_dev->irq, oct);
  262. if (oct->flags & LIO_FLAG_MSI_ENABLED)
  263. pci_disable_msi(oct->pci_dev);
  264. dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
  265. lio_get_state_string(&oct->status));
  266. /* making it a common function for all OCTEON models */
  267. cleanup_aer_uncorrect_error_status(oct->pci_dev);
  268. }
  269. /**
  270. * liquidio_pcie_error_detected - called when PCI error is detected
  271. * @pdev: Pointer to PCI device
  272. * @state: The current pci connection state
  273. *
  274. * This function is called after a PCI bus error affecting
  275. * this device has been detected.
  276. */
  277. static pci_ers_result_t liquidio_pcie_error_detected(struct pci_dev *pdev,
  278. pci_channel_state_t state)
  279. {
  280. struct octeon_device *oct = pci_get_drvdata(pdev);
  281. /* Non-correctable Non-fatal errors */
  282. if (state == pci_channel_io_normal) {
  283. dev_err(&oct->pci_dev->dev, "Non-correctable non-fatal error reported:\n");
  284. cleanup_aer_uncorrect_error_status(oct->pci_dev);
  285. return PCI_ERS_RESULT_CAN_RECOVER;
  286. }
  287. /* Non-correctable Fatal errors */
  288. dev_err(&oct->pci_dev->dev, "Non-correctable FATAL reported by PCI AER driver\n");
  289. stop_pci_io(oct);
  290. /* Always return a DISCONNECT. There is no support for recovery but only
  291. * for a clean shutdown.
  292. */
  293. return PCI_ERS_RESULT_DISCONNECT;
  294. }
  295. /**
  296. * liquidio_pcie_mmio_enabled - mmio handler
  297. * @pdev: Pointer to PCI device
  298. */
  299. static pci_ers_result_t liquidio_pcie_mmio_enabled(struct pci_dev __maybe_unused *pdev)
  300. {
  301. /* We should never hit this since we never ask for a reset for a Fatal
  302. * Error. We always return DISCONNECT in io_error above.
  303. * But play safe and return RECOVERED for now.
  304. */
  305. return PCI_ERS_RESULT_RECOVERED;
  306. }
  307. /**
  308. * liquidio_pcie_slot_reset - called after the pci bus has been reset.
  309. * @pdev: Pointer to PCI device
  310. *
  311. * Restart the card from scratch, as if from a cold-boot. Implementation
  312. * resembles the first-half of the octeon_resume routine.
  313. */
  314. static pci_ers_result_t liquidio_pcie_slot_reset(struct pci_dev __maybe_unused *pdev)
  315. {
  316. /* We should never hit this since we never ask for a reset for a Fatal
  317. * Error. We always return DISCONNECT in io_error above.
  318. * But play safe and return RECOVERED for now.
  319. */
  320. return PCI_ERS_RESULT_RECOVERED;
  321. }
  322. /**
  323. * liquidio_pcie_resume - called when traffic can start flowing again.
  324. * @pdev: Pointer to PCI device
  325. *
  326. * This callback is called when the error recovery driver tells us that
  327. * its OK to resume normal operation. Implementation resembles the
  328. * second-half of the octeon_resume routine.
  329. */
  330. static void liquidio_pcie_resume(struct pci_dev __maybe_unused *pdev)
  331. {
  332. /* Nothing to be done here. */
  333. }
  334. #define liquidio_suspend NULL
  335. #define liquidio_resume NULL
  336. /* For PCI-E Advanced Error Recovery (AER) Interface */
  337. static const struct pci_error_handlers liquidio_err_handler = {
  338. .error_detected = liquidio_pcie_error_detected,
  339. .mmio_enabled = liquidio_pcie_mmio_enabled,
  340. .slot_reset = liquidio_pcie_slot_reset,
  341. .resume = liquidio_pcie_resume,
  342. };
  343. static const struct pci_device_id liquidio_pci_tbl[] = {
  344. { /* 68xx */
  345. PCI_VENDOR_ID_CAVIUM, 0x91, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
  346. },
  347. { /* 66xx */
  348. PCI_VENDOR_ID_CAVIUM, 0x92, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
  349. },
  350. { /* 23xx pf */
  351. PCI_VENDOR_ID_CAVIUM, 0x9702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0
  352. },
  353. {
  354. 0, 0, 0, 0, 0, 0, 0
  355. }
  356. };
  357. MODULE_DEVICE_TABLE(pci, liquidio_pci_tbl);
  358. static SIMPLE_DEV_PM_OPS(liquidio_pm_ops, liquidio_suspend, liquidio_resume);
  359. static struct pci_driver liquidio_pci_driver = {
  360. .name = "LiquidIO",
  361. .id_table = liquidio_pci_tbl,
  362. .probe = liquidio_probe,
  363. .remove = liquidio_remove,
  364. .err_handler = &liquidio_err_handler, /* For AER */
  365. .driver.pm = &liquidio_pm_ops,
  366. #ifdef CONFIG_PCI_IOV
  367. .sriov_configure = liquidio_enable_sriov,
  368. #endif
  369. };
  370. /**
  371. * liquidio_init_pci - register PCI driver
  372. */
  373. static int liquidio_init_pci(void)
  374. {
  375. return pci_register_driver(&liquidio_pci_driver);
  376. }
  377. /**
  378. * liquidio_deinit_pci - unregister PCI driver
  379. */
  380. static void liquidio_deinit_pci(void)
  381. {
  382. pci_unregister_driver(&liquidio_pci_driver);
  383. }
  384. /**
  385. * check_txq_status - Check Tx queue status, and take appropriate action
  386. * @lio: per-network private data
  387. * Return: 0 if full, number of queues woken up otherwise
  388. */
  389. static inline int check_txq_status(struct lio *lio)
  390. {
  391. int numqs = lio->netdev->real_num_tx_queues;
  392. int ret_val = 0;
  393. int q, iq;
  394. /* check each sub-queue state */
  395. for (q = 0; q < numqs; q++) {
  396. iq = lio->linfo.txpciq[q %
  397. lio->oct_dev->num_iqs].s.q_no;
  398. if (octnet_iq_is_full(lio->oct_dev, iq))
  399. continue;
  400. if (__netif_subqueue_stopped(lio->netdev, q)) {
  401. netif_wake_subqueue(lio->netdev, q);
  402. INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq,
  403. tx_restart, 1);
  404. ret_val++;
  405. }
  406. }
  407. return ret_val;
  408. }
  409. /**
  410. * print_link_info - Print link information
  411. * @netdev: network device
  412. */
  413. static void print_link_info(struct net_device *netdev)
  414. {
  415. struct lio *lio = GET_LIO(netdev);
  416. if (!ifstate_check(lio, LIO_IFSTATE_RESETTING) &&
  417. ifstate_check(lio, LIO_IFSTATE_REGISTERED)) {
  418. struct oct_link_info *linfo = &lio->linfo;
  419. if (linfo->link.s.link_up) {
  420. netif_info(lio, link, lio->netdev, "%d Mbps %s Duplex UP\n",
  421. linfo->link.s.speed,
  422. (linfo->link.s.duplex) ? "Full" : "Half");
  423. } else {
  424. netif_info(lio, link, lio->netdev, "Link Down\n");
  425. }
  426. }
  427. }
  428. /**
  429. * octnet_link_status_change - Routine to notify MTU change
  430. * @work: work_struct data structure
  431. */
  432. static void octnet_link_status_change(struct work_struct *work)
  433. {
  434. struct cavium_wk *wk = (struct cavium_wk *)work;
  435. struct lio *lio = (struct lio *)wk->ctxptr;
  436. /* lio->linfo.link.s.mtu always contains max MTU of the lio interface.
  437. * this API is invoked only when new max-MTU of the interface is
  438. * less than current MTU.
  439. */
  440. rtnl_lock();
  441. dev_set_mtu(lio->netdev, lio->linfo.link.s.mtu);
  442. rtnl_unlock();
  443. }
  444. /**
  445. * setup_link_status_change_wq - Sets up the mtu status change work
  446. * @netdev: network device
  447. */
  448. static inline int setup_link_status_change_wq(struct net_device *netdev)
  449. {
  450. struct lio *lio = GET_LIO(netdev);
  451. struct octeon_device *oct = lio->oct_dev;
  452. lio->link_status_wq.wq = alloc_workqueue("link-status",
  453. WQ_MEM_RECLAIM | WQ_PERCPU,
  454. 0);
  455. if (!lio->link_status_wq.wq) {
  456. dev_err(&oct->pci_dev->dev, "unable to create cavium link status wq\n");
  457. return -1;
  458. }
  459. INIT_DELAYED_WORK(&lio->link_status_wq.wk.work,
  460. octnet_link_status_change);
  461. lio->link_status_wq.wk.ctxptr = lio;
  462. return 0;
  463. }
  464. static inline void cleanup_link_status_change_wq(struct net_device *netdev)
  465. {
  466. struct lio *lio = GET_LIO(netdev);
  467. if (lio->link_status_wq.wq) {
  468. cancel_delayed_work_sync(&lio->link_status_wq.wk.work);
  469. destroy_workqueue(lio->link_status_wq.wq);
  470. }
  471. }
  472. /**
  473. * update_link_status - Update link status
  474. * @netdev: network device
  475. * @ls: link status structure
  476. *
  477. * Called on receipt of a link status response from the core application to
  478. * update each interface's link status.
  479. */
  480. static inline void update_link_status(struct net_device *netdev,
  481. union oct_link_status *ls)
  482. {
  483. struct lio *lio = GET_LIO(netdev);
  484. int changed = (lio->linfo.link.u64 != ls->u64);
  485. int current_max_mtu = lio->linfo.link.s.mtu;
  486. struct octeon_device *oct = lio->oct_dev;
  487. dev_dbg(&oct->pci_dev->dev, "%s: lio->linfo.link.u64=%llx, ls->u64=%llx\n",
  488. __func__, lio->linfo.link.u64, ls->u64);
  489. lio->linfo.link.u64 = ls->u64;
  490. if ((lio->intf_open) && (changed)) {
  491. print_link_info(netdev);
  492. lio->link_changes++;
  493. if (lio->linfo.link.s.link_up) {
  494. dev_dbg(&oct->pci_dev->dev, "%s: link_up", __func__);
  495. netif_carrier_on(netdev);
  496. wake_txqs(netdev);
  497. } else {
  498. dev_dbg(&oct->pci_dev->dev, "%s: link_off", __func__);
  499. netif_carrier_off(netdev);
  500. stop_txqs(netdev);
  501. }
  502. if (lio->linfo.link.s.mtu != current_max_mtu) {
  503. netif_info(lio, probe, lio->netdev, "Max MTU changed from %d to %d\n",
  504. current_max_mtu, lio->linfo.link.s.mtu);
  505. netdev->max_mtu = lio->linfo.link.s.mtu;
  506. }
  507. if (lio->linfo.link.s.mtu < netdev->mtu) {
  508. dev_warn(&oct->pci_dev->dev,
  509. "Current MTU is higher than new max MTU; Reducing the current mtu from %d to %d\n",
  510. netdev->mtu, lio->linfo.link.s.mtu);
  511. queue_delayed_work(lio->link_status_wq.wq,
  512. &lio->link_status_wq.wk.work, 0);
  513. }
  514. }
  515. }
  516. /**
  517. * lio_sync_octeon_time - send latest localtime to octeon firmware so that
  518. * firmware will correct it's time, in case there is a time skew
  519. *
  520. * @work: work scheduled to send time update to octeon firmware
  521. **/
  522. static void lio_sync_octeon_time(struct work_struct *work)
  523. {
  524. struct cavium_wk *wk = (struct cavium_wk *)work;
  525. struct lio *lio = (struct lio *)wk->ctxptr;
  526. struct octeon_device *oct = lio->oct_dev;
  527. struct octeon_soft_command *sc;
  528. struct timespec64 ts;
  529. struct lio_time *lt;
  530. int ret;
  531. sc = octeon_alloc_soft_command(oct, sizeof(struct lio_time), 16, 0);
  532. if (!sc) {
  533. dev_err(&oct->pci_dev->dev,
  534. "Failed to sync time to octeon: soft command allocation failed\n");
  535. return;
  536. }
  537. lt = (struct lio_time *)sc->virtdptr;
  538. /* Get time of the day */
  539. ktime_get_real_ts64(&ts);
  540. lt->sec = ts.tv_sec;
  541. lt->nsec = ts.tv_nsec;
  542. octeon_swap_8B_data((u64 *)lt, (sizeof(struct lio_time)) / 8);
  543. sc->iq_no = lio->linfo.txpciq[0].s.q_no;
  544. octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
  545. OPCODE_NIC_SYNC_OCTEON_TIME, 0, 0, 0);
  546. init_completion(&sc->complete);
  547. sc->sc_status = OCTEON_REQUEST_PENDING;
  548. ret = octeon_send_soft_command(oct, sc);
  549. if (ret == IQ_SEND_FAILED) {
  550. dev_err(&oct->pci_dev->dev,
  551. "Failed to sync time to octeon: failed to send soft command\n");
  552. octeon_free_soft_command(oct, sc);
  553. } else {
  554. WRITE_ONCE(sc->caller_is_done, true);
  555. }
  556. queue_delayed_work(lio->sync_octeon_time_wq.wq,
  557. &lio->sync_octeon_time_wq.wk.work,
  558. msecs_to_jiffies(LIO_SYNC_OCTEON_TIME_INTERVAL_MS));
  559. }
  560. /**
  561. * setup_sync_octeon_time_wq - prepare work to periodically update local time to octeon firmware
  562. *
  563. * @netdev: network device which should send time update to firmware
  564. **/
  565. static inline int setup_sync_octeon_time_wq(struct net_device *netdev)
  566. {
  567. struct lio *lio = GET_LIO(netdev);
  568. struct octeon_device *oct = lio->oct_dev;
  569. lio->sync_octeon_time_wq.wq =
  570. alloc_workqueue("update-octeon-time",
  571. WQ_MEM_RECLAIM | WQ_PERCPU, 0);
  572. if (!lio->sync_octeon_time_wq.wq) {
  573. dev_err(&oct->pci_dev->dev, "Unable to create wq to update octeon time\n");
  574. return -1;
  575. }
  576. INIT_DELAYED_WORK(&lio->sync_octeon_time_wq.wk.work,
  577. lio_sync_octeon_time);
  578. lio->sync_octeon_time_wq.wk.ctxptr = lio;
  579. queue_delayed_work(lio->sync_octeon_time_wq.wq,
  580. &lio->sync_octeon_time_wq.wk.work,
  581. msecs_to_jiffies(LIO_SYNC_OCTEON_TIME_INTERVAL_MS));
  582. return 0;
  583. }
  584. /**
  585. * cleanup_sync_octeon_time_wq - destroy wq
  586. *
  587. * @netdev: network device which should send time update to firmware
  588. *
  589. * Stop scheduling and destroy the work created to periodically update local
  590. * time to octeon firmware.
  591. **/
  592. static inline void cleanup_sync_octeon_time_wq(struct net_device *netdev)
  593. {
  594. struct lio *lio = GET_LIO(netdev);
  595. struct cavium_wq *time_wq = &lio->sync_octeon_time_wq;
  596. if (time_wq->wq) {
  597. cancel_delayed_work_sync(&time_wq->wk.work);
  598. destroy_workqueue(time_wq->wq);
  599. }
  600. }
  601. static struct octeon_device *get_other_octeon_device(struct octeon_device *oct)
  602. {
  603. struct octeon_device *other_oct;
  604. other_oct = lio_get_device(oct->octeon_id + 1);
  605. if (other_oct && other_oct->pci_dev) {
  606. int oct_busnum, other_oct_busnum;
  607. oct_busnum = oct->pci_dev->bus->number;
  608. other_oct_busnum = other_oct->pci_dev->bus->number;
  609. if (oct_busnum == other_oct_busnum) {
  610. int oct_slot, other_oct_slot;
  611. oct_slot = PCI_SLOT(oct->pci_dev->devfn);
  612. other_oct_slot = PCI_SLOT(other_oct->pci_dev->devfn);
  613. if (oct_slot == other_oct_slot)
  614. return other_oct;
  615. }
  616. }
  617. return NULL;
  618. }
  619. static void disable_all_vf_links(struct octeon_device *oct)
  620. {
  621. struct net_device *netdev;
  622. int max_vfs, vf, i;
  623. if (!oct)
  624. return;
  625. max_vfs = oct->sriov_info.max_vfs;
  626. for (i = 0; i < oct->ifcount; i++) {
  627. netdev = oct->props[i].netdev;
  628. if (!netdev)
  629. continue;
  630. for (vf = 0; vf < max_vfs; vf++)
  631. liquidio_set_vf_link_state(netdev, vf,
  632. IFLA_VF_LINK_STATE_DISABLE);
  633. }
  634. }
  635. static int liquidio_watchdog(void *param)
  636. {
  637. bool err_msg_was_printed[LIO_MAX_CORES];
  638. u16 mask_of_crashed_or_stuck_cores = 0;
  639. bool all_vf_links_are_disabled = false;
  640. struct octeon_device *oct = param;
  641. struct octeon_device *other_oct;
  642. #ifdef CONFIG_MODULE_UNLOAD
  643. long refcount, vfs_referencing_pf;
  644. u64 vfs_mask1, vfs_mask2;
  645. #endif
  646. int core;
  647. memset(err_msg_was_printed, 0, sizeof(err_msg_was_printed));
  648. while (!kthread_should_stop()) {
  649. /* sleep for a couple of seconds so that we don't hog the CPU */
  650. set_current_state(TASK_INTERRUPTIBLE);
  651. schedule_timeout(msecs_to_jiffies(2000));
  652. mask_of_crashed_or_stuck_cores =
  653. (u16)octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2);
  654. if (!mask_of_crashed_or_stuck_cores)
  655. continue;
  656. WRITE_ONCE(oct->cores_crashed, true);
  657. other_oct = get_other_octeon_device(oct);
  658. if (other_oct)
  659. WRITE_ONCE(other_oct->cores_crashed, true);
  660. for (core = 0; core < LIO_MAX_CORES; core++) {
  661. bool core_crashed_or_got_stuck;
  662. core_crashed_or_got_stuck =
  663. (mask_of_crashed_or_stuck_cores
  664. >> core) & 1;
  665. if (core_crashed_or_got_stuck &&
  666. !err_msg_was_printed[core]) {
  667. dev_err(&oct->pci_dev->dev,
  668. "ERROR: Octeon core %d crashed or got stuck! See oct-fwdump for details.\n",
  669. core);
  670. err_msg_was_printed[core] = true;
  671. }
  672. }
  673. if (all_vf_links_are_disabled)
  674. continue;
  675. disable_all_vf_links(oct);
  676. disable_all_vf_links(other_oct);
  677. all_vf_links_are_disabled = true;
  678. #ifdef CONFIG_MODULE_UNLOAD
  679. vfs_mask1 = READ_ONCE(oct->sriov_info.vf_drv_loaded_mask);
  680. vfs_mask2 = READ_ONCE(other_oct->sriov_info.vf_drv_loaded_mask);
  681. vfs_referencing_pf = hweight64(vfs_mask1);
  682. vfs_referencing_pf += hweight64(vfs_mask2);
  683. refcount = module_refcount(THIS_MODULE);
  684. if (refcount >= vfs_referencing_pf) {
  685. while (vfs_referencing_pf) {
  686. module_put(THIS_MODULE);
  687. vfs_referencing_pf--;
  688. }
  689. }
  690. #endif
  691. }
  692. return 0;
  693. }
  694. /**
  695. * liquidio_probe - PCI probe handler
  696. * @pdev: PCI device structure
  697. * @ent: unused
  698. */
  699. static int
  700. liquidio_probe(struct pci_dev *pdev, const struct pci_device_id __maybe_unused *ent)
  701. {
  702. struct octeon_device *oct_dev = NULL;
  703. struct handshake *hs;
  704. oct_dev = octeon_allocate_device(pdev->device,
  705. sizeof(struct octeon_device_priv));
  706. if (!oct_dev) {
  707. dev_err(&pdev->dev, "Unable to allocate device\n");
  708. return -ENOMEM;
  709. }
  710. if (pdev->device == OCTEON_CN23XX_PF_VID)
  711. oct_dev->msix_on = LIO_FLAG_MSIX_ENABLED;
  712. /* Enable PTP for 6XXX Device */
  713. if (((pdev->device == OCTEON_CN66XX) ||
  714. (pdev->device == OCTEON_CN68XX)))
  715. oct_dev->ptp_enable = true;
  716. else
  717. oct_dev->ptp_enable = false;
  718. dev_info(&pdev->dev, "Initializing device %x:%x.\n",
  719. (u32)pdev->vendor, (u32)pdev->device);
  720. /* Assign octeon_device for this device to the private data area. */
  721. pci_set_drvdata(pdev, oct_dev);
  722. /* set linux specific device pointer */
  723. oct_dev->pci_dev = (void *)pdev;
  724. oct_dev->subsystem_id = pdev->subsystem_vendor |
  725. (pdev->subsystem_device << 16);
  726. hs = &handshake[oct_dev->octeon_id];
  727. init_completion(&hs->init);
  728. init_completion(&hs->started);
  729. hs->pci_dev = pdev;
  730. if (oct_dev->octeon_id == 0)
  731. /* first LiquidIO NIC is detected */
  732. complete(&first_stage);
  733. if (octeon_device_init(oct_dev)) {
  734. complete(&hs->init);
  735. liquidio_remove(pdev);
  736. return -ENOMEM;
  737. }
  738. if (OCTEON_CN23XX_PF(oct_dev)) {
  739. u8 bus, device, function;
  740. if (atomic_read(oct_dev->adapter_refcount) == 1) {
  741. /* Each NIC gets one watchdog kernel thread. The first
  742. * PF (of each NIC) that gets pci_driver->probe()'d
  743. * creates that thread.
  744. */
  745. bus = pdev->bus->number;
  746. device = PCI_SLOT(pdev->devfn);
  747. function = PCI_FUNC(pdev->devfn);
  748. oct_dev->watchdog_task = kthread_run(liquidio_watchdog,
  749. oct_dev,
  750. "liowd/%02hhx:%02hhx.%hhx",
  751. bus, device, function);
  752. if (IS_ERR(oct_dev->watchdog_task)) {
  753. oct_dev->watchdog_task = NULL;
  754. dev_err(&oct_dev->pci_dev->dev,
  755. "failed to create kernel_thread\n");
  756. liquidio_remove(pdev);
  757. return -1;
  758. }
  759. }
  760. }
  761. oct_dev->rx_pause = 1;
  762. oct_dev->tx_pause = 1;
  763. dev_dbg(&oct_dev->pci_dev->dev, "Device is ready\n");
  764. return 0;
  765. }
  766. static bool fw_type_is_auto(void)
  767. {
  768. return strncmp(fw_type, LIO_FW_NAME_TYPE_AUTO,
  769. sizeof(LIO_FW_NAME_TYPE_AUTO)) == 0;
  770. }
  771. /**
  772. * octeon_pci_flr - PCI FLR for each Octeon device.
  773. * @oct: octeon device
  774. */
  775. static void octeon_pci_flr(struct octeon_device *oct)
  776. {
  777. int rc;
  778. pci_save_state(oct->pci_dev);
  779. pci_cfg_access_lock(oct->pci_dev);
  780. /* Quiesce the device completely */
  781. pci_write_config_word(oct->pci_dev, PCI_COMMAND,
  782. PCI_COMMAND_INTX_DISABLE);
  783. rc = __pci_reset_function_locked(oct->pci_dev);
  784. if (rc != 0)
  785. dev_err(&oct->pci_dev->dev, "Error %d resetting PCI function %d\n",
  786. rc, oct->pf_num);
  787. pci_cfg_access_unlock(oct->pci_dev);
  788. pci_restore_state(oct->pci_dev);
  789. }
  790. /**
  791. * octeon_destroy_resources - Destroy resources associated with octeon device
  792. * @oct: octeon device
  793. */
  794. static void octeon_destroy_resources(struct octeon_device *oct)
  795. {
  796. int i, refcount;
  797. struct msix_entry *msix_entries;
  798. struct octeon_device_priv *oct_priv = oct->priv;
  799. struct handshake *hs;
  800. switch (atomic_read(&oct->status)) {
  801. case OCT_DEV_RUNNING:
  802. case OCT_DEV_CORE_OK:
  803. /* No more instructions will be forwarded. */
  804. atomic_set(&oct->status, OCT_DEV_IN_RESET);
  805. oct->app_mode = CVM_DRV_INVALID_APP;
  806. dev_dbg(&oct->pci_dev->dev, "Device state is now %s\n",
  807. lio_get_state_string(&oct->status));
  808. schedule_timeout_uninterruptible(HZ / 10);
  809. fallthrough;
  810. case OCT_DEV_HOST_OK:
  811. case OCT_DEV_CONSOLE_INIT_DONE:
  812. /* Remove any consoles */
  813. octeon_remove_consoles(oct);
  814. fallthrough;
  815. case OCT_DEV_IO_QUEUES_DONE:
  816. if (lio_wait_for_instr_fetch(oct))
  817. dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n");
  818. if (wait_for_pending_requests(oct))
  819. dev_err(&oct->pci_dev->dev, "There were pending requests\n");
  820. /* Disable the input and output queues now. No more packets will
  821. * arrive from Octeon, but we should wait for all packet
  822. * processing to finish.
  823. */
  824. oct->fn_list.disable_io_queues(oct);
  825. if (lio_wait_for_oq_pkts(oct))
  826. dev_err(&oct->pci_dev->dev, "OQ had pending packets\n");
  827. /* Force all requests waiting to be fetched by OCTEON to
  828. * complete.
  829. */
  830. for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
  831. struct octeon_instr_queue *iq;
  832. if (!(oct->io_qmask.iq & BIT_ULL(i)))
  833. continue;
  834. iq = oct->instr_queue[i];
  835. if (atomic_read(&iq->instr_pending)) {
  836. spin_lock_bh(&iq->lock);
  837. iq->fill_cnt = 0;
  838. iq->octeon_read_index = iq->host_write_index;
  839. iq->stats.instr_processed +=
  840. atomic_read(&iq->instr_pending);
  841. lio_process_iq_request_list(oct, iq, 0);
  842. spin_unlock_bh(&iq->lock);
  843. }
  844. }
  845. lio_process_ordered_list(oct, 1);
  846. octeon_free_sc_done_list(oct);
  847. octeon_free_sc_zombie_list(oct);
  848. fallthrough;
  849. case OCT_DEV_INTR_SET_DONE:
  850. /* Disable interrupts */
  851. oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
  852. if (oct->msix_on) {
  853. msix_entries = (struct msix_entry *)oct->msix_entries;
  854. for (i = 0; i < oct->num_msix_irqs - 1; i++) {
  855. if (oct->ioq_vector[i].vector) {
  856. /* clear the affinity_cpumask */
  857. irq_set_affinity_hint(
  858. msix_entries[i].vector,
  859. NULL);
  860. free_irq(msix_entries[i].vector,
  861. &oct->ioq_vector[i]);
  862. oct->ioq_vector[i].vector = 0;
  863. }
  864. }
  865. /* non-iov vector's argument is oct struct */
  866. free_irq(msix_entries[i].vector, oct);
  867. pci_disable_msix(oct->pci_dev);
  868. kfree(oct->msix_entries);
  869. oct->msix_entries = NULL;
  870. } else {
  871. /* Release the interrupt line */
  872. free_irq(oct->pci_dev->irq, oct);
  873. if (oct->flags & LIO_FLAG_MSI_ENABLED)
  874. pci_disable_msi(oct->pci_dev);
  875. }
  876. kfree(oct->irq_name_storage);
  877. oct->irq_name_storage = NULL;
  878. fallthrough;
  879. case OCT_DEV_MSIX_ALLOC_VECTOR_DONE:
  880. if (OCTEON_CN23XX_PF(oct))
  881. octeon_free_ioq_vector(oct);
  882. fallthrough;
  883. case OCT_DEV_MBOX_SETUP_DONE:
  884. if (OCTEON_CN23XX_PF(oct))
  885. oct->fn_list.free_mbox(oct);
  886. fallthrough;
  887. case OCT_DEV_IN_RESET:
  888. case OCT_DEV_DROQ_INIT_DONE:
  889. /* Wait for any pending operations */
  890. mdelay(100);
  891. for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
  892. if (!(oct->io_qmask.oq & BIT_ULL(i)))
  893. continue;
  894. octeon_delete_droq(oct, i);
  895. }
  896. /* Force any pending handshakes to complete */
  897. for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
  898. hs = &handshake[i];
  899. if (hs->pci_dev) {
  900. handshake[oct->octeon_id].init_ok = 0;
  901. complete(&handshake[oct->octeon_id].init);
  902. handshake[oct->octeon_id].started_ok = 0;
  903. complete(&handshake[oct->octeon_id].started);
  904. }
  905. }
  906. fallthrough;
  907. case OCT_DEV_RESP_LIST_INIT_DONE:
  908. octeon_delete_response_list(oct);
  909. fallthrough;
  910. case OCT_DEV_INSTR_QUEUE_INIT_DONE:
  911. for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
  912. if (!(oct->io_qmask.iq & BIT_ULL(i)))
  913. continue;
  914. octeon_delete_instr_queue(oct, i);
  915. }
  916. #ifdef CONFIG_PCI_IOV
  917. if (oct->sriov_info.sriov_enabled)
  918. pci_disable_sriov(oct->pci_dev);
  919. #endif
  920. fallthrough;
  921. case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
  922. octeon_free_sc_buffer_pool(oct);
  923. fallthrough;
  924. case OCT_DEV_DISPATCH_INIT_DONE:
  925. octeon_delete_dispatch_list(oct);
  926. cancel_delayed_work_sync(&oct->nic_poll_work.work);
  927. fallthrough;
  928. case OCT_DEV_PCI_MAP_DONE:
  929. refcount = octeon_deregister_device(oct);
  930. /* Soft reset the octeon device before exiting.
  931. * However, if fw was loaded from card (i.e. autoboot),
  932. * perform an FLR instead.
  933. * Implementation note: only soft-reset the device
  934. * if it is a CN6XXX OR the LAST CN23XX device.
  935. */
  936. if (atomic_read(oct->adapter_fw_state) == FW_IS_PRELOADED)
  937. octeon_pci_flr(oct);
  938. else if (OCTEON_CN6XXX(oct) || !refcount)
  939. oct->fn_list.soft_reset(oct);
  940. octeon_unmap_pci_barx(oct, 0);
  941. octeon_unmap_pci_barx(oct, 1);
  942. fallthrough;
  943. case OCT_DEV_PCI_ENABLE_DONE:
  944. /* Disable the device, releasing the PCI INT */
  945. pci_disable_device(oct->pci_dev);
  946. fallthrough;
  947. case OCT_DEV_BEGIN_STATE:
  948. /* Nothing to be done here either */
  949. break;
  950. } /* end switch (oct->status) */
  951. tasklet_kill(&oct_priv->droq_tasklet);
  952. }
  953. /**
  954. * send_rx_ctrl_cmd - Send Rx control command
  955. * @lio: per-network private data
  956. * @start_stop: whether to start or stop
  957. */
  958. static int send_rx_ctrl_cmd(struct lio *lio, int start_stop)
  959. {
  960. struct octeon_soft_command *sc;
  961. union octnet_cmd *ncmd;
  962. struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
  963. int retval;
  964. if (oct->props[lio->ifidx].rx_on == start_stop)
  965. return 0;
  966. sc = (struct octeon_soft_command *)
  967. octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
  968. 16, 0);
  969. if (!sc) {
  970. netif_info(lio, rx_err, lio->netdev,
  971. "Failed to allocate octeon_soft_command struct\n");
  972. return -ENOMEM;
  973. }
  974. ncmd = (union octnet_cmd *)sc->virtdptr;
  975. ncmd->u64 = 0;
  976. ncmd->s.cmd = OCTNET_CMD_RX_CTL;
  977. ncmd->s.param1 = start_stop;
  978. octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
  979. sc->iq_no = lio->linfo.txpciq[0].s.q_no;
  980. octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
  981. OPCODE_NIC_CMD, 0, 0, 0);
  982. init_completion(&sc->complete);
  983. sc->sc_status = OCTEON_REQUEST_PENDING;
  984. retval = octeon_send_soft_command(oct, sc);
  985. if (retval == IQ_SEND_FAILED) {
  986. netif_info(lio, rx_err, lio->netdev, "Failed to send RX Control message\n");
  987. octeon_free_soft_command(oct, sc);
  988. } else {
  989. /* Sleep on a wait queue till the cond flag indicates that the
  990. * response arrived or timed-out.
  991. */
  992. retval = wait_for_sc_completion_timeout(oct, sc, 0);
  993. if (retval)
  994. return retval;
  995. oct->props[lio->ifidx].rx_on = start_stop;
  996. WRITE_ONCE(sc->caller_is_done, true);
  997. }
  998. return retval;
  999. }
  1000. /**
  1001. * liquidio_destroy_nic_device - Destroy NIC device interface
  1002. * @oct: octeon device
  1003. * @ifidx: which interface to destroy
  1004. *
  1005. * Cleanup associated with each interface for an Octeon device when NIC
  1006. * module is being unloaded or if initialization fails during load.
  1007. */
  1008. static void liquidio_destroy_nic_device(struct octeon_device *oct, int ifidx)
  1009. {
  1010. struct net_device *netdev = oct->props[ifidx].netdev;
  1011. struct octeon_device_priv *oct_priv = oct->priv;
  1012. struct napi_struct *napi, *n;
  1013. struct lio *lio;
  1014. if (!netdev) {
  1015. dev_err(&oct->pci_dev->dev, "%s No netdevice ptr for index %d\n",
  1016. __func__, ifidx);
  1017. return;
  1018. }
  1019. lio = GET_LIO(netdev);
  1020. dev_dbg(&oct->pci_dev->dev, "NIC device cleanup\n");
  1021. if (atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING)
  1022. liquidio_stop(netdev);
  1023. if (oct->props[lio->ifidx].napi_enabled == 1) {
  1024. list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
  1025. napi_disable(napi);
  1026. oct->props[lio->ifidx].napi_enabled = 0;
  1027. if (OCTEON_CN23XX_PF(oct))
  1028. oct->droq[0]->ops.poll_mode = 0;
  1029. }
  1030. /* Delete NAPI */
  1031. list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
  1032. netif_napi_del(napi);
  1033. tasklet_enable(&oct_priv->droq_tasklet);
  1034. if (atomic_read(&lio->ifstate) & LIO_IFSTATE_REGISTERED)
  1035. unregister_netdev(netdev);
  1036. cleanup_sync_octeon_time_wq(netdev);
  1037. cleanup_link_status_change_wq(netdev);
  1038. cleanup_rx_oom_poll_fn(netdev);
  1039. lio_delete_glists(lio);
  1040. free_netdev(netdev);
  1041. oct->props[ifidx].gmxport = -1;
  1042. oct->props[ifidx].netdev = NULL;
  1043. }
  1044. /**
  1045. * liquidio_stop_nic_module - Stop complete NIC functionality
  1046. * @oct: octeon device
  1047. */
  1048. static int liquidio_stop_nic_module(struct octeon_device *oct)
  1049. {
  1050. int i, j;
  1051. struct lio *lio;
  1052. dev_dbg(&oct->pci_dev->dev, "Stopping network interfaces\n");
  1053. device_lock(&oct->pci_dev->dev);
  1054. if (oct->devlink) {
  1055. devlink_unregister(oct->devlink);
  1056. devlink_free(oct->devlink);
  1057. oct->devlink = NULL;
  1058. }
  1059. device_unlock(&oct->pci_dev->dev);
  1060. if (!oct->ifcount) {
  1061. dev_err(&oct->pci_dev->dev, "Init for Octeon was not completed\n");
  1062. return 1;
  1063. }
  1064. spin_lock_bh(&oct->cmd_resp_wqlock);
  1065. oct->cmd_resp_state = OCT_DRV_OFFLINE;
  1066. spin_unlock_bh(&oct->cmd_resp_wqlock);
  1067. lio_vf_rep_destroy(oct);
  1068. for (i = 0; i < oct->ifcount; i++) {
  1069. lio = GET_LIO(oct->props[i].netdev);
  1070. for (j = 0; j < oct->num_oqs; j++)
  1071. octeon_unregister_droq_ops(oct,
  1072. lio->linfo.rxpciq[j].s.q_no);
  1073. }
  1074. for (i = 0; i < oct->ifcount; i++)
  1075. liquidio_destroy_nic_device(oct, i);
  1076. dev_dbg(&oct->pci_dev->dev, "Network interfaces stopped\n");
  1077. return 0;
  1078. }
  1079. /**
  1080. * liquidio_remove - Cleans up resources at unload time
  1081. * @pdev: PCI device structure
  1082. */
  1083. static void liquidio_remove(struct pci_dev *pdev)
  1084. {
  1085. struct octeon_device *oct_dev = pci_get_drvdata(pdev);
  1086. dev_dbg(&oct_dev->pci_dev->dev, "Stopping device\n");
  1087. if (oct_dev->watchdog_task)
  1088. kthread_stop(oct_dev->watchdog_task);
  1089. if (!oct_dev->octeon_id &&
  1090. oct_dev->fw_info.app_cap_flags & LIQUIDIO_SWITCHDEV_CAP)
  1091. lio_vf_rep_modexit();
  1092. if (oct_dev->app_mode && (oct_dev->app_mode == CVM_DRV_NIC_APP))
  1093. liquidio_stop_nic_module(oct_dev);
  1094. /* Reset the octeon device and cleanup all memory allocated for
  1095. * the octeon device by driver.
  1096. */
  1097. octeon_destroy_resources(oct_dev);
  1098. dev_info(&oct_dev->pci_dev->dev, "Device removed\n");
  1099. /* This octeon device has been removed. Update the global
  1100. * data structure to reflect this. Free the device structure.
  1101. */
  1102. octeon_free_device_mem(oct_dev);
  1103. }
  1104. /**
  1105. * octeon_chip_specific_setup - Identify the Octeon device and to map the BAR address space
  1106. * @oct: octeon device
  1107. */
  1108. static int octeon_chip_specific_setup(struct octeon_device *oct)
  1109. {
  1110. u32 dev_id, rev_id;
  1111. int ret = 1;
  1112. pci_read_config_dword(oct->pci_dev, 0, &dev_id);
  1113. pci_read_config_dword(oct->pci_dev, 8, &rev_id);
  1114. oct->rev_id = rev_id & 0xff;
  1115. switch (dev_id) {
  1116. case OCTEON_CN68XX_PCIID:
  1117. oct->chip_id = OCTEON_CN68XX;
  1118. ret = lio_setup_cn68xx_octeon_device(oct);
  1119. break;
  1120. case OCTEON_CN66XX_PCIID:
  1121. oct->chip_id = OCTEON_CN66XX;
  1122. ret = lio_setup_cn66xx_octeon_device(oct);
  1123. break;
  1124. case OCTEON_CN23XX_PCIID_PF:
  1125. oct->chip_id = OCTEON_CN23XX_PF_VID;
  1126. ret = setup_cn23xx_octeon_pf_device(oct);
  1127. if (ret)
  1128. break;
  1129. #ifdef CONFIG_PCI_IOV
  1130. if (!ret)
  1131. pci_sriov_set_totalvfs(oct->pci_dev,
  1132. oct->sriov_info.max_vfs);
  1133. #endif
  1134. break;
  1135. default:
  1136. dev_err(&oct->pci_dev->dev, "Unknown device found (dev_id: %x)\n",
  1137. dev_id);
  1138. }
  1139. return ret;
  1140. }
  1141. /**
  1142. * octeon_pci_os_setup - PCI initialization for each Octeon device.
  1143. * @oct: octeon device
  1144. */
  1145. static int octeon_pci_os_setup(struct octeon_device *oct)
  1146. {
  1147. /* setup PCI stuff first */
  1148. if (pci_enable_device(oct->pci_dev)) {
  1149. dev_err(&oct->pci_dev->dev, "pci_enable_device failed\n");
  1150. return 1;
  1151. }
  1152. if (dma_set_mask_and_coherent(&oct->pci_dev->dev, DMA_BIT_MASK(64))) {
  1153. dev_err(&oct->pci_dev->dev, "Unexpected DMA device capability\n");
  1154. pci_disable_device(oct->pci_dev);
  1155. return 1;
  1156. }
  1157. /* Enable PCI DMA Master. */
  1158. pci_set_master(oct->pci_dev);
  1159. return 0;
  1160. }
  1161. /**
  1162. * free_netbuf - Unmap and free network buffer
  1163. * @buf: buffer
  1164. */
  1165. static void free_netbuf(void *buf)
  1166. {
  1167. struct sk_buff *skb;
  1168. struct octnet_buf_free_info *finfo;
  1169. struct lio *lio;
  1170. finfo = (struct octnet_buf_free_info *)buf;
  1171. skb = finfo->skb;
  1172. lio = finfo->lio;
  1173. dma_unmap_single(&lio->oct_dev->pci_dev->dev, finfo->dptr, skb->len,
  1174. DMA_TO_DEVICE);
  1175. tx_buffer_free(skb);
  1176. }
  1177. /**
  1178. * free_netsgbuf - Unmap and free gather buffer
  1179. * @buf: buffer
  1180. */
  1181. static void free_netsgbuf(void *buf)
  1182. {
  1183. struct octnet_buf_free_info *finfo;
  1184. struct sk_buff *skb;
  1185. struct lio *lio;
  1186. struct octnic_gather *g;
  1187. int i, frags, iq;
  1188. finfo = (struct octnet_buf_free_info *)buf;
  1189. skb = finfo->skb;
  1190. lio = finfo->lio;
  1191. g = finfo->g;
  1192. frags = skb_shinfo(skb)->nr_frags;
  1193. dma_unmap_single(&lio->oct_dev->pci_dev->dev,
  1194. g->sg[0].ptr[0], (skb->len - skb->data_len),
  1195. DMA_TO_DEVICE);
  1196. i = 1;
  1197. while (frags--) {
  1198. skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
  1199. dma_unmap_page(&lio->oct_dev->pci_dev->dev,
  1200. g->sg[(i >> 2)].ptr[(i & 3)],
  1201. skb_frag_size(frag), DMA_TO_DEVICE);
  1202. i++;
  1203. }
  1204. iq = skb_iq(lio->oct_dev, skb);
  1205. spin_lock(&lio->glist_lock[iq]);
  1206. list_add_tail(&g->list, &lio->glist[iq]);
  1207. spin_unlock(&lio->glist_lock[iq]);
  1208. tx_buffer_free(skb);
  1209. }
  1210. /**
  1211. * free_netsgbuf_with_resp - Unmap and free gather buffer with response
  1212. * @buf: buffer
  1213. */
  1214. static void free_netsgbuf_with_resp(void *buf)
  1215. {
  1216. struct octeon_soft_command *sc;
  1217. struct octnet_buf_free_info *finfo;
  1218. struct sk_buff *skb;
  1219. struct lio *lio;
  1220. struct octnic_gather *g;
  1221. int i, frags, iq;
  1222. sc = (struct octeon_soft_command *)buf;
  1223. skb = (struct sk_buff *)sc->callback_arg;
  1224. finfo = (struct octnet_buf_free_info *)&skb->cb;
  1225. lio = finfo->lio;
  1226. g = finfo->g;
  1227. frags = skb_shinfo(skb)->nr_frags;
  1228. dma_unmap_single(&lio->oct_dev->pci_dev->dev,
  1229. g->sg[0].ptr[0], (skb->len - skb->data_len),
  1230. DMA_TO_DEVICE);
  1231. i = 1;
  1232. while (frags--) {
  1233. skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
  1234. dma_unmap_page(&lio->oct_dev->pci_dev->dev,
  1235. g->sg[(i >> 2)].ptr[(i & 3)],
  1236. skb_frag_size(frag), DMA_TO_DEVICE);
  1237. i++;
  1238. }
  1239. iq = skb_iq(lio->oct_dev, skb);
  1240. spin_lock(&lio->glist_lock[iq]);
  1241. list_add_tail(&g->list, &lio->glist[iq]);
  1242. spin_unlock(&lio->glist_lock[iq]);
  1243. /* Don't free the skb yet */
  1244. }
  1245. /**
  1246. * liquidio_ptp_adjfine - Adjust ptp frequency
  1247. * @ptp: PTP clock info
  1248. * @scaled_ppm: how much to adjust by, in scaled parts-per-million
  1249. *
  1250. * Scaled parts per million is ppm with a 16-bit binary fractional field.
  1251. */
  1252. static int liquidio_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
  1253. {
  1254. struct lio *lio = container_of(ptp, struct lio, ptp_info);
  1255. struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
  1256. s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
  1257. u64 comp, delta;
  1258. unsigned long flags;
  1259. bool neg_adj = false;
  1260. if (ppb < 0) {
  1261. neg_adj = true;
  1262. ppb = -ppb;
  1263. }
  1264. /* The hardware adds the clock compensation value to the
  1265. * PTP clock on every coprocessor clock cycle, so we
  1266. * compute the delta in terms of coprocessor clocks.
  1267. */
  1268. delta = (u64)ppb << 32;
  1269. do_div(delta, oct->coproc_clock_rate);
  1270. spin_lock_irqsave(&lio->ptp_lock, flags);
  1271. comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP);
  1272. if (neg_adj)
  1273. comp -= delta;
  1274. else
  1275. comp += delta;
  1276. lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP);
  1277. spin_unlock_irqrestore(&lio->ptp_lock, flags);
  1278. return 0;
  1279. }
  1280. /**
  1281. * liquidio_ptp_adjtime - Adjust ptp time
  1282. * @ptp: PTP clock info
  1283. * @delta: how much to adjust by, in nanosecs
  1284. */
  1285. static int liquidio_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
  1286. {
  1287. unsigned long flags;
  1288. struct lio *lio = container_of(ptp, struct lio, ptp_info);
  1289. spin_lock_irqsave(&lio->ptp_lock, flags);
  1290. lio->ptp_adjust += delta;
  1291. spin_unlock_irqrestore(&lio->ptp_lock, flags);
  1292. return 0;
  1293. }
  1294. /**
  1295. * liquidio_ptp_gettime - Get hardware clock time, including any adjustment
  1296. * @ptp: PTP clock info
  1297. * @ts: timespec
  1298. */
  1299. static int liquidio_ptp_gettime(struct ptp_clock_info *ptp,
  1300. struct timespec64 *ts)
  1301. {
  1302. u64 ns;
  1303. unsigned long flags;
  1304. struct lio *lio = container_of(ptp, struct lio, ptp_info);
  1305. struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
  1306. spin_lock_irqsave(&lio->ptp_lock, flags);
  1307. ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI);
  1308. ns += lio->ptp_adjust;
  1309. spin_unlock_irqrestore(&lio->ptp_lock, flags);
  1310. *ts = ns_to_timespec64(ns);
  1311. return 0;
  1312. }
  1313. /**
  1314. * liquidio_ptp_settime - Set hardware clock time. Reset adjustment
  1315. * @ptp: PTP clock info
  1316. * @ts: timespec
  1317. */
  1318. static int liquidio_ptp_settime(struct ptp_clock_info *ptp,
  1319. const struct timespec64 *ts)
  1320. {
  1321. u64 ns;
  1322. unsigned long flags;
  1323. struct lio *lio = container_of(ptp, struct lio, ptp_info);
  1324. struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
  1325. ns = timespec64_to_ns(ts);
  1326. spin_lock_irqsave(&lio->ptp_lock, flags);
  1327. lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI);
  1328. lio->ptp_adjust = 0;
  1329. spin_unlock_irqrestore(&lio->ptp_lock, flags);
  1330. return 0;
  1331. }
  1332. /**
  1333. * liquidio_ptp_enable - Check if PTP is enabled
  1334. * @ptp: PTP clock info
  1335. * @rq: request
  1336. * @on: is it on
  1337. */
  1338. static int
  1339. liquidio_ptp_enable(struct ptp_clock_info __maybe_unused *ptp,
  1340. struct ptp_clock_request __maybe_unused *rq,
  1341. int __maybe_unused on)
  1342. {
  1343. return -EOPNOTSUPP;
  1344. }
  1345. /**
  1346. * oct_ptp_open - Open PTP clock source
  1347. * @netdev: network device
  1348. */
  1349. static void oct_ptp_open(struct net_device *netdev)
  1350. {
  1351. struct lio *lio = GET_LIO(netdev);
  1352. struct octeon_device *oct = (struct octeon_device *)lio->oct_dev;
  1353. spin_lock_init(&lio->ptp_lock);
  1354. snprintf(lio->ptp_info.name, 16, "%s", netdev->name);
  1355. lio->ptp_info.owner = THIS_MODULE;
  1356. lio->ptp_info.max_adj = 250000000;
  1357. lio->ptp_info.n_alarm = 0;
  1358. lio->ptp_info.n_ext_ts = 0;
  1359. lio->ptp_info.n_per_out = 0;
  1360. lio->ptp_info.pps = 0;
  1361. lio->ptp_info.adjfine = liquidio_ptp_adjfine;
  1362. lio->ptp_info.adjtime = liquidio_ptp_adjtime;
  1363. lio->ptp_info.gettime64 = liquidio_ptp_gettime;
  1364. lio->ptp_info.settime64 = liquidio_ptp_settime;
  1365. lio->ptp_info.enable = liquidio_ptp_enable;
  1366. lio->ptp_adjust = 0;
  1367. lio->ptp_clock = ptp_clock_register(&lio->ptp_info,
  1368. &oct->pci_dev->dev);
  1369. if (IS_ERR(lio->ptp_clock))
  1370. lio->ptp_clock = NULL;
  1371. }
  1372. /**
  1373. * liquidio_ptp_init - Init PTP clock
  1374. * @oct: octeon device
  1375. */
  1376. static void liquidio_ptp_init(struct octeon_device *oct)
  1377. {
  1378. u64 clock_comp, cfg;
  1379. clock_comp = (u64)NSEC_PER_SEC << 32;
  1380. do_div(clock_comp, oct->coproc_clock_rate);
  1381. lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP);
  1382. /* Enable */
  1383. cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG);
  1384. lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG);
  1385. }
  1386. /**
  1387. * load_firmware - Load firmware to device
  1388. * @oct: octeon device
  1389. *
  1390. * Maps device to firmware filename, requests firmware, and downloads it
  1391. */
  1392. static int load_firmware(struct octeon_device *oct)
  1393. {
  1394. int ret = 0;
  1395. const struct firmware *fw;
  1396. char fw_name[LIO_MAX_FW_FILENAME_LEN];
  1397. char *tmp_fw_type;
  1398. if (fw_type_is_auto()) {
  1399. tmp_fw_type = LIO_FW_NAME_TYPE_NIC;
  1400. strscpy_pad(fw_type, tmp_fw_type, sizeof(fw_type));
  1401. } else {
  1402. tmp_fw_type = fw_type;
  1403. }
  1404. sprintf(fw_name, "%s%s%s_%s%s", LIO_FW_DIR, LIO_FW_BASE_NAME,
  1405. octeon_get_conf(oct)->card_name, tmp_fw_type,
  1406. LIO_FW_NAME_SUFFIX);
  1407. ret = request_firmware(&fw, fw_name, &oct->pci_dev->dev);
  1408. if (ret) {
  1409. dev_err(&oct->pci_dev->dev, "Request firmware failed. Could not find file %s.\n",
  1410. fw_name);
  1411. release_firmware(fw);
  1412. return ret;
  1413. }
  1414. ret = octeon_download_firmware(oct, fw->data, fw->size);
  1415. release_firmware(fw);
  1416. return ret;
  1417. }
  1418. /**
  1419. * octnet_poll_check_txq_status - Poll routine for checking transmit queue status
  1420. * @work: work_struct data structure
  1421. */
  1422. static void octnet_poll_check_txq_status(struct work_struct *work)
  1423. {
  1424. struct cavium_wk *wk = (struct cavium_wk *)work;
  1425. struct lio *lio = (struct lio *)wk->ctxptr;
  1426. if (!ifstate_check(lio, LIO_IFSTATE_RUNNING))
  1427. return;
  1428. check_txq_status(lio);
  1429. queue_delayed_work(lio->txq_status_wq.wq,
  1430. &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
  1431. }
  1432. /**
  1433. * setup_tx_poll_fn - Sets up the txq poll check
  1434. * @netdev: network device
  1435. */
  1436. static inline int setup_tx_poll_fn(struct net_device *netdev)
  1437. {
  1438. struct lio *lio = GET_LIO(netdev);
  1439. struct octeon_device *oct = lio->oct_dev;
  1440. lio->txq_status_wq.wq = alloc_workqueue("txq-status",
  1441. WQ_MEM_RECLAIM | WQ_PERCPU, 0);
  1442. if (!lio->txq_status_wq.wq) {
  1443. dev_err(&oct->pci_dev->dev, "unable to create cavium txq status wq\n");
  1444. return -1;
  1445. }
  1446. INIT_DELAYED_WORK(&lio->txq_status_wq.wk.work,
  1447. octnet_poll_check_txq_status);
  1448. lio->txq_status_wq.wk.ctxptr = lio;
  1449. queue_delayed_work(lio->txq_status_wq.wq,
  1450. &lio->txq_status_wq.wk.work, msecs_to_jiffies(1));
  1451. return 0;
  1452. }
  1453. static inline void cleanup_tx_poll_fn(struct net_device *netdev)
  1454. {
  1455. struct lio *lio = GET_LIO(netdev);
  1456. if (lio->txq_status_wq.wq) {
  1457. cancel_delayed_work_sync(&lio->txq_status_wq.wk.work);
  1458. destroy_workqueue(lio->txq_status_wq.wq);
  1459. }
  1460. }
  1461. /**
  1462. * liquidio_open - Net device open for LiquidIO
  1463. * @netdev: network device
  1464. */
  1465. static int liquidio_open(struct net_device *netdev)
  1466. {
  1467. struct lio *lio = GET_LIO(netdev);
  1468. struct octeon_device *oct = lio->oct_dev;
  1469. struct octeon_device_priv *oct_priv = oct->priv;
  1470. struct napi_struct *napi, *n;
  1471. int ret = 0;
  1472. if (oct->props[lio->ifidx].napi_enabled == 0) {
  1473. tasklet_disable(&oct_priv->droq_tasklet);
  1474. list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
  1475. napi_enable(napi);
  1476. oct->props[lio->ifidx].napi_enabled = 1;
  1477. if (OCTEON_CN23XX_PF(oct))
  1478. oct->droq[0]->ops.poll_mode = 1;
  1479. }
  1480. if (oct->ptp_enable)
  1481. oct_ptp_open(netdev);
  1482. ifstate_set(lio, LIO_IFSTATE_RUNNING);
  1483. if (!OCTEON_CN23XX_PF(oct) || !oct->msix_on) {
  1484. ret = setup_tx_poll_fn(netdev);
  1485. if (ret)
  1486. goto err_poll;
  1487. }
  1488. netif_tx_start_all_queues(netdev);
  1489. /* Ready for link status updates */
  1490. lio->intf_open = 1;
  1491. netif_info(lio, ifup, lio->netdev, "Interface Open, ready for traffic\n");
  1492. /* tell Octeon to start forwarding packets to host */
  1493. ret = send_rx_ctrl_cmd(lio, 1);
  1494. if (ret)
  1495. goto err_rx_ctrl;
  1496. /* start periodical statistics fetch */
  1497. INIT_DELAYED_WORK(&lio->stats_wk.work, lio_fetch_stats);
  1498. lio->stats_wk.ctxptr = lio;
  1499. schedule_delayed_work(&lio->stats_wk.work, msecs_to_jiffies
  1500. (LIQUIDIO_NDEV_STATS_POLL_TIME_MS));
  1501. dev_info(&oct->pci_dev->dev, "%s interface is opened\n",
  1502. netdev->name);
  1503. return 0;
  1504. err_rx_ctrl:
  1505. if (!OCTEON_CN23XX_PF(oct) || !oct->msix_on)
  1506. cleanup_tx_poll_fn(netdev);
  1507. err_poll:
  1508. if (lio->ptp_clock) {
  1509. ptp_clock_unregister(lio->ptp_clock);
  1510. lio->ptp_clock = NULL;
  1511. }
  1512. if (oct->props[lio->ifidx].napi_enabled == 1) {
  1513. list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
  1514. napi_disable(napi);
  1515. oct->props[lio->ifidx].napi_enabled = 0;
  1516. if (OCTEON_CN23XX_PF(oct))
  1517. oct->droq[0]->ops.poll_mode = 0;
  1518. }
  1519. return ret;
  1520. }
  1521. /**
  1522. * liquidio_stop - Net device stop for LiquidIO
  1523. * @netdev: network device
  1524. */
  1525. static int liquidio_stop(struct net_device *netdev)
  1526. {
  1527. struct lio *lio = GET_LIO(netdev);
  1528. struct octeon_device *oct = lio->oct_dev;
  1529. struct octeon_device_priv *oct_priv = oct->priv;
  1530. struct napi_struct *napi, *n;
  1531. int ret = 0;
  1532. ifstate_reset(lio, LIO_IFSTATE_RUNNING);
  1533. /* Stop any link updates */
  1534. lio->intf_open = 0;
  1535. stop_txqs(netdev);
  1536. /* Inform that netif carrier is down */
  1537. netif_carrier_off(netdev);
  1538. netif_tx_disable(netdev);
  1539. lio->linfo.link.s.link_up = 0;
  1540. lio->link_changes++;
  1541. /* Tell Octeon that nic interface is down. */
  1542. ret = send_rx_ctrl_cmd(lio, 0);
  1543. if (ret)
  1544. return ret;
  1545. if (OCTEON_CN23XX_PF(oct)) {
  1546. if (!oct->msix_on)
  1547. cleanup_tx_poll_fn(netdev);
  1548. } else {
  1549. cleanup_tx_poll_fn(netdev);
  1550. }
  1551. cancel_delayed_work_sync(&lio->stats_wk.work);
  1552. if (lio->ptp_clock) {
  1553. ptp_clock_unregister(lio->ptp_clock);
  1554. lio->ptp_clock = NULL;
  1555. }
  1556. /* Wait for any pending Rx descriptors */
  1557. if (lio_wait_for_clean_oq(oct))
  1558. netif_info(lio, rx_err, lio->netdev,
  1559. "Proceeding with stop interface after partial RX desc processing\n");
  1560. if (oct->props[lio->ifidx].napi_enabled == 1) {
  1561. list_for_each_entry_safe(napi, n, &netdev->napi_list, dev_list)
  1562. napi_disable(napi);
  1563. oct->props[lio->ifidx].napi_enabled = 0;
  1564. if (OCTEON_CN23XX_PF(oct))
  1565. oct->droq[0]->ops.poll_mode = 0;
  1566. tasklet_enable(&oct_priv->droq_tasklet);
  1567. }
  1568. dev_info(&oct->pci_dev->dev, "%s interface is stopped\n", netdev->name);
  1569. return ret;
  1570. }
  1571. /**
  1572. * get_new_flags - Converts a mask based on net device flags
  1573. * @netdev: network device
  1574. *
  1575. * This routine generates a octnet_ifflags mask from the net device flags
  1576. * received from the OS.
  1577. */
  1578. static inline enum octnet_ifflags get_new_flags(struct net_device *netdev)
  1579. {
  1580. enum octnet_ifflags f = OCTNET_IFFLAG_UNICAST;
  1581. if (netdev->flags & IFF_PROMISC)
  1582. f |= OCTNET_IFFLAG_PROMISC;
  1583. if (netdev->flags & IFF_ALLMULTI)
  1584. f |= OCTNET_IFFLAG_ALLMULTI;
  1585. if (netdev->flags & IFF_MULTICAST) {
  1586. f |= OCTNET_IFFLAG_MULTICAST;
  1587. /* Accept all multicast addresses if there are more than we
  1588. * can handle
  1589. */
  1590. if (netdev_mc_count(netdev) > MAX_OCTEON_MULTICAST_ADDR)
  1591. f |= OCTNET_IFFLAG_ALLMULTI;
  1592. }
  1593. if (netdev->flags & IFF_BROADCAST)
  1594. f |= OCTNET_IFFLAG_BROADCAST;
  1595. return f;
  1596. }
  1597. /**
  1598. * liquidio_set_mcast_list - Net device set_multicast_list
  1599. * @netdev: network device
  1600. */
  1601. static void liquidio_set_mcast_list(struct net_device *netdev)
  1602. {
  1603. struct lio *lio = GET_LIO(netdev);
  1604. struct octeon_device *oct = lio->oct_dev;
  1605. struct octnic_ctrl_pkt nctrl;
  1606. struct netdev_hw_addr *ha;
  1607. u64 *mc;
  1608. int ret;
  1609. int mc_count = min(netdev_mc_count(netdev), MAX_OCTEON_MULTICAST_ADDR);
  1610. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  1611. /* Create a ctrl pkt command to be sent to core app. */
  1612. nctrl.ncmd.u64 = 0;
  1613. nctrl.ncmd.s.cmd = OCTNET_CMD_SET_MULTI_LIST;
  1614. nctrl.ncmd.s.param1 = get_new_flags(netdev);
  1615. nctrl.ncmd.s.param2 = mc_count;
  1616. nctrl.ncmd.s.more = mc_count;
  1617. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  1618. nctrl.netpndev = (u64)netdev;
  1619. nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
  1620. /* copy all the addresses into the udd */
  1621. mc = &nctrl.udd[0];
  1622. netdev_for_each_mc_addr(ha, netdev) {
  1623. *mc = 0;
  1624. memcpy(((u8 *)mc) + 2, ha->addr, ETH_ALEN);
  1625. /* no need to swap bytes */
  1626. if (++mc > &nctrl.udd[mc_count])
  1627. break;
  1628. }
  1629. /* Apparently, any activity in this call from the kernel has to
  1630. * be atomic. So we won't wait for response.
  1631. */
  1632. ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
  1633. if (ret) {
  1634. dev_err(&oct->pci_dev->dev, "DEVFLAGS change failed in core (ret: 0x%x)\n",
  1635. ret);
  1636. }
  1637. }
  1638. /**
  1639. * liquidio_set_mac - Net device set_mac_address
  1640. * @netdev: network device
  1641. * @p: pointer to sockaddr
  1642. */
  1643. static int liquidio_set_mac(struct net_device *netdev, void *p)
  1644. {
  1645. int ret = 0;
  1646. struct lio *lio = GET_LIO(netdev);
  1647. struct octeon_device *oct = lio->oct_dev;
  1648. struct sockaddr *addr = (struct sockaddr *)p;
  1649. struct octnic_ctrl_pkt nctrl;
  1650. if (!is_valid_ether_addr(addr->sa_data))
  1651. return -EADDRNOTAVAIL;
  1652. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  1653. nctrl.ncmd.u64 = 0;
  1654. nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
  1655. nctrl.ncmd.s.param1 = 0;
  1656. nctrl.ncmd.s.more = 1;
  1657. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  1658. nctrl.netpndev = (u64)netdev;
  1659. nctrl.udd[0] = 0;
  1660. /* The MAC Address is presented in network byte order. */
  1661. memcpy((u8 *)&nctrl.udd[0] + 2, addr->sa_data, ETH_ALEN);
  1662. ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
  1663. if (ret < 0) {
  1664. dev_err(&oct->pci_dev->dev, "MAC Address change failed\n");
  1665. return -ENOMEM;
  1666. }
  1667. if (nctrl.sc_status) {
  1668. dev_err(&oct->pci_dev->dev,
  1669. "%s: MAC Address change failed. sc return=%x\n",
  1670. __func__, nctrl.sc_status);
  1671. return -EIO;
  1672. }
  1673. eth_hw_addr_set(netdev, addr->sa_data);
  1674. memcpy(((u8 *)&lio->linfo.hw_addr) + 2, addr->sa_data, ETH_ALEN);
  1675. return 0;
  1676. }
  1677. static void
  1678. liquidio_get_stats64(struct net_device *netdev,
  1679. struct rtnl_link_stats64 *lstats)
  1680. {
  1681. struct lio *lio = GET_LIO(netdev);
  1682. struct octeon_device *oct;
  1683. u64 pkts = 0, drop = 0, bytes = 0;
  1684. struct oct_droq_stats *oq_stats;
  1685. struct oct_iq_stats *iq_stats;
  1686. int i, iq_no, oq_no;
  1687. oct = lio->oct_dev;
  1688. if (ifstate_check(lio, LIO_IFSTATE_RESETTING))
  1689. return;
  1690. for (i = 0; i < oct->num_iqs; i++) {
  1691. iq_no = lio->linfo.txpciq[i].s.q_no;
  1692. iq_stats = &oct->instr_queue[iq_no]->stats;
  1693. pkts += iq_stats->tx_done;
  1694. drop += iq_stats->tx_dropped;
  1695. bytes += iq_stats->tx_tot_bytes;
  1696. }
  1697. lstats->tx_packets = pkts;
  1698. lstats->tx_bytes = bytes;
  1699. lstats->tx_dropped = drop;
  1700. pkts = 0;
  1701. drop = 0;
  1702. bytes = 0;
  1703. for (i = 0; i < oct->num_oqs; i++) {
  1704. oq_no = lio->linfo.rxpciq[i].s.q_no;
  1705. oq_stats = &oct->droq[oq_no]->stats;
  1706. pkts += oq_stats->rx_pkts_received;
  1707. drop += (oq_stats->rx_dropped +
  1708. oq_stats->dropped_nodispatch +
  1709. oq_stats->dropped_toomany +
  1710. oq_stats->dropped_nomem);
  1711. bytes += oq_stats->rx_bytes_received;
  1712. }
  1713. lstats->rx_bytes = bytes;
  1714. lstats->rx_packets = pkts;
  1715. lstats->rx_dropped = drop;
  1716. lstats->multicast = oct->link_stats.fromwire.fw_total_mcast;
  1717. lstats->collisions = oct->link_stats.fromhost.total_collisions;
  1718. /* detailed rx_errors: */
  1719. lstats->rx_length_errors = oct->link_stats.fromwire.l2_err;
  1720. /* recved pkt with crc error */
  1721. lstats->rx_crc_errors = oct->link_stats.fromwire.fcs_err;
  1722. /* recv'd frame alignment error */
  1723. lstats->rx_frame_errors = oct->link_stats.fromwire.frame_err;
  1724. /* recv'r fifo overrun */
  1725. lstats->rx_fifo_errors = oct->link_stats.fromwire.fifo_err;
  1726. lstats->rx_errors = lstats->rx_length_errors + lstats->rx_crc_errors +
  1727. lstats->rx_frame_errors + lstats->rx_fifo_errors;
  1728. /* detailed tx_errors */
  1729. lstats->tx_aborted_errors = oct->link_stats.fromhost.fw_err_pko;
  1730. lstats->tx_carrier_errors = oct->link_stats.fromhost.fw_err_link;
  1731. lstats->tx_fifo_errors = oct->link_stats.fromhost.fifo_err;
  1732. lstats->tx_errors = lstats->tx_aborted_errors +
  1733. lstats->tx_carrier_errors +
  1734. lstats->tx_fifo_errors;
  1735. }
  1736. static int liquidio_hwtstamp_set(struct net_device *netdev,
  1737. struct kernel_hwtstamp_config *conf,
  1738. struct netlink_ext_ack *extack)
  1739. {
  1740. struct lio *lio = GET_LIO(netdev);
  1741. if (!lio->oct_dev->ptp_enable)
  1742. return -EOPNOTSUPP;
  1743. switch (conf->tx_type) {
  1744. case HWTSTAMP_TX_ON:
  1745. case HWTSTAMP_TX_OFF:
  1746. break;
  1747. default:
  1748. return -ERANGE;
  1749. }
  1750. switch (conf->rx_filter) {
  1751. case HWTSTAMP_FILTER_NONE:
  1752. break;
  1753. case HWTSTAMP_FILTER_ALL:
  1754. case HWTSTAMP_FILTER_SOME:
  1755. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  1756. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  1757. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  1758. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  1759. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  1760. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  1761. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  1762. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  1763. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  1764. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  1765. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  1766. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  1767. case HWTSTAMP_FILTER_NTP_ALL:
  1768. conf->rx_filter = HWTSTAMP_FILTER_ALL;
  1769. break;
  1770. default:
  1771. return -ERANGE;
  1772. }
  1773. if (conf->rx_filter == HWTSTAMP_FILTER_ALL)
  1774. ifstate_set(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
  1775. else
  1776. ifstate_reset(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED);
  1777. return 0;
  1778. }
  1779. static int liquidio_hwtstamp_get(struct net_device *netdev,
  1780. struct kernel_hwtstamp_config *conf)
  1781. {
  1782. struct lio *lio = GET_LIO(netdev);
  1783. /* TX timestamping is technically always on */
  1784. conf->tx_type = HWTSTAMP_TX_ON;
  1785. conf->rx_filter = ifstate_check(lio, LIO_IFSTATE_RX_TIMESTAMP_ENABLED) ?
  1786. HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
  1787. return 0;
  1788. }
  1789. /**
  1790. * handle_timestamp - handle a Tx timestamp response
  1791. * @oct: octeon device
  1792. * @status: response status
  1793. * @buf: pointer to skb
  1794. */
  1795. static void handle_timestamp(struct octeon_device *oct,
  1796. u32 status,
  1797. void *buf)
  1798. {
  1799. struct octnet_buf_free_info *finfo;
  1800. struct octeon_soft_command *sc;
  1801. struct oct_timestamp_resp *resp;
  1802. struct lio *lio;
  1803. struct sk_buff *skb = (struct sk_buff *)buf;
  1804. finfo = (struct octnet_buf_free_info *)skb->cb;
  1805. lio = finfo->lio;
  1806. sc = finfo->sc;
  1807. oct = lio->oct_dev;
  1808. resp = (struct oct_timestamp_resp *)sc->virtrptr;
  1809. if (status != OCTEON_REQUEST_DONE) {
  1810. dev_err(&oct->pci_dev->dev, "Tx timestamp instruction failed. Status: %llx\n",
  1811. CVM_CAST64(status));
  1812. resp->timestamp = 0;
  1813. }
  1814. octeon_swap_8B_data(&resp->timestamp, 1);
  1815. if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) != 0)) {
  1816. struct skb_shared_hwtstamps ts;
  1817. u64 ns = resp->timestamp;
  1818. netif_info(lio, tx_done, lio->netdev,
  1819. "Got resulting SKBTX_HW_TSTAMP skb=%p ns=%016llu\n",
  1820. skb, (unsigned long long)ns);
  1821. ts.hwtstamp = ns_to_ktime(ns + lio->ptp_adjust);
  1822. skb_tstamp_tx(skb, &ts);
  1823. }
  1824. octeon_free_soft_command(oct, sc);
  1825. tx_buffer_free(skb);
  1826. }
  1827. /**
  1828. * send_nic_timestamp_pkt - Send a data packet that will be timestamped
  1829. * @oct: octeon device
  1830. * @ndata: pointer to network data
  1831. * @finfo: pointer to private network data
  1832. * @xmit_more: more is coming
  1833. */
  1834. static inline int send_nic_timestamp_pkt(struct octeon_device *oct,
  1835. struct octnic_data_pkt *ndata,
  1836. struct octnet_buf_free_info *finfo,
  1837. int xmit_more)
  1838. {
  1839. int retval;
  1840. struct octeon_soft_command *sc;
  1841. struct lio *lio;
  1842. int ring_doorbell;
  1843. u32 len;
  1844. lio = finfo->lio;
  1845. sc = octeon_alloc_soft_command_resp(oct, &ndata->cmd,
  1846. sizeof(struct oct_timestamp_resp));
  1847. finfo->sc = sc;
  1848. if (!sc) {
  1849. dev_err(&oct->pci_dev->dev, "No memory for timestamped data packet\n");
  1850. return IQ_SEND_FAILED;
  1851. }
  1852. if (ndata->reqtype == REQTYPE_NORESP_NET)
  1853. ndata->reqtype = REQTYPE_RESP_NET;
  1854. else if (ndata->reqtype == REQTYPE_NORESP_NET_SG)
  1855. ndata->reqtype = REQTYPE_RESP_NET_SG;
  1856. sc->callback = handle_timestamp;
  1857. sc->callback_arg = finfo->skb;
  1858. sc->iq_no = ndata->q_no;
  1859. if (OCTEON_CN23XX_PF(oct))
  1860. len = (u32)((struct octeon_instr_ih3 *)
  1861. (&sc->cmd.cmd3.ih3))->dlengsz;
  1862. else
  1863. len = (u32)((struct octeon_instr_ih2 *)
  1864. (&sc->cmd.cmd2.ih2))->dlengsz;
  1865. ring_doorbell = !xmit_more;
  1866. retval = octeon_send_command(oct, sc->iq_no, ring_doorbell, &sc->cmd,
  1867. sc, len, ndata->reqtype);
  1868. if (retval == IQ_SEND_FAILED) {
  1869. dev_err(&oct->pci_dev->dev, "timestamp data packet failed status: %x\n",
  1870. retval);
  1871. octeon_free_soft_command(oct, sc);
  1872. } else {
  1873. netif_info(lio, tx_queued, lio->netdev, "Queued timestamp packet\n");
  1874. }
  1875. return retval;
  1876. }
  1877. /**
  1878. * liquidio_xmit - Transmit networks packets to the Octeon interface
  1879. * @skb: skbuff struct to be passed to network layer.
  1880. * @netdev: pointer to network device
  1881. *
  1882. * Return: whether the packet was transmitted to the device okay or not
  1883. * (NETDEV_TX_OK or NETDEV_TX_BUSY)
  1884. */
  1885. static netdev_tx_t liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
  1886. {
  1887. struct lio *lio;
  1888. struct octnet_buf_free_info *finfo;
  1889. union octnic_cmd_setup cmdsetup;
  1890. struct octnic_data_pkt ndata;
  1891. struct octeon_device *oct;
  1892. struct oct_iq_stats *stats;
  1893. struct octeon_instr_irh *irh;
  1894. union tx_info *tx_info;
  1895. int status = 0;
  1896. int q_idx = 0, iq_no = 0;
  1897. int j, xmit_more = 0;
  1898. u64 dptr = 0;
  1899. u32 tag = 0;
  1900. lio = GET_LIO(netdev);
  1901. oct = lio->oct_dev;
  1902. q_idx = skb_iq(oct, skb);
  1903. tag = q_idx;
  1904. iq_no = lio->linfo.txpciq[q_idx].s.q_no;
  1905. stats = &oct->instr_queue[iq_no]->stats;
  1906. /* Check for all conditions in which the current packet cannot be
  1907. * transmitted.
  1908. */
  1909. if (!(atomic_read(&lio->ifstate) & LIO_IFSTATE_RUNNING) ||
  1910. (!lio->linfo.link.s.link_up) ||
  1911. (skb->len <= 0)) {
  1912. netif_info(lio, tx_err, lio->netdev,
  1913. "Transmit failed link_status : %d\n",
  1914. lio->linfo.link.s.link_up);
  1915. goto lio_xmit_failed;
  1916. }
  1917. /* Use space in skb->cb to store info used to unmap and
  1918. * free the buffers.
  1919. */
  1920. finfo = (struct octnet_buf_free_info *)skb->cb;
  1921. finfo->lio = lio;
  1922. finfo->skb = skb;
  1923. finfo->sc = NULL;
  1924. /* Prepare the attributes for the data to be passed to OSI. */
  1925. memset(&ndata, 0, sizeof(struct octnic_data_pkt));
  1926. ndata.buf = (void *)finfo;
  1927. ndata.q_no = iq_no;
  1928. if (octnet_iq_is_full(oct, ndata.q_no)) {
  1929. /* defer sending if queue is full */
  1930. netif_info(lio, tx_err, lio->netdev, "Transmit failed iq:%d full\n",
  1931. ndata.q_no);
  1932. stats->tx_iq_busy++;
  1933. return NETDEV_TX_BUSY;
  1934. }
  1935. /* pr_info(" XMIT - valid Qs: %d, 1st Q no: %d, cpu: %d, q_no:%d\n",
  1936. * lio->linfo.num_txpciq, lio->txq, cpu, ndata.q_no);
  1937. */
  1938. ndata.datasize = skb->len;
  1939. cmdsetup.u64 = 0;
  1940. cmdsetup.s.iq_no = iq_no;
  1941. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1942. if (skb->encapsulation) {
  1943. cmdsetup.s.tnl_csum = 1;
  1944. stats->tx_vxlan++;
  1945. } else {
  1946. cmdsetup.s.transport_csum = 1;
  1947. }
  1948. }
  1949. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
  1950. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  1951. cmdsetup.s.timestamp = 1;
  1952. }
  1953. if (skb_shinfo(skb)->nr_frags == 0) {
  1954. cmdsetup.s.u.datasize = skb->len;
  1955. octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
  1956. /* Offload checksum calculation for TCP/UDP packets */
  1957. dptr = dma_map_single(&oct->pci_dev->dev,
  1958. skb->data,
  1959. skb->len,
  1960. DMA_TO_DEVICE);
  1961. if (dma_mapping_error(&oct->pci_dev->dev, dptr)) {
  1962. dev_err(&oct->pci_dev->dev, "%s DMA mapping error 1\n",
  1963. __func__);
  1964. stats->tx_dmamap_fail++;
  1965. return NETDEV_TX_BUSY;
  1966. }
  1967. if (OCTEON_CN23XX_PF(oct))
  1968. ndata.cmd.cmd3.dptr = dptr;
  1969. else
  1970. ndata.cmd.cmd2.dptr = dptr;
  1971. finfo->dptr = dptr;
  1972. ndata.reqtype = REQTYPE_NORESP_NET;
  1973. } else {
  1974. int i, frags;
  1975. skb_frag_t *frag;
  1976. struct octnic_gather *g;
  1977. spin_lock(&lio->glist_lock[q_idx]);
  1978. g = (struct octnic_gather *)
  1979. lio_list_delete_head(&lio->glist[q_idx]);
  1980. spin_unlock(&lio->glist_lock[q_idx]);
  1981. if (!g) {
  1982. netif_info(lio, tx_err, lio->netdev,
  1983. "Transmit scatter gather: glist null!\n");
  1984. goto lio_xmit_failed;
  1985. }
  1986. cmdsetup.s.gather = 1;
  1987. cmdsetup.s.u.gatherptrs = (skb_shinfo(skb)->nr_frags + 1);
  1988. octnet_prepare_pci_cmd(oct, &ndata.cmd, &cmdsetup, tag);
  1989. memset(g->sg, 0, g->sg_size);
  1990. g->sg[0].ptr[0] = dma_map_single(&oct->pci_dev->dev,
  1991. skb->data,
  1992. (skb->len - skb->data_len),
  1993. DMA_TO_DEVICE);
  1994. if (dma_mapping_error(&oct->pci_dev->dev, g->sg[0].ptr[0])) {
  1995. dev_err(&oct->pci_dev->dev, "%s DMA mapping error 2\n",
  1996. __func__);
  1997. stats->tx_dmamap_fail++;
  1998. return NETDEV_TX_BUSY;
  1999. }
  2000. add_sg_size(&g->sg[0], (skb->len - skb->data_len), 0);
  2001. frags = skb_shinfo(skb)->nr_frags;
  2002. i = 1;
  2003. while (frags--) {
  2004. frag = &skb_shinfo(skb)->frags[i - 1];
  2005. g->sg[(i >> 2)].ptr[(i & 3)] =
  2006. skb_frag_dma_map(&oct->pci_dev->dev,
  2007. frag, 0, skb_frag_size(frag),
  2008. DMA_TO_DEVICE);
  2009. if (dma_mapping_error(&oct->pci_dev->dev,
  2010. g->sg[i >> 2].ptr[i & 3])) {
  2011. dma_unmap_single(&oct->pci_dev->dev,
  2012. g->sg[0].ptr[0],
  2013. skb->len - skb->data_len,
  2014. DMA_TO_DEVICE);
  2015. for (j = 1; j < i; j++) {
  2016. frag = &skb_shinfo(skb)->frags[j - 1];
  2017. dma_unmap_page(&oct->pci_dev->dev,
  2018. g->sg[j >> 2].ptr[j & 3],
  2019. skb_frag_size(frag),
  2020. DMA_TO_DEVICE);
  2021. }
  2022. dev_err(&oct->pci_dev->dev, "%s DMA mapping error 3\n",
  2023. __func__);
  2024. return NETDEV_TX_BUSY;
  2025. }
  2026. add_sg_size(&g->sg[(i >> 2)], skb_frag_size(frag),
  2027. (i & 3));
  2028. i++;
  2029. }
  2030. dptr = g->sg_dma_ptr;
  2031. if (OCTEON_CN23XX_PF(oct))
  2032. ndata.cmd.cmd3.dptr = dptr;
  2033. else
  2034. ndata.cmd.cmd2.dptr = dptr;
  2035. finfo->dptr = dptr;
  2036. finfo->g = g;
  2037. ndata.reqtype = REQTYPE_NORESP_NET_SG;
  2038. }
  2039. if (OCTEON_CN23XX_PF(oct)) {
  2040. irh = (struct octeon_instr_irh *)&ndata.cmd.cmd3.irh;
  2041. tx_info = (union tx_info *)&ndata.cmd.cmd3.ossp[0];
  2042. } else {
  2043. irh = (struct octeon_instr_irh *)&ndata.cmd.cmd2.irh;
  2044. tx_info = (union tx_info *)&ndata.cmd.cmd2.ossp[0];
  2045. }
  2046. if (skb_shinfo(skb)->gso_size) {
  2047. tx_info->s.gso_size = skb_shinfo(skb)->gso_size;
  2048. tx_info->s.gso_segs = skb_shinfo(skb)->gso_segs;
  2049. stats->tx_gso++;
  2050. }
  2051. /* HW insert VLAN tag */
  2052. if (skb_vlan_tag_present(skb)) {
  2053. irh->priority = skb_vlan_tag_get(skb) >> 13;
  2054. irh->vlan = skb_vlan_tag_get(skb) & 0xfff;
  2055. }
  2056. xmit_more = netdev_xmit_more();
  2057. if (unlikely(cmdsetup.s.timestamp))
  2058. status = send_nic_timestamp_pkt(oct, &ndata, finfo, xmit_more);
  2059. else
  2060. status = octnet_send_nic_data_pkt(oct, &ndata, xmit_more);
  2061. if (status == IQ_SEND_FAILED)
  2062. goto lio_xmit_failed;
  2063. netif_info(lio, tx_queued, lio->netdev, "Transmit queued successfully\n");
  2064. if (status == IQ_SEND_STOP)
  2065. netif_stop_subqueue(netdev, q_idx);
  2066. netif_trans_update(netdev);
  2067. if (tx_info->s.gso_segs)
  2068. stats->tx_done += tx_info->s.gso_segs;
  2069. else
  2070. stats->tx_done++;
  2071. stats->tx_tot_bytes += ndata.datasize;
  2072. return NETDEV_TX_OK;
  2073. lio_xmit_failed:
  2074. stats->tx_dropped++;
  2075. netif_info(lio, tx_err, lio->netdev, "IQ%d Transmit dropped:%llu\n",
  2076. iq_no, stats->tx_dropped);
  2077. if (dptr)
  2078. dma_unmap_single(&oct->pci_dev->dev, dptr,
  2079. ndata.datasize, DMA_TO_DEVICE);
  2080. octeon_ring_doorbell_locked(oct, iq_no);
  2081. tx_buffer_free(skb);
  2082. return NETDEV_TX_OK;
  2083. }
  2084. /**
  2085. * liquidio_tx_timeout - Network device Tx timeout
  2086. * @netdev: pointer to network device
  2087. * @txqueue: index of the hung transmit queue
  2088. */
  2089. static void liquidio_tx_timeout(struct net_device *netdev, unsigned int txqueue)
  2090. {
  2091. struct lio *lio;
  2092. lio = GET_LIO(netdev);
  2093. netif_info(lio, tx_err, lio->netdev,
  2094. "Transmit timeout tx_dropped:%ld, waking up queues now!!\n",
  2095. netdev->stats.tx_dropped);
  2096. netif_trans_update(netdev);
  2097. wake_txqs(netdev);
  2098. }
  2099. static int liquidio_vlan_rx_add_vid(struct net_device *netdev,
  2100. __be16 proto __attribute__((unused)),
  2101. u16 vid)
  2102. {
  2103. struct lio *lio = GET_LIO(netdev);
  2104. struct octeon_device *oct = lio->oct_dev;
  2105. struct octnic_ctrl_pkt nctrl;
  2106. int ret = 0;
  2107. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  2108. nctrl.ncmd.u64 = 0;
  2109. nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
  2110. nctrl.ncmd.s.param1 = vid;
  2111. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  2112. nctrl.netpndev = (u64)netdev;
  2113. nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
  2114. ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
  2115. if (ret) {
  2116. dev_err(&oct->pci_dev->dev, "Add VLAN filter failed in core (ret: 0x%x)\n",
  2117. ret);
  2118. if (ret > 0)
  2119. ret = -EIO;
  2120. }
  2121. return ret;
  2122. }
  2123. static int liquidio_vlan_rx_kill_vid(struct net_device *netdev,
  2124. __be16 proto __attribute__((unused)),
  2125. u16 vid)
  2126. {
  2127. struct lio *lio = GET_LIO(netdev);
  2128. struct octeon_device *oct = lio->oct_dev;
  2129. struct octnic_ctrl_pkt nctrl;
  2130. int ret = 0;
  2131. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  2132. nctrl.ncmd.u64 = 0;
  2133. nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
  2134. nctrl.ncmd.s.param1 = vid;
  2135. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  2136. nctrl.netpndev = (u64)netdev;
  2137. nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
  2138. ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
  2139. if (ret) {
  2140. dev_err(&oct->pci_dev->dev, "Del VLAN filter failed in core (ret: 0x%x)\n",
  2141. ret);
  2142. if (ret > 0)
  2143. ret = -EIO;
  2144. }
  2145. return ret;
  2146. }
  2147. /**
  2148. * liquidio_set_rxcsum_command - Sending command to enable/disable RX checksum offload
  2149. * @netdev: pointer to network device
  2150. * @command: OCTNET_CMD_TNL_RX_CSUM_CTL
  2151. * @rx_cmd: OCTNET_CMD_RXCSUM_ENABLE/OCTNET_CMD_RXCSUM_DISABLE
  2152. * Returns: SUCCESS or FAILURE
  2153. */
  2154. static int liquidio_set_rxcsum_command(struct net_device *netdev, int command,
  2155. u8 rx_cmd)
  2156. {
  2157. struct lio *lio = GET_LIO(netdev);
  2158. struct octeon_device *oct = lio->oct_dev;
  2159. struct octnic_ctrl_pkt nctrl;
  2160. int ret = 0;
  2161. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  2162. nctrl.ncmd.u64 = 0;
  2163. nctrl.ncmd.s.cmd = command;
  2164. nctrl.ncmd.s.param1 = rx_cmd;
  2165. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  2166. nctrl.netpndev = (u64)netdev;
  2167. nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
  2168. ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
  2169. if (ret) {
  2170. dev_err(&oct->pci_dev->dev,
  2171. "DEVFLAGS RXCSUM change failed in core(ret:0x%x)\n",
  2172. ret);
  2173. if (ret > 0)
  2174. ret = -EIO;
  2175. }
  2176. return ret;
  2177. }
  2178. /**
  2179. * liquidio_vxlan_port_command - Sending command to add/delete VxLAN UDP port to firmware
  2180. * @netdev: pointer to network device
  2181. * @command: OCTNET_CMD_VXLAN_PORT_CONFIG
  2182. * @vxlan_port: VxLAN port to be added or deleted
  2183. * @vxlan_cmd_bit: OCTNET_CMD_VXLAN_PORT_ADD,
  2184. * OCTNET_CMD_VXLAN_PORT_DEL
  2185. * Return: SUCCESS or FAILURE
  2186. */
  2187. static int liquidio_vxlan_port_command(struct net_device *netdev, int command,
  2188. u16 vxlan_port, u8 vxlan_cmd_bit)
  2189. {
  2190. struct lio *lio = GET_LIO(netdev);
  2191. struct octeon_device *oct = lio->oct_dev;
  2192. struct octnic_ctrl_pkt nctrl;
  2193. int ret = 0;
  2194. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  2195. nctrl.ncmd.u64 = 0;
  2196. nctrl.ncmd.s.cmd = command;
  2197. nctrl.ncmd.s.more = vxlan_cmd_bit;
  2198. nctrl.ncmd.s.param1 = vxlan_port;
  2199. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  2200. nctrl.netpndev = (u64)netdev;
  2201. nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
  2202. ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
  2203. if (ret) {
  2204. dev_err(&oct->pci_dev->dev,
  2205. "VxLAN port add/delete failed in core (ret:0x%x)\n",
  2206. ret);
  2207. if (ret > 0)
  2208. ret = -EIO;
  2209. }
  2210. return ret;
  2211. }
  2212. static int liquidio_udp_tunnel_set_port(struct net_device *netdev,
  2213. unsigned int table, unsigned int entry,
  2214. struct udp_tunnel_info *ti)
  2215. {
  2216. return liquidio_vxlan_port_command(netdev,
  2217. OCTNET_CMD_VXLAN_PORT_CONFIG,
  2218. htons(ti->port),
  2219. OCTNET_CMD_VXLAN_PORT_ADD);
  2220. }
  2221. static int liquidio_udp_tunnel_unset_port(struct net_device *netdev,
  2222. unsigned int table,
  2223. unsigned int entry,
  2224. struct udp_tunnel_info *ti)
  2225. {
  2226. return liquidio_vxlan_port_command(netdev,
  2227. OCTNET_CMD_VXLAN_PORT_CONFIG,
  2228. htons(ti->port),
  2229. OCTNET_CMD_VXLAN_PORT_DEL);
  2230. }
  2231. static const struct udp_tunnel_nic_info liquidio_udp_tunnels = {
  2232. .set_port = liquidio_udp_tunnel_set_port,
  2233. .unset_port = liquidio_udp_tunnel_unset_port,
  2234. .tables = {
  2235. { .n_entries = 1024, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
  2236. },
  2237. };
  2238. /**
  2239. * liquidio_fix_features - Net device fix features
  2240. * @netdev: pointer to network device
  2241. * @request: features requested
  2242. * Return: updated features list
  2243. */
  2244. static netdev_features_t liquidio_fix_features(struct net_device *netdev,
  2245. netdev_features_t request)
  2246. {
  2247. struct lio *lio = netdev_priv(netdev);
  2248. if ((request & NETIF_F_RXCSUM) &&
  2249. !(lio->dev_capability & NETIF_F_RXCSUM))
  2250. request &= ~NETIF_F_RXCSUM;
  2251. if ((request & NETIF_F_HW_CSUM) &&
  2252. !(lio->dev_capability & NETIF_F_HW_CSUM))
  2253. request &= ~NETIF_F_HW_CSUM;
  2254. if ((request & NETIF_F_TSO) && !(lio->dev_capability & NETIF_F_TSO))
  2255. request &= ~NETIF_F_TSO;
  2256. if ((request & NETIF_F_TSO6) && !(lio->dev_capability & NETIF_F_TSO6))
  2257. request &= ~NETIF_F_TSO6;
  2258. if ((request & NETIF_F_LRO) && !(lio->dev_capability & NETIF_F_LRO))
  2259. request &= ~NETIF_F_LRO;
  2260. /*Disable LRO if RXCSUM is off */
  2261. if (!(request & NETIF_F_RXCSUM) && (netdev->features & NETIF_F_LRO) &&
  2262. (lio->dev_capability & NETIF_F_LRO))
  2263. request &= ~NETIF_F_LRO;
  2264. if ((request & NETIF_F_HW_VLAN_CTAG_FILTER) &&
  2265. !(lio->dev_capability & NETIF_F_HW_VLAN_CTAG_FILTER))
  2266. request &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
  2267. return request;
  2268. }
  2269. /**
  2270. * liquidio_set_features - Net device set features
  2271. * @netdev: pointer to network device
  2272. * @features: features to enable/disable
  2273. */
  2274. static int liquidio_set_features(struct net_device *netdev,
  2275. netdev_features_t features)
  2276. {
  2277. struct lio *lio = netdev_priv(netdev);
  2278. if ((features & NETIF_F_LRO) &&
  2279. (lio->dev_capability & NETIF_F_LRO) &&
  2280. !(netdev->features & NETIF_F_LRO))
  2281. liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
  2282. OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
  2283. else if (!(features & NETIF_F_LRO) &&
  2284. (lio->dev_capability & NETIF_F_LRO) &&
  2285. (netdev->features & NETIF_F_LRO))
  2286. liquidio_set_feature(netdev, OCTNET_CMD_LRO_DISABLE,
  2287. OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
  2288. /* Sending command to firmware to enable/disable RX checksum
  2289. * offload settings using ethtool
  2290. */
  2291. if (!(netdev->features & NETIF_F_RXCSUM) &&
  2292. (lio->enc_dev_capability & NETIF_F_RXCSUM) &&
  2293. (features & NETIF_F_RXCSUM))
  2294. liquidio_set_rxcsum_command(netdev,
  2295. OCTNET_CMD_TNL_RX_CSUM_CTL,
  2296. OCTNET_CMD_RXCSUM_ENABLE);
  2297. else if ((netdev->features & NETIF_F_RXCSUM) &&
  2298. (lio->enc_dev_capability & NETIF_F_RXCSUM) &&
  2299. !(features & NETIF_F_RXCSUM))
  2300. liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL,
  2301. OCTNET_CMD_RXCSUM_DISABLE);
  2302. if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) &&
  2303. (lio->dev_capability & NETIF_F_HW_VLAN_CTAG_FILTER) &&
  2304. !(netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
  2305. liquidio_set_feature(netdev, OCTNET_CMD_VLAN_FILTER_CTL,
  2306. OCTNET_CMD_VLAN_FILTER_ENABLE);
  2307. else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) &&
  2308. (lio->dev_capability & NETIF_F_HW_VLAN_CTAG_FILTER) &&
  2309. (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
  2310. liquidio_set_feature(netdev, OCTNET_CMD_VLAN_FILTER_CTL,
  2311. OCTNET_CMD_VLAN_FILTER_DISABLE);
  2312. return 0;
  2313. }
  2314. static int __liquidio_set_vf_mac(struct net_device *netdev, int vfidx,
  2315. u8 *mac, bool is_admin_assigned)
  2316. {
  2317. struct lio *lio = GET_LIO(netdev);
  2318. struct octeon_device *oct = lio->oct_dev;
  2319. struct octnic_ctrl_pkt nctrl;
  2320. int ret = 0;
  2321. if (!is_valid_ether_addr(mac))
  2322. return -EINVAL;
  2323. if (vfidx < 0 || vfidx >= oct->sriov_info.max_vfs)
  2324. return -EINVAL;
  2325. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  2326. nctrl.ncmd.u64 = 0;
  2327. nctrl.ncmd.s.cmd = OCTNET_CMD_CHANGE_MACADDR;
  2328. /* vfidx is 0 based, but vf_num (param1) is 1 based */
  2329. nctrl.ncmd.s.param1 = vfidx + 1;
  2330. nctrl.ncmd.s.more = 1;
  2331. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  2332. nctrl.netpndev = (u64)netdev;
  2333. if (is_admin_assigned) {
  2334. nctrl.ncmd.s.param2 = true;
  2335. nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
  2336. }
  2337. nctrl.udd[0] = 0;
  2338. /* The MAC Address is presented in network byte order. */
  2339. ether_addr_copy((u8 *)&nctrl.udd[0] + 2, mac);
  2340. oct->sriov_info.vf_macaddr[vfidx] = nctrl.udd[0];
  2341. ret = octnet_send_nic_ctrl_pkt(oct, &nctrl);
  2342. if (ret > 0)
  2343. ret = -EIO;
  2344. return ret;
  2345. }
  2346. static int liquidio_set_vf_mac(struct net_device *netdev, int vfidx, u8 *mac)
  2347. {
  2348. struct lio *lio = GET_LIO(netdev);
  2349. struct octeon_device *oct = lio->oct_dev;
  2350. int retval;
  2351. if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
  2352. return -EINVAL;
  2353. retval = __liquidio_set_vf_mac(netdev, vfidx, mac, true);
  2354. if (!retval)
  2355. cn23xx_tell_vf_its_macaddr_changed(oct, vfidx, mac);
  2356. return retval;
  2357. }
  2358. static int liquidio_set_vf_spoofchk(struct net_device *netdev, int vfidx,
  2359. bool enable)
  2360. {
  2361. struct lio *lio = GET_LIO(netdev);
  2362. struct octeon_device *oct = lio->oct_dev;
  2363. struct octnic_ctrl_pkt nctrl;
  2364. int retval;
  2365. if (!(oct->fw_info.app_cap_flags & LIQUIDIO_SPOOFCHK_CAP)) {
  2366. netif_info(lio, drv, lio->netdev,
  2367. "firmware does not support spoofchk\n");
  2368. return -EOPNOTSUPP;
  2369. }
  2370. if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced) {
  2371. netif_info(lio, drv, lio->netdev, "Invalid vfidx %d\n", vfidx);
  2372. return -EINVAL;
  2373. }
  2374. if (enable) {
  2375. if (oct->sriov_info.vf_spoofchk[vfidx])
  2376. return 0;
  2377. } else {
  2378. /* Clear */
  2379. if (!oct->sriov_info.vf_spoofchk[vfidx])
  2380. return 0;
  2381. }
  2382. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  2383. nctrl.ncmd.s.cmdgroup = OCTNET_CMD_GROUP1;
  2384. nctrl.ncmd.s.cmd = OCTNET_CMD_SET_VF_SPOOFCHK;
  2385. nctrl.ncmd.s.param1 =
  2386. vfidx + 1; /* vfidx is 0 based,
  2387. * but vf_num (param1) is 1 based
  2388. */
  2389. nctrl.ncmd.s.param2 = enable;
  2390. nctrl.ncmd.s.more = 0;
  2391. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  2392. nctrl.cb_fn = NULL;
  2393. retval = octnet_send_nic_ctrl_pkt(oct, &nctrl);
  2394. if (retval) {
  2395. netif_info(lio, drv, lio->netdev,
  2396. "Failed to set VF %d spoofchk %s\n", vfidx,
  2397. enable ? "on" : "off");
  2398. return -1;
  2399. }
  2400. oct->sriov_info.vf_spoofchk[vfidx] = enable;
  2401. netif_info(lio, drv, lio->netdev, "VF %u spoofchk is %s\n", vfidx,
  2402. enable ? "on" : "off");
  2403. return 0;
  2404. }
  2405. static int liquidio_set_vf_vlan(struct net_device *netdev, int vfidx,
  2406. u16 vlan, u8 qos, __be16 vlan_proto)
  2407. {
  2408. struct lio *lio = GET_LIO(netdev);
  2409. struct octeon_device *oct = lio->oct_dev;
  2410. struct octnic_ctrl_pkt nctrl;
  2411. u16 vlantci;
  2412. int ret = 0;
  2413. if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
  2414. return -EINVAL;
  2415. if (vlan_proto != htons(ETH_P_8021Q))
  2416. return -EPROTONOSUPPORT;
  2417. if (vlan >= VLAN_N_VID || qos > 7)
  2418. return -EINVAL;
  2419. if (vlan)
  2420. vlantci = vlan | (u16)qos << VLAN_PRIO_SHIFT;
  2421. else
  2422. vlantci = 0;
  2423. if (oct->sriov_info.vf_vlantci[vfidx] == vlantci)
  2424. return 0;
  2425. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  2426. if (vlan)
  2427. nctrl.ncmd.s.cmd = OCTNET_CMD_ADD_VLAN_FILTER;
  2428. else
  2429. nctrl.ncmd.s.cmd = OCTNET_CMD_DEL_VLAN_FILTER;
  2430. nctrl.ncmd.s.param1 = vlantci;
  2431. nctrl.ncmd.s.param2 =
  2432. vfidx + 1; /* vfidx is 0 based, but vf_num (param2) is 1 based */
  2433. nctrl.ncmd.s.more = 0;
  2434. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  2435. nctrl.cb_fn = NULL;
  2436. ret = octnet_send_nic_ctrl_pkt(oct, &nctrl);
  2437. if (ret) {
  2438. if (ret > 0)
  2439. ret = -EIO;
  2440. return ret;
  2441. }
  2442. oct->sriov_info.vf_vlantci[vfidx] = vlantci;
  2443. return ret;
  2444. }
  2445. static int liquidio_get_vf_config(struct net_device *netdev, int vfidx,
  2446. struct ifla_vf_info *ivi)
  2447. {
  2448. struct lio *lio = GET_LIO(netdev);
  2449. struct octeon_device *oct = lio->oct_dev;
  2450. u8 *macaddr;
  2451. if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
  2452. return -EINVAL;
  2453. memset(ivi, 0, sizeof(struct ifla_vf_info));
  2454. ivi->vf = vfidx;
  2455. macaddr = 2 + (u8 *)&oct->sriov_info.vf_macaddr[vfidx];
  2456. ether_addr_copy(&ivi->mac[0], macaddr);
  2457. ivi->vlan = oct->sriov_info.vf_vlantci[vfidx] & VLAN_VID_MASK;
  2458. ivi->qos = oct->sriov_info.vf_vlantci[vfidx] >> VLAN_PRIO_SHIFT;
  2459. if (oct->sriov_info.trusted_vf.active &&
  2460. oct->sriov_info.trusted_vf.id == vfidx)
  2461. ivi->trusted = true;
  2462. else
  2463. ivi->trusted = false;
  2464. ivi->linkstate = oct->sriov_info.vf_linkstate[vfidx];
  2465. ivi->spoofchk = oct->sriov_info.vf_spoofchk[vfidx];
  2466. ivi->max_tx_rate = lio->linfo.link.s.speed;
  2467. ivi->min_tx_rate = 0;
  2468. return 0;
  2469. }
  2470. static int liquidio_send_vf_trust_cmd(struct lio *lio, int vfidx, bool trusted)
  2471. {
  2472. struct octeon_device *oct = lio->oct_dev;
  2473. struct octeon_soft_command *sc;
  2474. int retval;
  2475. sc = octeon_alloc_soft_command(oct, 0, 16, 0);
  2476. if (!sc)
  2477. return -ENOMEM;
  2478. sc->iq_no = lio->linfo.txpciq[0].s.q_no;
  2479. /* vfidx is 0 based, but vf_num (param1) is 1 based */
  2480. octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
  2481. OPCODE_NIC_SET_TRUSTED_VF, 0, vfidx + 1,
  2482. trusted);
  2483. init_completion(&sc->complete);
  2484. sc->sc_status = OCTEON_REQUEST_PENDING;
  2485. retval = octeon_send_soft_command(oct, sc);
  2486. if (retval == IQ_SEND_FAILED) {
  2487. octeon_free_soft_command(oct, sc);
  2488. retval = -1;
  2489. } else {
  2490. /* Wait for response or timeout */
  2491. retval = wait_for_sc_completion_timeout(oct, sc, 0);
  2492. if (retval)
  2493. return (retval);
  2494. WRITE_ONCE(sc->caller_is_done, true);
  2495. }
  2496. return retval;
  2497. }
  2498. static int liquidio_set_vf_trust(struct net_device *netdev, int vfidx,
  2499. bool setting)
  2500. {
  2501. struct lio *lio = GET_LIO(netdev);
  2502. struct octeon_device *oct = lio->oct_dev;
  2503. if (strcmp(oct->fw_info.liquidio_firmware_version, "1.7.1") < 0) {
  2504. /* trusted vf is not supported by firmware older than 1.7.1 */
  2505. return -EOPNOTSUPP;
  2506. }
  2507. if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced) {
  2508. netif_info(lio, drv, lio->netdev, "Invalid vfidx %d\n", vfidx);
  2509. return -EINVAL;
  2510. }
  2511. if (setting) {
  2512. /* Set */
  2513. if (oct->sriov_info.trusted_vf.active &&
  2514. oct->sriov_info.trusted_vf.id == vfidx)
  2515. return 0;
  2516. if (oct->sriov_info.trusted_vf.active) {
  2517. netif_info(lio, drv, lio->netdev, "More than one trusted VF is not allowed\n");
  2518. return -EPERM;
  2519. }
  2520. } else {
  2521. /* Clear */
  2522. if (!oct->sriov_info.trusted_vf.active)
  2523. return 0;
  2524. }
  2525. if (!liquidio_send_vf_trust_cmd(lio, vfidx, setting)) {
  2526. if (setting) {
  2527. oct->sriov_info.trusted_vf.id = vfidx;
  2528. oct->sriov_info.trusted_vf.active = true;
  2529. } else {
  2530. oct->sriov_info.trusted_vf.active = false;
  2531. }
  2532. netif_info(lio, drv, lio->netdev, "VF %u is %strusted\n", vfidx,
  2533. setting ? "" : "not ");
  2534. } else {
  2535. netif_info(lio, drv, lio->netdev, "Failed to set VF trusted\n");
  2536. return -1;
  2537. }
  2538. return 0;
  2539. }
  2540. static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx,
  2541. int linkstate)
  2542. {
  2543. struct lio *lio = GET_LIO(netdev);
  2544. struct octeon_device *oct = lio->oct_dev;
  2545. struct octnic_ctrl_pkt nctrl;
  2546. int ret = 0;
  2547. if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
  2548. return -EINVAL;
  2549. if (oct->sriov_info.vf_linkstate[vfidx] == linkstate)
  2550. return 0;
  2551. memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
  2552. nctrl.ncmd.s.cmd = OCTNET_CMD_SET_VF_LINKSTATE;
  2553. nctrl.ncmd.s.param1 =
  2554. vfidx + 1; /* vfidx is 0 based, but vf_num (param1) is 1 based */
  2555. nctrl.ncmd.s.param2 = linkstate;
  2556. nctrl.ncmd.s.more = 0;
  2557. nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
  2558. nctrl.cb_fn = NULL;
  2559. ret = octnet_send_nic_ctrl_pkt(oct, &nctrl);
  2560. if (!ret)
  2561. oct->sriov_info.vf_linkstate[vfidx] = linkstate;
  2562. else if (ret > 0)
  2563. ret = -EIO;
  2564. return ret;
  2565. }
  2566. static int
  2567. liquidio_eswitch_mode_get(struct devlink *devlink, u16 *mode)
  2568. {
  2569. struct lio_devlink_priv *priv;
  2570. struct octeon_device *oct;
  2571. priv = devlink_priv(devlink);
  2572. oct = priv->oct;
  2573. *mode = oct->eswitch_mode;
  2574. return 0;
  2575. }
  2576. static int
  2577. liquidio_eswitch_mode_set(struct devlink *devlink, u16 mode,
  2578. struct netlink_ext_ack *extack)
  2579. {
  2580. struct lio_devlink_priv *priv;
  2581. struct octeon_device *oct;
  2582. int ret = 0;
  2583. priv = devlink_priv(devlink);
  2584. oct = priv->oct;
  2585. if (!(oct->fw_info.app_cap_flags & LIQUIDIO_SWITCHDEV_CAP))
  2586. return -EINVAL;
  2587. if (oct->eswitch_mode == mode)
  2588. return 0;
  2589. switch (mode) {
  2590. case DEVLINK_ESWITCH_MODE_SWITCHDEV:
  2591. oct->eswitch_mode = mode;
  2592. ret = lio_vf_rep_create(oct);
  2593. break;
  2594. case DEVLINK_ESWITCH_MODE_LEGACY:
  2595. lio_vf_rep_destroy(oct);
  2596. oct->eswitch_mode = mode;
  2597. break;
  2598. default:
  2599. ret = -EINVAL;
  2600. }
  2601. return ret;
  2602. }
  2603. static const struct devlink_ops liquidio_devlink_ops = {
  2604. .eswitch_mode_get = liquidio_eswitch_mode_get,
  2605. .eswitch_mode_set = liquidio_eswitch_mode_set,
  2606. };
  2607. static int
  2608. liquidio_get_port_parent_id(struct net_device *dev,
  2609. struct netdev_phys_item_id *ppid)
  2610. {
  2611. struct lio *lio = GET_LIO(dev);
  2612. struct octeon_device *oct = lio->oct_dev;
  2613. if (oct->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
  2614. return -EOPNOTSUPP;
  2615. ppid->id_len = ETH_ALEN;
  2616. ether_addr_copy(ppid->id, (void *)&lio->linfo.hw_addr + 2);
  2617. return 0;
  2618. }
  2619. static int liquidio_get_vf_stats(struct net_device *netdev, int vfidx,
  2620. struct ifla_vf_stats *vf_stats)
  2621. {
  2622. struct lio *lio = GET_LIO(netdev);
  2623. struct octeon_device *oct = lio->oct_dev;
  2624. struct oct_vf_stats stats;
  2625. int ret;
  2626. if (vfidx < 0 || vfidx >= oct->sriov_info.num_vfs_alloced)
  2627. return -EINVAL;
  2628. memset(&stats, 0, sizeof(struct oct_vf_stats));
  2629. ret = cn23xx_get_vf_stats(oct, vfidx, &stats);
  2630. if (!ret) {
  2631. vf_stats->rx_packets = stats.rx_packets;
  2632. vf_stats->tx_packets = stats.tx_packets;
  2633. vf_stats->rx_bytes = stats.rx_bytes;
  2634. vf_stats->tx_bytes = stats.tx_bytes;
  2635. vf_stats->broadcast = stats.broadcast;
  2636. vf_stats->multicast = stats.multicast;
  2637. }
  2638. return ret;
  2639. }
  2640. static const struct net_device_ops lionetdevops = {
  2641. .ndo_open = liquidio_open,
  2642. .ndo_stop = liquidio_stop,
  2643. .ndo_start_xmit = liquidio_xmit,
  2644. .ndo_get_stats64 = liquidio_get_stats64,
  2645. .ndo_set_mac_address = liquidio_set_mac,
  2646. .ndo_set_rx_mode = liquidio_set_mcast_list,
  2647. .ndo_tx_timeout = liquidio_tx_timeout,
  2648. .ndo_vlan_rx_add_vid = liquidio_vlan_rx_add_vid,
  2649. .ndo_vlan_rx_kill_vid = liquidio_vlan_rx_kill_vid,
  2650. .ndo_change_mtu = liquidio_change_mtu,
  2651. .ndo_fix_features = liquidio_fix_features,
  2652. .ndo_set_features = liquidio_set_features,
  2653. .ndo_set_vf_mac = liquidio_set_vf_mac,
  2654. .ndo_set_vf_vlan = liquidio_set_vf_vlan,
  2655. .ndo_get_vf_config = liquidio_get_vf_config,
  2656. .ndo_set_vf_spoofchk = liquidio_set_vf_spoofchk,
  2657. .ndo_set_vf_trust = liquidio_set_vf_trust,
  2658. .ndo_set_vf_link_state = liquidio_set_vf_link_state,
  2659. .ndo_get_vf_stats = liquidio_get_vf_stats,
  2660. .ndo_get_port_parent_id = liquidio_get_port_parent_id,
  2661. .ndo_hwtstamp_get = liquidio_hwtstamp_get,
  2662. .ndo_hwtstamp_set = liquidio_hwtstamp_set,
  2663. };
  2664. /**
  2665. * liquidio_init - Entry point for the liquidio module
  2666. */
  2667. static int __init liquidio_init(void)
  2668. {
  2669. int i;
  2670. struct handshake *hs;
  2671. init_completion(&first_stage);
  2672. octeon_init_device_list(OCTEON_CONFIG_TYPE_DEFAULT);
  2673. if (liquidio_init_pci())
  2674. return -EINVAL;
  2675. wait_for_completion_timeout(&first_stage, msecs_to_jiffies(1000));
  2676. for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
  2677. hs = &handshake[i];
  2678. if (hs->pci_dev) {
  2679. wait_for_completion(&hs->init);
  2680. if (!hs->init_ok) {
  2681. /* init handshake failed */
  2682. dev_err(&hs->pci_dev->dev,
  2683. "Failed to init device\n");
  2684. liquidio_deinit_pci();
  2685. return -EIO;
  2686. }
  2687. }
  2688. }
  2689. for (i = 0; i < MAX_OCTEON_DEVICES; i++) {
  2690. hs = &handshake[i];
  2691. if (hs->pci_dev) {
  2692. wait_for_completion_timeout(&hs->started,
  2693. msecs_to_jiffies(30000));
  2694. if (!hs->started_ok) {
  2695. /* starter handshake failed */
  2696. dev_err(&hs->pci_dev->dev,
  2697. "Firmware failed to start\n");
  2698. liquidio_deinit_pci();
  2699. return -EIO;
  2700. }
  2701. }
  2702. }
  2703. return 0;
  2704. }
  2705. static int lio_nic_info(struct octeon_recv_info *recv_info, void *buf)
  2706. {
  2707. struct octeon_device *oct = (struct octeon_device *)buf;
  2708. struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
  2709. int gmxport = 0;
  2710. union oct_link_status *ls;
  2711. int i;
  2712. if (recv_pkt->buffer_size[0] != (sizeof(*ls) + OCT_DROQ_INFO_SIZE)) {
  2713. dev_err(&oct->pci_dev->dev, "Malformed NIC_INFO, len=%d, ifidx=%d\n",
  2714. recv_pkt->buffer_size[0],
  2715. recv_pkt->rh.r_nic_info.gmxport);
  2716. goto nic_info_err;
  2717. }
  2718. gmxport = recv_pkt->rh.r_nic_info.gmxport;
  2719. ls = (union oct_link_status *)(get_rbd(recv_pkt->buffer_ptr[0]) +
  2720. OCT_DROQ_INFO_SIZE);
  2721. octeon_swap_8B_data((u64 *)ls, (sizeof(union oct_link_status)) >> 3);
  2722. for (i = 0; i < oct->ifcount; i++) {
  2723. if (oct->props[i].gmxport == gmxport) {
  2724. update_link_status(oct->props[i].netdev, ls);
  2725. break;
  2726. }
  2727. }
  2728. nic_info_err:
  2729. for (i = 0; i < recv_pkt->buffer_count; i++)
  2730. recv_buffer_free(recv_pkt->buffer_ptr[i]);
  2731. octeon_free_recv_info(recv_info);
  2732. return 0;
  2733. }
  2734. /**
  2735. * setup_nic_devices - Setup network interfaces
  2736. * @octeon_dev: octeon device
  2737. *
  2738. * Called during init time for each device. It assumes the NIC
  2739. * is already up and running. The link information for each
  2740. * interface is passed in link_info.
  2741. */
  2742. static int setup_nic_devices(struct octeon_device *octeon_dev)
  2743. {
  2744. struct lio *lio = NULL;
  2745. struct net_device *netdev;
  2746. u8 mac[6], i, j, *fw_ver, *micro_ver;
  2747. unsigned long micro;
  2748. u32 cur_ver;
  2749. struct octeon_soft_command *sc;
  2750. struct liquidio_if_cfg_resp *resp;
  2751. struct octdev_props *props;
  2752. int retval, num_iqueues, num_oqueues;
  2753. int max_num_queues = 0;
  2754. union oct_nic_if_cfg if_cfg;
  2755. unsigned int base_queue;
  2756. unsigned int gmx_port_id;
  2757. u32 resp_size, data_size;
  2758. u32 ifidx_or_pfnum;
  2759. struct lio_version *vdata;
  2760. struct devlink *devlink;
  2761. struct lio_devlink_priv *lio_devlink;
  2762. /* This is to handle link status changes */
  2763. octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
  2764. OPCODE_NIC_INFO,
  2765. lio_nic_info, octeon_dev);
  2766. /* REQTYPE_RESP_NET and REQTYPE_SOFT_COMMAND do not have free functions.
  2767. * They are handled directly.
  2768. */
  2769. octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET,
  2770. free_netbuf);
  2771. octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_NORESP_NET_SG,
  2772. free_netsgbuf);
  2773. octeon_register_reqtype_free_fn(octeon_dev, REQTYPE_RESP_NET_SG,
  2774. free_netsgbuf_with_resp);
  2775. for (i = 0; i < octeon_dev->ifcount; i++) {
  2776. resp_size = sizeof(struct liquidio_if_cfg_resp);
  2777. data_size = sizeof(struct lio_version);
  2778. sc = (struct octeon_soft_command *)
  2779. octeon_alloc_soft_command(octeon_dev, data_size,
  2780. resp_size, 0);
  2781. resp = (struct liquidio_if_cfg_resp *)sc->virtrptr;
  2782. vdata = (struct lio_version *)sc->virtdptr;
  2783. *((u64 *)vdata) = 0;
  2784. vdata->major = cpu_to_be16(LIQUIDIO_BASE_MAJOR_VERSION);
  2785. vdata->minor = cpu_to_be16(LIQUIDIO_BASE_MINOR_VERSION);
  2786. vdata->micro = cpu_to_be16(LIQUIDIO_BASE_MICRO_VERSION);
  2787. if (OCTEON_CN23XX_PF(octeon_dev)) {
  2788. num_iqueues = octeon_dev->sriov_info.num_pf_rings;
  2789. num_oqueues = octeon_dev->sriov_info.num_pf_rings;
  2790. base_queue = octeon_dev->sriov_info.pf_srn;
  2791. gmx_port_id = octeon_dev->pf_num;
  2792. ifidx_or_pfnum = octeon_dev->pf_num;
  2793. } else {
  2794. num_iqueues = CFG_GET_NUM_TXQS_NIC_IF(
  2795. octeon_get_conf(octeon_dev), i);
  2796. num_oqueues = CFG_GET_NUM_RXQS_NIC_IF(
  2797. octeon_get_conf(octeon_dev), i);
  2798. base_queue = CFG_GET_BASE_QUE_NIC_IF(
  2799. octeon_get_conf(octeon_dev), i);
  2800. gmx_port_id = CFG_GET_GMXID_NIC_IF(
  2801. octeon_get_conf(octeon_dev), i);
  2802. ifidx_or_pfnum = i;
  2803. }
  2804. dev_dbg(&octeon_dev->pci_dev->dev,
  2805. "requesting config for interface %d, iqs %d, oqs %d\n",
  2806. ifidx_or_pfnum, num_iqueues, num_oqueues);
  2807. if_cfg.u64 = 0;
  2808. if_cfg.s.num_iqueues = num_iqueues;
  2809. if_cfg.s.num_oqueues = num_oqueues;
  2810. if_cfg.s.base_queue = base_queue;
  2811. if_cfg.s.gmx_port_id = gmx_port_id;
  2812. sc->iq_no = 0;
  2813. octeon_prepare_soft_command(octeon_dev, sc, OPCODE_NIC,
  2814. OPCODE_NIC_IF_CFG, 0,
  2815. if_cfg.u64, 0);
  2816. init_completion(&sc->complete);
  2817. sc->sc_status = OCTEON_REQUEST_PENDING;
  2818. retval = octeon_send_soft_command(octeon_dev, sc);
  2819. if (retval == IQ_SEND_FAILED) {
  2820. dev_err(&octeon_dev->pci_dev->dev,
  2821. "iq/oq config failed status: %x\n",
  2822. retval);
  2823. /* Soft instr is freed by driver in case of failure. */
  2824. octeon_free_soft_command(octeon_dev, sc);
  2825. return(-EIO);
  2826. }
  2827. /* Sleep on a wait queue till the cond flag indicates that the
  2828. * response arrived or timed-out.
  2829. */
  2830. retval = wait_for_sc_completion_timeout(octeon_dev, sc, 0);
  2831. if (retval)
  2832. return retval;
  2833. retval = resp->status;
  2834. if (retval) {
  2835. dev_err(&octeon_dev->pci_dev->dev, "iq/oq config failed\n");
  2836. WRITE_ONCE(sc->caller_is_done, true);
  2837. goto setup_nic_dev_done;
  2838. }
  2839. snprintf(octeon_dev->fw_info.liquidio_firmware_version,
  2840. 32, "%s",
  2841. resp->cfg_info.liquidio_firmware_version);
  2842. /* Verify f/w version (in case of 'auto' loading from flash) */
  2843. fw_ver = octeon_dev->fw_info.liquidio_firmware_version;
  2844. if (memcmp(LIQUIDIO_BASE_VERSION,
  2845. fw_ver,
  2846. strlen(LIQUIDIO_BASE_VERSION))) {
  2847. dev_err(&octeon_dev->pci_dev->dev,
  2848. "Unmatched firmware version. Expected %s.x, got %s.\n",
  2849. LIQUIDIO_BASE_VERSION, fw_ver);
  2850. WRITE_ONCE(sc->caller_is_done, true);
  2851. goto setup_nic_dev_done;
  2852. } else if (atomic_read(octeon_dev->adapter_fw_state) ==
  2853. FW_IS_PRELOADED) {
  2854. dev_info(&octeon_dev->pci_dev->dev,
  2855. "Using auto-loaded firmware version %s.\n",
  2856. fw_ver);
  2857. }
  2858. /* extract micro version field; point past '<maj>.<min>.' */
  2859. micro_ver = fw_ver + strlen(LIQUIDIO_BASE_VERSION) + 1;
  2860. if (kstrtoul(micro_ver, 10, &micro) != 0)
  2861. micro = 0;
  2862. octeon_dev->fw_info.ver.maj = LIQUIDIO_BASE_MAJOR_VERSION;
  2863. octeon_dev->fw_info.ver.min = LIQUIDIO_BASE_MINOR_VERSION;
  2864. octeon_dev->fw_info.ver.rev = micro;
  2865. octeon_swap_8B_data((u64 *)(&resp->cfg_info),
  2866. (sizeof(struct liquidio_if_cfg_info)) >> 3);
  2867. num_iqueues = hweight64(resp->cfg_info.iqmask);
  2868. num_oqueues = hweight64(resp->cfg_info.oqmask);
  2869. if (!(num_iqueues) || !(num_oqueues)) {
  2870. dev_err(&octeon_dev->pci_dev->dev,
  2871. "Got bad iqueues (%016llx) or oqueues (%016llx) from firmware.\n",
  2872. resp->cfg_info.iqmask,
  2873. resp->cfg_info.oqmask);
  2874. WRITE_ONCE(sc->caller_is_done, true);
  2875. goto setup_nic_dev_done;
  2876. }
  2877. if (OCTEON_CN6XXX(octeon_dev)) {
  2878. max_num_queues = CFG_GET_IQ_MAX_Q(CHIP_CONF(octeon_dev,
  2879. cn6xxx));
  2880. } else if (OCTEON_CN23XX_PF(octeon_dev)) {
  2881. max_num_queues = CFG_GET_IQ_MAX_Q(CHIP_CONF(octeon_dev,
  2882. cn23xx_pf));
  2883. }
  2884. dev_dbg(&octeon_dev->pci_dev->dev,
  2885. "interface %d, iqmask %016llx, oqmask %016llx, numiqueues %d, numoqueues %d max_num_queues: %d\n",
  2886. i, resp->cfg_info.iqmask, resp->cfg_info.oqmask,
  2887. num_iqueues, num_oqueues, max_num_queues);
  2888. netdev = alloc_etherdev_mq(LIO_SIZE, max_num_queues);
  2889. if (!netdev) {
  2890. dev_err(&octeon_dev->pci_dev->dev, "Device allocation failed\n");
  2891. WRITE_ONCE(sc->caller_is_done, true);
  2892. goto setup_nic_dev_done;
  2893. }
  2894. SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev);
  2895. /* Associate the routines that will handle different
  2896. * netdev tasks.
  2897. */
  2898. netdev->netdev_ops = &lionetdevops;
  2899. lio = GET_LIO(netdev);
  2900. memset(lio, 0, sizeof(struct lio));
  2901. lio->ifidx = ifidx_or_pfnum;
  2902. props = &octeon_dev->props[i];
  2903. props->gmxport = resp->cfg_info.linfo.gmxport;
  2904. props->netdev = netdev;
  2905. /* Point to the properties for octeon device to which this
  2906. * interface belongs.
  2907. */
  2908. lio->oct_dev = octeon_dev;
  2909. lio->octprops = props;
  2910. lio->netdev = netdev;
  2911. retval = netif_set_real_num_rx_queues(netdev, num_oqueues);
  2912. if (retval) {
  2913. dev_err(&octeon_dev->pci_dev->dev,
  2914. "setting real number rx failed\n");
  2915. WRITE_ONCE(sc->caller_is_done, true);
  2916. goto setup_nic_dev_free;
  2917. }
  2918. retval = netif_set_real_num_tx_queues(netdev, num_iqueues);
  2919. if (retval) {
  2920. dev_err(&octeon_dev->pci_dev->dev,
  2921. "setting real number tx failed\n");
  2922. WRITE_ONCE(sc->caller_is_done, true);
  2923. goto setup_nic_dev_free;
  2924. }
  2925. lio->linfo.num_rxpciq = num_oqueues;
  2926. lio->linfo.num_txpciq = num_iqueues;
  2927. for (j = 0; j < num_oqueues; j++) {
  2928. lio->linfo.rxpciq[j].u64 =
  2929. resp->cfg_info.linfo.rxpciq[j].u64;
  2930. }
  2931. for (j = 0; j < num_iqueues; j++) {
  2932. lio->linfo.txpciq[j].u64 =
  2933. resp->cfg_info.linfo.txpciq[j].u64;
  2934. }
  2935. lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
  2936. lio->linfo.gmxport = resp->cfg_info.linfo.gmxport;
  2937. lio->linfo.link.u64 = resp->cfg_info.linfo.link.u64;
  2938. WRITE_ONCE(sc->caller_is_done, true);
  2939. lio->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  2940. if (OCTEON_CN23XX_PF(octeon_dev) ||
  2941. OCTEON_CN6XXX(octeon_dev)) {
  2942. lio->dev_capability = NETIF_F_HIGHDMA
  2943. | NETIF_F_IP_CSUM
  2944. | NETIF_F_IPV6_CSUM
  2945. | NETIF_F_SG | NETIF_F_RXCSUM
  2946. | NETIF_F_GRO
  2947. | NETIF_F_TSO | NETIF_F_TSO6
  2948. | NETIF_F_LRO;
  2949. }
  2950. netif_set_tso_max_size(netdev, OCTNIC_GSO_MAX_SIZE);
  2951. /* Copy of transmit encapsulation capabilities:
  2952. * TSO, TSO6, Checksums for this device
  2953. */
  2954. lio->enc_dev_capability = NETIF_F_IP_CSUM
  2955. | NETIF_F_IPV6_CSUM
  2956. | NETIF_F_GSO_UDP_TUNNEL
  2957. | NETIF_F_HW_CSUM | NETIF_F_SG
  2958. | NETIF_F_RXCSUM
  2959. | NETIF_F_TSO | NETIF_F_TSO6
  2960. | NETIF_F_LRO;
  2961. netdev->hw_enc_features = (lio->enc_dev_capability &
  2962. ~NETIF_F_LRO);
  2963. netdev->udp_tunnel_nic_info = &liquidio_udp_tunnels;
  2964. lio->dev_capability |= NETIF_F_GSO_UDP_TUNNEL;
  2965. netdev->vlan_features = lio->dev_capability;
  2966. /* Add any unchangeable hw features */
  2967. lio->dev_capability |= NETIF_F_HW_VLAN_CTAG_FILTER |
  2968. NETIF_F_HW_VLAN_CTAG_RX |
  2969. NETIF_F_HW_VLAN_CTAG_TX;
  2970. netdev->features = (lio->dev_capability & ~NETIF_F_LRO);
  2971. netdev->hw_features = lio->dev_capability;
  2972. /*HW_VLAN_RX and HW_VLAN_FILTER is always on*/
  2973. netdev->hw_features = netdev->hw_features &
  2974. ~NETIF_F_HW_VLAN_CTAG_RX;
  2975. /* MTU range: 68 - 16000 */
  2976. netdev->min_mtu = LIO_MIN_MTU_SIZE;
  2977. netdev->max_mtu = LIO_MAX_MTU_SIZE;
  2978. dev_dbg(&octeon_dev->pci_dev->dev,
  2979. "if%d gmx: %d hw_addr: 0x%llx\n", i,
  2980. lio->linfo.gmxport, CVM_CAST64(lio->linfo.hw_addr));
  2981. for (j = 0; j < octeon_dev->sriov_info.max_vfs; j++) {
  2982. u8 vfmac[ETH_ALEN];
  2983. eth_random_addr(vfmac);
  2984. if (__liquidio_set_vf_mac(netdev, j, vfmac, false)) {
  2985. dev_err(&octeon_dev->pci_dev->dev,
  2986. "Error setting VF%d MAC address\n",
  2987. j);
  2988. goto setup_nic_dev_free;
  2989. }
  2990. }
  2991. /* 64-bit swap required on LE machines */
  2992. octeon_swap_8B_data(&lio->linfo.hw_addr, 1);
  2993. for (j = 0; j < 6; j++)
  2994. mac[j] = *((u8 *)(((u8 *)&lio->linfo.hw_addr) + 2 + j));
  2995. /* Copy MAC Address to OS network device structure */
  2996. eth_hw_addr_set(netdev, mac);
  2997. /* By default all interfaces on a single Octeon uses the same
  2998. * tx and rx queues
  2999. */
  3000. lio->txq = lio->linfo.txpciq[0].s.q_no;
  3001. lio->rxq = lio->linfo.rxpciq[0].s.q_no;
  3002. if (liquidio_setup_io_queues(octeon_dev, i,
  3003. lio->linfo.num_txpciq,
  3004. lio->linfo.num_rxpciq)) {
  3005. dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n");
  3006. goto setup_nic_dev_free;
  3007. }
  3008. ifstate_set(lio, LIO_IFSTATE_DROQ_OPS);
  3009. lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq);
  3010. lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq);
  3011. if (lio_setup_glists(octeon_dev, lio, num_iqueues)) {
  3012. dev_err(&octeon_dev->pci_dev->dev,
  3013. "Gather list allocation failed\n");
  3014. goto setup_nic_dev_free;
  3015. }
  3016. /* Register ethtool support */
  3017. liquidio_set_ethtool_ops(netdev);
  3018. if (lio->oct_dev->chip_id == OCTEON_CN23XX_PF_VID)
  3019. octeon_dev->priv_flags = OCT_PRIV_FLAG_DEFAULT;
  3020. else
  3021. octeon_dev->priv_flags = 0x0;
  3022. if (netdev->features & NETIF_F_LRO)
  3023. liquidio_set_feature(netdev, OCTNET_CMD_LRO_ENABLE,
  3024. OCTNIC_LROIPV4 | OCTNIC_LROIPV6);
  3025. liquidio_set_feature(netdev, OCTNET_CMD_VLAN_FILTER_CTL,
  3026. OCTNET_CMD_VLAN_FILTER_ENABLE);
  3027. if ((debug != -1) && (debug & NETIF_MSG_HW))
  3028. liquidio_set_feature(netdev,
  3029. OCTNET_CMD_VERBOSE_ENABLE, 0);
  3030. if (setup_link_status_change_wq(netdev))
  3031. goto setup_nic_dev_free;
  3032. if ((octeon_dev->fw_info.app_cap_flags &
  3033. LIQUIDIO_TIME_SYNC_CAP) &&
  3034. setup_sync_octeon_time_wq(netdev))
  3035. goto setup_nic_dev_free;
  3036. if (setup_rx_oom_poll_fn(netdev))
  3037. goto setup_nic_dev_free;
  3038. /* Register the network device with the OS */
  3039. if (register_netdev(netdev)) {
  3040. dev_err(&octeon_dev->pci_dev->dev, "Device registration failed\n");
  3041. goto setup_nic_dev_free;
  3042. }
  3043. dev_dbg(&octeon_dev->pci_dev->dev,
  3044. "Setup NIC ifidx:%d mac:%02x%02x%02x%02x%02x%02x\n",
  3045. i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  3046. netif_carrier_off(netdev);
  3047. lio->link_changes++;
  3048. ifstate_set(lio, LIO_IFSTATE_REGISTERED);
  3049. /* Sending command to firmware to enable Rx checksum offload
  3050. * by default at the time of setup of Liquidio driver for
  3051. * this device
  3052. */
  3053. liquidio_set_rxcsum_command(netdev, OCTNET_CMD_TNL_RX_CSUM_CTL,
  3054. OCTNET_CMD_RXCSUM_ENABLE);
  3055. liquidio_set_feature(netdev, OCTNET_CMD_TNL_TX_CSUM_CTL,
  3056. OCTNET_CMD_TXCSUM_ENABLE);
  3057. dev_dbg(&octeon_dev->pci_dev->dev,
  3058. "NIC ifidx:%d Setup successful\n", i);
  3059. if (octeon_dev->subsystem_id ==
  3060. OCTEON_CN2350_25GB_SUBSYS_ID ||
  3061. octeon_dev->subsystem_id ==
  3062. OCTEON_CN2360_25GB_SUBSYS_ID) {
  3063. cur_ver = OCT_FW_VER(octeon_dev->fw_info.ver.maj,
  3064. octeon_dev->fw_info.ver.min,
  3065. octeon_dev->fw_info.ver.rev);
  3066. /* speed control unsupported in f/w older than 1.7.2 */
  3067. if (cur_ver < OCT_FW_VER(1, 7, 2)) {
  3068. dev_info(&octeon_dev->pci_dev->dev,
  3069. "speed setting not supported by f/w.");
  3070. octeon_dev->speed_setting = 25;
  3071. octeon_dev->no_speed_setting = 1;
  3072. } else {
  3073. liquidio_get_speed(lio);
  3074. }
  3075. if (octeon_dev->speed_setting == 0) {
  3076. octeon_dev->speed_setting = 25;
  3077. octeon_dev->no_speed_setting = 1;
  3078. }
  3079. } else {
  3080. octeon_dev->no_speed_setting = 1;
  3081. octeon_dev->speed_setting = 10;
  3082. }
  3083. octeon_dev->speed_boot = octeon_dev->speed_setting;
  3084. /* don't read FEC setting if unsupported by f/w (see above) */
  3085. if (octeon_dev->speed_boot == 25 &&
  3086. !octeon_dev->no_speed_setting) {
  3087. liquidio_get_fec(lio);
  3088. octeon_dev->props[lio->ifidx].fec_boot =
  3089. octeon_dev->props[lio->ifidx].fec;
  3090. }
  3091. }
  3092. device_lock(&octeon_dev->pci_dev->dev);
  3093. devlink = devlink_alloc(&liquidio_devlink_ops,
  3094. sizeof(struct lio_devlink_priv),
  3095. &octeon_dev->pci_dev->dev);
  3096. if (!devlink) {
  3097. device_unlock(&octeon_dev->pci_dev->dev);
  3098. dev_err(&octeon_dev->pci_dev->dev, "devlink alloc failed\n");
  3099. i--;
  3100. goto setup_nic_dev_free;
  3101. }
  3102. lio_devlink = devlink_priv(devlink);
  3103. lio_devlink->oct = octeon_dev;
  3104. octeon_dev->devlink = devlink;
  3105. octeon_dev->eswitch_mode = DEVLINK_ESWITCH_MODE_LEGACY;
  3106. devlink_register(devlink);
  3107. device_unlock(&octeon_dev->pci_dev->dev);
  3108. return 0;
  3109. setup_nic_dev_free:
  3110. do {
  3111. dev_err(&octeon_dev->pci_dev->dev,
  3112. "NIC ifidx:%d Setup failed\n", i);
  3113. liquidio_destroy_nic_device(octeon_dev, i);
  3114. } while (i--);
  3115. setup_nic_dev_done:
  3116. return -ENODEV;
  3117. }
  3118. #ifdef CONFIG_PCI_IOV
  3119. static int octeon_enable_sriov(struct octeon_device *oct)
  3120. {
  3121. unsigned int num_vfs_alloced = oct->sriov_info.num_vfs_alloced;
  3122. struct pci_dev *vfdev;
  3123. int err;
  3124. u32 u;
  3125. if (OCTEON_CN23XX_PF(oct) && num_vfs_alloced) {
  3126. err = pci_enable_sriov(oct->pci_dev,
  3127. oct->sriov_info.num_vfs_alloced);
  3128. if (err) {
  3129. dev_err(&oct->pci_dev->dev,
  3130. "OCTEON: Failed to enable PCI sriov: %d\n",
  3131. err);
  3132. oct->sriov_info.num_vfs_alloced = 0;
  3133. return err;
  3134. }
  3135. oct->sriov_info.sriov_enabled = 1;
  3136. /* init lookup table that maps DPI ring number to VF pci_dev
  3137. * struct pointer
  3138. */
  3139. u = 0;
  3140. vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
  3141. OCTEON_CN23XX_VF_VID, NULL);
  3142. while (vfdev) {
  3143. if (vfdev->is_virtfn &&
  3144. (vfdev->physfn == oct->pci_dev)) {
  3145. oct->sriov_info.dpiring_to_vfpcidev_lut[u] =
  3146. vfdev;
  3147. u += oct->sriov_info.rings_per_vf;
  3148. }
  3149. vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
  3150. OCTEON_CN23XX_VF_VID, vfdev);
  3151. }
  3152. }
  3153. return num_vfs_alloced;
  3154. }
  3155. static int lio_pci_sriov_disable(struct octeon_device *oct)
  3156. {
  3157. int u;
  3158. if (pci_vfs_assigned(oct->pci_dev)) {
  3159. dev_err(&oct->pci_dev->dev, "VFs are still assigned to VMs.\n");
  3160. return -EPERM;
  3161. }
  3162. pci_disable_sriov(oct->pci_dev);
  3163. u = 0;
  3164. while (u < MAX_POSSIBLE_VFS) {
  3165. oct->sriov_info.dpiring_to_vfpcidev_lut[u] = NULL;
  3166. u += oct->sriov_info.rings_per_vf;
  3167. }
  3168. oct->sriov_info.num_vfs_alloced = 0;
  3169. dev_info(&oct->pci_dev->dev, "oct->pf_num:%d disabled VFs\n",
  3170. oct->pf_num);
  3171. return 0;
  3172. }
  3173. static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs)
  3174. {
  3175. struct octeon_device *oct = pci_get_drvdata(dev);
  3176. int ret = 0;
  3177. if ((num_vfs == oct->sriov_info.num_vfs_alloced) &&
  3178. (oct->sriov_info.sriov_enabled)) {
  3179. dev_info(&oct->pci_dev->dev, "oct->pf_num:%d already enabled num_vfs:%d\n",
  3180. oct->pf_num, num_vfs);
  3181. return 0;
  3182. }
  3183. if (!num_vfs) {
  3184. lio_vf_rep_destroy(oct);
  3185. ret = lio_pci_sriov_disable(oct);
  3186. } else if (num_vfs > oct->sriov_info.max_vfs) {
  3187. dev_err(&oct->pci_dev->dev,
  3188. "OCTEON: Max allowed VFs:%d user requested:%d",
  3189. oct->sriov_info.max_vfs, num_vfs);
  3190. ret = -EPERM;
  3191. } else {
  3192. oct->sriov_info.num_vfs_alloced = num_vfs;
  3193. ret = octeon_enable_sriov(oct);
  3194. dev_info(&oct->pci_dev->dev, "oct->pf_num:%d num_vfs:%d\n",
  3195. oct->pf_num, num_vfs);
  3196. ret = lio_vf_rep_create(oct);
  3197. if (ret)
  3198. dev_info(&oct->pci_dev->dev,
  3199. "vf representor create failed");
  3200. }
  3201. return ret;
  3202. }
  3203. #endif
  3204. /**
  3205. * liquidio_init_nic_module - initialize the NIC
  3206. * @oct: octeon device
  3207. *
  3208. * This initialization routine is called once the Octeon device application is
  3209. * up and running
  3210. */
  3211. static int liquidio_init_nic_module(struct octeon_device *oct)
  3212. {
  3213. int i, retval = 0;
  3214. int num_nic_ports = CFG_GET_NUM_NIC_PORTS(octeon_get_conf(oct));
  3215. dev_dbg(&oct->pci_dev->dev, "Initializing network interfaces\n");
  3216. /* only default iq and oq were initialized
  3217. * initialize the rest as well
  3218. */
  3219. /* run port_config command for each port */
  3220. oct->ifcount = num_nic_ports;
  3221. memset(oct->props, 0, sizeof(struct octdev_props) * num_nic_ports);
  3222. for (i = 0; i < MAX_OCTEON_LINKS; i++)
  3223. oct->props[i].gmxport = -1;
  3224. retval = setup_nic_devices(oct);
  3225. if (retval) {
  3226. dev_err(&oct->pci_dev->dev, "Setup NIC devices failed\n");
  3227. goto octnet_init_failure;
  3228. }
  3229. /* Call vf_rep_modinit if the firmware is switchdev capable
  3230. * and do it from the first liquidio function probed.
  3231. */
  3232. if (!oct->octeon_id &&
  3233. oct->fw_info.app_cap_flags & LIQUIDIO_SWITCHDEV_CAP) {
  3234. retval = lio_vf_rep_modinit();
  3235. if (retval) {
  3236. liquidio_stop_nic_module(oct);
  3237. goto octnet_init_failure;
  3238. }
  3239. }
  3240. liquidio_ptp_init(oct);
  3241. dev_dbg(&oct->pci_dev->dev, "Network interfaces ready\n");
  3242. return retval;
  3243. octnet_init_failure:
  3244. oct->ifcount = 0;
  3245. return retval;
  3246. }
  3247. /**
  3248. * nic_starter - finish init
  3249. * @work: work struct work_struct
  3250. *
  3251. * starter callback that invokes the remaining initialization work after the NIC is up and running.
  3252. */
  3253. static void nic_starter(struct work_struct *work)
  3254. {
  3255. struct octeon_device *oct;
  3256. struct cavium_wk *wk = (struct cavium_wk *)work;
  3257. oct = (struct octeon_device *)wk->ctxptr;
  3258. if (atomic_read(&oct->status) == OCT_DEV_RUNNING)
  3259. return;
  3260. /* If the status of the device is CORE_OK, the core
  3261. * application has reported its application type. Call
  3262. * any registered handlers now and move to the RUNNING
  3263. * state.
  3264. */
  3265. if (atomic_read(&oct->status) != OCT_DEV_CORE_OK) {
  3266. schedule_delayed_work(&oct->nic_poll_work.work,
  3267. LIQUIDIO_STARTER_POLL_INTERVAL_MS);
  3268. return;
  3269. }
  3270. atomic_set(&oct->status, OCT_DEV_RUNNING);
  3271. if (oct->app_mode && oct->app_mode == CVM_DRV_NIC_APP) {
  3272. dev_dbg(&oct->pci_dev->dev, "Starting NIC module\n");
  3273. if (liquidio_init_nic_module(oct))
  3274. dev_err(&oct->pci_dev->dev, "NIC initialization failed\n");
  3275. else
  3276. handshake[oct->octeon_id].started_ok = 1;
  3277. } else {
  3278. dev_err(&oct->pci_dev->dev,
  3279. "Unexpected application running on NIC (%d). Check firmware.\n",
  3280. oct->app_mode);
  3281. }
  3282. complete(&handshake[oct->octeon_id].started);
  3283. }
  3284. static int
  3285. octeon_recv_vf_drv_notice(struct octeon_recv_info *recv_info, void *buf)
  3286. {
  3287. struct octeon_device *oct = (struct octeon_device *)buf;
  3288. struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
  3289. int i, notice, vf_idx;
  3290. bool cores_crashed;
  3291. u64 *data, vf_num;
  3292. notice = recv_pkt->rh.r.ossp;
  3293. data = (u64 *)(get_rbd(recv_pkt->buffer_ptr[0]) + OCT_DROQ_INFO_SIZE);
  3294. /* the first 64-bit word of data is the vf_num */
  3295. vf_num = data[0];
  3296. octeon_swap_8B_data(&vf_num, 1);
  3297. vf_idx = (int)vf_num - 1;
  3298. cores_crashed = READ_ONCE(oct->cores_crashed);
  3299. if (notice == VF_DRV_LOADED) {
  3300. if (!(oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx))) {
  3301. oct->sriov_info.vf_drv_loaded_mask |= BIT_ULL(vf_idx);
  3302. dev_info(&oct->pci_dev->dev,
  3303. "driver for VF%d was loaded\n", vf_idx);
  3304. if (!cores_crashed)
  3305. try_module_get(THIS_MODULE);
  3306. }
  3307. } else if (notice == VF_DRV_REMOVED) {
  3308. if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vf_idx)) {
  3309. oct->sriov_info.vf_drv_loaded_mask &= ~BIT_ULL(vf_idx);
  3310. dev_info(&oct->pci_dev->dev,
  3311. "driver for VF%d was removed\n", vf_idx);
  3312. if (!cores_crashed)
  3313. module_put(THIS_MODULE);
  3314. }
  3315. } else if (notice == VF_DRV_MACADDR_CHANGED) {
  3316. u8 *b = (u8 *)&data[1];
  3317. oct->sriov_info.vf_macaddr[vf_idx] = data[1];
  3318. dev_info(&oct->pci_dev->dev,
  3319. "VF driver changed VF%d's MAC address to %pM\n",
  3320. vf_idx, b + 2);
  3321. }
  3322. for (i = 0; i < recv_pkt->buffer_count; i++)
  3323. recv_buffer_free(recv_pkt->buffer_ptr[i]);
  3324. octeon_free_recv_info(recv_info);
  3325. return 0;
  3326. }
  3327. /**
  3328. * octeon_device_init - Device initialization for each Octeon device that is probed
  3329. * @octeon_dev: octeon device
  3330. */
  3331. static int octeon_device_init(struct octeon_device *octeon_dev)
  3332. {
  3333. int j, ret;
  3334. char bootcmd[] = "\n";
  3335. char *dbg_enb = NULL;
  3336. enum lio_fw_state fw_state;
  3337. struct octeon_device_priv *oct_priv = octeon_dev->priv;
  3338. atomic_set(&octeon_dev->status, OCT_DEV_BEGIN_STATE);
  3339. /* Enable access to the octeon device and make its DMA capability
  3340. * known to the OS.
  3341. */
  3342. if (octeon_pci_os_setup(octeon_dev))
  3343. return 1;
  3344. atomic_set(&octeon_dev->status, OCT_DEV_PCI_ENABLE_DONE);
  3345. /* Identify the Octeon type and map the BAR address space. */
  3346. if (octeon_chip_specific_setup(octeon_dev)) {
  3347. dev_err(&octeon_dev->pci_dev->dev, "Chip specific setup failed\n");
  3348. return 1;
  3349. }
  3350. atomic_set(&octeon_dev->status, OCT_DEV_PCI_MAP_DONE);
  3351. /* Only add a reference after setting status 'OCT_DEV_PCI_MAP_DONE',
  3352. * since that is what is required for the reference to be removed
  3353. * during de-initialization (see 'octeon_destroy_resources').
  3354. */
  3355. octeon_register_device(octeon_dev, octeon_dev->pci_dev->bus->number,
  3356. PCI_SLOT(octeon_dev->pci_dev->devfn),
  3357. PCI_FUNC(octeon_dev->pci_dev->devfn),
  3358. true);
  3359. octeon_dev->app_mode = CVM_DRV_INVALID_APP;
  3360. /* CN23XX supports preloaded firmware if the following is true:
  3361. *
  3362. * The adapter indicates that firmware is currently running AND
  3363. * 'fw_type' is 'auto'.
  3364. *
  3365. * (default state is NEEDS_TO_BE_LOADED, override it if appropriate).
  3366. */
  3367. if (OCTEON_CN23XX_PF(octeon_dev) &&
  3368. cn23xx_fw_loaded(octeon_dev) && fw_type_is_auto()) {
  3369. atomic_cmpxchg(octeon_dev->adapter_fw_state,
  3370. FW_NEEDS_TO_BE_LOADED, FW_IS_PRELOADED);
  3371. }
  3372. /* If loading firmware, only first device of adapter needs to do so. */
  3373. fw_state = atomic_cmpxchg(octeon_dev->adapter_fw_state,
  3374. FW_NEEDS_TO_BE_LOADED,
  3375. FW_IS_BEING_LOADED);
  3376. /* Here, [local variable] 'fw_state' is set to one of:
  3377. *
  3378. * FW_IS_PRELOADED: No firmware is to be loaded (see above)
  3379. * FW_NEEDS_TO_BE_LOADED: The driver's first instance will load
  3380. * firmware to the adapter.
  3381. * FW_IS_BEING_LOADED: The driver's second instance will not load
  3382. * firmware to the adapter.
  3383. */
  3384. /* Prior to f/w load, perform a soft reset of the Octeon device;
  3385. * if error resetting, return w/error.
  3386. */
  3387. if (fw_state == FW_NEEDS_TO_BE_LOADED)
  3388. if (octeon_dev->fn_list.soft_reset(octeon_dev))
  3389. return 1;
  3390. /* Initialize the dispatch mechanism used to push packets arriving on
  3391. * Octeon Output queues.
  3392. */
  3393. if (octeon_init_dispatch_list(octeon_dev))
  3394. return 1;
  3395. octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
  3396. OPCODE_NIC_CORE_DRV_ACTIVE,
  3397. octeon_core_drv_init,
  3398. octeon_dev);
  3399. octeon_register_dispatch_fn(octeon_dev, OPCODE_NIC,
  3400. OPCODE_NIC_VF_DRV_NOTICE,
  3401. octeon_recv_vf_drv_notice, octeon_dev);
  3402. INIT_DELAYED_WORK(&octeon_dev->nic_poll_work.work, nic_starter);
  3403. octeon_dev->nic_poll_work.ctxptr = (void *)octeon_dev;
  3404. schedule_delayed_work(&octeon_dev->nic_poll_work.work,
  3405. LIQUIDIO_STARTER_POLL_INTERVAL_MS);
  3406. atomic_set(&octeon_dev->status, OCT_DEV_DISPATCH_INIT_DONE);
  3407. if (octeon_set_io_queues_off(octeon_dev)) {
  3408. dev_err(&octeon_dev->pci_dev->dev, "setting io queues off failed\n");
  3409. return 1;
  3410. }
  3411. if (OCTEON_CN23XX_PF(octeon_dev)) {
  3412. ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
  3413. if (ret) {
  3414. dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Failed to configure device registers\n");
  3415. return ret;
  3416. }
  3417. }
  3418. /* Initialize soft command buffer pool
  3419. */
  3420. if (octeon_setup_sc_buffer_pool(octeon_dev)) {
  3421. dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
  3422. return 1;
  3423. }
  3424. atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
  3425. /* Setup the data structures that manage this Octeon's Input queues. */
  3426. if (octeon_setup_instr_queues(octeon_dev)) {
  3427. dev_err(&octeon_dev->pci_dev->dev,
  3428. "instruction queue initialization failed\n");
  3429. return 1;
  3430. }
  3431. atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
  3432. /* Initialize lists to manage the requests of different types that
  3433. * arrive from user & kernel applications for this octeon device.
  3434. */
  3435. if (octeon_setup_response_list(octeon_dev)) {
  3436. dev_err(&octeon_dev->pci_dev->dev, "Response list allocation failed\n");
  3437. return 1;
  3438. }
  3439. atomic_set(&octeon_dev->status, OCT_DEV_RESP_LIST_INIT_DONE);
  3440. if (octeon_setup_output_queues(octeon_dev)) {
  3441. dev_err(&octeon_dev->pci_dev->dev, "Output queue initialization failed\n");
  3442. return 1;
  3443. }
  3444. atomic_set(&octeon_dev->status, OCT_DEV_DROQ_INIT_DONE);
  3445. if (OCTEON_CN23XX_PF(octeon_dev)) {
  3446. if (octeon_dev->fn_list.setup_mbox(octeon_dev)) {
  3447. dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Mailbox setup failed\n");
  3448. return 1;
  3449. }
  3450. atomic_set(&octeon_dev->status, OCT_DEV_MBOX_SETUP_DONE);
  3451. if (octeon_allocate_ioq_vector
  3452. (octeon_dev,
  3453. octeon_dev->sriov_info.num_pf_rings)) {
  3454. dev_err(&octeon_dev->pci_dev->dev, "OCTEON: ioq vector allocation failed\n");
  3455. return 1;
  3456. }
  3457. atomic_set(&octeon_dev->status, OCT_DEV_MSIX_ALLOC_VECTOR_DONE);
  3458. } else {
  3459. /* The input and output queue registers were setup earlier (the
  3460. * queues were not enabled). Any additional registers
  3461. * that need to be programmed should be done now.
  3462. */
  3463. ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
  3464. if (ret) {
  3465. dev_err(&octeon_dev->pci_dev->dev,
  3466. "Failed to configure device registers\n");
  3467. return ret;
  3468. }
  3469. }
  3470. /* Initialize the tasklet that handles output queue packet processing.*/
  3471. dev_dbg(&octeon_dev->pci_dev->dev, "Initializing droq tasklet\n");
  3472. tasklet_setup(&oct_priv->droq_tasklet, octeon_droq_bh);
  3473. /* Setup the interrupt handler and record the INT SUM register address
  3474. */
  3475. if (octeon_setup_interrupt(octeon_dev,
  3476. octeon_dev->sriov_info.num_pf_rings))
  3477. return 1;
  3478. /* Enable Octeon device interrupts */
  3479. octeon_dev->fn_list.enable_interrupt(octeon_dev, OCTEON_ALL_INTR);
  3480. atomic_set(&octeon_dev->status, OCT_DEV_INTR_SET_DONE);
  3481. /* Send Credit for Octeon Output queues. Credits are always sent BEFORE
  3482. * the output queue is enabled.
  3483. * This ensures that we'll receive the f/w CORE DRV_ACTIVE message in
  3484. * case we've configured CN23XX_SLI_GBL_CONTROL[NOPTR_D] = 0.
  3485. * Otherwise, it is possible that the DRV_ACTIVE message will be sent
  3486. * before any credits have been issued, causing the ring to be reset
  3487. * (and the f/w appear to never have started).
  3488. */
  3489. for (j = 0; j < octeon_dev->num_oqs; j++)
  3490. writel(octeon_dev->droq[j]->max_count,
  3491. octeon_dev->droq[j]->pkts_credit_reg);
  3492. /* Enable the input and output queues for this Octeon device */
  3493. ret = octeon_dev->fn_list.enable_io_queues(octeon_dev);
  3494. if (ret) {
  3495. dev_err(&octeon_dev->pci_dev->dev, "Failed to enable input/output queues");
  3496. return ret;
  3497. }
  3498. atomic_set(&octeon_dev->status, OCT_DEV_IO_QUEUES_DONE);
  3499. if (fw_state == FW_NEEDS_TO_BE_LOADED) {
  3500. dev_dbg(&octeon_dev->pci_dev->dev, "Waiting for DDR initialization...\n");
  3501. if (!ddr_timeout) {
  3502. dev_info(&octeon_dev->pci_dev->dev,
  3503. "WAITING. Set ddr_timeout to non-zero value to proceed with initialization.\n");
  3504. }
  3505. schedule_timeout_uninterruptible(HZ * LIO_RESET_SECS);
  3506. /* Wait for the octeon to initialize DDR after the soft-reset.*/
  3507. while (!ddr_timeout) {
  3508. set_current_state(TASK_INTERRUPTIBLE);
  3509. if (schedule_timeout(HZ / 10)) {
  3510. /* user probably pressed Control-C */
  3511. return 1;
  3512. }
  3513. }
  3514. ret = octeon_wait_for_ddr_init(octeon_dev, &ddr_timeout);
  3515. if (ret) {
  3516. dev_err(&octeon_dev->pci_dev->dev,
  3517. "DDR not initialized. Please confirm that board is configured to boot from Flash, ret: %d\n",
  3518. ret);
  3519. return 1;
  3520. }
  3521. if (octeon_wait_for_bootloader(octeon_dev, 1000)) {
  3522. dev_err(&octeon_dev->pci_dev->dev, "Board not responding\n");
  3523. return 1;
  3524. }
  3525. /* Divert uboot to take commands from host instead. */
  3526. ret = octeon_console_send_cmd(octeon_dev, bootcmd, 50);
  3527. dev_dbg(&octeon_dev->pci_dev->dev, "Initializing consoles\n");
  3528. ret = octeon_init_consoles(octeon_dev);
  3529. if (ret) {
  3530. dev_err(&octeon_dev->pci_dev->dev, "Could not access board consoles\n");
  3531. return 1;
  3532. }
  3533. /* If console debug enabled, specify empty string to use default
  3534. * enablement ELSE specify NULL string for 'disabled'.
  3535. */
  3536. dbg_enb = octeon_console_debug_enabled(0) ? "" : NULL;
  3537. ret = octeon_add_console(octeon_dev, 0, dbg_enb);
  3538. if (ret) {
  3539. dev_err(&octeon_dev->pci_dev->dev, "Could not access board console\n");
  3540. return 1;
  3541. } else if (octeon_console_debug_enabled(0)) {
  3542. /* If console was added AND we're logging console output
  3543. * then set our console print function.
  3544. */
  3545. octeon_dev->console[0].print = octeon_dbg_console_print;
  3546. }
  3547. atomic_set(&octeon_dev->status, OCT_DEV_CONSOLE_INIT_DONE);
  3548. dev_dbg(&octeon_dev->pci_dev->dev, "Loading firmware\n");
  3549. ret = load_firmware(octeon_dev);
  3550. if (ret) {
  3551. dev_err(&octeon_dev->pci_dev->dev, "Could not load firmware to board\n");
  3552. return 1;
  3553. }
  3554. atomic_set(octeon_dev->adapter_fw_state, FW_HAS_BEEN_LOADED);
  3555. }
  3556. handshake[octeon_dev->octeon_id].init_ok = 1;
  3557. complete(&handshake[octeon_dev->octeon_id].init);
  3558. atomic_set(&octeon_dev->status, OCT_DEV_HOST_OK);
  3559. oct_priv->dev = octeon_dev;
  3560. return 0;
  3561. }
  3562. /**
  3563. * octeon_dbg_console_print - Debug console print function
  3564. * @oct: octeon device
  3565. * @console_num: console number
  3566. * @prefix: first portion of line to display
  3567. * @suffix: second portion of line to display
  3568. *
  3569. * The OCTEON debug console outputs entire lines (excluding '\n').
  3570. * Normally, the line will be passed in the 'prefix' parameter.
  3571. * However, due to buffering, it is possible for a line to be split into two
  3572. * parts, in which case they will be passed as the 'prefix' parameter and
  3573. * 'suffix' parameter.
  3574. */
  3575. static int octeon_dbg_console_print(struct octeon_device *oct, u32 console_num,
  3576. char *prefix, char *suffix)
  3577. {
  3578. if (prefix && suffix)
  3579. dev_info(&oct->pci_dev->dev, "%u: %s%s\n", console_num, prefix,
  3580. suffix);
  3581. else if (prefix)
  3582. dev_info(&oct->pci_dev->dev, "%u: %s\n", console_num, prefix);
  3583. else if (suffix)
  3584. dev_info(&oct->pci_dev->dev, "%u: %s\n", console_num, suffix);
  3585. return 0;
  3586. }
  3587. /**
  3588. * liquidio_exit - Exits the module
  3589. */
  3590. static void __exit liquidio_exit(void)
  3591. {
  3592. liquidio_deinit_pci();
  3593. pr_info("LiquidIO network module is now unloaded\n");
  3594. }
  3595. module_init(liquidio_init);
  3596. module_exit(liquidio_exit);