cnic.c 149 KB

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  1. /* cnic.c: QLogic CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2014 Broadcom Corporation
  4. * Copyright (c) 2014-2015 QLogic Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. *
  10. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  11. * Previously modified and maintained by: Michael Chan <mchan@broadcom.com>
  12. * Maintained By: Dept-HSGLinuxNICDev@qlogic.com
  13. */
  14. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/errno.h>
  18. #include <linux/list.h>
  19. #include <linux/slab.h>
  20. #include <linux/pci.h>
  21. #include <linux/init.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/uio_driver.h>
  24. #include <linux/in.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/delay.h>
  27. #include <linux/ethtool.h>
  28. #include <linux/if_vlan.h>
  29. #include <linux/prefetch.h>
  30. #include <linux/random.h>
  31. #include <linux/workqueue.h>
  32. #if IS_ENABLED(CONFIG_VLAN_8021Q)
  33. #define BCM_VLAN 1
  34. #endif
  35. #include <net/ip.h>
  36. #include <net/tcp.h>
  37. #include <net/route.h>
  38. #include <net/ipv6.h>
  39. #include <net/ip6_route.h>
  40. #include <net/ip6_checksum.h>
  41. #include <scsi/iscsi_if.h>
  42. #define BCM_CNIC 1
  43. #include "cnic_if.h"
  44. #include "bnx2.h"
  45. #include "bnx2x/bnx2x.h"
  46. #include "bnx2x/bnx2x_reg.h"
  47. #include "bnx2x/bnx2x_fw_defs.h"
  48. #include "bnx2x/bnx2x_hsi.h"
  49. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  50. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  51. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  52. #include "cnic.h"
  53. #include "cnic_defs.h"
  54. #define CNIC_MODULE_NAME "cnic"
  55. static char version[] =
  56. "QLogic " CNIC_MODULE_NAME "Driver v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  57. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  58. "Chen (zongxi@broadcom.com");
  59. MODULE_DESCRIPTION("QLogic cnic Driver");
  60. MODULE_LICENSE("GPL");
  61. MODULE_VERSION(CNIC_MODULE_VERSION);
  62. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  63. static LIST_HEAD(cnic_dev_list);
  64. static LIST_HEAD(cnic_udev_list);
  65. static DEFINE_RWLOCK(cnic_dev_lock);
  66. static DEFINE_MUTEX(cnic_lock);
  67. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  68. /* helper function, assuming cnic_lock is held */
  69. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  70. {
  71. return rcu_dereference_protected(cnic_ulp_tbl[type],
  72. lockdep_is_held(&cnic_lock));
  73. }
  74. static int cnic_service_bnx2(void *, void *);
  75. static int cnic_service_bnx2x(void *, void *);
  76. static int cnic_ctl(void *, struct cnic_ctl_info *);
  77. static struct cnic_ops cnic_bnx2_ops = {
  78. .cnic_owner = THIS_MODULE,
  79. .cnic_handler = cnic_service_bnx2,
  80. .cnic_ctl = cnic_ctl,
  81. };
  82. static struct cnic_ops cnic_bnx2x_ops = {
  83. .cnic_owner = THIS_MODULE,
  84. .cnic_handler = cnic_service_bnx2x,
  85. .cnic_ctl = cnic_ctl,
  86. };
  87. static struct workqueue_struct *cnic_wq;
  88. static void cnic_shutdown_rings(struct cnic_dev *);
  89. static void cnic_init_rings(struct cnic_dev *);
  90. static int cnic_cm_set_pg(struct cnic_sock *);
  91. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  92. {
  93. struct cnic_uio_dev *udev = uinfo->priv;
  94. struct cnic_dev *dev;
  95. if (!capable(CAP_NET_ADMIN))
  96. return -EPERM;
  97. if (udev->uio_dev != -1)
  98. return -EBUSY;
  99. rtnl_lock();
  100. dev = udev->dev;
  101. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  102. rtnl_unlock();
  103. return -ENODEV;
  104. }
  105. udev->uio_dev = iminor(inode);
  106. cnic_shutdown_rings(dev);
  107. cnic_init_rings(dev);
  108. rtnl_unlock();
  109. return 0;
  110. }
  111. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  112. {
  113. struct cnic_uio_dev *udev = uinfo->priv;
  114. udev->uio_dev = -1;
  115. return 0;
  116. }
  117. static inline void cnic_hold(struct cnic_dev *dev)
  118. {
  119. atomic_inc(&dev->ref_count);
  120. }
  121. static inline void cnic_put(struct cnic_dev *dev)
  122. {
  123. atomic_dec(&dev->ref_count);
  124. }
  125. static inline void csk_hold(struct cnic_sock *csk)
  126. {
  127. atomic_inc(&csk->ref_count);
  128. }
  129. static inline void csk_put(struct cnic_sock *csk)
  130. {
  131. atomic_dec(&csk->ref_count);
  132. }
  133. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  134. {
  135. struct cnic_dev *cdev;
  136. read_lock(&cnic_dev_lock);
  137. list_for_each_entry(cdev, &cnic_dev_list, list) {
  138. if (netdev == cdev->netdev) {
  139. cnic_hold(cdev);
  140. read_unlock(&cnic_dev_lock);
  141. return cdev;
  142. }
  143. }
  144. read_unlock(&cnic_dev_lock);
  145. return NULL;
  146. }
  147. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  148. {
  149. atomic_inc(&ulp_ops->ref_count);
  150. }
  151. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  152. {
  153. atomic_dec(&ulp_ops->ref_count);
  154. }
  155. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  156. {
  157. struct cnic_local *cp = dev->cnic_priv;
  158. struct cnic_eth_dev *ethdev = cp->ethdev;
  159. struct drv_ctl_info info;
  160. struct drv_ctl_io *io = &info.data.io;
  161. memset(&info, 0, sizeof(struct drv_ctl_info));
  162. info.cmd = DRV_CTL_CTX_WR_CMD;
  163. io->cid_addr = cid_addr;
  164. io->offset = off;
  165. io->data = val;
  166. ethdev->drv_ctl(dev->netdev, &info);
  167. }
  168. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  169. {
  170. struct cnic_local *cp = dev->cnic_priv;
  171. struct cnic_eth_dev *ethdev = cp->ethdev;
  172. struct drv_ctl_info info;
  173. struct drv_ctl_io *io = &info.data.io;
  174. memset(&info, 0, sizeof(struct drv_ctl_info));
  175. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  176. io->offset = off;
  177. io->dma_addr = addr;
  178. ethdev->drv_ctl(dev->netdev, &info);
  179. }
  180. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  181. {
  182. struct cnic_local *cp = dev->cnic_priv;
  183. struct cnic_eth_dev *ethdev = cp->ethdev;
  184. struct drv_ctl_info info;
  185. struct drv_ctl_l2_ring *ring = &info.data.ring;
  186. memset(&info, 0, sizeof(struct drv_ctl_info));
  187. if (start)
  188. info.cmd = DRV_CTL_START_L2_CMD;
  189. else
  190. info.cmd = DRV_CTL_STOP_L2_CMD;
  191. ring->cid = cid;
  192. ring->client_id = cl_id;
  193. ethdev->drv_ctl(dev->netdev, &info);
  194. }
  195. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  196. {
  197. struct cnic_local *cp = dev->cnic_priv;
  198. struct cnic_eth_dev *ethdev = cp->ethdev;
  199. struct drv_ctl_info info;
  200. struct drv_ctl_io *io = &info.data.io;
  201. memset(&info, 0, sizeof(struct drv_ctl_info));
  202. info.cmd = DRV_CTL_IO_WR_CMD;
  203. io->offset = off;
  204. io->data = val;
  205. ethdev->drv_ctl(dev->netdev, &info);
  206. }
  207. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  208. {
  209. struct cnic_local *cp = dev->cnic_priv;
  210. struct cnic_eth_dev *ethdev = cp->ethdev;
  211. struct drv_ctl_info info;
  212. struct drv_ctl_io *io = &info.data.io;
  213. memset(&info, 0, sizeof(struct drv_ctl_info));
  214. info.cmd = DRV_CTL_IO_RD_CMD;
  215. io->offset = off;
  216. ethdev->drv_ctl(dev->netdev, &info);
  217. return io->data;
  218. }
  219. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg, int state)
  220. {
  221. struct cnic_local *cp = dev->cnic_priv;
  222. struct cnic_eth_dev *ethdev = cp->ethdev;
  223. struct drv_ctl_info info;
  224. struct fcoe_capabilities *fcoe_cap =
  225. &info.data.register_data.fcoe_features;
  226. memset(&info, 0, sizeof(struct drv_ctl_info));
  227. if (reg) {
  228. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  229. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  230. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  231. } else {
  232. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  233. }
  234. info.data.ulp_type = ulp_type;
  235. info.drv_state = state;
  236. ethdev->drv_ctl(dev->netdev, &info);
  237. }
  238. static int cnic_in_use(struct cnic_sock *csk)
  239. {
  240. return test_bit(SK_F_INUSE, &csk->flags);
  241. }
  242. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  243. {
  244. struct cnic_local *cp = dev->cnic_priv;
  245. struct cnic_eth_dev *ethdev = cp->ethdev;
  246. struct drv_ctl_info info;
  247. memset(&info, 0, sizeof(struct drv_ctl_info));
  248. info.cmd = cmd;
  249. info.data.credit.credit_count = count;
  250. ethdev->drv_ctl(dev->netdev, &info);
  251. }
  252. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  253. {
  254. u32 i;
  255. if (!cp->ctx_tbl)
  256. return -EINVAL;
  257. for (i = 0; i < cp->max_cid_space; i++) {
  258. if (cp->ctx_tbl[i].cid == cid) {
  259. *l5_cid = i;
  260. return 0;
  261. }
  262. }
  263. return -EINVAL;
  264. }
  265. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  266. struct cnic_sock *csk)
  267. {
  268. struct iscsi_path path_req;
  269. char *buf = NULL;
  270. u16 len = 0;
  271. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  272. struct cnic_ulp_ops *ulp_ops;
  273. struct cnic_uio_dev *udev = cp->udev;
  274. int rc = 0, retry = 0;
  275. if (!udev || udev->uio_dev == -1)
  276. return -ENODEV;
  277. if (csk) {
  278. len = sizeof(path_req);
  279. buf = (char *) &path_req;
  280. memset(&path_req, 0, len);
  281. msg_type = ISCSI_KEVENT_PATH_REQ;
  282. path_req.handle = (u64) csk->l5_cid;
  283. if (test_bit(SK_F_IPV6, &csk->flags)) {
  284. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  285. sizeof(struct in6_addr));
  286. path_req.ip_addr_len = 16;
  287. } else {
  288. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  289. sizeof(struct in_addr));
  290. path_req.ip_addr_len = 4;
  291. }
  292. path_req.vlan_id = csk->vlan_id;
  293. path_req.pmtu = csk->mtu;
  294. }
  295. while (retry < 3) {
  296. rc = 0;
  297. rcu_read_lock();
  298. ulp_ops = rcu_dereference(cp->ulp_ops[CNIC_ULP_ISCSI]);
  299. if (ulp_ops)
  300. rc = ulp_ops->iscsi_nl_send_msg(
  301. cp->ulp_handle[CNIC_ULP_ISCSI],
  302. msg_type, buf, len);
  303. rcu_read_unlock();
  304. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  305. break;
  306. msleep(100);
  307. retry++;
  308. }
  309. return rc;
  310. }
  311. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  312. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  313. char *buf, u16 len)
  314. {
  315. int rc = -EINVAL;
  316. switch (msg_type) {
  317. case ISCSI_UEVENT_PATH_UPDATE: {
  318. struct cnic_local *cp;
  319. u32 l5_cid;
  320. struct cnic_sock *csk;
  321. struct iscsi_path *path_resp;
  322. if (len < sizeof(*path_resp))
  323. break;
  324. path_resp = (struct iscsi_path *) buf;
  325. cp = dev->cnic_priv;
  326. l5_cid = (u32) path_resp->handle;
  327. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  328. break;
  329. if (!rcu_access_pointer(cp->ulp_ops[CNIC_ULP_L4])) {
  330. rc = -ENODEV;
  331. break;
  332. }
  333. csk = &cp->csk_tbl[l5_cid];
  334. csk_hold(csk);
  335. if (cnic_in_use(csk) &&
  336. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  337. csk->vlan_id = path_resp->vlan_id;
  338. memcpy(csk->ha, path_resp->mac_addr, ETH_ALEN);
  339. if (test_bit(SK_F_IPV6, &csk->flags))
  340. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  341. sizeof(struct in6_addr));
  342. else
  343. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  344. sizeof(struct in_addr));
  345. if (is_valid_ether_addr(csk->ha)) {
  346. cnic_cm_set_pg(csk);
  347. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  348. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  349. cnic_cm_upcall(cp, csk,
  350. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  351. clear_bit(SK_F_CONNECT_START, &csk->flags);
  352. }
  353. }
  354. csk_put(csk);
  355. rc = 0;
  356. }
  357. }
  358. return rc;
  359. }
  360. static int cnic_offld_prep(struct cnic_sock *csk)
  361. {
  362. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  363. return 0;
  364. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  365. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  366. return 0;
  367. }
  368. return 1;
  369. }
  370. static int cnic_close_prep(struct cnic_sock *csk)
  371. {
  372. clear_bit(SK_F_CONNECT_START, &csk->flags);
  373. smp_mb__after_atomic();
  374. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  375. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  376. msleep(1);
  377. return 1;
  378. }
  379. return 0;
  380. }
  381. static int cnic_abort_prep(struct cnic_sock *csk)
  382. {
  383. clear_bit(SK_F_CONNECT_START, &csk->flags);
  384. smp_mb__after_atomic();
  385. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  386. msleep(1);
  387. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  388. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  389. return 1;
  390. }
  391. return 0;
  392. }
  393. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  394. {
  395. struct cnic_dev *dev;
  396. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  397. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  398. return -EINVAL;
  399. }
  400. mutex_lock(&cnic_lock);
  401. if (cnic_ulp_tbl_prot(ulp_type)) {
  402. pr_err("%s: Type %d has already been registered\n",
  403. __func__, ulp_type);
  404. mutex_unlock(&cnic_lock);
  405. return -EBUSY;
  406. }
  407. read_lock(&cnic_dev_lock);
  408. list_for_each_entry(dev, &cnic_dev_list, list) {
  409. struct cnic_local *cp = dev->cnic_priv;
  410. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  411. }
  412. read_unlock(&cnic_dev_lock);
  413. atomic_set(&ulp_ops->ref_count, 0);
  414. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  415. mutex_unlock(&cnic_lock);
  416. /* Prevent race conditions with netdev_event */
  417. rtnl_lock();
  418. list_for_each_entry(dev, &cnic_dev_list, list) {
  419. struct cnic_local *cp = dev->cnic_priv;
  420. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  421. ulp_ops->cnic_init(dev);
  422. }
  423. rtnl_unlock();
  424. return 0;
  425. }
  426. int cnic_unregister_driver(int ulp_type)
  427. {
  428. struct cnic_dev *dev;
  429. struct cnic_ulp_ops *ulp_ops;
  430. int i = 0;
  431. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  432. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  433. return -EINVAL;
  434. }
  435. mutex_lock(&cnic_lock);
  436. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  437. if (!ulp_ops) {
  438. pr_err("%s: Type %d has not been registered\n",
  439. __func__, ulp_type);
  440. goto out_unlock;
  441. }
  442. read_lock(&cnic_dev_lock);
  443. list_for_each_entry(dev, &cnic_dev_list, list) {
  444. struct cnic_local *cp = dev->cnic_priv;
  445. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  446. pr_err("%s: Type %d still has devices registered\n",
  447. __func__, ulp_type);
  448. read_unlock(&cnic_dev_lock);
  449. goto out_unlock;
  450. }
  451. }
  452. read_unlock(&cnic_dev_lock);
  453. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  454. mutex_unlock(&cnic_lock);
  455. synchronize_rcu();
  456. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  457. msleep(100);
  458. i++;
  459. }
  460. if (atomic_read(&ulp_ops->ref_count) != 0)
  461. pr_warn("%s: Failed waiting for ref count to go to zero\n",
  462. __func__);
  463. return 0;
  464. out_unlock:
  465. mutex_unlock(&cnic_lock);
  466. return -EINVAL;
  467. }
  468. static int cnic_start_hw(struct cnic_dev *);
  469. static void cnic_stop_hw(struct cnic_dev *);
  470. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  471. void *ulp_ctx)
  472. {
  473. struct cnic_local *cp = dev->cnic_priv;
  474. struct cnic_ulp_ops *ulp_ops;
  475. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  476. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  477. return -EINVAL;
  478. }
  479. mutex_lock(&cnic_lock);
  480. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  481. pr_err("%s: Driver with type %d has not been registered\n",
  482. __func__, ulp_type);
  483. mutex_unlock(&cnic_lock);
  484. return -EAGAIN;
  485. }
  486. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  487. pr_err("%s: Type %d has already been registered to this device\n",
  488. __func__, ulp_type);
  489. mutex_unlock(&cnic_lock);
  490. return -EBUSY;
  491. }
  492. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  493. cp->ulp_handle[ulp_type] = ulp_ctx;
  494. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  495. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  496. cnic_hold(dev);
  497. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  498. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  499. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  500. mutex_unlock(&cnic_lock);
  501. cnic_ulp_ctl(dev, ulp_type, true, DRV_ACTIVE);
  502. return 0;
  503. }
  504. EXPORT_SYMBOL(cnic_register_driver);
  505. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  506. {
  507. struct cnic_local *cp = dev->cnic_priv;
  508. int i = 0;
  509. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  510. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  511. return -EINVAL;
  512. }
  513. if (ulp_type == CNIC_ULP_ISCSI)
  514. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  515. mutex_lock(&cnic_lock);
  516. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  517. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  518. cnic_put(dev);
  519. } else {
  520. pr_err("%s: device not registered to this ulp type %d\n",
  521. __func__, ulp_type);
  522. mutex_unlock(&cnic_lock);
  523. return -EINVAL;
  524. }
  525. mutex_unlock(&cnic_lock);
  526. if (ulp_type == CNIC_ULP_FCOE)
  527. dev->fcoe_cap = NULL;
  528. synchronize_rcu();
  529. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  530. i < 20) {
  531. msleep(100);
  532. i++;
  533. }
  534. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  535. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  536. if (test_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  537. cnic_ulp_ctl(dev, ulp_type, false, DRV_UNLOADED);
  538. else
  539. cnic_ulp_ctl(dev, ulp_type, false, DRV_INACTIVE);
  540. return 0;
  541. }
  542. EXPORT_SYMBOL(cnic_unregister_driver);
  543. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  544. u32 next)
  545. {
  546. id_tbl->start = start_id;
  547. id_tbl->max = size;
  548. id_tbl->next = next;
  549. spin_lock_init(&id_tbl->lock);
  550. id_tbl->table = bitmap_zalloc(size, GFP_KERNEL);
  551. if (!id_tbl->table)
  552. return -ENOMEM;
  553. return 0;
  554. }
  555. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  556. {
  557. bitmap_free(id_tbl->table);
  558. id_tbl->table = NULL;
  559. }
  560. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  561. {
  562. int ret = -1;
  563. id -= id_tbl->start;
  564. if (id >= id_tbl->max)
  565. return ret;
  566. spin_lock(&id_tbl->lock);
  567. if (!test_bit(id, id_tbl->table)) {
  568. set_bit(id, id_tbl->table);
  569. ret = 0;
  570. }
  571. spin_unlock(&id_tbl->lock);
  572. return ret;
  573. }
  574. /* Returns -1 if not successful */
  575. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  576. {
  577. u32 id;
  578. spin_lock(&id_tbl->lock);
  579. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  580. if (id >= id_tbl->max) {
  581. id = -1;
  582. if (id_tbl->next != 0) {
  583. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  584. if (id >= id_tbl->next)
  585. id = -1;
  586. }
  587. }
  588. if (id < id_tbl->max) {
  589. set_bit(id, id_tbl->table);
  590. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  591. id += id_tbl->start;
  592. }
  593. spin_unlock(&id_tbl->lock);
  594. return id;
  595. }
  596. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  597. {
  598. if (id == -1)
  599. return;
  600. id -= id_tbl->start;
  601. if (id >= id_tbl->max)
  602. return;
  603. clear_bit(id, id_tbl->table);
  604. }
  605. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  606. {
  607. int i;
  608. if (!dma->pg_arr)
  609. return;
  610. for (i = 0; i < dma->num_pages; i++) {
  611. if (dma->pg_arr[i]) {
  612. dma_free_coherent(&dev->pcidev->dev, CNIC_PAGE_SIZE,
  613. dma->pg_arr[i], dma->pg_map_arr[i]);
  614. dma->pg_arr[i] = NULL;
  615. }
  616. }
  617. if (dma->pgtbl) {
  618. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  619. dma->pgtbl, dma->pgtbl_map);
  620. dma->pgtbl = NULL;
  621. }
  622. kfree(dma->pg_arr);
  623. dma->pg_arr = NULL;
  624. dma->num_pages = 0;
  625. }
  626. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  627. {
  628. int i;
  629. __le32 *page_table = (__le32 *) dma->pgtbl;
  630. for (i = 0; i < dma->num_pages; i++) {
  631. /* Each entry needs to be in big endian format. */
  632. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  633. page_table++;
  634. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  635. page_table++;
  636. }
  637. }
  638. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  639. {
  640. int i;
  641. __le32 *page_table = (__le32 *) dma->pgtbl;
  642. for (i = 0; i < dma->num_pages; i++) {
  643. /* Each entry needs to be in little endian format. */
  644. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  645. page_table++;
  646. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  647. page_table++;
  648. }
  649. }
  650. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  651. int pages, int use_pg_tbl)
  652. {
  653. int i, size;
  654. struct cnic_local *cp = dev->cnic_priv;
  655. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  656. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  657. if (dma->pg_arr == NULL)
  658. return -ENOMEM;
  659. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  660. dma->num_pages = pages;
  661. for (i = 0; i < pages; i++) {
  662. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  663. CNIC_PAGE_SIZE,
  664. &dma->pg_map_arr[i],
  665. GFP_ATOMIC);
  666. if (dma->pg_arr[i] == NULL)
  667. goto error;
  668. }
  669. if (!use_pg_tbl)
  670. return 0;
  671. dma->pgtbl_size = ((pages * 8) + CNIC_PAGE_SIZE - 1) &
  672. ~(CNIC_PAGE_SIZE - 1);
  673. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  674. &dma->pgtbl_map, GFP_ATOMIC);
  675. if (dma->pgtbl == NULL)
  676. goto error;
  677. cp->setup_pgtbl(dev, dma);
  678. return 0;
  679. error:
  680. cnic_free_dma(dev, dma);
  681. return -ENOMEM;
  682. }
  683. static void cnic_free_context(struct cnic_dev *dev)
  684. {
  685. struct cnic_local *cp = dev->cnic_priv;
  686. int i;
  687. for (i = 0; i < cp->ctx_blks; i++) {
  688. if (cp->ctx_arr[i].ctx) {
  689. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  690. cp->ctx_arr[i].ctx,
  691. cp->ctx_arr[i].mapping);
  692. cp->ctx_arr[i].ctx = NULL;
  693. }
  694. }
  695. }
  696. static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
  697. {
  698. if (udev->l2_buf) {
  699. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  700. udev->l2_buf, udev->l2_buf_map);
  701. udev->l2_buf = NULL;
  702. }
  703. if (udev->l2_ring) {
  704. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  705. udev->l2_ring, udev->l2_ring_map);
  706. udev->l2_ring = NULL;
  707. }
  708. }
  709. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  710. {
  711. uio_unregister_device(&udev->cnic_uinfo);
  712. __cnic_free_uio_rings(udev);
  713. pci_dev_put(udev->pdev);
  714. kfree(udev);
  715. }
  716. static void cnic_free_uio(struct cnic_uio_dev *udev)
  717. {
  718. if (!udev)
  719. return;
  720. write_lock(&cnic_dev_lock);
  721. list_del_init(&udev->list);
  722. write_unlock(&cnic_dev_lock);
  723. __cnic_free_uio(udev);
  724. }
  725. static void cnic_free_resc(struct cnic_dev *dev)
  726. {
  727. struct cnic_local *cp = dev->cnic_priv;
  728. struct cnic_uio_dev *udev = cp->udev;
  729. if (udev) {
  730. udev->dev = NULL;
  731. cp->udev = NULL;
  732. if (udev->uio_dev == -1)
  733. __cnic_free_uio_rings(udev);
  734. }
  735. cnic_free_context(dev);
  736. kfree(cp->ctx_arr);
  737. cp->ctx_arr = NULL;
  738. cp->ctx_blks = 0;
  739. cnic_free_dma(dev, &cp->gbl_buf_info);
  740. cnic_free_dma(dev, &cp->kwq_info);
  741. cnic_free_dma(dev, &cp->kwq_16_data_info);
  742. cnic_free_dma(dev, &cp->kcq2.dma);
  743. cnic_free_dma(dev, &cp->kcq1.dma);
  744. kfree(cp->iscsi_tbl);
  745. cp->iscsi_tbl = NULL;
  746. kfree(cp->ctx_tbl);
  747. cp->ctx_tbl = NULL;
  748. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  749. cnic_free_id_tbl(&cp->cid_tbl);
  750. }
  751. static int cnic_alloc_context(struct cnic_dev *dev)
  752. {
  753. struct cnic_local *cp = dev->cnic_priv;
  754. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  755. int i, k, arr_size;
  756. cp->ctx_blk_size = CNIC_PAGE_SIZE;
  757. cp->cids_per_blk = CNIC_PAGE_SIZE / 128;
  758. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  759. sizeof(struct cnic_ctx);
  760. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  761. if (cp->ctx_arr == NULL)
  762. return -ENOMEM;
  763. k = 0;
  764. for (i = 0; i < 2; i++) {
  765. u32 j, reg, off, lo, hi;
  766. if (i == 0)
  767. off = BNX2_PG_CTX_MAP;
  768. else
  769. off = BNX2_ISCSI_CTX_MAP;
  770. reg = cnic_reg_rd_ind(dev, off);
  771. lo = reg >> 16;
  772. hi = reg & 0xffff;
  773. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  774. cp->ctx_arr[k].cid = j;
  775. }
  776. cp->ctx_blks = k;
  777. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  778. cp->ctx_blks = 0;
  779. return -ENOMEM;
  780. }
  781. for (i = 0; i < cp->ctx_blks; i++) {
  782. cp->ctx_arr[i].ctx =
  783. dma_alloc_coherent(&dev->pcidev->dev,
  784. CNIC_PAGE_SIZE,
  785. &cp->ctx_arr[i].mapping,
  786. GFP_KERNEL);
  787. if (cp->ctx_arr[i].ctx == NULL)
  788. return -ENOMEM;
  789. }
  790. }
  791. return 0;
  792. }
  793. static u16 cnic_bnx2_next_idx(u16 idx)
  794. {
  795. return idx + 1;
  796. }
  797. static u16 cnic_bnx2_hw_idx(u16 idx)
  798. {
  799. return idx;
  800. }
  801. static u16 cnic_bnx2x_next_idx(u16 idx)
  802. {
  803. idx++;
  804. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  805. idx++;
  806. return idx;
  807. }
  808. static u16 cnic_bnx2x_hw_idx(u16 idx)
  809. {
  810. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  811. idx++;
  812. return idx;
  813. }
  814. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  815. bool use_pg_tbl)
  816. {
  817. int err, i, use_page_tbl = 0;
  818. struct kcqe **kcq;
  819. if (use_pg_tbl)
  820. use_page_tbl = 1;
  821. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  822. if (err)
  823. return err;
  824. kcq = (struct kcqe **) info->dma.pg_arr;
  825. info->kcq = kcq;
  826. info->next_idx = cnic_bnx2_next_idx;
  827. info->hw_idx = cnic_bnx2_hw_idx;
  828. if (use_pg_tbl)
  829. return 0;
  830. info->next_idx = cnic_bnx2x_next_idx;
  831. info->hw_idx = cnic_bnx2x_hw_idx;
  832. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  833. struct bnx2x_bd_chain_next *next =
  834. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  835. int j = i + 1;
  836. if (j >= KCQ_PAGE_CNT)
  837. j = 0;
  838. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  839. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  840. }
  841. return 0;
  842. }
  843. static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
  844. {
  845. struct cnic_local *cp = udev->dev->cnic_priv;
  846. if (udev->l2_ring)
  847. return 0;
  848. udev->l2_ring_size = pages * CNIC_PAGE_SIZE;
  849. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  850. &udev->l2_ring_map, GFP_KERNEL);
  851. if (!udev->l2_ring)
  852. return -ENOMEM;
  853. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  854. udev->l2_buf_size = CNIC_PAGE_ALIGN(udev->l2_buf_size);
  855. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  856. &udev->l2_buf_map, GFP_KERNEL);
  857. if (!udev->l2_buf) {
  858. __cnic_free_uio_rings(udev);
  859. return -ENOMEM;
  860. }
  861. return 0;
  862. }
  863. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  864. {
  865. struct cnic_local *cp = dev->cnic_priv;
  866. struct cnic_uio_dev *udev;
  867. list_for_each_entry(udev, &cnic_udev_list, list) {
  868. if (udev->pdev == dev->pcidev) {
  869. udev->dev = dev;
  870. if (__cnic_alloc_uio_rings(udev, pages)) {
  871. udev->dev = NULL;
  872. return -ENOMEM;
  873. }
  874. cp->udev = udev;
  875. return 0;
  876. }
  877. }
  878. udev = kzalloc_obj(struct cnic_uio_dev, GFP_ATOMIC);
  879. if (!udev)
  880. return -ENOMEM;
  881. udev->uio_dev = -1;
  882. udev->dev = dev;
  883. udev->pdev = dev->pcidev;
  884. if (__cnic_alloc_uio_rings(udev, pages))
  885. goto err_udev;
  886. list_add(&udev->list, &cnic_udev_list);
  887. pci_dev_get(udev->pdev);
  888. cp->udev = udev;
  889. return 0;
  890. err_udev:
  891. kfree(udev);
  892. return -ENOMEM;
  893. }
  894. static int cnic_init_uio(struct cnic_dev *dev)
  895. {
  896. struct cnic_local *cp = dev->cnic_priv;
  897. struct cnic_uio_dev *udev = cp->udev;
  898. struct uio_info *uinfo;
  899. int ret = 0;
  900. if (!udev)
  901. return -ENOMEM;
  902. uinfo = &udev->cnic_uinfo;
  903. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  904. uinfo->mem[0].internal_addr = dev->regview;
  905. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  906. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  907. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  908. TX_MAX_TSS_RINGS + 1);
  909. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  910. CNIC_PAGE_MASK;
  911. uinfo->mem[1].dma_addr = cp->status_blk_map;
  912. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  913. uinfo->mem[1].size = PAGE_ALIGN(BNX2_SBLK_MSIX_ALIGN_SIZE * 9);
  914. else
  915. uinfo->mem[1].size = PAGE_ALIGN(BNX2_SBLK_MSIX_ALIGN_SIZE);
  916. uinfo->name = "bnx2_cnic";
  917. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  918. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  919. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  920. CNIC_PAGE_MASK;
  921. uinfo->mem[1].dma_addr = cp->status_blk_map;
  922. uinfo->mem[1].size = PAGE_ALIGN(sizeof(*cp->bnx2x_def_status_blk));
  923. uinfo->name = "bnx2x_cnic";
  924. }
  925. uinfo->mem[1].dma_device = &dev->pcidev->dev;
  926. uinfo->mem[1].memtype = UIO_MEM_DMA_COHERENT;
  927. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  928. uinfo->mem[2].dma_addr = udev->l2_ring_map;
  929. uinfo->mem[2].size = PAGE_ALIGN(udev->l2_ring_size);
  930. uinfo->mem[2].dma_device = &dev->pcidev->dev;
  931. uinfo->mem[2].memtype = UIO_MEM_DMA_COHERENT;
  932. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  933. uinfo->mem[3].dma_addr = udev->l2_buf_map;
  934. uinfo->mem[3].size = PAGE_ALIGN(udev->l2_buf_size);
  935. uinfo->mem[3].dma_device = &dev->pcidev->dev;
  936. uinfo->mem[3].memtype = UIO_MEM_DMA_COHERENT;
  937. uinfo->version = CNIC_MODULE_VERSION;
  938. uinfo->irq = UIO_IRQ_CUSTOM;
  939. uinfo->open = cnic_uio_open;
  940. uinfo->release = cnic_uio_close;
  941. if (udev->uio_dev == -1) {
  942. if (!uinfo->priv) {
  943. uinfo->priv = udev;
  944. ret = uio_register_device(&udev->pdev->dev, uinfo);
  945. }
  946. } else {
  947. cnic_init_rings(dev);
  948. }
  949. return ret;
  950. }
  951. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  952. {
  953. struct cnic_local *cp = dev->cnic_priv;
  954. int ret;
  955. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  956. if (ret)
  957. goto error;
  958. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  959. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  960. if (ret)
  961. goto error;
  962. ret = cnic_alloc_context(dev);
  963. if (ret)
  964. goto error;
  965. ret = cnic_alloc_uio_rings(dev, 2);
  966. if (ret)
  967. goto error;
  968. ret = cnic_init_uio(dev);
  969. if (ret)
  970. goto error;
  971. return 0;
  972. error:
  973. cnic_free_resc(dev);
  974. return ret;
  975. }
  976. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  977. {
  978. struct cnic_local *cp = dev->cnic_priv;
  979. struct bnx2x *bp = netdev_priv(dev->netdev);
  980. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  981. int total_mem, blks, i;
  982. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  983. blks = total_mem / ctx_blk_size;
  984. if (total_mem % ctx_blk_size)
  985. blks++;
  986. if (blks > cp->ethdev->ctx_tbl_len)
  987. return -ENOMEM;
  988. cp->ctx_arr = kzalloc_objs(struct cnic_ctx, blks);
  989. if (cp->ctx_arr == NULL)
  990. return -ENOMEM;
  991. cp->ctx_blks = blks;
  992. cp->ctx_blk_size = ctx_blk_size;
  993. if (!CHIP_IS_E1(bp))
  994. cp->ctx_align = 0;
  995. else
  996. cp->ctx_align = ctx_blk_size;
  997. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  998. for (i = 0; i < blks; i++) {
  999. cp->ctx_arr[i].ctx =
  1000. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  1001. &cp->ctx_arr[i].mapping,
  1002. GFP_KERNEL);
  1003. if (cp->ctx_arr[i].ctx == NULL)
  1004. return -ENOMEM;
  1005. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  1006. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  1007. cnic_free_context(dev);
  1008. cp->ctx_blk_size += cp->ctx_align;
  1009. i = -1;
  1010. continue;
  1011. }
  1012. }
  1013. }
  1014. return 0;
  1015. }
  1016. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  1017. {
  1018. struct cnic_local *cp = dev->cnic_priv;
  1019. struct bnx2x *bp = netdev_priv(dev->netdev);
  1020. struct cnic_eth_dev *ethdev = cp->ethdev;
  1021. u32 start_cid = ethdev->starting_cid;
  1022. int i, j, n, ret, pages;
  1023. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  1024. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  1025. cp->iscsi_start_cid = start_cid;
  1026. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  1027. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  1028. cp->max_cid_space += dev->max_fcoe_conn;
  1029. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  1030. if (!cp->fcoe_init_cid)
  1031. cp->fcoe_init_cid = 0x10;
  1032. }
  1033. cp->iscsi_tbl = kzalloc_objs(struct cnic_iscsi, MAX_ISCSI_TBL_SZ);
  1034. if (!cp->iscsi_tbl)
  1035. goto error;
  1036. cp->ctx_tbl = kzalloc_objs(struct cnic_context, cp->max_cid_space);
  1037. if (!cp->ctx_tbl)
  1038. goto error;
  1039. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1040. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1041. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1042. }
  1043. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1044. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1045. pages = CNIC_PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1046. CNIC_PAGE_SIZE;
  1047. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1048. if (ret)
  1049. goto error;
  1050. n = CNIC_PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1051. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1052. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1053. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1054. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1055. off;
  1056. if ((i % n) == (n - 1))
  1057. j++;
  1058. }
  1059. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1060. if (ret)
  1061. goto error;
  1062. if (CNIC_SUPPORTS_FCOE(bp)) {
  1063. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1064. if (ret)
  1065. goto error;
  1066. }
  1067. pages = CNIC_PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / CNIC_PAGE_SIZE;
  1068. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1069. if (ret)
  1070. goto error;
  1071. ret = cnic_alloc_bnx2x_context(dev);
  1072. if (ret)
  1073. goto error;
  1074. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  1075. return 0;
  1076. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1077. cp->status_blk_map = cp->ethdev->irq_arr[1].status_blk_map;
  1078. cp->l2_rx_ring_size = 15;
  1079. ret = cnic_alloc_uio_rings(dev, 4);
  1080. if (ret)
  1081. goto error;
  1082. ret = cnic_init_uio(dev);
  1083. if (ret)
  1084. goto error;
  1085. return 0;
  1086. error:
  1087. cnic_free_resc(dev);
  1088. return -ENOMEM;
  1089. }
  1090. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1091. {
  1092. return cp->max_kwq_idx -
  1093. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1094. }
  1095. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1096. u32 num_wqes)
  1097. {
  1098. struct cnic_local *cp = dev->cnic_priv;
  1099. struct kwqe *prod_qe;
  1100. u16 prod, sw_prod, i;
  1101. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1102. return -EAGAIN; /* bnx2 is down */
  1103. spin_lock_bh(&cp->cnic_ulp_lock);
  1104. if (num_wqes > cnic_kwq_avail(cp) &&
  1105. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1106. spin_unlock_bh(&cp->cnic_ulp_lock);
  1107. return -EAGAIN;
  1108. }
  1109. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1110. prod = cp->kwq_prod_idx;
  1111. sw_prod = prod & MAX_KWQ_IDX;
  1112. for (i = 0; i < num_wqes; i++) {
  1113. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1114. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1115. prod++;
  1116. sw_prod = prod & MAX_KWQ_IDX;
  1117. }
  1118. cp->kwq_prod_idx = prod;
  1119. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1120. spin_unlock_bh(&cp->cnic_ulp_lock);
  1121. return 0;
  1122. }
  1123. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1124. union l5cm_specific_data *l5_data)
  1125. {
  1126. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1127. dma_addr_t map;
  1128. map = ctx->kwqe_data_mapping;
  1129. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1130. l5_data->phy_address.hi = (u64) map >> 32;
  1131. return ctx->kwqe_data;
  1132. }
  1133. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1134. u32 type, union l5cm_specific_data *l5_data)
  1135. {
  1136. struct cnic_local *cp = dev->cnic_priv;
  1137. struct bnx2x *bp = netdev_priv(dev->netdev);
  1138. struct l5cm_spe kwqe;
  1139. struct kwqe_16 *kwq[1];
  1140. u16 type_16;
  1141. int ret;
  1142. kwqe.hdr.conn_and_cmd_data =
  1143. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1144. BNX2X_HW_CID(bp, cid)));
  1145. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1146. type_16 |= (bp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1147. SPE_HDR_FUNCTION_ID;
  1148. kwqe.hdr.type = cpu_to_le16(type_16);
  1149. kwqe.hdr.reserved1 = 0;
  1150. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1151. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1152. kwq[0] = (struct kwqe_16 *) &kwqe;
  1153. spin_lock_bh(&cp->cnic_ulp_lock);
  1154. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1155. spin_unlock_bh(&cp->cnic_ulp_lock);
  1156. if (ret == 1)
  1157. return 0;
  1158. return ret;
  1159. }
  1160. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1161. struct kcqe *cqes[], u32 num_cqes)
  1162. {
  1163. struct cnic_local *cp = dev->cnic_priv;
  1164. struct cnic_ulp_ops *ulp_ops;
  1165. rcu_read_lock();
  1166. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1167. if (likely(ulp_ops)) {
  1168. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1169. cqes, num_cqes);
  1170. }
  1171. rcu_read_unlock();
  1172. }
  1173. static void cnic_bnx2x_set_tcp_options(struct cnic_dev *dev, int time_stamps,
  1174. int en_tcp_dack)
  1175. {
  1176. struct bnx2x *bp = netdev_priv(dev->netdev);
  1177. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1178. u16 tstorm_flags = 0;
  1179. if (time_stamps) {
  1180. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1181. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1182. }
  1183. if (en_tcp_dack)
  1184. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN;
  1185. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1186. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), xstorm_flags);
  1187. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1188. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), tstorm_flags);
  1189. }
  1190. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1191. {
  1192. struct cnic_local *cp = dev->cnic_priv;
  1193. struct bnx2x *bp = netdev_priv(dev->netdev);
  1194. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1195. int hq_bds, pages;
  1196. u32 pfid = bp->pfid;
  1197. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1198. cp->num_ccells = req1->num_ccells_per_conn;
  1199. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1200. cp->num_iscsi_tasks;
  1201. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1202. BNX2X_ISCSI_R2TQE_SIZE;
  1203. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1204. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1205. hq_bds = pages * (CNIC_PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1206. cp->num_cqs = req1->num_cqs;
  1207. if (!dev->max_iscsi_conn)
  1208. return 0;
  1209. /* init Tstorm RAM */
  1210. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1211. req1->rq_num_wqes);
  1212. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1213. CNIC_PAGE_SIZE);
  1214. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1215. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1216. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1217. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1218. req1->num_tasks_per_conn);
  1219. /* init Ustorm RAM */
  1220. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1221. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1222. req1->rq_buffer_size);
  1223. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1224. CNIC_PAGE_SIZE);
  1225. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1226. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1227. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1228. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1229. req1->num_tasks_per_conn);
  1230. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1231. req1->rq_num_wqes);
  1232. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1233. req1->cq_num_wqes);
  1234. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1235. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1236. /* init Xstorm RAM */
  1237. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1238. CNIC_PAGE_SIZE);
  1239. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1240. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1241. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1242. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1243. req1->num_tasks_per_conn);
  1244. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1245. hq_bds);
  1246. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1247. req1->num_tasks_per_conn);
  1248. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1249. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1250. /* init Cstorm RAM */
  1251. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1252. CNIC_PAGE_SIZE);
  1253. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1254. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1255. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1256. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1257. req1->num_tasks_per_conn);
  1258. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1259. req1->cq_num_wqes);
  1260. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1261. hq_bds);
  1262. cnic_bnx2x_set_tcp_options(dev,
  1263. req1->flags & ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE,
  1264. req1->flags & ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE);
  1265. return 0;
  1266. }
  1267. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1268. {
  1269. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1270. struct bnx2x *bp = netdev_priv(dev->netdev);
  1271. u32 pfid = bp->pfid;
  1272. struct iscsi_kcqe kcqe;
  1273. struct kcqe *cqes[1];
  1274. memset(&kcqe, 0, sizeof(kcqe));
  1275. if (!dev->max_iscsi_conn) {
  1276. kcqe.completion_status =
  1277. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1278. goto done;
  1279. }
  1280. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1281. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1282. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1283. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1284. req2->error_bit_map[1]);
  1285. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1286. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1287. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1288. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1289. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1290. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1291. req2->error_bit_map[1]);
  1292. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1293. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1294. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1295. done:
  1296. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1297. cqes[0] = (struct kcqe *) &kcqe;
  1298. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1299. return 0;
  1300. }
  1301. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1302. {
  1303. struct cnic_local *cp = dev->cnic_priv;
  1304. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1305. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1306. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1307. cnic_free_dma(dev, &iscsi->hq_info);
  1308. cnic_free_dma(dev, &iscsi->r2tq_info);
  1309. cnic_free_dma(dev, &iscsi->task_array_info);
  1310. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1311. } else {
  1312. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1313. }
  1314. ctx->cid = 0;
  1315. }
  1316. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1317. {
  1318. u32 cid;
  1319. int ret, pages;
  1320. struct cnic_local *cp = dev->cnic_priv;
  1321. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1322. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1323. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1324. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1325. if (cid == -1) {
  1326. ret = -ENOMEM;
  1327. goto error;
  1328. }
  1329. ctx->cid = cid;
  1330. return 0;
  1331. }
  1332. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1333. if (cid == -1) {
  1334. ret = -ENOMEM;
  1335. goto error;
  1336. }
  1337. ctx->cid = cid;
  1338. pages = CNIC_PAGE_ALIGN(cp->task_array_size) / CNIC_PAGE_SIZE;
  1339. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1340. if (ret)
  1341. goto error;
  1342. pages = CNIC_PAGE_ALIGN(cp->r2tq_size) / CNIC_PAGE_SIZE;
  1343. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1344. if (ret)
  1345. goto error;
  1346. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1347. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1348. if (ret)
  1349. goto error;
  1350. return 0;
  1351. error:
  1352. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1353. return ret;
  1354. }
  1355. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1356. struct regpair *ctx_addr)
  1357. {
  1358. struct cnic_local *cp = dev->cnic_priv;
  1359. struct cnic_eth_dev *ethdev = cp->ethdev;
  1360. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1361. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1362. unsigned long align_off = 0;
  1363. dma_addr_t ctx_map;
  1364. void *ctx;
  1365. if (cp->ctx_align) {
  1366. unsigned long mask = cp->ctx_align - 1;
  1367. if (cp->ctx_arr[blk].mapping & mask)
  1368. align_off = cp->ctx_align -
  1369. (cp->ctx_arr[blk].mapping & mask);
  1370. }
  1371. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1372. (off * BNX2X_CONTEXT_MEM_SIZE);
  1373. ctx = cp->ctx_arr[blk].ctx + align_off +
  1374. (off * BNX2X_CONTEXT_MEM_SIZE);
  1375. if (init)
  1376. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1377. ctx_addr->lo = ctx_map & 0xffffffff;
  1378. ctx_addr->hi = (u64) ctx_map >> 32;
  1379. return ctx;
  1380. }
  1381. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1382. u32 num)
  1383. {
  1384. struct cnic_local *cp = dev->cnic_priv;
  1385. struct bnx2x *bp = netdev_priv(dev->netdev);
  1386. struct iscsi_kwqe_conn_offload1 *req1 =
  1387. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1388. struct iscsi_kwqe_conn_offload2 *req2 =
  1389. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1390. struct iscsi_kwqe_conn_offload3 *req3;
  1391. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1392. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1393. u32 cid = ctx->cid;
  1394. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1395. struct iscsi_context *ictx;
  1396. struct regpair context_addr;
  1397. int i, j, n = 2, n_max;
  1398. u8 port = BP_PORT(bp);
  1399. ctx->ctx_flags = 0;
  1400. if (!req2->num_additional_wqes)
  1401. return -EINVAL;
  1402. n_max = req2->num_additional_wqes + 2;
  1403. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1404. if (ictx == NULL)
  1405. return -ENOMEM;
  1406. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1407. ictx->xstorm_ag_context.hq_prod = 1;
  1408. ictx->xstorm_st_context.iscsi.first_burst_length =
  1409. ISCSI_DEF_FIRST_BURST_LEN;
  1410. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1411. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1412. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1413. req1->sq_page_table_addr_lo;
  1414. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1415. req1->sq_page_table_addr_hi;
  1416. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1417. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1418. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1419. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1420. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1421. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1422. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1423. iscsi->hq_info.pgtbl[0];
  1424. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1425. iscsi->hq_info.pgtbl[1];
  1426. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1427. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1428. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1429. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1430. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1431. iscsi->r2tq_info.pgtbl[0];
  1432. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1433. iscsi->r2tq_info.pgtbl[1];
  1434. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1435. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1436. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1437. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1438. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1439. BNX2X_ISCSI_PBL_NOT_CACHED;
  1440. ictx->xstorm_st_context.iscsi.flags.flags |=
  1441. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1442. ictx->xstorm_st_context.iscsi.flags.flags |=
  1443. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1444. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1445. ETH_P_8021Q;
  1446. if (BNX2X_CHIP_IS_E2_PLUS(bp) &&
  1447. bp->common.chip_port_mode == CHIP_2_PORT_MODE) {
  1448. port = 0;
  1449. }
  1450. ictx->xstorm_st_context.common.flags =
  1451. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1452. ictx->xstorm_st_context.common.flags =
  1453. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1454. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1455. /* TSTORM requires the base address of RQ DB & not PTE */
  1456. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1457. req2->rq_page_table_addr_lo & CNIC_PAGE_MASK;
  1458. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1459. req2->rq_page_table_addr_hi;
  1460. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1461. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1462. ictx->tstorm_st_context.tcp.flags2 |=
  1463. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1464. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1465. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1466. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1467. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1468. req2->rq_page_table_addr_lo;
  1469. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1470. req2->rq_page_table_addr_hi;
  1471. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1472. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1473. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1474. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1475. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1476. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1477. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1478. iscsi->r2tq_info.pgtbl[0];
  1479. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1480. iscsi->r2tq_info.pgtbl[1];
  1481. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1482. req1->cq_page_table_addr_lo;
  1483. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1484. req1->cq_page_table_addr_hi;
  1485. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1486. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1487. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1488. ictx->ustorm_st_context.task_pbe_cache_index =
  1489. BNX2X_ISCSI_PBL_NOT_CACHED;
  1490. ictx->ustorm_st_context.task_pdu_cache_index =
  1491. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1492. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1493. if (j == 3) {
  1494. if (n >= n_max)
  1495. break;
  1496. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1497. j = 0;
  1498. }
  1499. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1500. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1501. req3->qp_first_pte[j].hi;
  1502. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1503. req3->qp_first_pte[j].lo;
  1504. }
  1505. ictx->ustorm_st_context.task_pbl_base.lo =
  1506. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1507. ictx->ustorm_st_context.task_pbl_base.hi =
  1508. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1509. ictx->ustorm_st_context.tce_phy_addr.lo =
  1510. iscsi->task_array_info.pgtbl[0];
  1511. ictx->ustorm_st_context.tce_phy_addr.hi =
  1512. iscsi->task_array_info.pgtbl[1];
  1513. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1514. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1515. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1516. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1517. ISCSI_DEF_MAX_BURST_LEN;
  1518. ictx->ustorm_st_context.negotiated_rx |=
  1519. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1520. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1521. ictx->cstorm_st_context.hq_pbl_base.lo =
  1522. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1523. ictx->cstorm_st_context.hq_pbl_base.hi =
  1524. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1525. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1526. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1527. ictx->cstorm_st_context.task_pbl_base.lo =
  1528. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1529. ictx->cstorm_st_context.task_pbl_base.hi =
  1530. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1531. /* CSTORM and USTORM initialization is different, CSTORM requires
  1532. * CQ DB base & not PTE addr */
  1533. ictx->cstorm_st_context.cq_db_base.lo =
  1534. req1->cq_page_table_addr_lo & CNIC_PAGE_MASK;
  1535. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1536. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1537. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1538. for (i = 0; i < cp->num_cqs; i++) {
  1539. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1540. ISCSI_INITIAL_SN;
  1541. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1542. ISCSI_INITIAL_SN;
  1543. }
  1544. ictx->xstorm_ag_context.cdu_reserved =
  1545. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1546. ISCSI_CONNECTION_TYPE);
  1547. ictx->ustorm_ag_context.cdu_usage =
  1548. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1549. ISCSI_CONNECTION_TYPE);
  1550. return 0;
  1551. }
  1552. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1553. u32 num, int *work)
  1554. {
  1555. struct iscsi_kwqe_conn_offload1 *req1;
  1556. struct iscsi_kwqe_conn_offload2 *req2;
  1557. struct cnic_local *cp = dev->cnic_priv;
  1558. struct bnx2x *bp = netdev_priv(dev->netdev);
  1559. struct cnic_context *ctx;
  1560. struct iscsi_kcqe kcqe;
  1561. struct kcqe *cqes[1];
  1562. u32 l5_cid;
  1563. int ret = 0;
  1564. if (num < 2) {
  1565. *work = num;
  1566. return -EINVAL;
  1567. }
  1568. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1569. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1570. if ((num - 2) < req2->num_additional_wqes) {
  1571. *work = num;
  1572. return -EINVAL;
  1573. }
  1574. *work = 2 + req2->num_additional_wqes;
  1575. l5_cid = req1->iscsi_conn_id;
  1576. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1577. return -EINVAL;
  1578. memset(&kcqe, 0, sizeof(kcqe));
  1579. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1580. kcqe.iscsi_conn_id = l5_cid;
  1581. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1582. ctx = &cp->ctx_tbl[l5_cid];
  1583. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1584. kcqe.completion_status =
  1585. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1586. goto done;
  1587. }
  1588. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1589. atomic_dec(&cp->iscsi_conn);
  1590. goto done;
  1591. }
  1592. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1593. if (ret) {
  1594. atomic_dec(&cp->iscsi_conn);
  1595. goto done;
  1596. }
  1597. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1598. if (ret < 0) {
  1599. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1600. atomic_dec(&cp->iscsi_conn);
  1601. goto done;
  1602. }
  1603. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1604. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(bp, cp->ctx_tbl[l5_cid].cid);
  1605. done:
  1606. cqes[0] = (struct kcqe *) &kcqe;
  1607. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1608. return 0;
  1609. }
  1610. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1611. {
  1612. struct cnic_local *cp = dev->cnic_priv;
  1613. struct iscsi_kwqe_conn_update *req =
  1614. (struct iscsi_kwqe_conn_update *) kwqe;
  1615. void *data;
  1616. union l5cm_specific_data l5_data;
  1617. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1618. int ret;
  1619. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1620. return -EINVAL;
  1621. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1622. if (!data)
  1623. return -ENOMEM;
  1624. memcpy(data, kwqe, sizeof(struct kwqe));
  1625. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1626. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1627. return ret;
  1628. }
  1629. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1630. {
  1631. struct cnic_local *cp = dev->cnic_priv;
  1632. struct bnx2x *bp = netdev_priv(dev->netdev);
  1633. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1634. union l5cm_specific_data l5_data;
  1635. int ret;
  1636. u32 hw_cid;
  1637. init_waitqueue_head(&ctx->waitq);
  1638. ctx->wait_cond = 0;
  1639. memset(&l5_data, 0, sizeof(l5_data));
  1640. hw_cid = BNX2X_HW_CID(bp, ctx->cid);
  1641. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1642. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1643. if (ret == 0) {
  1644. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1645. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1646. return -EBUSY;
  1647. }
  1648. return 0;
  1649. }
  1650. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1651. {
  1652. struct cnic_local *cp = dev->cnic_priv;
  1653. struct iscsi_kwqe_conn_destroy *req =
  1654. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1655. u32 l5_cid = req->reserved0;
  1656. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1657. int ret = 0;
  1658. struct iscsi_kcqe kcqe;
  1659. struct kcqe *cqes[1];
  1660. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1661. goto skip_cfc_delete;
  1662. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1663. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1664. if (delta > (2 * HZ))
  1665. delta = 0;
  1666. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1667. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1668. goto destroy_reply;
  1669. }
  1670. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1671. skip_cfc_delete:
  1672. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1673. if (!ret) {
  1674. atomic_dec(&cp->iscsi_conn);
  1675. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1676. }
  1677. destroy_reply:
  1678. memset(&kcqe, 0, sizeof(kcqe));
  1679. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1680. kcqe.iscsi_conn_id = l5_cid;
  1681. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1682. kcqe.iscsi_conn_context_id = req->context_id;
  1683. cqes[0] = (struct kcqe *) &kcqe;
  1684. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1685. return 0;
  1686. }
  1687. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1688. struct l4_kwq_connect_req1 *kwqe1,
  1689. struct l4_kwq_connect_req3 *kwqe3,
  1690. struct l5cm_active_conn_buffer *conn_buf)
  1691. {
  1692. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1693. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1694. &conn_buf->xstorm_conn_buffer;
  1695. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1696. &conn_buf->tstorm_conn_buffer;
  1697. struct regpair context_addr;
  1698. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1699. struct in6_addr src_ip, dst_ip;
  1700. int i;
  1701. u32 *addrp;
  1702. addrp = (u32 *) &conn_addr->local_ip_addr;
  1703. for (i = 0; i < 4; i++, addrp++)
  1704. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1705. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1706. for (i = 0; i < 4; i++, addrp++)
  1707. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1708. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1709. xstorm_buf->context_addr.hi = context_addr.hi;
  1710. xstorm_buf->context_addr.lo = context_addr.lo;
  1711. xstorm_buf->mss = 0xffff;
  1712. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1713. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1714. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1715. xstorm_buf->pseudo_header_checksum =
  1716. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1717. if (kwqe3->ka_timeout) {
  1718. tstorm_buf->ka_enable = 1;
  1719. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1720. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1721. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1722. }
  1723. tstorm_buf->max_rt_time = 0xffffffff;
  1724. }
  1725. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1726. {
  1727. struct bnx2x *bp = netdev_priv(dev->netdev);
  1728. u32 pfid = bp->pfid;
  1729. u8 *mac = dev->mac_addr;
  1730. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1731. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1732. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1733. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1734. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1735. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1736. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1737. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1738. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1739. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1740. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1741. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1742. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1743. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1744. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1745. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1746. mac[4]);
  1747. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1748. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1749. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1750. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1751. mac[2]);
  1752. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1753. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1754. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1755. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1756. mac[0]);
  1757. }
  1758. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1759. u32 num, int *work)
  1760. {
  1761. struct cnic_local *cp = dev->cnic_priv;
  1762. struct bnx2x *bp = netdev_priv(dev->netdev);
  1763. struct l4_kwq_connect_req1 *kwqe1 =
  1764. (struct l4_kwq_connect_req1 *) wqes[0];
  1765. struct l4_kwq_connect_req3 *kwqe3;
  1766. struct l5cm_active_conn_buffer *conn_buf;
  1767. struct l5cm_conn_addr_params *conn_addr;
  1768. union l5cm_specific_data l5_data;
  1769. u32 l5_cid = kwqe1->pg_cid;
  1770. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1771. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1772. int ret;
  1773. if (num < 2) {
  1774. *work = num;
  1775. return -EINVAL;
  1776. }
  1777. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1778. *work = 3;
  1779. else
  1780. *work = 2;
  1781. if (num < *work) {
  1782. *work = num;
  1783. return -EINVAL;
  1784. }
  1785. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1786. netdev_err(dev->netdev, "conn_buf size too big\n");
  1787. return -ENOMEM;
  1788. }
  1789. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1790. if (!conn_buf)
  1791. return -ENOMEM;
  1792. memset(conn_buf, 0, sizeof(*conn_buf));
  1793. conn_addr = &conn_buf->conn_addr_buf;
  1794. conn_addr->remote_addr_0 = csk->ha[0];
  1795. conn_addr->remote_addr_1 = csk->ha[1];
  1796. conn_addr->remote_addr_2 = csk->ha[2];
  1797. conn_addr->remote_addr_3 = csk->ha[3];
  1798. conn_addr->remote_addr_4 = csk->ha[4];
  1799. conn_addr->remote_addr_5 = csk->ha[5];
  1800. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1801. struct l4_kwq_connect_req2 *kwqe2 =
  1802. (struct l4_kwq_connect_req2 *) wqes[1];
  1803. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1804. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1805. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1806. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1807. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1808. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1809. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1810. }
  1811. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1812. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1813. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1814. conn_addr->local_tcp_port = kwqe1->src_port;
  1815. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1816. conn_addr->pmtu = kwqe3->pmtu;
  1817. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1818. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1819. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(bp->pfid), csk->vlan_id);
  1820. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1821. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1822. if (!ret)
  1823. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1824. return ret;
  1825. }
  1826. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1827. {
  1828. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1829. union l5cm_specific_data l5_data;
  1830. int ret;
  1831. memset(&l5_data, 0, sizeof(l5_data));
  1832. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1833. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1834. return ret;
  1835. }
  1836. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1837. {
  1838. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1839. union l5cm_specific_data l5_data;
  1840. int ret;
  1841. memset(&l5_data, 0, sizeof(l5_data));
  1842. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1843. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1844. return ret;
  1845. }
  1846. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1847. {
  1848. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1849. struct l4_kcq kcqe;
  1850. struct kcqe *cqes[1];
  1851. memset(&kcqe, 0, sizeof(kcqe));
  1852. kcqe.pg_host_opaque = req->host_opaque;
  1853. kcqe.pg_cid = req->host_opaque;
  1854. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1855. cqes[0] = (struct kcqe *) &kcqe;
  1856. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1857. return 0;
  1858. }
  1859. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1860. {
  1861. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1862. struct l4_kcq kcqe;
  1863. struct kcqe *cqes[1];
  1864. memset(&kcqe, 0, sizeof(kcqe));
  1865. kcqe.pg_host_opaque = req->pg_host_opaque;
  1866. kcqe.pg_cid = req->pg_cid;
  1867. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1868. cqes[0] = (struct kcqe *) &kcqe;
  1869. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1870. return 0;
  1871. }
  1872. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1873. {
  1874. struct fcoe_kwqe_stat *req;
  1875. struct fcoe_stat_ramrod_params *fcoe_stat;
  1876. union l5cm_specific_data l5_data;
  1877. struct cnic_local *cp = dev->cnic_priv;
  1878. struct bnx2x *bp = netdev_priv(dev->netdev);
  1879. int ret;
  1880. u32 cid;
  1881. req = (struct fcoe_kwqe_stat *) kwqe;
  1882. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1883. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1884. if (!fcoe_stat)
  1885. return -ENOMEM;
  1886. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1887. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1888. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1889. FCOE_CONNECTION_TYPE, &l5_data);
  1890. return ret;
  1891. }
  1892. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1893. u32 num, int *work)
  1894. {
  1895. int ret;
  1896. struct cnic_local *cp = dev->cnic_priv;
  1897. struct bnx2x *bp = netdev_priv(dev->netdev);
  1898. u32 cid;
  1899. struct fcoe_init_ramrod_params *fcoe_init;
  1900. struct fcoe_kwqe_init1 *req1;
  1901. struct fcoe_kwqe_init2 *req2;
  1902. struct fcoe_kwqe_init3 *req3;
  1903. union l5cm_specific_data l5_data;
  1904. if (num < 3) {
  1905. *work = num;
  1906. return -EINVAL;
  1907. }
  1908. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1909. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1910. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1911. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1912. *work = 1;
  1913. return -EINVAL;
  1914. }
  1915. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1916. *work = 2;
  1917. return -EINVAL;
  1918. }
  1919. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1920. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1921. return -ENOMEM;
  1922. }
  1923. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1924. if (!fcoe_init)
  1925. return -ENOMEM;
  1926. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1927. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1928. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1929. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1930. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1931. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1932. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1933. fcoe_init->sb_num = cp->status_blk_num;
  1934. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1935. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1936. cp->kcq2.sw_prod_idx = 0;
  1937. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1938. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1939. FCOE_CONNECTION_TYPE, &l5_data);
  1940. *work = 3;
  1941. return ret;
  1942. }
  1943. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1944. u32 num, int *work)
  1945. {
  1946. int ret = 0;
  1947. u32 cid = -1, l5_cid;
  1948. struct cnic_local *cp = dev->cnic_priv;
  1949. struct bnx2x *bp = netdev_priv(dev->netdev);
  1950. struct fcoe_kwqe_conn_offload1 *req1;
  1951. struct fcoe_kwqe_conn_offload2 *req2;
  1952. struct fcoe_kwqe_conn_offload3 *req3;
  1953. struct fcoe_kwqe_conn_offload4 *req4;
  1954. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1955. struct cnic_context *ctx;
  1956. struct fcoe_context *fctx;
  1957. struct regpair ctx_addr;
  1958. union l5cm_specific_data l5_data;
  1959. struct fcoe_kcqe kcqe;
  1960. struct kcqe *cqes[1];
  1961. if (num < 4) {
  1962. *work = num;
  1963. return -EINVAL;
  1964. }
  1965. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1966. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1967. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1968. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1969. *work = 4;
  1970. l5_cid = req1->fcoe_conn_id;
  1971. if (l5_cid >= dev->max_fcoe_conn)
  1972. goto err_reply;
  1973. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1974. ctx = &cp->ctx_tbl[l5_cid];
  1975. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1976. goto err_reply;
  1977. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1978. if (ret) {
  1979. ret = 0;
  1980. goto err_reply;
  1981. }
  1982. cid = ctx->cid;
  1983. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1984. if (fctx) {
  1985. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1986. u32 val;
  1987. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1988. FCOE_CONNECTION_TYPE);
  1989. fctx->xstorm_ag_context.cdu_reserved = val;
  1990. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1991. FCOE_CONNECTION_TYPE);
  1992. fctx->ustorm_ag_context.cdu_usage = val;
  1993. }
  1994. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1995. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1996. goto err_reply;
  1997. }
  1998. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1999. if (!fcoe_offload)
  2000. goto err_reply;
  2001. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  2002. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  2003. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  2004. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  2005. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  2006. cid = BNX2X_HW_CID(bp, cid);
  2007. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  2008. FCOE_CONNECTION_TYPE, &l5_data);
  2009. if (!ret)
  2010. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  2011. return ret;
  2012. err_reply:
  2013. if (cid != -1)
  2014. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  2015. memset(&kcqe, 0, sizeof(kcqe));
  2016. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  2017. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  2018. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  2019. cqes[0] = (struct kcqe *) &kcqe;
  2020. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2021. return ret;
  2022. }
  2023. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  2024. {
  2025. struct fcoe_kwqe_conn_enable_disable *req;
  2026. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  2027. union l5cm_specific_data l5_data;
  2028. int ret;
  2029. u32 cid, l5_cid;
  2030. struct cnic_local *cp = dev->cnic_priv;
  2031. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2032. cid = req->context_id;
  2033. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  2034. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  2035. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  2036. return -ENOMEM;
  2037. }
  2038. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2039. if (!fcoe_enable)
  2040. return -ENOMEM;
  2041. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  2042. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  2043. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  2044. FCOE_CONNECTION_TYPE, &l5_data);
  2045. return ret;
  2046. }
  2047. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2048. {
  2049. struct fcoe_kwqe_conn_enable_disable *req;
  2050. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2051. union l5cm_specific_data l5_data;
  2052. int ret;
  2053. u32 cid, l5_cid;
  2054. struct cnic_local *cp = dev->cnic_priv;
  2055. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2056. cid = req->context_id;
  2057. l5_cid = req->conn_id;
  2058. if (l5_cid >= dev->max_fcoe_conn)
  2059. return -EINVAL;
  2060. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2061. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2062. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2063. return -ENOMEM;
  2064. }
  2065. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2066. if (!fcoe_disable)
  2067. return -ENOMEM;
  2068. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2069. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2070. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2071. FCOE_CONNECTION_TYPE, &l5_data);
  2072. return ret;
  2073. }
  2074. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2075. {
  2076. struct fcoe_kwqe_conn_destroy *req;
  2077. union l5cm_specific_data l5_data;
  2078. int ret;
  2079. u32 cid, l5_cid;
  2080. struct cnic_local *cp = dev->cnic_priv;
  2081. struct cnic_context *ctx;
  2082. struct fcoe_kcqe kcqe;
  2083. struct kcqe *cqes[1];
  2084. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2085. cid = req->context_id;
  2086. l5_cid = req->conn_id;
  2087. if (l5_cid >= dev->max_fcoe_conn)
  2088. return -EINVAL;
  2089. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2090. ctx = &cp->ctx_tbl[l5_cid];
  2091. init_waitqueue_head(&ctx->waitq);
  2092. ctx->wait_cond = 0;
  2093. memset(&kcqe, 0, sizeof(kcqe));
  2094. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2095. memset(&l5_data, 0, sizeof(l5_data));
  2096. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2097. FCOE_CONNECTION_TYPE, &l5_data);
  2098. if (ret == 0) {
  2099. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2100. if (ctx->wait_cond)
  2101. kcqe.completion_status = 0;
  2102. }
  2103. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2104. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2105. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2106. kcqe.fcoe_conn_id = req->conn_id;
  2107. kcqe.fcoe_conn_context_id = cid;
  2108. cqes[0] = (struct kcqe *) &kcqe;
  2109. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2110. return ret;
  2111. }
  2112. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2113. {
  2114. struct cnic_local *cp = dev->cnic_priv;
  2115. u32 i;
  2116. for (i = start_cid; i < cp->max_cid_space; i++) {
  2117. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2118. int j;
  2119. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2120. msleep(10);
  2121. for (j = 0; j < 5; j++) {
  2122. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2123. break;
  2124. msleep(20);
  2125. }
  2126. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2127. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2128. ctx->cid);
  2129. }
  2130. }
  2131. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2132. {
  2133. union l5cm_specific_data l5_data;
  2134. struct cnic_local *cp = dev->cnic_priv;
  2135. struct bnx2x *bp = netdev_priv(dev->netdev);
  2136. int ret;
  2137. u32 cid;
  2138. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2139. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  2140. memset(&l5_data, 0, sizeof(l5_data));
  2141. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2142. FCOE_CONNECTION_TYPE, &l5_data);
  2143. return ret;
  2144. }
  2145. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2146. {
  2147. struct cnic_local *cp = dev->cnic_priv;
  2148. struct kcqe kcqe;
  2149. struct kcqe *cqes[1];
  2150. u32 cid;
  2151. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2152. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2153. u32 kcqe_op;
  2154. int ulp_type;
  2155. cid = kwqe->kwqe_info0;
  2156. memset(&kcqe, 0, sizeof(kcqe));
  2157. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2158. u32 l5_cid = 0;
  2159. ulp_type = CNIC_ULP_FCOE;
  2160. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2161. struct fcoe_kwqe_conn_enable_disable *req;
  2162. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2163. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2164. cid = req->context_id;
  2165. l5_cid = req->conn_id;
  2166. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2167. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2168. } else {
  2169. return;
  2170. }
  2171. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2172. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2173. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2174. kcqe.kcqe_info2 = cid;
  2175. kcqe.kcqe_info0 = l5_cid;
  2176. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2177. ulp_type = CNIC_ULP_ISCSI;
  2178. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2179. cid = kwqe->kwqe_info1;
  2180. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2181. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2182. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2183. kcqe.kcqe_info2 = cid;
  2184. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2185. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2186. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2187. ulp_type = CNIC_ULP_L4;
  2188. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2189. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2190. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2191. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2192. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2193. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2194. else
  2195. return;
  2196. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2197. KCQE_FLAGS_LAYER_MASK_L4;
  2198. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2199. l4kcqe->cid = cid;
  2200. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2201. } else {
  2202. return;
  2203. }
  2204. cqes[0] = &kcqe;
  2205. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2206. }
  2207. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2208. struct kwqe *wqes[], u32 num_wqes)
  2209. {
  2210. int i, work, ret;
  2211. u32 opcode;
  2212. struct kwqe *kwqe;
  2213. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2214. return -EAGAIN; /* bnx2 is down */
  2215. for (i = 0; i < num_wqes; ) {
  2216. kwqe = wqes[i];
  2217. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2218. work = 1;
  2219. switch (opcode) {
  2220. case ISCSI_KWQE_OPCODE_INIT1:
  2221. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2222. break;
  2223. case ISCSI_KWQE_OPCODE_INIT2:
  2224. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2225. break;
  2226. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2227. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2228. num_wqes - i, &work);
  2229. break;
  2230. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2231. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2232. break;
  2233. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2234. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2235. break;
  2236. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2237. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2238. &work);
  2239. break;
  2240. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2241. ret = cnic_bnx2x_close(dev, kwqe);
  2242. break;
  2243. case L4_KWQE_OPCODE_VALUE_RESET:
  2244. ret = cnic_bnx2x_reset(dev, kwqe);
  2245. break;
  2246. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2247. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2248. break;
  2249. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2250. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2251. break;
  2252. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2253. ret = 0;
  2254. break;
  2255. default:
  2256. ret = 0;
  2257. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2258. opcode);
  2259. break;
  2260. }
  2261. if (ret < 0) {
  2262. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2263. opcode);
  2264. /* Possibly bnx2x parity error, send completion
  2265. * to ulp drivers with error code to speed up
  2266. * cleanup and reset recovery.
  2267. */
  2268. if (ret == -EIO || ret == -EAGAIN)
  2269. cnic_bnx2x_kwqe_err(dev, kwqe);
  2270. }
  2271. i += work;
  2272. }
  2273. return 0;
  2274. }
  2275. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2276. struct kwqe *wqes[], u32 num_wqes)
  2277. {
  2278. struct bnx2x *bp = netdev_priv(dev->netdev);
  2279. int i, work, ret;
  2280. u32 opcode;
  2281. struct kwqe *kwqe;
  2282. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2283. return -EAGAIN; /* bnx2 is down */
  2284. if (!BNX2X_CHIP_IS_E2_PLUS(bp))
  2285. return -EINVAL;
  2286. for (i = 0; i < num_wqes; ) {
  2287. kwqe = wqes[i];
  2288. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2289. work = 1;
  2290. switch (opcode) {
  2291. case FCOE_KWQE_OPCODE_INIT1:
  2292. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2293. num_wqes - i, &work);
  2294. break;
  2295. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2296. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2297. num_wqes - i, &work);
  2298. break;
  2299. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2300. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2301. break;
  2302. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2303. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2304. break;
  2305. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2306. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2307. break;
  2308. case FCOE_KWQE_OPCODE_DESTROY:
  2309. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2310. break;
  2311. case FCOE_KWQE_OPCODE_STAT:
  2312. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2313. break;
  2314. default:
  2315. ret = 0;
  2316. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2317. opcode);
  2318. break;
  2319. }
  2320. if (ret < 0) {
  2321. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2322. opcode);
  2323. /* Possibly bnx2x parity error, send completion
  2324. * to ulp drivers with error code to speed up
  2325. * cleanup and reset recovery.
  2326. */
  2327. if (ret == -EIO || ret == -EAGAIN)
  2328. cnic_bnx2x_kwqe_err(dev, kwqe);
  2329. }
  2330. i += work;
  2331. }
  2332. return 0;
  2333. }
  2334. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2335. u32 num_wqes)
  2336. {
  2337. int ret = -EINVAL;
  2338. u32 layer_code;
  2339. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2340. return -EAGAIN; /* bnx2x is down */
  2341. if (!num_wqes)
  2342. return 0;
  2343. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2344. switch (layer_code) {
  2345. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2346. case KWQE_FLAGS_LAYER_MASK_L4:
  2347. case KWQE_FLAGS_LAYER_MASK_L2:
  2348. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2349. break;
  2350. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2351. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2352. break;
  2353. }
  2354. return ret;
  2355. }
  2356. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2357. {
  2358. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2359. return KCQE_FLAGS_LAYER_MASK_L4;
  2360. return opflag & KCQE_FLAGS_LAYER_MASK;
  2361. }
  2362. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2363. {
  2364. struct cnic_local *cp = dev->cnic_priv;
  2365. int i, j, comp = 0;
  2366. i = 0;
  2367. j = 1;
  2368. while (num_cqes) {
  2369. struct cnic_ulp_ops *ulp_ops;
  2370. int ulp_type;
  2371. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2372. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2373. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2374. comp++;
  2375. while (j < num_cqes) {
  2376. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2377. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2378. break;
  2379. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2380. comp++;
  2381. j++;
  2382. }
  2383. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2384. ulp_type = CNIC_ULP_RDMA;
  2385. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2386. ulp_type = CNIC_ULP_ISCSI;
  2387. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2388. ulp_type = CNIC_ULP_FCOE;
  2389. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2390. ulp_type = CNIC_ULP_L4;
  2391. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2392. goto end;
  2393. else {
  2394. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2395. kcqe_op_flag);
  2396. goto end;
  2397. }
  2398. rcu_read_lock();
  2399. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2400. if (likely(ulp_ops)) {
  2401. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2402. cp->completed_kcq + i, j);
  2403. }
  2404. rcu_read_unlock();
  2405. end:
  2406. num_cqes -= j;
  2407. i += j;
  2408. j = 1;
  2409. }
  2410. if (unlikely(comp))
  2411. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2412. }
  2413. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2414. {
  2415. struct cnic_local *cp = dev->cnic_priv;
  2416. u16 i, ri, hw_prod, last;
  2417. struct kcqe *kcqe;
  2418. int kcqe_cnt = 0, last_cnt = 0;
  2419. i = ri = last = info->sw_prod_idx;
  2420. ri &= MAX_KCQ_IDX;
  2421. hw_prod = *info->hw_prod_idx_ptr;
  2422. hw_prod = info->hw_idx(hw_prod);
  2423. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2424. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2425. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2426. i = info->next_idx(i);
  2427. ri = i & MAX_KCQ_IDX;
  2428. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2429. last_cnt = kcqe_cnt;
  2430. last = i;
  2431. }
  2432. }
  2433. info->sw_prod_idx = last;
  2434. return last_cnt;
  2435. }
  2436. static int cnic_l2_completion(struct cnic_local *cp)
  2437. {
  2438. u16 hw_cons, sw_cons;
  2439. struct cnic_uio_dev *udev = cp->udev;
  2440. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2441. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  2442. u32 cmd;
  2443. int comp = 0;
  2444. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2445. return 0;
  2446. hw_cons = *cp->rx_cons_ptr;
  2447. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2448. hw_cons++;
  2449. sw_cons = cp->rx_cons;
  2450. while (sw_cons != hw_cons) {
  2451. u8 cqe_fp_flags;
  2452. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2453. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2454. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2455. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2456. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2457. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2458. cmd == RAMROD_CMD_ID_ETH_HALT)
  2459. comp++;
  2460. }
  2461. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2462. }
  2463. return comp;
  2464. }
  2465. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2466. {
  2467. u16 rx_cons, tx_cons;
  2468. int comp = 0;
  2469. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2470. return;
  2471. rx_cons = *cp->rx_cons_ptr;
  2472. tx_cons = *cp->tx_cons_ptr;
  2473. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2474. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2475. comp = cnic_l2_completion(cp);
  2476. cp->tx_cons = tx_cons;
  2477. cp->rx_cons = rx_cons;
  2478. if (cp->udev)
  2479. uio_event_notify(&cp->udev->cnic_uinfo);
  2480. }
  2481. if (comp)
  2482. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2483. }
  2484. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2485. {
  2486. struct cnic_local *cp = dev->cnic_priv;
  2487. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2488. int kcqe_cnt;
  2489. /* status block index must be read before reading other fields */
  2490. rmb();
  2491. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2492. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2493. service_kcqes(dev, kcqe_cnt);
  2494. /* Tell compiler that status_blk fields can change. */
  2495. barrier();
  2496. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2497. /* status block index must be read first */
  2498. rmb();
  2499. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2500. }
  2501. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2502. cnic_chk_pkt_rings(cp);
  2503. return status_idx;
  2504. }
  2505. static int cnic_service_bnx2(void *data, void *status_blk)
  2506. {
  2507. struct cnic_dev *dev = data;
  2508. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2509. struct status_block *sblk = status_blk;
  2510. return sblk->status_idx;
  2511. }
  2512. return cnic_service_bnx2_queues(dev);
  2513. }
  2514. static void cnic_service_bnx2_msix(struct work_struct *work)
  2515. {
  2516. struct cnic_local *cp = from_work(cp, work, cnic_irq_bh_work);
  2517. struct cnic_dev *dev = cp->dev;
  2518. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2519. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2520. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2521. }
  2522. static void cnic_doirq(struct cnic_dev *dev)
  2523. {
  2524. struct cnic_local *cp = dev->cnic_priv;
  2525. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2526. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2527. prefetch(cp->status_blk.gen);
  2528. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2529. queue_work(system_bh_wq, &cp->cnic_irq_bh_work);
  2530. }
  2531. }
  2532. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2533. {
  2534. struct cnic_dev *dev = dev_instance;
  2535. struct cnic_local *cp = dev->cnic_priv;
  2536. if (cp->ack_int)
  2537. cp->ack_int(dev);
  2538. cnic_doirq(dev);
  2539. return IRQ_HANDLED;
  2540. }
  2541. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2542. u16 index, u8 op, u8 update)
  2543. {
  2544. struct bnx2x *bp = netdev_priv(dev->netdev);
  2545. u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp) * 32 +
  2546. COMMAND_REG_INT_ACK);
  2547. struct igu_ack_register igu_ack;
  2548. igu_ack.status_block_index = index;
  2549. igu_ack.sb_id_and_flags =
  2550. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2551. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2552. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2553. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2554. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2555. }
  2556. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2557. u16 index, u8 op, u8 update)
  2558. {
  2559. struct igu_regular cmd_data;
  2560. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2561. cmd_data.sb_id_and_flags =
  2562. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2563. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2564. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2565. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2566. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2567. }
  2568. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2569. {
  2570. struct cnic_local *cp = dev->cnic_priv;
  2571. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2572. IGU_INT_DISABLE, 0);
  2573. }
  2574. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2575. {
  2576. struct cnic_local *cp = dev->cnic_priv;
  2577. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2578. IGU_INT_DISABLE, 0);
  2579. }
  2580. static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
  2581. {
  2582. struct cnic_local *cp = dev->cnic_priv;
  2583. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
  2584. IGU_INT_ENABLE, 1);
  2585. }
  2586. static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
  2587. {
  2588. struct cnic_local *cp = dev->cnic_priv;
  2589. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
  2590. IGU_INT_ENABLE, 1);
  2591. }
  2592. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2593. {
  2594. u32 last_status = *info->status_idx_ptr;
  2595. int kcqe_cnt;
  2596. /* status block index must be read before reading the KCQ */
  2597. rmb();
  2598. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2599. service_kcqes(dev, kcqe_cnt);
  2600. /* Tell compiler that sblk fields can change. */
  2601. barrier();
  2602. last_status = *info->status_idx_ptr;
  2603. /* status block index must be read before reading the KCQ */
  2604. rmb();
  2605. }
  2606. return last_status;
  2607. }
  2608. static void cnic_service_bnx2x_bh_work(struct work_struct *work)
  2609. {
  2610. struct cnic_local *cp = from_work(cp, work, cnic_irq_bh_work);
  2611. struct cnic_dev *dev = cp->dev;
  2612. struct bnx2x *bp = netdev_priv(dev->netdev);
  2613. u32 status_idx, new_status_idx;
  2614. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2615. return;
  2616. while (1) {
  2617. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2618. CNIC_WR16(dev, cp->kcq1.io_addr,
  2619. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2620. if (!CNIC_SUPPORTS_FCOE(bp)) {
  2621. cp->arm_int(dev, status_idx);
  2622. break;
  2623. }
  2624. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2625. if (new_status_idx != status_idx)
  2626. continue;
  2627. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2628. MAX_KCQ_IDX);
  2629. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2630. status_idx, IGU_INT_ENABLE, 1);
  2631. break;
  2632. }
  2633. }
  2634. static int cnic_service_bnx2x(void *data, void *status_blk)
  2635. {
  2636. struct cnic_dev *dev = data;
  2637. struct cnic_local *cp = dev->cnic_priv;
  2638. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2639. cnic_doirq(dev);
  2640. cnic_chk_pkt_rings(cp);
  2641. return 0;
  2642. }
  2643. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2644. {
  2645. struct cnic_ulp_ops *ulp_ops;
  2646. if (if_type == CNIC_ULP_ISCSI)
  2647. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2648. mutex_lock(&cnic_lock);
  2649. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2650. lockdep_is_held(&cnic_lock));
  2651. if (!ulp_ops) {
  2652. mutex_unlock(&cnic_lock);
  2653. return;
  2654. }
  2655. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2656. mutex_unlock(&cnic_lock);
  2657. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2658. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2659. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2660. }
  2661. static void cnic_ulp_stop(struct cnic_dev *dev)
  2662. {
  2663. struct cnic_local *cp = dev->cnic_priv;
  2664. int if_type;
  2665. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2666. cnic_ulp_stop_one(cp, if_type);
  2667. }
  2668. static void cnic_ulp_start(struct cnic_dev *dev)
  2669. {
  2670. struct cnic_local *cp = dev->cnic_priv;
  2671. int if_type;
  2672. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2673. struct cnic_ulp_ops *ulp_ops;
  2674. mutex_lock(&cnic_lock);
  2675. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2676. lockdep_is_held(&cnic_lock));
  2677. if (!ulp_ops || !ulp_ops->cnic_start) {
  2678. mutex_unlock(&cnic_lock);
  2679. continue;
  2680. }
  2681. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2682. mutex_unlock(&cnic_lock);
  2683. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2684. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2685. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2686. }
  2687. }
  2688. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2689. {
  2690. struct cnic_local *cp = dev->cnic_priv;
  2691. struct cnic_ulp_ops *ulp_ops;
  2692. int rc;
  2693. mutex_lock(&cnic_lock);
  2694. ulp_ops = rcu_dereference_protected(cp->ulp_ops[ulp_type],
  2695. lockdep_is_held(&cnic_lock));
  2696. if (ulp_ops && ulp_ops->cnic_get_stats)
  2697. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2698. else
  2699. rc = -ENODEV;
  2700. mutex_unlock(&cnic_lock);
  2701. return rc;
  2702. }
  2703. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2704. {
  2705. struct cnic_dev *dev = data;
  2706. int ulp_type = CNIC_ULP_ISCSI;
  2707. switch (info->cmd) {
  2708. case CNIC_CTL_STOP_CMD:
  2709. cnic_hold(dev);
  2710. cnic_ulp_stop(dev);
  2711. cnic_stop_hw(dev);
  2712. cnic_put(dev);
  2713. break;
  2714. case CNIC_CTL_START_CMD:
  2715. cnic_hold(dev);
  2716. if (!cnic_start_hw(dev))
  2717. cnic_ulp_start(dev);
  2718. cnic_put(dev);
  2719. break;
  2720. case CNIC_CTL_STOP_ISCSI_CMD: {
  2721. struct cnic_local *cp = dev->cnic_priv;
  2722. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2723. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2724. break;
  2725. }
  2726. case CNIC_CTL_COMPLETION_CMD: {
  2727. struct cnic_ctl_completion *comp = &info->data.comp;
  2728. u32 cid = BNX2X_SW_CID(comp->cid);
  2729. u32 l5_cid;
  2730. struct cnic_local *cp = dev->cnic_priv;
  2731. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2732. break;
  2733. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2734. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2735. if (unlikely(comp->error)) {
  2736. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2737. netdev_err(dev->netdev,
  2738. "CID %x CFC delete comp error %x\n",
  2739. cid, comp->error);
  2740. }
  2741. ctx->wait_cond = 1;
  2742. wake_up(&ctx->waitq);
  2743. }
  2744. break;
  2745. }
  2746. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2747. ulp_type = CNIC_ULP_FCOE;
  2748. fallthrough;
  2749. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2750. cnic_hold(dev);
  2751. cnic_copy_ulp_stats(dev, ulp_type);
  2752. cnic_put(dev);
  2753. break;
  2754. default:
  2755. return -EINVAL;
  2756. }
  2757. return 0;
  2758. }
  2759. static void cnic_ulp_init(struct cnic_dev *dev)
  2760. {
  2761. int i;
  2762. struct cnic_local *cp = dev->cnic_priv;
  2763. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2764. struct cnic_ulp_ops *ulp_ops;
  2765. mutex_lock(&cnic_lock);
  2766. ulp_ops = cnic_ulp_tbl_prot(i);
  2767. if (!ulp_ops || !ulp_ops->cnic_init) {
  2768. mutex_unlock(&cnic_lock);
  2769. continue;
  2770. }
  2771. ulp_get(ulp_ops);
  2772. mutex_unlock(&cnic_lock);
  2773. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2774. ulp_ops->cnic_init(dev);
  2775. ulp_put(ulp_ops);
  2776. }
  2777. }
  2778. static void cnic_ulp_exit(struct cnic_dev *dev)
  2779. {
  2780. int i;
  2781. struct cnic_local *cp = dev->cnic_priv;
  2782. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2783. struct cnic_ulp_ops *ulp_ops;
  2784. mutex_lock(&cnic_lock);
  2785. ulp_ops = cnic_ulp_tbl_prot(i);
  2786. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2787. mutex_unlock(&cnic_lock);
  2788. continue;
  2789. }
  2790. ulp_get(ulp_ops);
  2791. mutex_unlock(&cnic_lock);
  2792. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2793. ulp_ops->cnic_exit(dev);
  2794. ulp_put(ulp_ops);
  2795. }
  2796. }
  2797. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2798. {
  2799. struct cnic_dev *dev = csk->dev;
  2800. struct l4_kwq_offload_pg *l4kwqe;
  2801. struct kwqe *wqes[1];
  2802. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2803. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2804. wqes[0] = (struct kwqe *) l4kwqe;
  2805. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2806. l4kwqe->flags =
  2807. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2808. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2809. l4kwqe->da0 = csk->ha[0];
  2810. l4kwqe->da1 = csk->ha[1];
  2811. l4kwqe->da2 = csk->ha[2];
  2812. l4kwqe->da3 = csk->ha[3];
  2813. l4kwqe->da4 = csk->ha[4];
  2814. l4kwqe->da5 = csk->ha[5];
  2815. l4kwqe->sa0 = dev->mac_addr[0];
  2816. l4kwqe->sa1 = dev->mac_addr[1];
  2817. l4kwqe->sa2 = dev->mac_addr[2];
  2818. l4kwqe->sa3 = dev->mac_addr[3];
  2819. l4kwqe->sa4 = dev->mac_addr[4];
  2820. l4kwqe->sa5 = dev->mac_addr[5];
  2821. l4kwqe->etype = ETH_P_IP;
  2822. l4kwqe->ipid_start = DEF_IPID_START;
  2823. l4kwqe->host_opaque = csk->l5_cid;
  2824. if (csk->vlan_id) {
  2825. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2826. l4kwqe->vlan_tag = csk->vlan_id;
  2827. l4kwqe->l2hdr_nbytes += 4;
  2828. }
  2829. return dev->submit_kwqes(dev, wqes, 1);
  2830. }
  2831. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2832. {
  2833. struct cnic_dev *dev = csk->dev;
  2834. struct l4_kwq_update_pg *l4kwqe;
  2835. struct kwqe *wqes[1];
  2836. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2837. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2838. wqes[0] = (struct kwqe *) l4kwqe;
  2839. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2840. l4kwqe->flags =
  2841. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2842. l4kwqe->pg_cid = csk->pg_cid;
  2843. l4kwqe->da0 = csk->ha[0];
  2844. l4kwqe->da1 = csk->ha[1];
  2845. l4kwqe->da2 = csk->ha[2];
  2846. l4kwqe->da3 = csk->ha[3];
  2847. l4kwqe->da4 = csk->ha[4];
  2848. l4kwqe->da5 = csk->ha[5];
  2849. l4kwqe->pg_host_opaque = csk->l5_cid;
  2850. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2851. return dev->submit_kwqes(dev, wqes, 1);
  2852. }
  2853. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2854. {
  2855. struct cnic_dev *dev = csk->dev;
  2856. struct l4_kwq_upload *l4kwqe;
  2857. struct kwqe *wqes[1];
  2858. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2859. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2860. wqes[0] = (struct kwqe *) l4kwqe;
  2861. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2862. l4kwqe->flags =
  2863. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2864. l4kwqe->cid = csk->pg_cid;
  2865. return dev->submit_kwqes(dev, wqes, 1);
  2866. }
  2867. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2868. {
  2869. struct cnic_dev *dev = csk->dev;
  2870. struct l4_kwq_connect_req1 *l4kwqe1;
  2871. struct l4_kwq_connect_req2 *l4kwqe2;
  2872. struct l4_kwq_connect_req3 *l4kwqe3;
  2873. struct kwqe *wqes[3];
  2874. u8 tcp_flags = 0;
  2875. int num_wqes = 2;
  2876. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2877. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2878. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2879. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2880. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2881. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2882. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2883. l4kwqe3->flags =
  2884. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2885. l4kwqe3->ka_timeout = csk->ka_timeout;
  2886. l4kwqe3->ka_interval = csk->ka_interval;
  2887. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2888. l4kwqe3->tos = csk->tos;
  2889. l4kwqe3->ttl = csk->ttl;
  2890. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2891. l4kwqe3->pmtu = csk->mtu;
  2892. l4kwqe3->rcv_buf = csk->rcv_buf;
  2893. l4kwqe3->snd_buf = csk->snd_buf;
  2894. l4kwqe3->seed = csk->seed;
  2895. wqes[0] = (struct kwqe *) l4kwqe1;
  2896. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2897. wqes[1] = (struct kwqe *) l4kwqe2;
  2898. wqes[2] = (struct kwqe *) l4kwqe3;
  2899. num_wqes = 3;
  2900. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2901. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2902. l4kwqe2->flags =
  2903. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2904. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2905. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2906. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2907. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2908. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2909. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2910. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2911. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2912. sizeof(struct tcphdr);
  2913. } else {
  2914. wqes[1] = (struct kwqe *) l4kwqe3;
  2915. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2916. sizeof(struct tcphdr);
  2917. }
  2918. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2919. l4kwqe1->flags =
  2920. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2921. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2922. l4kwqe1->cid = csk->cid;
  2923. l4kwqe1->pg_cid = csk->pg_cid;
  2924. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2925. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2926. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2927. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2928. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2929. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2930. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2931. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2932. if (csk->tcp_flags & SK_TCP_NAGLE)
  2933. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2934. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2935. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2936. if (csk->tcp_flags & SK_TCP_SACK)
  2937. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2938. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2939. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2940. l4kwqe1->tcp_flags = tcp_flags;
  2941. return dev->submit_kwqes(dev, wqes, num_wqes);
  2942. }
  2943. static int cnic_cm_close_req(struct cnic_sock *csk)
  2944. {
  2945. struct cnic_dev *dev = csk->dev;
  2946. struct l4_kwq_close_req *l4kwqe;
  2947. struct kwqe *wqes[1];
  2948. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2949. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2950. wqes[0] = (struct kwqe *) l4kwqe;
  2951. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2952. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2953. l4kwqe->cid = csk->cid;
  2954. return dev->submit_kwqes(dev, wqes, 1);
  2955. }
  2956. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2957. {
  2958. struct cnic_dev *dev = csk->dev;
  2959. struct l4_kwq_reset_req *l4kwqe;
  2960. struct kwqe *wqes[1];
  2961. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2962. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2963. wqes[0] = (struct kwqe *) l4kwqe;
  2964. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2965. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2966. l4kwqe->cid = csk->cid;
  2967. return dev->submit_kwqes(dev, wqes, 1);
  2968. }
  2969. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2970. u32 l5_cid, struct cnic_sock **csk, void *context)
  2971. {
  2972. struct cnic_local *cp = dev->cnic_priv;
  2973. struct cnic_sock *csk1;
  2974. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2975. return -EINVAL;
  2976. if (cp->ctx_tbl) {
  2977. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2978. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2979. return -EAGAIN;
  2980. }
  2981. csk1 = &cp->csk_tbl[l5_cid];
  2982. if (atomic_read(&csk1->ref_count))
  2983. return -EAGAIN;
  2984. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2985. return -EBUSY;
  2986. csk1->dev = dev;
  2987. csk1->cid = cid;
  2988. csk1->l5_cid = l5_cid;
  2989. csk1->ulp_type = ulp_type;
  2990. csk1->context = context;
  2991. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2992. csk1->ka_interval = DEF_KA_INTERVAL;
  2993. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2994. csk1->tos = DEF_TOS;
  2995. csk1->ttl = DEF_TTL;
  2996. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2997. csk1->rcv_buf = DEF_RCV_BUF;
  2998. csk1->snd_buf = DEF_SND_BUF;
  2999. csk1->seed = DEF_SEED;
  3000. csk1->tcp_flags = 0;
  3001. *csk = csk1;
  3002. return 0;
  3003. }
  3004. static void cnic_cm_cleanup(struct cnic_sock *csk)
  3005. {
  3006. if (csk->src_port) {
  3007. struct cnic_dev *dev = csk->dev;
  3008. struct cnic_local *cp = dev->cnic_priv;
  3009. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  3010. csk->src_port = 0;
  3011. }
  3012. }
  3013. static void cnic_close_conn(struct cnic_sock *csk)
  3014. {
  3015. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  3016. cnic_cm_upload_pg(csk);
  3017. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3018. }
  3019. cnic_cm_cleanup(csk);
  3020. }
  3021. static int cnic_cm_destroy(struct cnic_sock *csk)
  3022. {
  3023. if (!cnic_in_use(csk))
  3024. return -EINVAL;
  3025. csk_hold(csk);
  3026. clear_bit(SK_F_INUSE, &csk->flags);
  3027. smp_mb__after_atomic();
  3028. while (atomic_read(&csk->ref_count) != 1)
  3029. msleep(1);
  3030. cnic_cm_cleanup(csk);
  3031. csk->flags = 0;
  3032. csk_put(csk);
  3033. return 0;
  3034. }
  3035. static inline u16 cnic_get_vlan(struct net_device *dev,
  3036. struct net_device **vlan_dev)
  3037. {
  3038. if (is_vlan_dev(dev)) {
  3039. *vlan_dev = vlan_dev_real_dev(dev);
  3040. return vlan_dev_vlan_id(dev);
  3041. }
  3042. *vlan_dev = dev;
  3043. return 0;
  3044. }
  3045. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  3046. struct dst_entry **dst)
  3047. {
  3048. #if defined(CONFIG_INET)
  3049. struct rtable *rt;
  3050. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0,
  3051. RT_SCOPE_UNIVERSE);
  3052. if (!IS_ERR(rt)) {
  3053. *dst = &rt->dst;
  3054. return 0;
  3055. }
  3056. return PTR_ERR(rt);
  3057. #else
  3058. return -ENETUNREACH;
  3059. #endif
  3060. }
  3061. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3062. struct dst_entry **dst)
  3063. {
  3064. #if IS_ENABLED(CONFIG_IPV6)
  3065. struct flowi6 fl6;
  3066. memset(&fl6, 0, sizeof(fl6));
  3067. fl6.daddr = dst_addr->sin6_addr;
  3068. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3069. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3070. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3071. if ((*dst)->error) {
  3072. dst_release(*dst);
  3073. *dst = NULL;
  3074. return -ENETUNREACH;
  3075. } else
  3076. return 0;
  3077. #endif
  3078. return -ENETUNREACH;
  3079. }
  3080. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3081. int ulp_type)
  3082. {
  3083. struct cnic_dev *dev = NULL;
  3084. struct dst_entry *dst;
  3085. struct net_device *netdev = NULL;
  3086. int err = -ENETUNREACH;
  3087. if (dst_addr->sin_family == AF_INET)
  3088. err = cnic_get_v4_route(dst_addr, &dst);
  3089. else if (dst_addr->sin_family == AF_INET6) {
  3090. struct sockaddr_in6 *dst_addr6 =
  3091. (struct sockaddr_in6 *) dst_addr;
  3092. err = cnic_get_v6_route(dst_addr6, &dst);
  3093. } else
  3094. return NULL;
  3095. if (err)
  3096. return NULL;
  3097. if (!dst->dev)
  3098. goto done;
  3099. cnic_get_vlan(dst->dev, &netdev);
  3100. dev = cnic_from_netdev(netdev);
  3101. done:
  3102. dst_release(dst);
  3103. if (dev)
  3104. cnic_put(dev);
  3105. return dev;
  3106. }
  3107. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3108. {
  3109. struct cnic_dev *dev = csk->dev;
  3110. struct cnic_local *cp = dev->cnic_priv;
  3111. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3112. }
  3113. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3114. {
  3115. struct cnic_dev *dev = csk->dev;
  3116. struct cnic_local *cp = dev->cnic_priv;
  3117. int is_v6, rc = 0;
  3118. struct dst_entry *dst = NULL;
  3119. struct net_device *realdev;
  3120. __be16 local_port;
  3121. u32 port_id;
  3122. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3123. saddr->remote.v6.sin6_family == AF_INET6)
  3124. is_v6 = 1;
  3125. else if (saddr->local.v4.sin_family == AF_INET &&
  3126. saddr->remote.v4.sin_family == AF_INET)
  3127. is_v6 = 0;
  3128. else
  3129. return -EINVAL;
  3130. clear_bit(SK_F_IPV6, &csk->flags);
  3131. if (is_v6) {
  3132. set_bit(SK_F_IPV6, &csk->flags);
  3133. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3134. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3135. sizeof(struct in6_addr));
  3136. csk->dst_port = saddr->remote.v6.sin6_port;
  3137. local_port = saddr->local.v6.sin6_port;
  3138. } else {
  3139. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3140. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3141. csk->dst_port = saddr->remote.v4.sin_port;
  3142. local_port = saddr->local.v4.sin_port;
  3143. }
  3144. csk->vlan_id = 0;
  3145. csk->mtu = dev->netdev->mtu;
  3146. if (dst && dst->dev) {
  3147. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3148. if (realdev == dev->netdev) {
  3149. csk->vlan_id = vlan;
  3150. csk->mtu = dst_mtu(dst);
  3151. }
  3152. }
  3153. port_id = be16_to_cpu(local_port);
  3154. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3155. port_id < CNIC_LOCAL_PORT_MAX) {
  3156. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3157. port_id = 0;
  3158. } else
  3159. port_id = 0;
  3160. if (!port_id) {
  3161. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3162. if (port_id == -1) {
  3163. rc = -ENOMEM;
  3164. goto err_out;
  3165. }
  3166. local_port = cpu_to_be16(port_id);
  3167. }
  3168. csk->src_port = local_port;
  3169. err_out:
  3170. dst_release(dst);
  3171. return rc;
  3172. }
  3173. static void cnic_init_csk_state(struct cnic_sock *csk)
  3174. {
  3175. csk->state = 0;
  3176. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3177. clear_bit(SK_F_CLOSING, &csk->flags);
  3178. }
  3179. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3180. {
  3181. struct cnic_local *cp = csk->dev->cnic_priv;
  3182. int err = 0;
  3183. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3184. return -EOPNOTSUPP;
  3185. if (!cnic_in_use(csk))
  3186. return -EINVAL;
  3187. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3188. return -EINVAL;
  3189. cnic_init_csk_state(csk);
  3190. err = cnic_get_route(csk, saddr);
  3191. if (err)
  3192. goto err_out;
  3193. err = cnic_resolve_addr(csk, saddr);
  3194. if (!err)
  3195. return 0;
  3196. err_out:
  3197. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3198. return err;
  3199. }
  3200. static int cnic_cm_abort(struct cnic_sock *csk)
  3201. {
  3202. struct cnic_local *cp = csk->dev->cnic_priv;
  3203. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3204. if (!cnic_in_use(csk))
  3205. return -EINVAL;
  3206. if (cnic_abort_prep(csk))
  3207. return cnic_cm_abort_req(csk);
  3208. /* Getting here means that we haven't started connect, or
  3209. * connect was not successful, or it has been reset by the target.
  3210. */
  3211. cp->close_conn(csk, opcode);
  3212. if (csk->state != opcode) {
  3213. /* Wait for remote reset sequence to complete */
  3214. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3215. msleep(1);
  3216. return -EALREADY;
  3217. }
  3218. return 0;
  3219. }
  3220. static int cnic_cm_close(struct cnic_sock *csk)
  3221. {
  3222. if (!cnic_in_use(csk))
  3223. return -EINVAL;
  3224. if (cnic_close_prep(csk)) {
  3225. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3226. return cnic_cm_close_req(csk);
  3227. } else {
  3228. /* Wait for remote reset sequence to complete */
  3229. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3230. msleep(1);
  3231. return -EALREADY;
  3232. }
  3233. return 0;
  3234. }
  3235. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3236. u8 opcode)
  3237. {
  3238. struct cnic_ulp_ops *ulp_ops;
  3239. int ulp_type = csk->ulp_type;
  3240. rcu_read_lock();
  3241. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3242. if (ulp_ops) {
  3243. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3244. ulp_ops->cm_connect_complete(csk);
  3245. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3246. ulp_ops->cm_close_complete(csk);
  3247. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3248. ulp_ops->cm_remote_abort(csk);
  3249. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3250. ulp_ops->cm_abort_complete(csk);
  3251. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3252. ulp_ops->cm_remote_close(csk);
  3253. }
  3254. rcu_read_unlock();
  3255. }
  3256. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3257. {
  3258. if (cnic_offld_prep(csk)) {
  3259. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3260. cnic_cm_update_pg(csk);
  3261. else
  3262. cnic_cm_offload_pg(csk);
  3263. }
  3264. return 0;
  3265. }
  3266. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3267. {
  3268. struct cnic_local *cp = dev->cnic_priv;
  3269. u32 l5_cid = kcqe->pg_host_opaque;
  3270. u8 opcode = kcqe->op_code;
  3271. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3272. csk_hold(csk);
  3273. if (!cnic_in_use(csk))
  3274. goto done;
  3275. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3276. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3277. goto done;
  3278. }
  3279. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3280. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3281. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3282. cnic_cm_upcall(cp, csk,
  3283. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3284. goto done;
  3285. }
  3286. csk->pg_cid = kcqe->pg_cid;
  3287. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3288. cnic_cm_conn_req(csk);
  3289. done:
  3290. csk_put(csk);
  3291. }
  3292. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3293. {
  3294. struct cnic_local *cp = dev->cnic_priv;
  3295. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3296. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3297. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3298. ctx->timestamp = jiffies;
  3299. ctx->wait_cond = 1;
  3300. wake_up(&ctx->waitq);
  3301. }
  3302. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3303. {
  3304. struct cnic_local *cp = dev->cnic_priv;
  3305. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3306. u8 opcode = l4kcqe->op_code;
  3307. u32 l5_cid;
  3308. struct cnic_sock *csk;
  3309. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3310. cnic_process_fcoe_term_conn(dev, kcqe);
  3311. return;
  3312. }
  3313. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3314. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3315. cnic_cm_process_offld_pg(dev, l4kcqe);
  3316. return;
  3317. }
  3318. l5_cid = l4kcqe->conn_id;
  3319. if (opcode & 0x80)
  3320. l5_cid = l4kcqe->cid;
  3321. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3322. return;
  3323. csk = &cp->csk_tbl[l5_cid];
  3324. csk_hold(csk);
  3325. if (!cnic_in_use(csk)) {
  3326. csk_put(csk);
  3327. return;
  3328. }
  3329. switch (opcode) {
  3330. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3331. if (l4kcqe->status != 0) {
  3332. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3333. cnic_cm_upcall(cp, csk,
  3334. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3335. }
  3336. break;
  3337. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3338. if (l4kcqe->status == 0)
  3339. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3340. else if (l4kcqe->status ==
  3341. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3342. set_bit(SK_F_HW_ERR, &csk->flags);
  3343. smp_mb__before_atomic();
  3344. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3345. cnic_cm_upcall(cp, csk, opcode);
  3346. break;
  3347. case L5CM_RAMROD_CMD_ID_CLOSE: {
  3348. struct iscsi_kcqe *l5kcqe = (struct iscsi_kcqe *) kcqe;
  3349. if (l4kcqe->status == 0 && l5kcqe->completion_status == 0)
  3350. break;
  3351. netdev_warn(dev->netdev, "RAMROD CLOSE compl with status 0x%x completion status 0x%x\n",
  3352. l4kcqe->status, l5kcqe->completion_status);
  3353. opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3354. }
  3355. fallthrough;
  3356. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3357. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3358. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3359. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3360. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3361. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3362. set_bit(SK_F_HW_ERR, &csk->flags);
  3363. cp->close_conn(csk, opcode);
  3364. break;
  3365. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3366. /* after we already sent CLOSE_REQ */
  3367. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3368. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3369. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3370. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3371. else
  3372. cnic_cm_upcall(cp, csk, opcode);
  3373. break;
  3374. }
  3375. csk_put(csk);
  3376. }
  3377. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3378. {
  3379. struct cnic_dev *dev = data;
  3380. int i;
  3381. for (i = 0; i < num; i++)
  3382. cnic_cm_process_kcqe(dev, kcqe[i]);
  3383. }
  3384. static struct cnic_ulp_ops cm_ulp_ops = {
  3385. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3386. };
  3387. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3388. {
  3389. struct cnic_local *cp = dev->cnic_priv;
  3390. kvfree(cp->csk_tbl);
  3391. cp->csk_tbl = NULL;
  3392. cnic_free_id_tbl(&cp->csk_port_tbl);
  3393. }
  3394. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3395. {
  3396. struct cnic_local *cp = dev->cnic_priv;
  3397. u32 port_id;
  3398. int i;
  3399. cp->csk_tbl = kvzalloc_objs(struct cnic_sock, MAX_CM_SK_TBL_SZ);
  3400. if (!cp->csk_tbl)
  3401. return -ENOMEM;
  3402. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++)
  3403. atomic_set(&cp->csk_tbl[i].ref_count, 0);
  3404. port_id = get_random_u32_below(CNIC_LOCAL_PORT_RANGE);
  3405. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3406. CNIC_LOCAL_PORT_MIN, port_id)) {
  3407. cnic_cm_free_mem(dev);
  3408. return -ENOMEM;
  3409. }
  3410. return 0;
  3411. }
  3412. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3413. {
  3414. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3415. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3416. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3417. csk->state = opcode;
  3418. }
  3419. /* 1. If event opcode matches the expected event in csk->state
  3420. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3421. * event
  3422. * 3. If the expected event is 0, meaning the connection was never
  3423. * never established, we accept the opcode from cm_abort.
  3424. */
  3425. if (opcode == csk->state || csk->state == 0 ||
  3426. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3427. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3428. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3429. if (csk->state == 0)
  3430. csk->state = opcode;
  3431. return 1;
  3432. }
  3433. }
  3434. return 0;
  3435. }
  3436. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3437. {
  3438. struct cnic_dev *dev = csk->dev;
  3439. struct cnic_local *cp = dev->cnic_priv;
  3440. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3441. cnic_cm_upcall(cp, csk, opcode);
  3442. return;
  3443. }
  3444. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3445. cnic_close_conn(csk);
  3446. csk->state = opcode;
  3447. cnic_cm_upcall(cp, csk, opcode);
  3448. }
  3449. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3450. {
  3451. }
  3452. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3453. {
  3454. u32 seed;
  3455. seed = get_random_u32();
  3456. cnic_ctx_wr(dev, 45, 0, seed);
  3457. return 0;
  3458. }
  3459. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3460. {
  3461. struct cnic_dev *dev = csk->dev;
  3462. struct cnic_local *cp = dev->cnic_priv;
  3463. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3464. union l5cm_specific_data l5_data;
  3465. u32 cmd = 0;
  3466. int close_complete = 0;
  3467. switch (opcode) {
  3468. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3469. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3470. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3471. if (cnic_ready_to_close(csk, opcode)) {
  3472. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3473. close_complete = 1;
  3474. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3475. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3476. else
  3477. close_complete = 1;
  3478. }
  3479. break;
  3480. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3481. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3482. break;
  3483. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3484. close_complete = 1;
  3485. break;
  3486. }
  3487. if (cmd) {
  3488. memset(&l5_data, 0, sizeof(l5_data));
  3489. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3490. &l5_data);
  3491. } else if (close_complete) {
  3492. ctx->timestamp = jiffies;
  3493. cnic_close_conn(csk);
  3494. cnic_cm_upcall(cp, csk, csk->state);
  3495. }
  3496. }
  3497. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3498. {
  3499. struct cnic_local *cp = dev->cnic_priv;
  3500. if (!cp->ctx_tbl)
  3501. return;
  3502. if (!netif_running(dev->netdev))
  3503. return;
  3504. cnic_bnx2x_delete_wait(dev, 0);
  3505. cancel_delayed_work_sync(&cp->delete_task);
  3506. if (atomic_read(&cp->iscsi_conn) != 0)
  3507. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3508. atomic_read(&cp->iscsi_conn));
  3509. }
  3510. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3511. {
  3512. struct bnx2x *bp = netdev_priv(dev->netdev);
  3513. u32 pfid = bp->pfid;
  3514. u32 port = BP_PORT(bp);
  3515. cnic_init_bnx2x_mac(dev);
  3516. cnic_bnx2x_set_tcp_options(dev, 0, 1);
  3517. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3518. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3519. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3520. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3521. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3522. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3523. DEF_MAX_DA_COUNT);
  3524. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3525. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3526. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3527. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3528. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3529. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3530. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3531. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3532. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3533. DEF_MAX_CWND);
  3534. return 0;
  3535. }
  3536. static void cnic_delete_task(struct work_struct *work)
  3537. {
  3538. struct cnic_local *cp;
  3539. struct cnic_dev *dev;
  3540. u32 i;
  3541. int need_resched = 0;
  3542. cp = container_of(work, struct cnic_local, delete_task.work);
  3543. dev = cp->dev;
  3544. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3545. struct drv_ctl_info info;
  3546. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3547. memset(&info, 0, sizeof(struct drv_ctl_info));
  3548. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3549. cp->ethdev->drv_ctl(dev->netdev, &info);
  3550. }
  3551. for (i = 0; i < cp->max_cid_space; i++) {
  3552. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3553. int err;
  3554. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3555. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3556. continue;
  3557. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3558. need_resched = 1;
  3559. continue;
  3560. }
  3561. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3562. continue;
  3563. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3564. cnic_free_bnx2x_conn_resc(dev, i);
  3565. if (!err) {
  3566. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3567. atomic_dec(&cp->iscsi_conn);
  3568. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3569. }
  3570. }
  3571. if (need_resched)
  3572. queue_delayed_work(cnic_wq, &cp->delete_task,
  3573. msecs_to_jiffies(10));
  3574. }
  3575. static int cnic_cm_open(struct cnic_dev *dev)
  3576. {
  3577. struct cnic_local *cp = dev->cnic_priv;
  3578. int err;
  3579. err = cnic_cm_alloc_mem(dev);
  3580. if (err)
  3581. return err;
  3582. err = cp->start_cm(dev);
  3583. if (err)
  3584. goto err_out;
  3585. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3586. dev->cm_create = cnic_cm_create;
  3587. dev->cm_destroy = cnic_cm_destroy;
  3588. dev->cm_connect = cnic_cm_connect;
  3589. dev->cm_abort = cnic_cm_abort;
  3590. dev->cm_close = cnic_cm_close;
  3591. dev->cm_select_dev = cnic_cm_select_dev;
  3592. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3593. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3594. return 0;
  3595. err_out:
  3596. cnic_cm_free_mem(dev);
  3597. return err;
  3598. }
  3599. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3600. {
  3601. struct cnic_local *cp = dev->cnic_priv;
  3602. int i;
  3603. if (!cp->csk_tbl)
  3604. return 0;
  3605. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3606. struct cnic_sock *csk = &cp->csk_tbl[i];
  3607. clear_bit(SK_F_INUSE, &csk->flags);
  3608. cnic_cm_cleanup(csk);
  3609. }
  3610. cnic_cm_free_mem(dev);
  3611. return 0;
  3612. }
  3613. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3614. {
  3615. u32 cid_addr;
  3616. int i;
  3617. cid_addr = GET_CID_ADDR(cid);
  3618. for (i = 0; i < CTX_SIZE; i += 4)
  3619. cnic_ctx_wr(dev, cid_addr, i, 0);
  3620. }
  3621. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3622. {
  3623. struct cnic_local *cp = dev->cnic_priv;
  3624. int ret = 0, i;
  3625. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3626. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3627. return 0;
  3628. for (i = 0; i < cp->ctx_blks; i++) {
  3629. int j;
  3630. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3631. u32 val;
  3632. memset(cp->ctx_arr[i].ctx, 0, CNIC_PAGE_SIZE);
  3633. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3634. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3635. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3636. (u64) cp->ctx_arr[i].mapping >> 32);
  3637. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3638. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3639. for (j = 0; j < 10; j++) {
  3640. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3641. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3642. break;
  3643. udelay(5);
  3644. }
  3645. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3646. ret = -EBUSY;
  3647. break;
  3648. }
  3649. }
  3650. return ret;
  3651. }
  3652. static void cnic_free_irq(struct cnic_dev *dev)
  3653. {
  3654. struct cnic_local *cp = dev->cnic_priv;
  3655. struct cnic_eth_dev *ethdev = cp->ethdev;
  3656. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3657. cp->disable_int_sync(dev);
  3658. cancel_work_sync(&cp->cnic_irq_bh_work);
  3659. free_irq(ethdev->irq_arr[0].vector, dev);
  3660. }
  3661. }
  3662. static int cnic_request_irq(struct cnic_dev *dev)
  3663. {
  3664. struct cnic_local *cp = dev->cnic_priv;
  3665. struct cnic_eth_dev *ethdev = cp->ethdev;
  3666. int err;
  3667. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3668. if (err)
  3669. disable_work_sync(&cp->cnic_irq_bh_work);
  3670. return err;
  3671. }
  3672. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3673. {
  3674. struct cnic_local *cp = dev->cnic_priv;
  3675. struct cnic_eth_dev *ethdev = cp->ethdev;
  3676. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3677. int err, i = 0;
  3678. int sblk_num = cp->status_blk_num;
  3679. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3680. BNX2_HC_SB_CONFIG_1;
  3681. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3682. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3683. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3684. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3685. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3686. INIT_WORK(&cp->cnic_irq_bh_work, cnic_service_bnx2_msix);
  3687. err = cnic_request_irq(dev);
  3688. if (err)
  3689. return err;
  3690. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3691. i < 10) {
  3692. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3693. 1 << (11 + sblk_num));
  3694. udelay(10);
  3695. i++;
  3696. barrier();
  3697. }
  3698. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3699. cnic_free_irq(dev);
  3700. goto failed;
  3701. }
  3702. } else {
  3703. struct status_block *sblk = cp->status_blk.gen;
  3704. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3705. int i = 0;
  3706. while (sblk->status_completion_producer_index && i < 10) {
  3707. CNIC_WR(dev, BNX2_HC_COMMAND,
  3708. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3709. udelay(10);
  3710. i++;
  3711. barrier();
  3712. }
  3713. if (sblk->status_completion_producer_index)
  3714. goto failed;
  3715. }
  3716. return 0;
  3717. failed:
  3718. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3719. return -EBUSY;
  3720. }
  3721. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3722. {
  3723. struct cnic_local *cp = dev->cnic_priv;
  3724. struct cnic_eth_dev *ethdev = cp->ethdev;
  3725. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3726. return;
  3727. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3728. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3729. }
  3730. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3731. {
  3732. struct cnic_local *cp = dev->cnic_priv;
  3733. struct cnic_eth_dev *ethdev = cp->ethdev;
  3734. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3735. return;
  3736. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3737. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3738. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3739. synchronize_irq(ethdev->irq_arr[0].vector);
  3740. }
  3741. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3742. {
  3743. struct cnic_local *cp = dev->cnic_priv;
  3744. struct cnic_eth_dev *ethdev = cp->ethdev;
  3745. struct cnic_uio_dev *udev = cp->udev;
  3746. u32 cid_addr, tx_cid, sb_id;
  3747. u32 val, offset0, offset1, offset2, offset3;
  3748. int i;
  3749. struct bnx2_tx_bd *txbd;
  3750. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3751. struct status_block *s_blk = cp->status_blk.gen;
  3752. sb_id = cp->status_blk_num;
  3753. tx_cid = 20;
  3754. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3755. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3756. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3757. tx_cid = TX_TSS_CID + sb_id - 1;
  3758. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3759. (TX_TSS_CID << 7));
  3760. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3761. }
  3762. cp->tx_cons = *cp->tx_cons_ptr;
  3763. cid_addr = GET_CID_ADDR(tx_cid);
  3764. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  3765. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3766. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3767. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3768. offset0 = BNX2_L2CTX_TYPE_XI;
  3769. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3770. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3771. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3772. } else {
  3773. cnic_init_context(dev, tx_cid);
  3774. cnic_init_context(dev, tx_cid + 1);
  3775. offset0 = BNX2_L2CTX_TYPE;
  3776. offset1 = BNX2_L2CTX_CMD_TYPE;
  3777. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3778. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3779. }
  3780. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3781. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3782. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3783. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3784. txbd = udev->l2_ring;
  3785. buf_map = udev->l2_buf_map;
  3786. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i++, txbd++) {
  3787. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3788. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3789. }
  3790. val = (u64) ring_map >> 32;
  3791. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3792. txbd->tx_bd_haddr_hi = val;
  3793. val = (u64) ring_map & 0xffffffff;
  3794. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3795. txbd->tx_bd_haddr_lo = val;
  3796. }
  3797. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3798. {
  3799. struct cnic_local *cp = dev->cnic_priv;
  3800. struct cnic_eth_dev *ethdev = cp->ethdev;
  3801. struct cnic_uio_dev *udev = cp->udev;
  3802. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3803. int i;
  3804. struct bnx2_rx_bd *rxbd;
  3805. struct status_block *s_blk = cp->status_blk.gen;
  3806. dma_addr_t ring_map = udev->l2_ring_map;
  3807. sb_id = cp->status_blk_num;
  3808. cnic_init_context(dev, 2);
  3809. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3810. coal_reg = BNX2_HC_COMMAND;
  3811. coal_val = CNIC_RD(dev, coal_reg);
  3812. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3813. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3814. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3815. coal_reg = BNX2_HC_COALESCE_NOW;
  3816. coal_val = 1 << (11 + sb_id);
  3817. }
  3818. i = 0;
  3819. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3820. CNIC_WR(dev, coal_reg, coal_val);
  3821. udelay(10);
  3822. i++;
  3823. barrier();
  3824. }
  3825. cp->rx_cons = *cp->rx_cons_ptr;
  3826. cid_addr = GET_CID_ADDR(2);
  3827. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3828. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3829. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3830. if (sb_id == 0)
  3831. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3832. else
  3833. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3834. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3835. rxbd = udev->l2_ring + CNIC_PAGE_SIZE;
  3836. for (i = 0; i < BNX2_MAX_RX_DESC_CNT; i++, rxbd++) {
  3837. dma_addr_t buf_map;
  3838. int n = (i % cp->l2_rx_ring_size) + 1;
  3839. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3840. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3841. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3842. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3843. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3844. }
  3845. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  3846. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3847. rxbd->rx_bd_haddr_hi = val;
  3848. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  3849. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3850. rxbd->rx_bd_haddr_lo = val;
  3851. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3852. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3853. }
  3854. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3855. {
  3856. struct kwqe *wqes[1], l2kwqe;
  3857. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3858. wqes[0] = &l2kwqe;
  3859. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3860. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3861. KWQE_OPCODE_SHIFT) | 2;
  3862. dev->submit_kwqes(dev, wqes, 1);
  3863. }
  3864. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3865. {
  3866. struct cnic_local *cp = dev->cnic_priv;
  3867. u32 val;
  3868. val = cp->func << 2;
  3869. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3870. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3871. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3872. dev->mac_addr[0] = (u8) (val >> 8);
  3873. dev->mac_addr[1] = (u8) val;
  3874. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3875. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3876. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3877. dev->mac_addr[2] = (u8) (val >> 24);
  3878. dev->mac_addr[3] = (u8) (val >> 16);
  3879. dev->mac_addr[4] = (u8) (val >> 8);
  3880. dev->mac_addr[5] = (u8) val;
  3881. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3882. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3883. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3884. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3885. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3886. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3887. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3888. }
  3889. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3890. {
  3891. struct cnic_local *cp = dev->cnic_priv;
  3892. struct cnic_eth_dev *ethdev = cp->ethdev;
  3893. struct status_block *sblk = cp->status_blk.gen;
  3894. u32 val, kcq_cid_addr, kwq_cid_addr;
  3895. int err;
  3896. cnic_set_bnx2_mac(dev);
  3897. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3898. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3899. if (CNIC_PAGE_BITS > 12)
  3900. val |= (12 - 8) << 4;
  3901. else
  3902. val |= (CNIC_PAGE_BITS - 8) << 4;
  3903. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3904. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3905. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3906. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3907. err = cnic_setup_5709_context(dev, 1);
  3908. if (err)
  3909. return err;
  3910. cnic_init_context(dev, KWQ_CID);
  3911. cnic_init_context(dev, KCQ_CID);
  3912. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3913. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3914. cp->max_kwq_idx = MAX_KWQ_IDX;
  3915. cp->kwq_prod_idx = 0;
  3916. cp->kwq_con_idx = 0;
  3917. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3918. if (BNX2_CHIP(cp) == BNX2_CHIP_5706 || BNX2_CHIP(cp) == BNX2_CHIP_5708)
  3919. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3920. else
  3921. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3922. /* Initialize the kernel work queue context. */
  3923. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3924. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3925. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3926. val = (CNIC_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3927. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3928. val = ((CNIC_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3929. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3930. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3931. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3932. val = (u32) cp->kwq_info.pgtbl_map;
  3933. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3934. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3935. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3936. cp->kcq1.sw_prod_idx = 0;
  3937. cp->kcq1.hw_prod_idx_ptr =
  3938. &sblk->status_completion_producer_index;
  3939. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3940. /* Initialize the kernel complete queue context. */
  3941. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3942. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3943. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3944. val = (CNIC_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3945. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3946. val = ((CNIC_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3947. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3948. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3949. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3950. val = (u32) cp->kcq1.dma.pgtbl_map;
  3951. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3952. cp->int_num = 0;
  3953. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3954. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3955. u32 sb_id = cp->status_blk_num;
  3956. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3957. cp->kcq1.hw_prod_idx_ptr =
  3958. &msblk->status_completion_producer_index;
  3959. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3960. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3961. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3962. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3963. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3964. }
  3965. /* Enable Commnad Scheduler notification when we write to the
  3966. * host producer index of the kernel contexts. */
  3967. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3968. /* Enable Command Scheduler notification when we write to either
  3969. * the Send Queue or Receive Queue producer indexes of the kernel
  3970. * bypass contexts. */
  3971. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3972. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3973. /* Notify COM when the driver post an application buffer. */
  3974. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3975. /* Set the CP and COM doorbells. These two processors polls the
  3976. * doorbell for a non zero value before running. This must be done
  3977. * after setting up the kernel queue contexts. */
  3978. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3979. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3980. cnic_init_bnx2_tx_ring(dev);
  3981. cnic_init_bnx2_rx_ring(dev);
  3982. err = cnic_init_bnx2_irq(dev);
  3983. if (err) {
  3984. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3985. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3986. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3987. return err;
  3988. }
  3989. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  3990. return 0;
  3991. }
  3992. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3993. {
  3994. struct cnic_local *cp = dev->cnic_priv;
  3995. struct cnic_eth_dev *ethdev = cp->ethdev;
  3996. u32 start_offset = ethdev->ctx_tbl_offset;
  3997. int i;
  3998. for (i = 0; i < cp->ctx_blks; i++) {
  3999. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  4000. dma_addr_t map = ctx->mapping;
  4001. if (cp->ctx_align) {
  4002. unsigned long mask = cp->ctx_align - 1;
  4003. map = (map + mask) & ~mask;
  4004. }
  4005. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  4006. }
  4007. }
  4008. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  4009. {
  4010. struct cnic_local *cp = dev->cnic_priv;
  4011. struct cnic_eth_dev *ethdev = cp->ethdev;
  4012. int err = 0;
  4013. INIT_WORK(&cp->cnic_irq_bh_work, cnic_service_bnx2x_bh_work);
  4014. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  4015. err = cnic_request_irq(dev);
  4016. return err;
  4017. }
  4018. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  4019. u16 sb_id, u8 sb_index,
  4020. u8 disable)
  4021. {
  4022. struct bnx2x *bp = netdev_priv(dev->netdev);
  4023. u32 addr = BAR_CSTRORM_INTMEM +
  4024. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4025. offsetof(struct hc_status_block_data_e1x, index_data) +
  4026. sizeof(struct hc_index_data)*sb_index +
  4027. offsetof(struct hc_index_data, flags);
  4028. u16 flags = CNIC_RD16(dev, addr);
  4029. /* clear and set */
  4030. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  4031. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  4032. HC_INDEX_DATA_HC_ENABLED);
  4033. CNIC_WR16(dev, addr, flags);
  4034. }
  4035. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  4036. {
  4037. struct cnic_local *cp = dev->cnic_priv;
  4038. struct bnx2x *bp = netdev_priv(dev->netdev);
  4039. u8 sb_id = cp->status_blk_num;
  4040. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4041. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4042. offsetof(struct hc_status_block_data_e1x, index_data) +
  4043. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  4044. offsetof(struct hc_index_data, timeout), 64 / 4);
  4045. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  4046. }
  4047. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  4048. {
  4049. }
  4050. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  4051. struct client_init_ramrod_data *data)
  4052. {
  4053. struct cnic_local *cp = dev->cnic_priv;
  4054. struct bnx2x *bp = netdev_priv(dev->netdev);
  4055. struct cnic_uio_dev *udev = cp->udev;
  4056. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  4057. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  4058. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4059. int i;
  4060. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4061. u32 val;
  4062. memset(txbd, 0, CNIC_PAGE_SIZE);
  4063. buf_map = udev->l2_buf_map;
  4064. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  4065. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  4066. struct eth_tx_parse_bd_e1x *pbd_e1x =
  4067. &((txbd + 1)->parse_bd_e1x);
  4068. struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
  4069. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  4070. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4071. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4072. reg_bd->addr_hi = start_bd->addr_hi;
  4073. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  4074. start_bd->nbytes = cpu_to_le16(0x10);
  4075. start_bd->nbd = cpu_to_le16(3);
  4076. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  4077. start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
  4078. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  4079. if (BNX2X_CHIP_IS_E2_PLUS(bp))
  4080. pbd_e2->parsing_data = (UNICAST_ADDRESS <<
  4081. ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
  4082. else
  4083. pbd_e1x->global_data = (UNICAST_ADDRESS <<
  4084. ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
  4085. }
  4086. val = (u64) ring_map >> 32;
  4087. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4088. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4089. val = (u64) ring_map & 0xffffffff;
  4090. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4091. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4092. /* Other ramrod params */
  4093. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4094. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4095. /* reset xstorm per client statistics */
  4096. if (cli < MAX_STAT_COUNTER_ID) {
  4097. data->general.statistics_zero_flg = 1;
  4098. data->general.statistics_en_flg = 1;
  4099. data->general.statistics_counter_id = cli;
  4100. }
  4101. cp->tx_cons_ptr =
  4102. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4103. }
  4104. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4105. struct client_init_ramrod_data *data)
  4106. {
  4107. struct cnic_local *cp = dev->cnic_priv;
  4108. struct bnx2x *bp = netdev_priv(dev->netdev);
  4109. struct cnic_uio_dev *udev = cp->udev;
  4110. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4111. CNIC_PAGE_SIZE);
  4112. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4113. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  4114. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4115. int i;
  4116. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4117. int cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4118. u32 val;
  4119. dma_addr_t ring_map = udev->l2_ring_map;
  4120. /* General data */
  4121. data->general.client_id = cli;
  4122. data->general.activate_flg = 1;
  4123. data->general.sp_client_id = cli;
  4124. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4125. data->general.func_id = bp->pfid;
  4126. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4127. dma_addr_t buf_map;
  4128. int n = (i % cp->l2_rx_ring_size) + 1;
  4129. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4130. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4131. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4132. }
  4133. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  4134. rxbd->addr_hi = cpu_to_le32(val);
  4135. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4136. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  4137. rxbd->addr_lo = cpu_to_le32(val);
  4138. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4139. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4140. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) >> 32;
  4141. rxcqe->addr_hi = cpu_to_le32(val);
  4142. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4143. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) & 0xffffffff;
  4144. rxcqe->addr_lo = cpu_to_le32(val);
  4145. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4146. /* Other ramrod params */
  4147. data->rx.client_qzone_id = cl_qzone_id;
  4148. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4149. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4150. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4151. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4152. data->rx.outer_vlan_removal_enable_flg = 1;
  4153. data->rx.silent_vlan_removal_flg = 1;
  4154. data->rx.silent_vlan_value = 0;
  4155. data->rx.silent_vlan_mask = 0xffff;
  4156. cp->rx_cons_ptr =
  4157. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4158. cp->rx_cons = *cp->rx_cons_ptr;
  4159. }
  4160. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4161. {
  4162. struct cnic_local *cp = dev->cnic_priv;
  4163. struct bnx2x *bp = netdev_priv(dev->netdev);
  4164. u32 pfid = bp->pfid;
  4165. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4166. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4167. cp->kcq1.sw_prod_idx = 0;
  4168. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4169. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4170. cp->kcq1.hw_prod_idx_ptr =
  4171. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4172. cp->kcq1.status_idx_ptr =
  4173. &sb->sb.running_index[SM_RX_ID];
  4174. } else {
  4175. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4176. cp->kcq1.hw_prod_idx_ptr =
  4177. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4178. cp->kcq1.status_idx_ptr =
  4179. &sb->sb.running_index[SM_RX_ID];
  4180. }
  4181. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4182. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4183. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4184. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4185. cp->kcq2.sw_prod_idx = 0;
  4186. cp->kcq2.hw_prod_idx_ptr =
  4187. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4188. cp->kcq2.status_idx_ptr =
  4189. &sb->sb.running_index[SM_RX_ID];
  4190. }
  4191. }
  4192. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4193. {
  4194. struct cnic_local *cp = dev->cnic_priv;
  4195. struct bnx2x *bp = netdev_priv(dev->netdev);
  4196. struct cnic_eth_dev *ethdev = cp->ethdev;
  4197. int ret;
  4198. u32 pfid;
  4199. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4200. cp->func = bp->pf_num;
  4201. pfid = bp->pfid;
  4202. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4203. cp->iscsi_start_cid, 0);
  4204. if (ret)
  4205. return -ENOMEM;
  4206. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4207. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4208. cp->fcoe_start_cid, 0);
  4209. if (ret)
  4210. return -ENOMEM;
  4211. }
  4212. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4213. cnic_init_bnx2x_kcq(dev);
  4214. /* Only 1 EQ */
  4215. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4216. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4217. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4218. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4219. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4220. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4221. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4222. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4223. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4224. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4225. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4226. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4227. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4228. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4229. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4230. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4231. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4232. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4233. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4234. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4235. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4236. HC_INDEX_ISCSI_EQ_CONS);
  4237. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4238. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4239. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4240. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4241. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4242. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4243. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4244. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4245. cnic_setup_bnx2x_context(dev);
  4246. ret = cnic_init_bnx2x_irq(dev);
  4247. if (ret)
  4248. return ret;
  4249. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  4250. return 0;
  4251. }
  4252. static void cnic_init_rings(struct cnic_dev *dev)
  4253. {
  4254. struct cnic_local *cp = dev->cnic_priv;
  4255. struct bnx2x *bp = netdev_priv(dev->netdev);
  4256. struct cnic_uio_dev *udev = cp->udev;
  4257. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4258. return;
  4259. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4260. cnic_init_bnx2_tx_ring(dev);
  4261. cnic_init_bnx2_rx_ring(dev);
  4262. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4263. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4264. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4265. u32 cid = cp->ethdev->iscsi_l2_cid;
  4266. u32 cl_qzone_id;
  4267. struct client_init_ramrod_data *data;
  4268. union l5cm_specific_data l5_data;
  4269. struct ustorm_eth_rx_producers rx_prods = {0};
  4270. u32 off, i, *cid_ptr;
  4271. rx_prods.bd_prod = 0;
  4272. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4273. barrier();
  4274. cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4275. off = BAR_USTRORM_INTMEM +
  4276. (BNX2X_CHIP_IS_E2_PLUS(bp) ?
  4277. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4278. USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), cli));
  4279. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4280. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4281. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4282. data = udev->l2_buf;
  4283. cid_ptr = udev->l2_buf + 12;
  4284. memset(data, 0, sizeof(*data));
  4285. cnic_init_bnx2x_tx_ring(dev, data);
  4286. cnic_init_bnx2x_rx_ring(dev, data);
  4287. data->general.fp_hsi_ver = ETH_FP_HSI_VERSION;
  4288. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4289. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4290. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4291. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4292. cid, ETH_CONNECTION_TYPE, &l5_data);
  4293. i = 0;
  4294. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4295. ++i < 10)
  4296. msleep(1);
  4297. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4298. netdev_err(dev->netdev,
  4299. "iSCSI CLIENT_SETUP did not complete\n");
  4300. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4301. cnic_ring_ctl(dev, cid, cli, 1);
  4302. *cid_ptr = cid >> 4;
  4303. *(cid_ptr + 1) = cid * bp->db_size;
  4304. *(cid_ptr + 2) = UIO_USE_TX_DOORBELL;
  4305. }
  4306. }
  4307. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4308. {
  4309. struct cnic_local *cp = dev->cnic_priv;
  4310. struct cnic_uio_dev *udev = cp->udev;
  4311. void *rx_ring;
  4312. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4313. return;
  4314. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4315. cnic_shutdown_bnx2_rx_ring(dev);
  4316. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4317. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4318. u32 cid = cp->ethdev->iscsi_l2_cid;
  4319. union l5cm_specific_data l5_data;
  4320. int i;
  4321. cnic_ring_ctl(dev, cid, cli, 0);
  4322. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4323. l5_data.phy_address.lo = cli;
  4324. l5_data.phy_address.hi = 0;
  4325. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4326. cid, ETH_CONNECTION_TYPE, &l5_data);
  4327. i = 0;
  4328. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4329. ++i < 10)
  4330. msleep(1);
  4331. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4332. netdev_err(dev->netdev,
  4333. "iSCSI CLIENT_HALT did not complete\n");
  4334. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4335. memset(&l5_data, 0, sizeof(l5_data));
  4336. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4337. cid, NONE_CONNECTION_TYPE, &l5_data);
  4338. msleep(10);
  4339. }
  4340. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4341. rx_ring = udev->l2_ring + CNIC_PAGE_SIZE;
  4342. memset(rx_ring, 0, CNIC_PAGE_SIZE);
  4343. }
  4344. static int cnic_register_netdev(struct cnic_dev *dev)
  4345. {
  4346. struct cnic_local *cp = dev->cnic_priv;
  4347. struct cnic_eth_dev *ethdev = cp->ethdev;
  4348. int err;
  4349. if (!ethdev)
  4350. return -ENODEV;
  4351. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4352. return 0;
  4353. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4354. if (err)
  4355. netdev_err(dev->netdev, "register_cnic failed\n");
  4356. /* Read iSCSI config again. On some bnx2x device, iSCSI config
  4357. * can change after firmware is downloaded.
  4358. */
  4359. dev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4360. if (ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  4361. dev->max_iscsi_conn = 0;
  4362. return err;
  4363. }
  4364. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4365. {
  4366. struct cnic_local *cp = dev->cnic_priv;
  4367. struct cnic_eth_dev *ethdev = cp->ethdev;
  4368. if (!ethdev)
  4369. return;
  4370. ethdev->drv_unregister_cnic(dev->netdev);
  4371. }
  4372. static int cnic_start_hw(struct cnic_dev *dev)
  4373. {
  4374. struct cnic_local *cp = dev->cnic_priv;
  4375. struct cnic_eth_dev *ethdev = cp->ethdev;
  4376. int err;
  4377. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4378. return -EALREADY;
  4379. dev->regview = ethdev->io_base;
  4380. pci_dev_get(dev->pcidev);
  4381. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4382. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4383. cp->status_blk_map = ethdev->irq_arr[0].status_blk_map;
  4384. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4385. err = cp->alloc_resc(dev);
  4386. if (err) {
  4387. netdev_err(dev->netdev, "allocate resource failure\n");
  4388. goto err1;
  4389. }
  4390. err = cp->start_hw(dev);
  4391. if (err)
  4392. goto err1;
  4393. err = cnic_cm_open(dev);
  4394. if (err)
  4395. goto err1;
  4396. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4397. cp->enable_int(dev);
  4398. return 0;
  4399. err1:
  4400. if (ethdev->drv_state & CNIC_DRV_STATE_HANDLES_IRQ)
  4401. cp->stop_hw(dev);
  4402. else
  4403. cp->free_resc(dev);
  4404. pci_dev_put(dev->pcidev);
  4405. return err;
  4406. }
  4407. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4408. {
  4409. cnic_disable_bnx2_int_sync(dev);
  4410. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4411. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4412. cnic_init_context(dev, KWQ_CID);
  4413. cnic_init_context(dev, KCQ_CID);
  4414. cnic_setup_5709_context(dev, 0);
  4415. cnic_free_irq(dev);
  4416. cnic_free_resc(dev);
  4417. }
  4418. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4419. {
  4420. struct cnic_local *cp = dev->cnic_priv;
  4421. struct bnx2x *bp = netdev_priv(dev->netdev);
  4422. u32 hc_index = HC_INDEX_ISCSI_EQ_CONS;
  4423. u32 sb_id = cp->status_blk_num;
  4424. u32 idx_off, syn_off;
  4425. cnic_free_irq(dev);
  4426. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4427. idx_off = offsetof(struct hc_status_block_e2, index_values) +
  4428. (hc_index * sizeof(u16));
  4429. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hc_index, sb_id);
  4430. } else {
  4431. idx_off = offsetof(struct hc_status_block_e1x, index_values) +
  4432. (hc_index * sizeof(u16));
  4433. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hc_index, sb_id);
  4434. }
  4435. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + syn_off, 0);
  4436. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(sb_id) +
  4437. idx_off, 0);
  4438. *cp->kcq1.hw_prod_idx_ptr = 0;
  4439. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4440. CSTORM_ISCSI_EQ_CONS_OFFSET(bp->pfid, 0), 0);
  4441. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4442. cnic_free_resc(dev);
  4443. }
  4444. static void cnic_stop_hw(struct cnic_dev *dev)
  4445. {
  4446. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4447. struct cnic_local *cp = dev->cnic_priv;
  4448. int i = 0;
  4449. /* Need to wait for the ring shutdown event to complete
  4450. * before clearing the CNIC_UP flag.
  4451. */
  4452. while (cp->udev && cp->udev->uio_dev != -1 && i < 15) {
  4453. msleep(100);
  4454. i++;
  4455. }
  4456. cnic_shutdown_rings(dev);
  4457. cp->stop_cm(dev);
  4458. cp->ethdev->drv_state &= ~CNIC_DRV_STATE_HANDLES_IRQ;
  4459. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4460. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4461. synchronize_rcu();
  4462. cnic_cm_shutdown(dev);
  4463. cp->stop_hw(dev);
  4464. pci_dev_put(dev->pcidev);
  4465. }
  4466. }
  4467. static void cnic_free_dev(struct cnic_dev *dev)
  4468. {
  4469. int i = 0;
  4470. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4471. msleep(100);
  4472. i++;
  4473. }
  4474. if (atomic_read(&dev->ref_count) != 0)
  4475. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4476. netdev_info(dev->netdev, "Removed CNIC device\n");
  4477. dev_put(dev->netdev);
  4478. kfree(dev);
  4479. }
  4480. static int cnic_get_fc_npiv_tbl(struct cnic_dev *dev,
  4481. struct cnic_fc_npiv_tbl *npiv_tbl)
  4482. {
  4483. struct cnic_local *cp = dev->cnic_priv;
  4484. struct bnx2x *bp = netdev_priv(dev->netdev);
  4485. int ret;
  4486. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4487. return -EAGAIN; /* bnx2x is down */
  4488. if (!BNX2X_CHIP_IS_E2_PLUS(bp))
  4489. return -EINVAL;
  4490. ret = cp->ethdev->drv_get_fc_npiv_tbl(dev->netdev, npiv_tbl);
  4491. return ret;
  4492. }
  4493. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4494. struct pci_dev *pdev)
  4495. {
  4496. struct cnic_dev *cdev;
  4497. struct cnic_local *cp;
  4498. int alloc_size;
  4499. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4500. cdev = kzalloc(alloc_size, GFP_KERNEL);
  4501. if (cdev == NULL)
  4502. return NULL;
  4503. cdev->netdev = dev;
  4504. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4505. cdev->register_device = cnic_register_device;
  4506. cdev->unregister_device = cnic_unregister_device;
  4507. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4508. cdev->get_fc_npiv_tbl = cnic_get_fc_npiv_tbl;
  4509. atomic_set(&cdev->ref_count, 0);
  4510. cp = cdev->cnic_priv;
  4511. cp->dev = cdev;
  4512. cp->l2_single_buf_size = 0x400;
  4513. cp->l2_rx_ring_size = 3;
  4514. spin_lock_init(&cp->cnic_ulp_lock);
  4515. netdev_info(dev, "Added CNIC device\n");
  4516. return cdev;
  4517. }
  4518. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4519. {
  4520. struct pci_dev *pdev;
  4521. struct cnic_dev *cdev;
  4522. struct cnic_local *cp;
  4523. struct bnx2 *bp = netdev_priv(dev);
  4524. struct cnic_eth_dev *ethdev = NULL;
  4525. if (bp->cnic_probe)
  4526. ethdev = (bp->cnic_probe)(dev);
  4527. if (!ethdev)
  4528. return NULL;
  4529. pdev = ethdev->pdev;
  4530. if (!pdev)
  4531. return NULL;
  4532. dev_hold(dev);
  4533. pci_dev_get(pdev);
  4534. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4535. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4536. (pdev->revision < 0x10)) {
  4537. pci_dev_put(pdev);
  4538. goto cnic_err;
  4539. }
  4540. pci_dev_put(pdev);
  4541. cdev = cnic_alloc_dev(dev, pdev);
  4542. if (cdev == NULL)
  4543. goto cnic_err;
  4544. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4545. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4546. cp = cdev->cnic_priv;
  4547. cp->ethdev = ethdev;
  4548. cdev->pcidev = pdev;
  4549. cp->chip_id = ethdev->chip_id;
  4550. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4551. cp->cnic_ops = &cnic_bnx2_ops;
  4552. cp->start_hw = cnic_start_bnx2_hw;
  4553. cp->stop_hw = cnic_stop_bnx2_hw;
  4554. cp->setup_pgtbl = cnic_setup_page_tbl;
  4555. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4556. cp->free_resc = cnic_free_resc;
  4557. cp->start_cm = cnic_cm_init_bnx2_hw;
  4558. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4559. cp->enable_int = cnic_enable_bnx2_int;
  4560. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4561. cp->close_conn = cnic_close_bnx2_conn;
  4562. return cdev;
  4563. cnic_err:
  4564. dev_put(dev);
  4565. return NULL;
  4566. }
  4567. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4568. {
  4569. struct pci_dev *pdev;
  4570. struct cnic_dev *cdev;
  4571. struct cnic_local *cp;
  4572. struct bnx2x *bp = netdev_priv(dev);
  4573. struct cnic_eth_dev *ethdev = NULL;
  4574. if (bp->cnic_probe)
  4575. ethdev = bp->cnic_probe(dev);
  4576. if (!ethdev)
  4577. return NULL;
  4578. pdev = ethdev->pdev;
  4579. if (!pdev)
  4580. return NULL;
  4581. dev_hold(dev);
  4582. cdev = cnic_alloc_dev(dev, pdev);
  4583. if (cdev == NULL) {
  4584. dev_put(dev);
  4585. return NULL;
  4586. }
  4587. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4588. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4589. cp = cdev->cnic_priv;
  4590. cp->ethdev = ethdev;
  4591. cdev->pcidev = pdev;
  4592. cp->chip_id = ethdev->chip_id;
  4593. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4594. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4595. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4596. if (CNIC_SUPPORTS_FCOE(bp)) {
  4597. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4598. cdev->max_fcoe_exchanges = ethdev->max_fcoe_exchanges;
  4599. }
  4600. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4601. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4602. memcpy(cdev->mac_addr, ethdev->iscsi_mac, ETH_ALEN);
  4603. cp->cnic_ops = &cnic_bnx2x_ops;
  4604. cp->start_hw = cnic_start_bnx2x_hw;
  4605. cp->stop_hw = cnic_stop_bnx2x_hw;
  4606. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4607. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4608. cp->free_resc = cnic_free_resc;
  4609. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4610. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4611. cp->enable_int = cnic_enable_bnx2x_int;
  4612. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4613. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4614. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4615. cp->arm_int = cnic_arm_bnx2x_e2_msix;
  4616. } else {
  4617. cp->ack_int = cnic_ack_bnx2x_msix;
  4618. cp->arm_int = cnic_arm_bnx2x_msix;
  4619. }
  4620. cp->close_conn = cnic_close_bnx2x_conn;
  4621. return cdev;
  4622. }
  4623. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4624. {
  4625. struct ethtool_drvinfo drvinfo;
  4626. struct cnic_dev *cdev = NULL;
  4627. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4628. memset(&drvinfo, 0, sizeof(drvinfo));
  4629. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4630. if (!strcmp(drvinfo.driver, "bnx2"))
  4631. cdev = init_bnx2_cnic(dev);
  4632. if (!strcmp(drvinfo.driver, "bnx2x"))
  4633. cdev = init_bnx2x_cnic(dev);
  4634. if (cdev) {
  4635. write_lock(&cnic_dev_lock);
  4636. list_add(&cdev->list, &cnic_dev_list);
  4637. write_unlock(&cnic_dev_lock);
  4638. }
  4639. }
  4640. return cdev;
  4641. }
  4642. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4643. u16 vlan_id)
  4644. {
  4645. int if_type;
  4646. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4647. struct cnic_ulp_ops *ulp_ops;
  4648. void *ctx;
  4649. mutex_lock(&cnic_lock);
  4650. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  4651. lockdep_is_held(&cnic_lock));
  4652. if (!ulp_ops || !ulp_ops->indicate_netevent) {
  4653. mutex_unlock(&cnic_lock);
  4654. continue;
  4655. }
  4656. ctx = cp->ulp_handle[if_type];
  4657. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4658. mutex_unlock(&cnic_lock);
  4659. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4660. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4661. }
  4662. }
  4663. /* netdev event handler */
  4664. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4665. void *ptr)
  4666. {
  4667. struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
  4668. struct cnic_dev *dev;
  4669. int new_dev = 0;
  4670. dev = cnic_from_netdev(netdev);
  4671. if (!dev && event == NETDEV_REGISTER) {
  4672. /* Check for the hot-plug device */
  4673. dev = is_cnic_dev(netdev);
  4674. if (dev) {
  4675. new_dev = 1;
  4676. cnic_hold(dev);
  4677. }
  4678. }
  4679. if (dev) {
  4680. struct cnic_local *cp = dev->cnic_priv;
  4681. if (new_dev)
  4682. cnic_ulp_init(dev);
  4683. else if (event == NETDEV_UNREGISTER)
  4684. cnic_ulp_exit(dev);
  4685. if (event == NETDEV_UP) {
  4686. if (cnic_register_netdev(dev) != 0) {
  4687. cnic_put(dev);
  4688. goto done;
  4689. }
  4690. if (!cnic_start_hw(dev))
  4691. cnic_ulp_start(dev);
  4692. }
  4693. cnic_rcv_netevent(cp, event, 0);
  4694. if (event == NETDEV_GOING_DOWN) {
  4695. cnic_ulp_stop(dev);
  4696. cnic_stop_hw(dev);
  4697. cnic_unregister_netdev(dev);
  4698. } else if (event == NETDEV_UNREGISTER) {
  4699. write_lock(&cnic_dev_lock);
  4700. list_del_init(&dev->list);
  4701. write_unlock(&cnic_dev_lock);
  4702. cnic_put(dev);
  4703. cnic_free_dev(dev);
  4704. goto done;
  4705. }
  4706. cnic_put(dev);
  4707. } else {
  4708. struct net_device *realdev;
  4709. u16 vid;
  4710. vid = cnic_get_vlan(netdev, &realdev);
  4711. if (realdev) {
  4712. dev = cnic_from_netdev(realdev);
  4713. if (dev) {
  4714. vid |= VLAN_CFI_MASK; /* make non-zero */
  4715. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4716. cnic_put(dev);
  4717. }
  4718. }
  4719. }
  4720. done:
  4721. return NOTIFY_DONE;
  4722. }
  4723. static struct notifier_block cnic_netdev_notifier = {
  4724. .notifier_call = cnic_netdev_event
  4725. };
  4726. static void cnic_release(void)
  4727. {
  4728. struct cnic_uio_dev *udev;
  4729. while (!list_empty(&cnic_udev_list)) {
  4730. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4731. list);
  4732. cnic_free_uio(udev);
  4733. }
  4734. }
  4735. static int __init cnic_init(void)
  4736. {
  4737. int rc = 0;
  4738. pr_info("%s", version);
  4739. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4740. if (rc) {
  4741. cnic_release();
  4742. return rc;
  4743. }
  4744. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4745. if (!cnic_wq) {
  4746. cnic_release();
  4747. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4748. return -ENOMEM;
  4749. }
  4750. return 0;
  4751. }
  4752. static void __exit cnic_exit(void)
  4753. {
  4754. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4755. cnic_release();
  4756. destroy_workqueue(cnic_wq);
  4757. }
  4758. module_init(cnic_init);
  4759. module_exit(cnic_exit);