tifm_sd.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * tifm_sd.c - TI FlashMedia driver
  4. *
  5. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  6. *
  7. * Special thanks to Brad Campbell for extensive testing of this driver.
  8. */
  9. #include <linux/tifm.h>
  10. #include <linux/mmc/host.h>
  11. #include <linux/highmem.h>
  12. #include <linux/scatterlist.h>
  13. #include <linux/module.h>
  14. #include <linux/workqueue.h>
  15. #include <asm/io.h>
  16. #define DRIVER_NAME "tifm_sd"
  17. #define DRIVER_VERSION "0.8"
  18. static bool no_dma = 0;
  19. static bool fixed_timeout = 0;
  20. module_param(no_dma, bool, 0644);
  21. module_param(fixed_timeout, bool, 0644);
  22. /* Constants here are mostly from OMAP5912 datasheet */
  23. #define TIFM_MMCSD_RESET 0x0002
  24. #define TIFM_MMCSD_CLKMASK 0x03ff
  25. #define TIFM_MMCSD_POWER 0x0800
  26. #define TIFM_MMCSD_4BBUS 0x8000
  27. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  28. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  29. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  30. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  31. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  32. #define TIFM_MMCSD_READ 0x8000
  33. #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
  34. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  35. #define TIFM_MMCSD_CD 0x0002 /* card detect */
  36. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  37. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  38. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  39. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  40. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  41. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  42. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  43. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  44. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  45. #define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
  46. #define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
  47. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  48. #define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
  49. #define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
  50. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  51. #define TIFM_MMCSD_RSP_R0 0x0000
  52. #define TIFM_MMCSD_RSP_R1 0x0100
  53. #define TIFM_MMCSD_RSP_R2 0x0200
  54. #define TIFM_MMCSD_RSP_R3 0x0300
  55. #define TIFM_MMCSD_RSP_R4 0x0400
  56. #define TIFM_MMCSD_RSP_R5 0x0500
  57. #define TIFM_MMCSD_RSP_R6 0x0600
  58. #define TIFM_MMCSD_RSP_BUSY 0x0800
  59. #define TIFM_MMCSD_CMD_BC 0x0000
  60. #define TIFM_MMCSD_CMD_BCR 0x1000
  61. #define TIFM_MMCSD_CMD_AC 0x2000
  62. #define TIFM_MMCSD_CMD_ADTC 0x3000
  63. #define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
  64. #define TIFM_MMCSD_REQ_TIMEOUT_MS 1000
  65. enum {
  66. CMD_READY = 0x0001,
  67. FIFO_READY = 0x0002,
  68. BRS_READY = 0x0004,
  69. SCMD_ACTIVE = 0x0008,
  70. SCMD_READY = 0x0010,
  71. CARD_BUSY = 0x0020,
  72. DATA_CARRY = 0x0040
  73. };
  74. struct tifm_sd {
  75. struct tifm_dev *dev;
  76. unsigned short eject:1,
  77. open_drain:1,
  78. no_dma:1;
  79. unsigned short cmd_flags;
  80. unsigned int clk_freq;
  81. unsigned int clk_div;
  82. unsigned long timeout_jiffies;
  83. struct work_struct finish_bh_work;
  84. struct timer_list timer;
  85. struct mmc_request *req;
  86. int sg_len;
  87. int sg_pos;
  88. unsigned int block_pos;
  89. struct scatterlist bounce_buf;
  90. unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
  91. };
  92. /* for some reason, host won't respond correctly to readw/writew */
  93. static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
  94. unsigned int off, unsigned int cnt)
  95. {
  96. struct tifm_dev *sock = host->dev;
  97. unsigned char *buf;
  98. unsigned int pos = 0, val;
  99. buf = kmap_local_page(pg) + off;
  100. if (host->cmd_flags & DATA_CARRY) {
  101. buf[pos++] = host->bounce_buf_data[0];
  102. host->cmd_flags &= ~DATA_CARRY;
  103. }
  104. while (pos < cnt) {
  105. val = readl(sock->addr + SOCK_MMCSD_DATA);
  106. buf[pos++] = val & 0xff;
  107. if (pos == cnt) {
  108. host->bounce_buf_data[0] = (val >> 8) & 0xff;
  109. host->cmd_flags |= DATA_CARRY;
  110. break;
  111. }
  112. buf[pos++] = (val >> 8) & 0xff;
  113. }
  114. kunmap_local(buf - off);
  115. }
  116. static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
  117. unsigned int off, unsigned int cnt)
  118. {
  119. struct tifm_dev *sock = host->dev;
  120. unsigned char *buf;
  121. unsigned int pos = 0, val;
  122. buf = kmap_local_page(pg) + off;
  123. if (host->cmd_flags & DATA_CARRY) {
  124. val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
  125. writel(val, sock->addr + SOCK_MMCSD_DATA);
  126. host->cmd_flags &= ~DATA_CARRY;
  127. }
  128. while (pos < cnt) {
  129. val = buf[pos++];
  130. if (pos == cnt) {
  131. host->bounce_buf_data[0] = val & 0xff;
  132. host->cmd_flags |= DATA_CARRY;
  133. break;
  134. }
  135. val |= (buf[pos++] << 8) & 0xff00;
  136. writel(val, sock->addr + SOCK_MMCSD_DATA);
  137. }
  138. kunmap_local(buf - off);
  139. }
  140. static void tifm_sd_transfer_data(struct tifm_sd *host)
  141. {
  142. struct mmc_data *r_data = host->req->cmd->data;
  143. struct scatterlist *sg = r_data->sg;
  144. unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
  145. unsigned int p_off, p_cnt;
  146. struct page *pg;
  147. if (host->sg_pos == host->sg_len)
  148. return;
  149. while (t_size) {
  150. cnt = sg[host->sg_pos].length - host->block_pos;
  151. if (!cnt) {
  152. host->block_pos = 0;
  153. host->sg_pos++;
  154. if (host->sg_pos == host->sg_len) {
  155. if ((r_data->flags & MMC_DATA_WRITE)
  156. && (host->cmd_flags & DATA_CARRY))
  157. writel(host->bounce_buf_data[0],
  158. host->dev->addr
  159. + SOCK_MMCSD_DATA);
  160. return;
  161. }
  162. cnt = sg[host->sg_pos].length;
  163. }
  164. off = sg[host->sg_pos].offset + host->block_pos;
  165. pg = sg_page(&sg[host->sg_pos]) + (off >> PAGE_SHIFT);
  166. p_off = offset_in_page(off);
  167. p_cnt = PAGE_SIZE - p_off;
  168. p_cnt = min(p_cnt, cnt);
  169. p_cnt = min(p_cnt, t_size);
  170. if (r_data->flags & MMC_DATA_READ)
  171. tifm_sd_read_fifo(host, pg, p_off, p_cnt);
  172. else if (r_data->flags & MMC_DATA_WRITE)
  173. tifm_sd_write_fifo(host, pg, p_off, p_cnt);
  174. t_size -= p_cnt;
  175. host->block_pos += p_cnt;
  176. }
  177. }
  178. static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
  179. struct page *src, unsigned int src_off,
  180. unsigned int count)
  181. {
  182. unsigned char *src_buf = kmap_local_page(src) + src_off;
  183. unsigned char *dst_buf = kmap_local_page(dst) + dst_off;
  184. memcpy(dst_buf, src_buf, count);
  185. kunmap_local(dst_buf - dst_off);
  186. kunmap_local(src_buf - src_off);
  187. }
  188. static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
  189. {
  190. struct scatterlist *sg = r_data->sg;
  191. unsigned int t_size = r_data->blksz;
  192. unsigned int off, cnt;
  193. unsigned int p_off, p_cnt;
  194. struct page *pg;
  195. dev_dbg(&host->dev->dev, "bouncing block\n");
  196. while (t_size) {
  197. cnt = sg[host->sg_pos].length - host->block_pos;
  198. if (!cnt) {
  199. host->block_pos = 0;
  200. host->sg_pos++;
  201. if (host->sg_pos == host->sg_len)
  202. return;
  203. cnt = sg[host->sg_pos].length;
  204. }
  205. off = sg[host->sg_pos].offset + host->block_pos;
  206. pg = sg_page(&sg[host->sg_pos]) + (off >> PAGE_SHIFT);
  207. p_off = offset_in_page(off);
  208. p_cnt = PAGE_SIZE - p_off;
  209. p_cnt = min(p_cnt, cnt);
  210. p_cnt = min(p_cnt, t_size);
  211. if (r_data->flags & MMC_DATA_WRITE)
  212. tifm_sd_copy_page(sg_page(&host->bounce_buf),
  213. r_data->blksz - t_size,
  214. pg, p_off, p_cnt);
  215. else if (r_data->flags & MMC_DATA_READ)
  216. tifm_sd_copy_page(pg, p_off, sg_page(&host->bounce_buf),
  217. r_data->blksz - t_size, p_cnt);
  218. t_size -= p_cnt;
  219. host->block_pos += p_cnt;
  220. }
  221. }
  222. static int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
  223. {
  224. struct tifm_dev *sock = host->dev;
  225. unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
  226. unsigned int dma_len, dma_blk_cnt, dma_off;
  227. struct scatterlist *sg = NULL;
  228. if (host->sg_pos == host->sg_len)
  229. return 1;
  230. if (host->cmd_flags & DATA_CARRY) {
  231. host->cmd_flags &= ~DATA_CARRY;
  232. tifm_sd_bounce_block(host, r_data);
  233. if (host->sg_pos == host->sg_len)
  234. return 1;
  235. }
  236. dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
  237. if (!dma_len) {
  238. host->block_pos = 0;
  239. host->sg_pos++;
  240. if (host->sg_pos == host->sg_len)
  241. return 1;
  242. dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
  243. }
  244. if (dma_len < t_size) {
  245. dma_blk_cnt = dma_len / r_data->blksz;
  246. dma_off = host->block_pos;
  247. host->block_pos += dma_blk_cnt * r_data->blksz;
  248. } else {
  249. dma_blk_cnt = TIFM_DMA_TSIZE;
  250. dma_off = host->block_pos;
  251. host->block_pos += t_size;
  252. }
  253. if (dma_blk_cnt)
  254. sg = &r_data->sg[host->sg_pos];
  255. else if (dma_len) {
  256. if (r_data->flags & MMC_DATA_WRITE)
  257. tifm_sd_bounce_block(host, r_data);
  258. else
  259. host->cmd_flags |= DATA_CARRY;
  260. sg = &host->bounce_buf;
  261. dma_off = 0;
  262. dma_blk_cnt = 1;
  263. } else
  264. return 1;
  265. dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
  266. writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
  267. if (r_data->flags & MMC_DATA_WRITE)
  268. writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
  269. sock->addr + SOCK_DMA_CONTROL);
  270. else
  271. writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
  272. sock->addr + SOCK_DMA_CONTROL);
  273. return 0;
  274. }
  275. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  276. {
  277. unsigned int rc = 0;
  278. switch (mmc_resp_type(cmd)) {
  279. case MMC_RSP_NONE:
  280. rc |= TIFM_MMCSD_RSP_R0;
  281. break;
  282. case MMC_RSP_R1B:
  283. rc |= TIFM_MMCSD_RSP_BUSY;
  284. fallthrough;
  285. case MMC_RSP_R1:
  286. rc |= TIFM_MMCSD_RSP_R1;
  287. break;
  288. case MMC_RSP_R2:
  289. rc |= TIFM_MMCSD_RSP_R2;
  290. break;
  291. case MMC_RSP_R3:
  292. rc |= TIFM_MMCSD_RSP_R3;
  293. break;
  294. default:
  295. BUG();
  296. }
  297. switch (mmc_cmd_type(cmd)) {
  298. case MMC_CMD_BC:
  299. rc |= TIFM_MMCSD_CMD_BC;
  300. break;
  301. case MMC_CMD_BCR:
  302. rc |= TIFM_MMCSD_CMD_BCR;
  303. break;
  304. case MMC_CMD_AC:
  305. rc |= TIFM_MMCSD_CMD_AC;
  306. break;
  307. case MMC_CMD_ADTC:
  308. rc |= TIFM_MMCSD_CMD_ADTC;
  309. break;
  310. default:
  311. BUG();
  312. }
  313. return rc;
  314. }
  315. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  316. {
  317. struct tifm_dev *sock = host->dev;
  318. unsigned int cmd_mask = tifm_sd_op_flags(cmd);
  319. if (host->open_drain)
  320. cmd_mask |= TIFM_MMCSD_ODTO;
  321. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  322. cmd_mask |= TIFM_MMCSD_READ;
  323. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  324. cmd->opcode, cmd->arg, cmd_mask);
  325. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  326. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  327. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  328. }
  329. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  330. {
  331. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  332. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  333. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  334. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  335. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  336. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  337. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  338. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  339. }
  340. static void tifm_sd_check_status(struct tifm_sd *host)
  341. {
  342. struct tifm_dev *sock = host->dev;
  343. struct mmc_command *cmd = host->req->cmd;
  344. if (cmd->error)
  345. goto finish_request;
  346. if (!(host->cmd_flags & CMD_READY))
  347. return;
  348. if (cmd->data) {
  349. if (cmd->data->error) {
  350. if ((host->cmd_flags & SCMD_ACTIVE)
  351. && !(host->cmd_flags & SCMD_READY))
  352. return;
  353. goto finish_request;
  354. }
  355. if (!(host->cmd_flags & BRS_READY))
  356. return;
  357. if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
  358. return;
  359. if (cmd->data->flags & MMC_DATA_WRITE) {
  360. if (host->req->stop) {
  361. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  362. host->cmd_flags |= SCMD_ACTIVE;
  363. writel(TIFM_MMCSD_EOFB
  364. | readl(sock->addr
  365. + SOCK_MMCSD_INT_ENABLE),
  366. sock->addr
  367. + SOCK_MMCSD_INT_ENABLE);
  368. tifm_sd_exec(host, host->req->stop);
  369. return;
  370. } else {
  371. if (!(host->cmd_flags & SCMD_READY)
  372. || (host->cmd_flags & CARD_BUSY))
  373. return;
  374. writel((~TIFM_MMCSD_EOFB)
  375. & readl(sock->addr
  376. + SOCK_MMCSD_INT_ENABLE),
  377. sock->addr
  378. + SOCK_MMCSD_INT_ENABLE);
  379. }
  380. } else {
  381. if (host->cmd_flags & CARD_BUSY)
  382. return;
  383. writel((~TIFM_MMCSD_EOFB)
  384. & readl(sock->addr
  385. + SOCK_MMCSD_INT_ENABLE),
  386. sock->addr + SOCK_MMCSD_INT_ENABLE);
  387. }
  388. } else {
  389. if (host->req->stop) {
  390. if (!(host->cmd_flags & SCMD_ACTIVE)) {
  391. host->cmd_flags |= SCMD_ACTIVE;
  392. tifm_sd_exec(host, host->req->stop);
  393. return;
  394. } else {
  395. if (!(host->cmd_flags & SCMD_READY))
  396. return;
  397. }
  398. }
  399. }
  400. }
  401. finish_request:
  402. queue_work(system_bh_wq, &host->finish_bh_work);
  403. }
  404. /* Called from interrupt handler */
  405. static void tifm_sd_data_event(struct tifm_dev *sock)
  406. {
  407. struct tifm_sd *host;
  408. unsigned int fifo_status = 0;
  409. struct mmc_data *r_data = NULL;
  410. spin_lock(&sock->lock);
  411. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  412. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  413. dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
  414. fifo_status, host->cmd_flags);
  415. if (host->req) {
  416. r_data = host->req->cmd->data;
  417. if (r_data && (fifo_status & TIFM_FIFO_READY)) {
  418. if (tifm_sd_set_dma_data(host, r_data)) {
  419. host->cmd_flags |= FIFO_READY;
  420. tifm_sd_check_status(host);
  421. }
  422. }
  423. }
  424. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  425. spin_unlock(&sock->lock);
  426. }
  427. /* Called from interrupt handler */
  428. static void tifm_sd_card_event(struct tifm_dev *sock)
  429. {
  430. struct tifm_sd *host;
  431. unsigned int host_status = 0;
  432. int cmd_error = 0;
  433. struct mmc_command *cmd = NULL;
  434. spin_lock(&sock->lock);
  435. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  436. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  437. dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
  438. host_status, host->cmd_flags);
  439. if (host->req) {
  440. cmd = host->req->cmd;
  441. if (host_status & TIFM_MMCSD_ERRMASK) {
  442. writel(host_status & TIFM_MMCSD_ERRMASK,
  443. sock->addr + SOCK_MMCSD_STATUS);
  444. if (host_status & TIFM_MMCSD_CTO)
  445. cmd_error = -ETIMEDOUT;
  446. else if (host_status & TIFM_MMCSD_CCRC)
  447. cmd_error = -EILSEQ;
  448. if (cmd->data) {
  449. if (host_status & TIFM_MMCSD_DTO)
  450. cmd->data->error = -ETIMEDOUT;
  451. else if (host_status & TIFM_MMCSD_DCRC)
  452. cmd->data->error = -EILSEQ;
  453. }
  454. writel(TIFM_FIFO_INT_SETALL,
  455. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  456. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  457. if (host->req->stop) {
  458. if (host->cmd_flags & SCMD_ACTIVE) {
  459. host->req->stop->error = cmd_error;
  460. host->cmd_flags |= SCMD_READY;
  461. } else {
  462. cmd->error = cmd_error;
  463. host->cmd_flags |= SCMD_ACTIVE;
  464. tifm_sd_exec(host, host->req->stop);
  465. goto done;
  466. }
  467. } else
  468. cmd->error = cmd_error;
  469. } else {
  470. if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
  471. if (!(host->cmd_flags & CMD_READY)) {
  472. host->cmd_flags |= CMD_READY;
  473. tifm_sd_fetch_resp(cmd, sock);
  474. } else if (host->cmd_flags & SCMD_ACTIVE) {
  475. host->cmd_flags |= SCMD_READY;
  476. tifm_sd_fetch_resp(host->req->stop,
  477. sock);
  478. }
  479. }
  480. if (host_status & TIFM_MMCSD_BRS)
  481. host->cmd_flags |= BRS_READY;
  482. }
  483. if (host->no_dma && cmd->data) {
  484. if (host_status & TIFM_MMCSD_AE)
  485. writel(host_status & TIFM_MMCSD_AE,
  486. sock->addr + SOCK_MMCSD_STATUS);
  487. if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
  488. | TIFM_MMCSD_BRS)) {
  489. tifm_sd_transfer_data(host);
  490. host_status &= ~TIFM_MMCSD_AE;
  491. }
  492. }
  493. if (host_status & TIFM_MMCSD_EOFB)
  494. host->cmd_flags &= ~CARD_BUSY;
  495. else if (host_status & TIFM_MMCSD_CB)
  496. host->cmd_flags |= CARD_BUSY;
  497. tifm_sd_check_status(host);
  498. }
  499. done:
  500. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  501. spin_unlock(&sock->lock);
  502. }
  503. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  504. struct mmc_data *data)
  505. {
  506. struct tifm_dev *sock = host->dev;
  507. unsigned int data_timeout = data->timeout_clks;
  508. if (fixed_timeout)
  509. return;
  510. data_timeout += data->timeout_ns /
  511. ((1000000000UL / host->clk_freq) * host->clk_div);
  512. if (data_timeout < 0xffff) {
  513. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  514. writel((~TIFM_MMCSD_DPE)
  515. & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  516. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  517. } else {
  518. data_timeout = (data_timeout >> 10) + 1;
  519. if (data_timeout > 0xffff)
  520. data_timeout = 0; /* set to unlimited */
  521. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  522. writel(TIFM_MMCSD_DPE
  523. | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  524. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  525. }
  526. }
  527. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  528. {
  529. struct tifm_sd *host = mmc_priv(mmc);
  530. struct tifm_dev *sock = host->dev;
  531. unsigned long flags;
  532. struct mmc_data *r_data = mrq->cmd->data;
  533. spin_lock_irqsave(&sock->lock, flags);
  534. if (host->eject) {
  535. mrq->cmd->error = -ENOMEDIUM;
  536. goto err_out;
  537. }
  538. if (host->req) {
  539. pr_err("%s : unfinished request detected\n",
  540. dev_name(&sock->dev));
  541. mrq->cmd->error = -ETIMEDOUT;
  542. goto err_out;
  543. }
  544. host->cmd_flags = 0;
  545. host->block_pos = 0;
  546. host->sg_pos = 0;
  547. if (mrq->data && !is_power_of_2(mrq->data->blksz))
  548. host->no_dma = 1;
  549. else
  550. host->no_dma = no_dma ? 1 : 0;
  551. if (r_data) {
  552. tifm_sd_set_data_timeout(host, r_data);
  553. if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
  554. writel(TIFM_MMCSD_EOFB
  555. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  556. sock->addr + SOCK_MMCSD_INT_ENABLE);
  557. if (host->no_dma) {
  558. writel(TIFM_MMCSD_BUFINT
  559. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  560. sock->addr + SOCK_MMCSD_INT_ENABLE);
  561. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
  562. | (TIFM_MMCSD_FIFO_SIZE - 1),
  563. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  564. host->sg_len = r_data->sg_len;
  565. } else {
  566. sg_init_one(&host->bounce_buf, host->bounce_buf_data,
  567. r_data->blksz);
  568. if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
  569. r_data->flags & MMC_DATA_WRITE
  570. ? DMA_TO_DEVICE
  571. : DMA_FROM_DEVICE)) {
  572. pr_err("%s : scatterlist map failed\n",
  573. dev_name(&sock->dev));
  574. mrq->cmd->error = -ENOMEM;
  575. goto err_out;
  576. }
  577. host->sg_len = tifm_map_sg(sock, r_data->sg,
  578. r_data->sg_len,
  579. r_data->flags
  580. & MMC_DATA_WRITE
  581. ? DMA_TO_DEVICE
  582. : DMA_FROM_DEVICE);
  583. if (host->sg_len < 1) {
  584. pr_err("%s : scatterlist map failed\n",
  585. dev_name(&sock->dev));
  586. tifm_unmap_sg(sock, &host->bounce_buf, 1,
  587. r_data->flags & MMC_DATA_WRITE
  588. ? DMA_TO_DEVICE
  589. : DMA_FROM_DEVICE);
  590. mrq->cmd->error = -ENOMEM;
  591. goto err_out;
  592. }
  593. writel(TIFM_FIFO_INT_SETALL,
  594. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  595. writel(ilog2(r_data->blksz) - 2,
  596. sock->addr + SOCK_FIFO_PAGE_SIZE);
  597. writel(TIFM_FIFO_ENABLE,
  598. sock->addr + SOCK_FIFO_CONTROL);
  599. writel(TIFM_FIFO_INTMASK,
  600. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  601. if (r_data->flags & MMC_DATA_WRITE)
  602. writel(TIFM_MMCSD_TXDE,
  603. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  604. else
  605. writel(TIFM_MMCSD_RXDE,
  606. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  607. tifm_sd_set_dma_data(host, r_data);
  608. }
  609. writel(r_data->blocks - 1,
  610. sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  611. writel(r_data->blksz - 1,
  612. sock->addr + SOCK_MMCSD_BLOCK_LEN);
  613. }
  614. host->req = mrq;
  615. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  616. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  617. sock->addr + SOCK_CONTROL);
  618. tifm_sd_exec(host, mrq->cmd);
  619. spin_unlock_irqrestore(&sock->lock, flags);
  620. return;
  621. err_out:
  622. spin_unlock_irqrestore(&sock->lock, flags);
  623. mmc_request_done(mmc, mrq);
  624. }
  625. static void tifm_sd_end_cmd(struct work_struct *t)
  626. {
  627. struct tifm_sd *host = from_work(host, t, finish_bh_work);
  628. struct tifm_dev *sock = host->dev;
  629. struct mmc_host *mmc = tifm_get_drvdata(sock);
  630. struct mmc_request *mrq;
  631. struct mmc_data *r_data = NULL;
  632. unsigned long flags;
  633. spin_lock_irqsave(&sock->lock, flags);
  634. timer_delete(&host->timer);
  635. mrq = host->req;
  636. host->req = NULL;
  637. if (!mrq) {
  638. pr_err(" %s : no request to complete?\n",
  639. dev_name(&sock->dev));
  640. spin_unlock_irqrestore(&sock->lock, flags);
  641. return;
  642. }
  643. r_data = mrq->cmd->data;
  644. if (r_data) {
  645. if (host->no_dma) {
  646. writel((~TIFM_MMCSD_BUFINT)
  647. & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  648. sock->addr + SOCK_MMCSD_INT_ENABLE);
  649. } else {
  650. tifm_unmap_sg(sock, &host->bounce_buf, 1,
  651. (r_data->flags & MMC_DATA_WRITE)
  652. ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  653. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  654. (r_data->flags & MMC_DATA_WRITE)
  655. ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  656. }
  657. r_data->bytes_xfered = r_data->blocks
  658. - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  659. r_data->bytes_xfered *= r_data->blksz;
  660. r_data->bytes_xfered += r_data->blksz
  661. - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  662. }
  663. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  664. sock->addr + SOCK_CONTROL);
  665. spin_unlock_irqrestore(&sock->lock, flags);
  666. mmc_request_done(mmc, mrq);
  667. }
  668. static void tifm_sd_abort(struct timer_list *t)
  669. {
  670. struct tifm_sd *host = timer_container_of(host, t, timer);
  671. pr_err("%s : card failed to respond for a long period of time "
  672. "(%x, %x)\n",
  673. dev_name(&host->dev->dev), host->req->cmd->opcode, host->cmd_flags);
  674. tifm_eject(host->dev);
  675. }
  676. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  677. {
  678. struct tifm_sd *host = mmc_priv(mmc);
  679. struct tifm_dev *sock = host->dev;
  680. unsigned int clk_div1, clk_div2;
  681. unsigned long flags;
  682. spin_lock_irqsave(&sock->lock, flags);
  683. dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
  684. "chip_select = %x, power_mode = %x, bus_width = %x\n",
  685. ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
  686. ios->power_mode, ios->bus_width);
  687. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  688. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  689. sock->addr + SOCK_MMCSD_CONFIG);
  690. } else {
  691. writel((~TIFM_MMCSD_4BBUS)
  692. & readl(sock->addr + SOCK_MMCSD_CONFIG),
  693. sock->addr + SOCK_MMCSD_CONFIG);
  694. }
  695. if (ios->clock) {
  696. clk_div1 = 20000000 / ios->clock;
  697. if (!clk_div1)
  698. clk_div1 = 1;
  699. clk_div2 = 24000000 / ios->clock;
  700. if (!clk_div2)
  701. clk_div2 = 1;
  702. if ((20000000 / clk_div1) > ios->clock)
  703. clk_div1++;
  704. if ((24000000 / clk_div2) > ios->clock)
  705. clk_div2++;
  706. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  707. host->clk_freq = 20000000;
  708. host->clk_div = clk_div1;
  709. writel((~TIFM_CTRL_FAST_CLK)
  710. & readl(sock->addr + SOCK_CONTROL),
  711. sock->addr + SOCK_CONTROL);
  712. } else {
  713. host->clk_freq = 24000000;
  714. host->clk_div = clk_div2;
  715. writel(TIFM_CTRL_FAST_CLK
  716. | readl(sock->addr + SOCK_CONTROL),
  717. sock->addr + SOCK_CONTROL);
  718. }
  719. } else {
  720. host->clk_div = 0;
  721. }
  722. host->clk_div &= TIFM_MMCSD_CLKMASK;
  723. writel(host->clk_div
  724. | ((~TIFM_MMCSD_CLKMASK)
  725. & readl(sock->addr + SOCK_MMCSD_CONFIG)),
  726. sock->addr + SOCK_MMCSD_CONFIG);
  727. host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
  728. /* chip_select : maybe later */
  729. //vdd
  730. //power is set before probe / after remove
  731. spin_unlock_irqrestore(&sock->lock, flags);
  732. }
  733. static int tifm_sd_ro(struct mmc_host *mmc)
  734. {
  735. int rc = 0;
  736. struct tifm_sd *host = mmc_priv(mmc);
  737. struct tifm_dev *sock = host->dev;
  738. unsigned long flags;
  739. spin_lock_irqsave(&sock->lock, flags);
  740. if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
  741. rc = 1;
  742. spin_unlock_irqrestore(&sock->lock, flags);
  743. return rc;
  744. }
  745. static const struct mmc_host_ops tifm_sd_ops = {
  746. .request = tifm_sd_request,
  747. .set_ios = tifm_sd_ios,
  748. .get_ro = tifm_sd_ro
  749. };
  750. static int tifm_sd_initialize_host(struct tifm_sd *host)
  751. {
  752. int rc;
  753. unsigned int host_status = 0;
  754. struct tifm_dev *sock = host->dev;
  755. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  756. host->clk_div = 61;
  757. host->clk_freq = 20000000;
  758. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  759. writel(host->clk_div | TIFM_MMCSD_POWER,
  760. sock->addr + SOCK_MMCSD_CONFIG);
  761. /* wait up to 0.51 sec for reset */
  762. for (rc = 32; rc <= 256; rc <<= 1) {
  763. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  764. rc = 0;
  765. break;
  766. }
  767. msleep(rc);
  768. }
  769. if (rc) {
  770. pr_err("%s : controller failed to reset\n",
  771. dev_name(&sock->dev));
  772. return -ENODEV;
  773. }
  774. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  775. writel(host->clk_div | TIFM_MMCSD_POWER,
  776. sock->addr + SOCK_MMCSD_CONFIG);
  777. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  778. // command timeout fixed to 64 clocks for now
  779. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
  780. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  781. for (rc = 16; rc <= 64; rc <<= 1) {
  782. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  783. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  784. if (!(host_status & TIFM_MMCSD_ERRMASK)
  785. && (host_status & TIFM_MMCSD_EOC)) {
  786. rc = 0;
  787. break;
  788. }
  789. msleep(rc);
  790. }
  791. if (rc) {
  792. pr_err("%s : card not ready - probe failed on initialization\n",
  793. dev_name(&sock->dev));
  794. return -ENODEV;
  795. }
  796. writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
  797. | TIFM_MMCSD_ERRMASK,
  798. sock->addr + SOCK_MMCSD_INT_ENABLE);
  799. return 0;
  800. }
  801. static int tifm_sd_probe(struct tifm_dev *sock)
  802. {
  803. struct mmc_host *mmc;
  804. struct tifm_sd *host;
  805. int rc = -EIO;
  806. if (!(TIFM_SOCK_STATE_OCCUPIED
  807. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  808. pr_warn("%s : card gone, unexpectedly\n",
  809. dev_name(&sock->dev));
  810. return rc;
  811. }
  812. mmc = devm_mmc_alloc_host(&sock->dev, sizeof(*host));
  813. if (!mmc)
  814. return -ENOMEM;
  815. host = mmc_priv(mmc);
  816. tifm_set_drvdata(sock, mmc);
  817. host->dev = sock;
  818. host->timeout_jiffies = msecs_to_jiffies(TIFM_MMCSD_REQ_TIMEOUT_MS);
  819. /*
  820. * We use a fixed request timeout of 1s, hence inform the core about it.
  821. * A future improvement should instead respect the cmd->busy_timeout.
  822. */
  823. mmc->max_busy_timeout = TIFM_MMCSD_REQ_TIMEOUT_MS;
  824. INIT_WORK(&host->finish_bh_work, tifm_sd_end_cmd);
  825. timer_setup(&host->timer, tifm_sd_abort, 0);
  826. mmc->ops = &tifm_sd_ops;
  827. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  828. mmc->caps = MMC_CAP_4_BIT_DATA;
  829. mmc->f_min = 20000000 / 60;
  830. mmc->f_max = 24000000;
  831. mmc->max_blk_count = 2048;
  832. mmc->max_segs = mmc->max_blk_count;
  833. mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
  834. mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
  835. mmc->max_req_size = mmc->max_seg_size;
  836. sock->card_event = tifm_sd_card_event;
  837. sock->data_event = tifm_sd_data_event;
  838. rc = tifm_sd_initialize_host(host);
  839. if (!rc)
  840. rc = mmc_add_host(mmc);
  841. return rc;
  842. }
  843. static void tifm_sd_remove(struct tifm_dev *sock)
  844. {
  845. struct mmc_host *mmc = tifm_get_drvdata(sock);
  846. struct tifm_sd *host = mmc_priv(mmc);
  847. unsigned long flags;
  848. spin_lock_irqsave(&sock->lock, flags);
  849. host->eject = 1;
  850. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  851. spin_unlock_irqrestore(&sock->lock, flags);
  852. cancel_work_sync(&host->finish_bh_work);
  853. spin_lock_irqsave(&sock->lock, flags);
  854. if (host->req) {
  855. writel(TIFM_FIFO_INT_SETALL,
  856. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  857. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  858. host->req->cmd->error = -ENOMEDIUM;
  859. if (host->req->stop)
  860. host->req->stop->error = -ENOMEDIUM;
  861. queue_work(system_bh_wq, &host->finish_bh_work);
  862. }
  863. spin_unlock_irqrestore(&sock->lock, flags);
  864. mmc_remove_host(mmc);
  865. dev_dbg(&sock->dev, "after remove\n");
  866. }
  867. #ifdef CONFIG_PM
  868. static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
  869. {
  870. return 0;
  871. }
  872. static int tifm_sd_resume(struct tifm_dev *sock)
  873. {
  874. struct mmc_host *mmc = tifm_get_drvdata(sock);
  875. struct tifm_sd *host = mmc_priv(mmc);
  876. int rc;
  877. rc = tifm_sd_initialize_host(host);
  878. dev_dbg(&sock->dev, "resume initialize %d\n", rc);
  879. if (rc)
  880. host->eject = 1;
  881. return rc;
  882. }
  883. #else
  884. #define tifm_sd_suspend NULL
  885. #define tifm_sd_resume NULL
  886. #endif /* CONFIG_PM */
  887. static struct tifm_device_id tifm_sd_id_tbl[] = {
  888. { TIFM_TYPE_SD }, { }
  889. };
  890. static struct tifm_driver tifm_sd_driver = {
  891. .driver = {
  892. .name = DRIVER_NAME,
  893. .owner = THIS_MODULE
  894. },
  895. .id_table = tifm_sd_id_tbl,
  896. .probe = tifm_sd_probe,
  897. .remove = tifm_sd_remove,
  898. .suspend = tifm_sd_suspend,
  899. .resume = tifm_sd_resume
  900. };
  901. static int __init tifm_sd_init(void)
  902. {
  903. return tifm_register_driver(&tifm_sd_driver);
  904. }
  905. static void __exit tifm_sd_exit(void)
  906. {
  907. tifm_unregister_driver(&tifm_sd_driver);
  908. }
  909. MODULE_AUTHOR("Alex Dubov");
  910. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  911. MODULE_LICENSE("GPL");
  912. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  913. MODULE_VERSION(DRIVER_VERSION);
  914. module_init(tifm_sd_init);
  915. module_exit(tifm_sd_exit);