sdhci_f_sdh30.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/drivers/mmc/host/sdhci_f_sdh30.c
  4. *
  5. * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
  6. * Vincent Yang <vincent.yang@tw.fujitsu.com>
  7. * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
  8. * Copyright (C) 2019 Socionext Inc.
  9. */
  10. #include <linux/acpi.h>
  11. #include <linux/err.h>
  12. #include <linux/delay.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/property.h>
  16. #include <linux/clk.h>
  17. #include <linux/reset.h>
  18. #include "sdhci-pltfm.h"
  19. #include "sdhci_f_sdh30.h"
  20. struct f_sdhost_priv {
  21. struct clk *clk_iface;
  22. struct clk *clk;
  23. struct reset_control *rst;
  24. u32 vendor_hs200;
  25. struct device *dev;
  26. bool enable_cmd_dat_delay;
  27. };
  28. static void *sdhci_f_sdhost_priv(struct sdhci_host *host)
  29. {
  30. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  31. return sdhci_pltfm_priv(pltfm_host);
  32. }
  33. static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
  34. {
  35. struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
  36. u32 ctrl = 0;
  37. usleep_range(2500, 3000);
  38. ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
  39. ctrl |= F_SDH30_CRES_O_DN;
  40. sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
  41. ctrl |= F_SDH30_MSEL_O_1_8;
  42. sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
  43. ctrl &= ~F_SDH30_CRES_O_DN;
  44. sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
  45. usleep_range(2500, 3000);
  46. if (priv->vendor_hs200) {
  47. dev_info(priv->dev, "%s: setting hs200\n", __func__);
  48. ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
  49. ctrl |= priv->vendor_hs200;
  50. sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL);
  51. }
  52. ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
  53. ctrl |= F_SDH30_CMD_CHK_DIS;
  54. sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
  55. }
  56. static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
  57. {
  58. return F_SDH30_MIN_CLOCK;
  59. }
  60. static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
  61. {
  62. struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
  63. u32 ctl;
  64. if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
  65. sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);
  66. sdhci_reset(host, mask);
  67. if (priv->enable_cmd_dat_delay) {
  68. ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
  69. ctl |= F_SDH30_CMD_DAT_DELAY;
  70. sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
  71. }
  72. if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) &&
  73. !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  74. ctl = sdhci_readl(host, F_SDH30_TEST);
  75. ctl |= F_SDH30_FORCE_CARD_INSERT;
  76. sdhci_writel(host, ctl, F_SDH30_TEST);
  77. }
  78. }
  79. static const struct sdhci_ops sdhci_f_sdh30_ops = {
  80. .voltage_switch = sdhci_f_sdh30_soft_voltage_switch,
  81. .get_min_clock = sdhci_f_sdh30_get_min_clock,
  82. .reset = sdhci_f_sdh30_reset,
  83. .set_clock = sdhci_set_clock,
  84. .set_bus_width = sdhci_set_bus_width,
  85. .set_uhs_signaling = sdhci_set_uhs_signaling,
  86. };
  87. static const struct sdhci_pltfm_data sdhci_f_sdh30_pltfm_data = {
  88. .ops = &sdhci_f_sdh30_ops,
  89. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
  90. | SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
  91. .quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE
  92. | SDHCI_QUIRK2_TUNING_WORK_AROUND,
  93. };
  94. static int sdhci_f_sdh30_probe(struct platform_device *pdev)
  95. {
  96. struct sdhci_host *host;
  97. struct device *dev = &pdev->dev;
  98. int ctrl = 0, ret = 0;
  99. struct f_sdhost_priv *priv;
  100. struct sdhci_pltfm_host *pltfm_host;
  101. u32 reg = 0;
  102. host = sdhci_pltfm_init(pdev, &sdhci_f_sdh30_pltfm_data,
  103. sizeof(struct f_sdhost_priv));
  104. if (IS_ERR(host))
  105. return PTR_ERR(host);
  106. pltfm_host = sdhci_priv(host);
  107. priv = sdhci_pltfm_priv(pltfm_host);
  108. priv->dev = dev;
  109. priv->enable_cmd_dat_delay = device_property_read_bool(dev,
  110. "fujitsu,cmd-dat-delay-select");
  111. ret = mmc_of_parse(host->mmc);
  112. if (ret)
  113. return ret;
  114. if (dev_of_node(dev)) {
  115. sdhci_get_of_property(pdev);
  116. priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
  117. if (IS_ERR(priv->clk_iface))
  118. return PTR_ERR(priv->clk_iface);
  119. ret = clk_prepare_enable(priv->clk_iface);
  120. if (ret)
  121. return ret;
  122. priv->clk = devm_clk_get(&pdev->dev, "core");
  123. if (IS_ERR(priv->clk)) {
  124. ret = PTR_ERR(priv->clk);
  125. goto err_clk;
  126. }
  127. ret = clk_prepare_enable(priv->clk);
  128. if (ret)
  129. goto err_clk;
  130. priv->rst = devm_reset_control_get_optional_shared(dev, NULL);
  131. if (IS_ERR(priv->rst)) {
  132. ret = PTR_ERR(priv->rst);
  133. goto err_rst;
  134. }
  135. ret = reset_control_deassert(priv->rst);
  136. if (ret)
  137. goto err_rst;
  138. }
  139. /* init vendor specific regs */
  140. ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
  141. ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
  142. F_SDH30_AHB_INCR_4;
  143. ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
  144. sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
  145. reg = sdhci_readl(host, F_SDH30_ESD_CONTROL);
  146. sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
  147. msleep(20);
  148. sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
  149. reg = sdhci_readl(host, SDHCI_CAPABILITIES);
  150. if (reg & SDHCI_CAN_DO_8BIT)
  151. priv->vendor_hs200 = F_SDH30_EMMC_HS200;
  152. if (!(reg & SDHCI_TIMEOUT_CLK_MASK))
  153. host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
  154. ret = sdhci_add_host(host);
  155. if (ret)
  156. goto err_add_host;
  157. return 0;
  158. err_add_host:
  159. reset_control_assert(priv->rst);
  160. err_rst:
  161. clk_disable_unprepare(priv->clk);
  162. err_clk:
  163. clk_disable_unprepare(priv->clk_iface);
  164. return ret;
  165. }
  166. static void sdhci_f_sdh30_remove(struct platform_device *pdev)
  167. {
  168. struct sdhci_host *host = platform_get_drvdata(pdev);
  169. struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
  170. struct clk *clk_iface = priv->clk_iface;
  171. struct reset_control *rst = priv->rst;
  172. struct clk *clk = priv->clk;
  173. sdhci_pltfm_remove(pdev);
  174. reset_control_assert(rst);
  175. clk_disable_unprepare(clk);
  176. clk_disable_unprepare(clk_iface);
  177. }
  178. #ifdef CONFIG_OF
  179. static const struct of_device_id f_sdh30_dt_ids[] = {
  180. { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
  181. { .compatible = "socionext,f-sdh30-e51-mmc" },
  182. { /* sentinel */ }
  183. };
  184. MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids);
  185. #endif
  186. #ifdef CONFIG_ACPI
  187. static const struct acpi_device_id f_sdh30_acpi_ids[] = {
  188. { "SCX0002" },
  189. { /* sentinel */ }
  190. };
  191. MODULE_DEVICE_TABLE(acpi, f_sdh30_acpi_ids);
  192. #endif
  193. static struct platform_driver sdhci_f_sdh30_driver = {
  194. .driver = {
  195. .name = "f_sdh30",
  196. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  197. .of_match_table = of_match_ptr(f_sdh30_dt_ids),
  198. .acpi_match_table = ACPI_PTR(f_sdh30_acpi_ids),
  199. .pm = &sdhci_pltfm_pmops,
  200. },
  201. .probe = sdhci_f_sdh30_probe,
  202. .remove = sdhci_f_sdh30_remove,
  203. };
  204. module_platform_driver(sdhci_f_sdh30_driver);
  205. MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver");
  206. MODULE_LICENSE("GPL v2");
  207. MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD., Socionext Inc.");
  208. MODULE_ALIAS("platform:f_sdh30");