rtsx_pcr.h 4.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /* Driver for Realtek PCI-Express card reader
  3. *
  4. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * Author:
  7. * Wei WANG <wei_wang@realsil.com.cn>
  8. */
  9. #ifndef __RTSX_PCR_H
  10. #define __RTSX_PCR_H
  11. #include <linux/rtsx_pci.h>
  12. #define MIN_DIV_N_PCR 80
  13. #define MAX_DIV_N_PCR 208
  14. #define RTS522A_PME_FORCE_CTL 0xFF78
  15. #define RTS522A_AUTOLOAD_CFG1 0xFF7C
  16. #define RTS522A_PM_CTRL3 0xFF7E
  17. #define RTS524A_PME_FORCE_CTL 0xFF78
  18. #define REG_EFUSE_BYPASS 0x08
  19. #define REG_EFUSE_POR 0x04
  20. #define REG_EFUSE_POWER_MASK 0x03
  21. #define REG_EFUSE_POWERON 0x03
  22. #define REG_EFUSE_POWEROFF 0x00
  23. #define RTS5250_CLK_CFG3 0xFF79
  24. #define RTS525A_CFG_MEM_PD 0xF0
  25. #define RTS524A_AUTOLOAD_CFG1 0xFF7C
  26. #define RTS524A_PM_CTRL3 0xFF7E
  27. #define RTS525A_BIOS_CFG 0xFF2D
  28. #define RTS525A_LOAD_BIOS_FLAG 0x01
  29. #define RTS525A_CLEAR_BIOS_FLAG 0x00
  30. #define RTS525A_EFUSE_CTL 0xFC32
  31. #define REG_EFUSE_ENABLE 0x80
  32. #define REG_EFUSE_MODE 0x40
  33. #define RTS525A_EFUSE_ADD 0xFC33
  34. #define REG_EFUSE_ADD_MASK 0x3F
  35. #define RTS525A_EFUSE_DATA 0xFC35
  36. #define LTR_ACTIVE_LATENCY_DEF 0x883C
  37. #define LTR_IDLE_LATENCY_DEF 0x892C
  38. #define LTR_L1OFF_LATENCY_DEF 0x9003
  39. #define L1_SNOOZE_DELAY_DEF 1
  40. #define LTR_L1OFF_SSPWRGATE_5249_DEF 0xAF
  41. #define LTR_L1OFF_SSPWRGATE_5250_DEF 0xFF
  42. #define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC
  43. #define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8
  44. #define CMD_TIMEOUT_DEF 100
  45. #define MASK_8_BIT_DEF 0xFF
  46. #define SSC_CLOCK_STABLE_WAIT 130
  47. #define RTS524A_OCP_THD_800 0x04
  48. #define RTS525A_OCP_THD_800 0x05
  49. #define RTS522A_OCP_THD_800 0x06
  50. int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
  51. int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
  52. void rts5209_init_params(struct rtsx_pcr *pcr);
  53. void rts5229_init_params(struct rtsx_pcr *pcr);
  54. void rtl8411_init_params(struct rtsx_pcr *pcr);
  55. void rtl8402_init_params(struct rtsx_pcr *pcr);
  56. void rts5227_init_params(struct rtsx_pcr *pcr);
  57. void rts522a_init_params(struct rtsx_pcr *pcr);
  58. void rts5249_init_params(struct rtsx_pcr *pcr);
  59. void rts524a_init_params(struct rtsx_pcr *pcr);
  60. void rts525a_init_params(struct rtsx_pcr *pcr);
  61. void rtl8411b_init_params(struct rtsx_pcr *pcr);
  62. void rts5260_init_params(struct rtsx_pcr *pcr);
  63. void rts5261_init_params(struct rtsx_pcr *pcr);
  64. void rts5228_init_params(struct rtsx_pcr *pcr);
  65. void rts5264_init_params(struct rtsx_pcr *pcr);
  66. static inline u8 map_sd_drive(int idx)
  67. {
  68. u8 sd_drive[4] = {
  69. 0x01, /* Type D */
  70. 0x02, /* Type C */
  71. 0x05, /* Type A */
  72. 0x03 /* Type B */
  73. };
  74. return sd_drive[idx];
  75. }
  76. #define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000))
  77. #define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80))
  78. #define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80)
  79. #define rtsx_check_mmc_support(reg) ((reg) & 0x10)
  80. #define rtsx_reg_to_rtd3(reg) ((reg) & 0x02)
  81. #define rtsx_reg_to_rtd3_uhsii(reg) ((reg) & 0x04)
  82. #define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03)
  83. #define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03)
  84. #define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
  85. #define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6)
  86. #define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000)
  87. #define rtsx_reg_check_cd_reverse(reg) ((reg) & 0x800000)
  88. #define rtsx_reg_check_wp_reverse(reg) ((reg) & 0x400000)
  89. #define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03)
  90. #define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08))
  91. #define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07)
  92. #define rts5209_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x07)
  93. #define rts5209_reg_to_card_drive_sel(reg) ((reg) >> 8)
  94. #define rtl8411_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x07)
  95. #define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03)
  96. #define set_pull_ctrl_tables(pcr, __device) \
  97. do { \
  98. pcr->sd_pull_ctl_enable_tbl = __device##_sd_pull_ctl_enable_tbl; \
  99. pcr->sd_pull_ctl_disable_tbl = __device##_sd_pull_ctl_disable_tbl; \
  100. pcr->ms_pull_ctl_enable_tbl = __device##_ms_pull_ctl_enable_tbl; \
  101. pcr->ms_pull_ctl_disable_tbl = __device##_ms_pull_ctl_disable_tbl; \
  102. } while (0)
  103. /* generic operations */
  104. int rtsx_gops_pm_reset(struct rtsx_pcr *pcr);
  105. int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency);
  106. int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val);
  107. void rtsx_pci_init_ocp(struct rtsx_pcr *pcr);
  108. void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr);
  109. void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr);
  110. int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val);
  111. void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr);
  112. void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr);
  113. void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr);
  114. #endif