aspeed-video.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. // Copyright 2020 IBM Corp.
  3. // Copyright (c) 2019-2020 Intel Corporation
  4. #include <linux/atomic.h>
  5. #include <linux/bitfield.h>
  6. #include <linux/cleanup.h>
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/device.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/jiffies.h>
  13. #include <linux/module.h>
  14. #include <linux/mutex.h>
  15. #include <linux/of.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/of_reserved_mem.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/sched.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/string.h>
  22. #include <linux/v4l2-controls.h>
  23. #include <linux/videodev2.h>
  24. #include <linux/wait.h>
  25. #include <linux/workqueue.h>
  26. #include <linux/debugfs.h>
  27. #include <linux/ktime.h>
  28. #include <linux/reset.h>
  29. #include <linux/regmap.h>
  30. #include <linux/mfd/syscon.h>
  31. #include <media/v4l2-ctrls.h>
  32. #include <media/v4l2-dev.h>
  33. #include <media/v4l2-device.h>
  34. #include <media/v4l2-dv-timings.h>
  35. #include <media/v4l2-event.h>
  36. #include <media/v4l2-ioctl.h>
  37. #include <media/videobuf2-dma-contig.h>
  38. #include <uapi/linux/aspeed-video.h>
  39. #define ASPEED_VIDEO_V4L2_MIN_BUF_REQ 3
  40. #define DEVICE_NAME "aspeed-video"
  41. #define ASPEED_VIDEO_JPEG_NUM_QUALITIES 12
  42. #define ASPEED_VIDEO_JPEG_HEADER_SIZE 10
  43. #define ASPEED_VIDEO_JPEG_QUANT_SIZE 116
  44. #define ASPEED_VIDEO_JPEG_DCT_SIZE 34
  45. #define MAX_FRAME_RATE 60
  46. #define MAX_HEIGHT 1200
  47. #define MAX_WIDTH 1920
  48. #define MIN_HEIGHT 480
  49. #define MIN_WIDTH 640
  50. #define NUM_POLARITY_CHECKS 10
  51. #define INVALID_RESOLUTION_RETRIES 2
  52. #define INVALID_RESOLUTION_DELAY msecs_to_jiffies(250)
  53. #define RESOLUTION_CHANGE_DELAY msecs_to_jiffies(500)
  54. #define MODE_DETECT_TIMEOUT msecs_to_jiffies(500)
  55. #define STOP_TIMEOUT msecs_to_jiffies(1000)
  56. #define DIRECT_FETCH_THRESHOLD 0x0c0000 /* 1024 * 768 */
  57. #define VE_MAX_SRC_BUFFER_SIZE 0x8ca000 /* 1920 * 1200, 32bpp */
  58. #define VE_JPEG_HEADER_SIZE 0x006000 /* 512 * 12 * 4 */
  59. #define VE_BCD_BUFF_SIZE 0x9000 /* (1920/8) * (1200/8) */
  60. #define VE_PROTECTION_KEY 0x000
  61. #define VE_PROTECTION_KEY_UNLOCK 0x1a038aa8
  62. #define VE_SEQ_CTRL 0x004
  63. #define VE_SEQ_CTRL_TRIG_MODE_DET BIT(0)
  64. #define VE_SEQ_CTRL_TRIG_CAPTURE BIT(1)
  65. #define VE_SEQ_CTRL_FORCE_IDLE BIT(2)
  66. #define VE_SEQ_CTRL_MULT_FRAME BIT(3)
  67. #define VE_SEQ_CTRL_TRIG_COMP BIT(4)
  68. #define VE_SEQ_CTRL_AUTO_COMP BIT(5)
  69. #define VE_SEQ_CTRL_EN_WATCHDOG BIT(7)
  70. #define VE_SEQ_CTRL_YUV420 BIT(10)
  71. #define VE_SEQ_CTRL_COMP_FMT GENMASK(11, 10)
  72. #define VE_SEQ_CTRL_HALT BIT(12)
  73. #define VE_SEQ_CTRL_EN_WATCHDOG_COMP BIT(14)
  74. #define VE_SEQ_CTRL_TRIG_JPG BIT(15)
  75. #define VE_SEQ_CTRL_CAP_BUSY BIT(16)
  76. #define VE_SEQ_CTRL_COMP_BUSY BIT(18)
  77. #define AST2500_VE_SEQ_CTRL_JPEG_MODE BIT(13)
  78. #define AST2400_VE_SEQ_CTRL_JPEG_MODE BIT(8)
  79. #define VE_CTRL 0x008
  80. #define VE_CTRL_HSYNC_POL BIT(0)
  81. #define VE_CTRL_VSYNC_POL BIT(1)
  82. #define VE_CTRL_SOURCE BIT(2)
  83. #define VE_CTRL_INT_DE BIT(4)
  84. #define VE_CTRL_DIRECT_FETCH BIT(5)
  85. #define VE_CTRL_CAPTURE_FMT GENMASK(7, 6)
  86. #define VE_CTRL_AUTO_OR_CURSOR BIT(8)
  87. #define VE_CTRL_CLK_INVERSE BIT(11)
  88. #define VE_CTRL_CLK_DELAY GENMASK(11, 9)
  89. #define VE_CTRL_INTERLACE BIT(14)
  90. #define VE_CTRL_HSYNC_POL_CTRL BIT(15)
  91. #define VE_CTRL_FRC GENMASK(23, 16)
  92. #define VE_TGS_0 0x00c
  93. #define VE_TGS_1 0x010
  94. #define VE_TGS_FIRST GENMASK(28, 16)
  95. #define VE_TGS_LAST GENMASK(12, 0)
  96. #define VE_SCALING_FACTOR 0x014
  97. #define VE_SCALING_FILTER0 0x018
  98. #define VE_SCALING_FILTER1 0x01c
  99. #define VE_SCALING_FILTER2 0x020
  100. #define VE_SCALING_FILTER3 0x024
  101. #define VE_BCD_CTRL 0x02C
  102. #define VE_BCD_CTRL_EN_BCD BIT(0)
  103. #define VE_BCD_CTRL_EN_ABCD BIT(1)
  104. #define VE_BCD_CTRL_EN_CB BIT(2)
  105. #define VE_BCD_CTRL_THR GENMASK(23, 16)
  106. #define VE_BCD_CTRL_ABCD_THR GENMASK(31, 24)
  107. #define VE_CAP_WINDOW 0x030
  108. #define VE_COMP_WINDOW 0x034
  109. #define VE_COMP_PROC_OFFSET 0x038
  110. #define VE_COMP_OFFSET 0x03c
  111. #define VE_JPEG_ADDR 0x040
  112. #define VE_SRC0_ADDR 0x044
  113. #define VE_SRC_SCANLINE_OFFSET 0x048
  114. #define VE_SRC1_ADDR 0x04c
  115. #define VE_BCD_ADDR 0x050
  116. #define VE_COMP_ADDR 0x054
  117. #define VE_STREAM_BUF_SIZE 0x058
  118. #define VE_STREAM_BUF_SIZE_N_PACKETS GENMASK(5, 3)
  119. #define VE_STREAM_BUF_SIZE_P_SIZE GENMASK(2, 0)
  120. #define VE_COMP_CTRL 0x060
  121. #define VE_COMP_CTRL_VQ_DCT_ONLY BIT(0)
  122. #define VE_COMP_CTRL_VQ_4COLOR BIT(1)
  123. #define VE_COMP_CTRL_QUANTIZE BIT(2)
  124. #define VE_COMP_CTRL_EN_BQ BIT(4)
  125. #define VE_COMP_CTRL_EN_CRYPTO BIT(5)
  126. #define VE_COMP_CTRL_DCT_CHR GENMASK(10, 6)
  127. #define VE_COMP_CTRL_DCT_LUM GENMASK(15, 11)
  128. #define VE_COMP_CTRL_EN_HQ BIT(16)
  129. #define VE_COMP_CTRL_RSVD BIT(19)
  130. #define VE_COMP_CTRL_ENCODE GENMASK(21, 20)
  131. #define VE_COMP_CTRL_HQ_DCT_CHR GENMASK(26, 22)
  132. #define VE_COMP_CTRL_HQ_DCT_LUM GENMASK(31, 27)
  133. #define VE_CB_ADDR 0x06C
  134. #define AST2400_VE_COMP_SIZE_READ_BACK 0x078
  135. #define AST2600_VE_COMP_SIZE_READ_BACK 0x084
  136. #define VE_SRC_LR_EDGE_DET 0x090
  137. #define VE_SRC_LR_EDGE_DET_LEFT GENMASK(11, 0)
  138. #define VE_SRC_LR_EDGE_DET_NO_V BIT(12)
  139. #define VE_SRC_LR_EDGE_DET_NO_H BIT(13)
  140. #define VE_SRC_LR_EDGE_DET_NO_DISP BIT(14)
  141. #define VE_SRC_LR_EDGE_DET_NO_CLK BIT(15)
  142. #define VE_SRC_LR_EDGE_DET_RT GENMASK(27, 16)
  143. #define VE_SRC_LR_EDGE_DET_INTERLACE BIT(31)
  144. #define VE_SRC_TB_EDGE_DET 0x094
  145. #define VE_SRC_TB_EDGE_DET_TOP GENMASK(12, 0)
  146. #define VE_SRC_TB_EDGE_DET_BOT GENMASK(28, 16)
  147. #define VE_MODE_DETECT_STATUS 0x098
  148. #define VE_MODE_DETECT_H_PERIOD GENMASK(11, 0)
  149. #define VE_MODE_DETECT_EXTSRC_ADC BIT(12)
  150. #define VE_MODE_DETECT_H_STABLE BIT(13)
  151. #define VE_MODE_DETECT_V_STABLE BIT(14)
  152. #define VE_MODE_DETECT_V_LINES GENMASK(27, 16)
  153. #define VE_MODE_DETECT_STATUS_VSYNC BIT(28)
  154. #define VE_MODE_DETECT_STATUS_HSYNC BIT(29)
  155. #define VE_MODE_DETECT_VSYNC_RDY BIT(30)
  156. #define VE_MODE_DETECT_HSYNC_RDY BIT(31)
  157. #define VE_SYNC_STATUS 0x09c
  158. #define VE_SYNC_STATUS_HSYNC GENMASK(11, 0)
  159. #define VE_SYNC_STATUS_VSYNC GENMASK(27, 16)
  160. #define VE_H_TOTAL_PIXELS 0x0A0
  161. #define VE_INTERRUPT_CTRL 0x304
  162. #define VE_INTERRUPT_STATUS 0x308
  163. #define VE_INTERRUPT_MODE_DETECT_WD BIT(0)
  164. #define VE_INTERRUPT_CAPTURE_COMPLETE BIT(1)
  165. #define VE_INTERRUPT_COMP_READY BIT(2)
  166. #define VE_INTERRUPT_COMP_COMPLETE BIT(3)
  167. #define VE_INTERRUPT_MODE_DETECT BIT(4)
  168. #define VE_INTERRUPT_FRAME_COMPLETE BIT(5)
  169. #define VE_INTERRUPT_DECODE_ERR BIT(6)
  170. #define VE_INTERRUPT_HALT_READY BIT(8)
  171. #define VE_INTERRUPT_HANG_WD BIT(9)
  172. #define VE_INTERRUPT_STREAM_DESC BIT(10)
  173. #define VE_INTERRUPT_VSYNC_DESC BIT(11)
  174. #define VE_MODE_DETECT 0x30c
  175. #define VE_MODE_DT_HOR_TOLER GENMASK(31, 28)
  176. #define VE_MODE_DT_VER_TOLER GENMASK(27, 24)
  177. #define VE_MODE_DT_HOR_STABLE GENMASK(23, 20)
  178. #define VE_MODE_DT_VER_STABLE GENMASK(19, 16)
  179. #define VE_MODE_DT_EDG_THROD GENMASK(15, 8)
  180. #define VE_MEM_RESTRICT_START 0x310
  181. #define VE_MEM_RESTRICT_END 0x314
  182. /* SCU's registers */
  183. #define SCU_MISC_CTRL 0xC0
  184. #define SCU_DPLL_SOURCE BIT(20)
  185. /* GFX's registers */
  186. #define GFX_CTRL 0x60
  187. #define GFX_CTRL_ENABLE BIT(0)
  188. #define GFX_CTRL_FMT GENMASK(9, 7)
  189. #define GFX_H_DISPLAY 0x70
  190. #define GFX_H_DISPLAY_DE GENMASK(28, 16)
  191. #define GFX_H_DISPLAY_TOTAL GENMASK(12, 0)
  192. #define GFX_V_DISPLAY 0x78
  193. #define GFX_V_DISPLAY_DE GENMASK(27, 16)
  194. #define GFX_V_DISPLAY_TOTAL GENMASK(11, 0)
  195. #define GFX_DISPLAY_ADDR 0x80
  196. /*
  197. * VIDEO_MODE_DETECT_DONE: a flag raised if signal lock
  198. * VIDEO_RES_CHANGE: a flag raised if res_change work on-going
  199. * VIDEO_RES_DETECT: a flag raised if res. detection on-going
  200. * VIDEO_STREAMING: a flag raised if user requires stream-on
  201. * VIDEO_FRAME_INPRG: a flag raised if hw working on a frame
  202. * VIDEO_STOPPED: a flag raised if device release
  203. * VIDEO_CLOCKS_ON: a flag raised if clk is on
  204. */
  205. enum {
  206. VIDEO_MODE_DETECT_DONE,
  207. VIDEO_RES_CHANGE,
  208. VIDEO_RES_DETECT,
  209. VIDEO_STREAMING,
  210. VIDEO_FRAME_INPRG,
  211. VIDEO_STOPPED,
  212. VIDEO_CLOCKS_ON,
  213. };
  214. enum aspeed_video_format {
  215. VIDEO_FMT_STANDARD = 0,
  216. VIDEO_FMT_ASPEED,
  217. VIDEO_FMT_MAX = VIDEO_FMT_ASPEED
  218. };
  219. // for VE_CTRL_CAPTURE_FMT
  220. enum aspeed_video_capture_format {
  221. VIDEO_CAP_FMT_YUV_STUDIO_SWING = 0,
  222. VIDEO_CAP_FMT_YUV_FULL_SWING,
  223. VIDEO_CAP_FMT_RGB,
  224. VIDEO_CAP_FMT_GRAY,
  225. VIDEO_CAP_FMT_MAX
  226. };
  227. struct aspeed_video_addr {
  228. unsigned int size;
  229. dma_addr_t dma;
  230. void *virt;
  231. };
  232. struct aspeed_video_buffer {
  233. struct vb2_v4l2_buffer vb;
  234. struct list_head link;
  235. };
  236. struct aspeed_video_perf {
  237. ktime_t last_sample;
  238. u32 totaltime;
  239. u32 duration;
  240. u32 duration_min;
  241. u32 duration_max;
  242. };
  243. #define to_aspeed_video_buffer(x) \
  244. container_of((x), struct aspeed_video_buffer, vb)
  245. /*
  246. * struct aspeed_video - driver data
  247. *
  248. * version: holds the version of aspeed SoC
  249. * res_work: holds the delayed_work for res-detection if unlock
  250. * buffers: holds the list of buffer queued from user
  251. * flags: holds the state of video
  252. * sequence: holds the last number of frame completed
  253. * max_compressed_size: holds max compressed stream's size
  254. * srcs: holds the buffer information for srcs
  255. * jpeg: holds the buffer information for jpeg header
  256. * bcd: holds the buffer information for bcd work
  257. * yuv420: a flag raised if JPEG subsampling is 420
  258. * format: holds the video format
  259. * hq_mode: a flag raised if HQ is enabled. Only for VIDEO_FMT_ASPEED
  260. * input: holds the video input
  261. * frame_rate: holds the frame_rate
  262. * jpeg_quality: holds jpeq's quality (0~11)
  263. * jpeg_hq_quality: holds hq's quality (1~12) only if hq_mode enabled
  264. * frame_bottom: end position of video data in vertical direction
  265. * frame_left: start position of video data in horizontal direction
  266. * frame_right: end position of video data in horizontal direction
  267. * frame_top: start position of video data in vertical direction
  268. * perf: holds the statistics primary for debugfs
  269. */
  270. struct aspeed_video {
  271. void __iomem *base;
  272. struct clk *eclk;
  273. struct clk *vclk;
  274. struct reset_control *reset;
  275. struct device *dev;
  276. struct v4l2_ctrl_handler ctrl_handler;
  277. struct v4l2_device v4l2_dev;
  278. struct v4l2_pix_format pix_fmt;
  279. struct v4l2_bt_timings active_timings;
  280. struct v4l2_bt_timings detected_timings;
  281. u32 v4l2_input_status;
  282. struct vb2_queue queue;
  283. struct video_device vdev;
  284. struct mutex video_lock; /* v4l2 and videobuf2 lock */
  285. struct regmap *scu;
  286. struct regmap *gfx;
  287. u32 version;
  288. u32 jpeg_mode;
  289. u32 comp_size_read;
  290. wait_queue_head_t wait;
  291. spinlock_t lock; /* buffer list lock */
  292. struct delayed_work res_work;
  293. struct list_head buffers;
  294. unsigned long flags;
  295. unsigned int sequence;
  296. unsigned int max_compressed_size;
  297. struct aspeed_video_addr srcs[2];
  298. struct aspeed_video_addr jpeg;
  299. struct aspeed_video_addr bcd;
  300. bool yuv420;
  301. enum aspeed_video_format format;
  302. bool hq_mode;
  303. enum aspeed_video_input input;
  304. unsigned int frame_rate;
  305. unsigned int jpeg_quality;
  306. unsigned int jpeg_hq_quality;
  307. unsigned int frame_bottom;
  308. unsigned int frame_left;
  309. unsigned int frame_right;
  310. unsigned int frame_top;
  311. struct aspeed_video_perf perf;
  312. };
  313. #define to_aspeed_video(x) container_of((x), struct aspeed_video, v4l2_dev)
  314. struct aspeed_video_config {
  315. u32 version;
  316. u32 jpeg_mode;
  317. u32 comp_size_read;
  318. };
  319. static const struct aspeed_video_config ast2400_config = {
  320. .version = 4,
  321. .jpeg_mode = AST2400_VE_SEQ_CTRL_JPEG_MODE,
  322. .comp_size_read = AST2400_VE_COMP_SIZE_READ_BACK,
  323. };
  324. static const struct aspeed_video_config ast2500_config = {
  325. .version = 5,
  326. .jpeg_mode = AST2500_VE_SEQ_CTRL_JPEG_MODE,
  327. .comp_size_read = AST2400_VE_COMP_SIZE_READ_BACK,
  328. };
  329. static const struct aspeed_video_config ast2600_config = {
  330. .version = 6,
  331. .jpeg_mode = AST2500_VE_SEQ_CTRL_JPEG_MODE,
  332. .comp_size_read = AST2600_VE_COMP_SIZE_READ_BACK,
  333. };
  334. static const u32 aspeed_video_jpeg_header[ASPEED_VIDEO_JPEG_HEADER_SIZE] = {
  335. 0xe0ffd8ff, 0x464a1000, 0x01004649, 0x60000101, 0x00006000, 0x0f00feff,
  336. 0x00002d05, 0x00000000, 0x00000000, 0x00dbff00
  337. };
  338. static const u32 aspeed_video_jpeg_quant[ASPEED_VIDEO_JPEG_QUANT_SIZE] = {
  339. 0x081100c0, 0x00000000, 0x00110103, 0x03011102, 0xc4ff0111, 0x00001f00,
  340. 0x01010501, 0x01010101, 0x00000000, 0x00000000, 0x04030201, 0x08070605,
  341. 0xff0b0a09, 0x10b500c4, 0x03010200, 0x03040203, 0x04040505, 0x7d010000,
  342. 0x00030201, 0x12051104, 0x06413121, 0x07615113, 0x32147122, 0x08a19181,
  343. 0xc1b14223, 0xf0d15215, 0x72623324, 0x160a0982, 0x1a191817, 0x28272625,
  344. 0x35342a29, 0x39383736, 0x4544433a, 0x49484746, 0x5554534a, 0x59585756,
  345. 0x6564635a, 0x69686766, 0x7574736a, 0x79787776, 0x8584837a, 0x89888786,
  346. 0x9493928a, 0x98979695, 0xa3a29a99, 0xa7a6a5a4, 0xb2aaa9a8, 0xb6b5b4b3,
  347. 0xbab9b8b7, 0xc5c4c3c2, 0xc9c8c7c6, 0xd4d3d2ca, 0xd8d7d6d5, 0xe2e1dad9,
  348. 0xe6e5e4e3, 0xeae9e8e7, 0xf4f3f2f1, 0xf8f7f6f5, 0xc4fffaf9, 0x00011f00,
  349. 0x01010103, 0x01010101, 0x00000101, 0x00000000, 0x04030201, 0x08070605,
  350. 0xff0b0a09, 0x11b500c4, 0x02010200, 0x04030404, 0x04040507, 0x77020100,
  351. 0x03020100, 0x21050411, 0x41120631, 0x71610751, 0x81322213, 0x91421408,
  352. 0x09c1b1a1, 0xf0523323, 0xd1726215, 0x3424160a, 0x17f125e1, 0x261a1918,
  353. 0x2a292827, 0x38373635, 0x44433a39, 0x48474645, 0x54534a49, 0x58575655,
  354. 0x64635a59, 0x68676665, 0x74736a69, 0x78777675, 0x83827a79, 0x87868584,
  355. 0x928a8988, 0x96959493, 0x9a999897, 0xa5a4a3a2, 0xa9a8a7a6, 0xb4b3b2aa,
  356. 0xb8b7b6b5, 0xc3c2bab9, 0xc7c6c5c4, 0xd2cac9c8, 0xd6d5d4d3, 0xdad9d8d7,
  357. 0xe5e4e3e2, 0xe9e8e7e6, 0xf4f3f2ea, 0xf8f7f6f5, 0xdafffaf9, 0x01030c00,
  358. 0x03110200, 0x003f0011
  359. };
  360. static const u32 aspeed_video_jpeg_dct[ASPEED_VIDEO_JPEG_NUM_QUALITIES]
  361. [ASPEED_VIDEO_JPEG_DCT_SIZE] = {
  362. { 0x0d140043, 0x0c0f110f, 0x11101114, 0x17141516, 0x1e20321e,
  363. 0x3d1e1b1b, 0x32242e2b, 0x4b4c3f48, 0x44463f47, 0x61735a50,
  364. 0x566c5550, 0x88644644, 0x7a766c65, 0x4d808280, 0x8c978d60,
  365. 0x7e73967d, 0xdbff7b80, 0x1f014300, 0x272d2121, 0x3030582d,
  366. 0x697bb958, 0xb8b9b97b, 0xb9b8a6a6, 0xb9b9b9b9, 0xb9b9b9b9,
  367. 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9,
  368. 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xffb9b9b9 },
  369. { 0x0c110043, 0x0a0d0f0d, 0x0f0e0f11, 0x14111213, 0x1a1c2b1a,
  370. 0x351a1818, 0x2b1f2826, 0x4142373f, 0x3c3d373e, 0x55644e46,
  371. 0x4b5f4a46, 0x77573d3c, 0x6b675f58, 0x43707170, 0x7a847b54,
  372. 0x6e64836d, 0xdbff6c70, 0x1b014300, 0x22271d1d, 0x2a2a4c27,
  373. 0x5b6ba04c, 0xa0a0a06b, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0,
  374. 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0,
  375. 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xffa0a0a0 },
  376. { 0x090e0043, 0x090a0c0a, 0x0c0b0c0e, 0x110e0f10, 0x15172415,
  377. 0x2c151313, 0x241a211f, 0x36372e34, 0x31322e33, 0x4653413a,
  378. 0x3e4e3d3a, 0x62483231, 0x58564e49, 0x385d5e5d, 0x656d6645,
  379. 0x5b536c5a, 0xdbff595d, 0x16014300, 0x1c201818, 0x22223f20,
  380. 0x4b58853f, 0x85858558, 0x85858585, 0x85858585, 0x85858585,
  381. 0x85858585, 0x85858585, 0x85858585, 0x85858585, 0x85858585,
  382. 0x85858585, 0x85858585, 0x85858585, 0xff858585 },
  383. { 0x070b0043, 0x07080a08, 0x0a090a0b, 0x0d0b0c0c, 0x11121c11,
  384. 0x23110f0f, 0x1c141a19, 0x2b2b2429, 0x27282428, 0x3842332e,
  385. 0x313e302e, 0x4e392827, 0x46443e3a, 0x2c4a4a4a, 0x50565137,
  386. 0x48425647, 0xdbff474a, 0x12014300, 0x161a1313, 0x1c1c331a,
  387. 0x3d486c33, 0x6c6c6c48, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c,
  388. 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c,
  389. 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0xff6c6c6c },
  390. { 0x06090043, 0x05060706, 0x07070709, 0x0a09090a, 0x0d0e160d,
  391. 0x1b0d0c0c, 0x16101413, 0x21221c20, 0x1e1f1c20, 0x2b332824,
  392. 0x26302624, 0x3d2d1f1e, 0x3735302d, 0x22393a39, 0x3f443f2b,
  393. 0x38334338, 0xdbff3739, 0x0d014300, 0x11130e0e, 0x15152613,
  394. 0x2d355026, 0x50505035, 0x50505050, 0x50505050, 0x50505050,
  395. 0x50505050, 0x50505050, 0x50505050, 0x50505050, 0x50505050,
  396. 0x50505050, 0x50505050, 0x50505050, 0xff505050 },
  397. { 0x04060043, 0x03040504, 0x05040506, 0x07060606, 0x09090f09,
  398. 0x12090808, 0x0f0a0d0d, 0x16161315, 0x14151315, 0x1d221b18,
  399. 0x19201918, 0x281e1514, 0x2423201e, 0x17262726, 0x2a2d2a1c,
  400. 0x25222d25, 0xdbff2526, 0x09014300, 0x0b0d0a0a, 0x0e0e1a0d,
  401. 0x1f25371a, 0x37373725, 0x37373737, 0x37373737, 0x37373737,
  402. 0x37373737, 0x37373737, 0x37373737, 0x37373737, 0x37373737,
  403. 0x37373737, 0x37373737, 0x37373737, 0xff373737 },
  404. { 0x02030043, 0x01020202, 0x02020203, 0x03030303, 0x04040704,
  405. 0x09040404, 0x07050606, 0x0b0b090a, 0x0a0a090a, 0x0e110d0c,
  406. 0x0c100c0c, 0x140f0a0a, 0x1211100f, 0x0b131313, 0x1516150e,
  407. 0x12111612, 0xdbff1213, 0x04014300, 0x05060505, 0x07070d06,
  408. 0x0f121b0d, 0x1b1b1b12, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b,
  409. 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b,
  410. 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0xff1b1b1b },
  411. { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503,
  412. 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908,
  413. 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09,
  414. 0x0c0b0f0c, 0xdbff0c0c, 0x03014300, 0x03040303, 0x04040804,
  415. 0x0a0c1208, 0x1212120c, 0x12121212, 0x12121212, 0x12121212,
  416. 0x12121212, 0x12121212, 0x12121212, 0x12121212, 0x12121212,
  417. 0x12121212, 0x12121212, 0x12121212, 0xff121212 },
  418. { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503,
  419. 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908,
  420. 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09,
  421. 0x0c0b0f0c, 0xdbff0c0c, 0x02014300, 0x03030202, 0x04040703,
  422. 0x080a0f07, 0x0f0f0f0a, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f,
  423. 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f,
  424. 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xff0f0f0f },
  425. { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x02020302,
  426. 0x04020202, 0x03020303, 0x05050405, 0x05050405, 0x07080606,
  427. 0x06080606, 0x0a070505, 0x09080807, 0x05090909, 0x0a0b0a07,
  428. 0x09080b09, 0xdbff0909, 0x02014300, 0x02030202, 0x03030503,
  429. 0x07080c05, 0x0c0c0c08, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c,
  430. 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c,
  431. 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0xff0c0c0c },
  432. { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010201,
  433. 0x03010101, 0x02010202, 0x03030303, 0x03030303, 0x04050404,
  434. 0x04050404, 0x06050303, 0x06050505, 0x03060606, 0x07070704,
  435. 0x06050706, 0xdbff0606, 0x01014300, 0x01020101, 0x02020402,
  436. 0x05060904, 0x09090906, 0x09090909, 0x09090909, 0x09090909,
  437. 0x09090909, 0x09090909, 0x09090909, 0x09090909, 0x09090909,
  438. 0x09090909, 0x09090909, 0x09090909, 0xff090909 },
  439. { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010101,
  440. 0x01010101, 0x01010101, 0x01010101, 0x01010101, 0x02020202,
  441. 0x02020202, 0x03020101, 0x03020202, 0x01030303, 0x03030302,
  442. 0x03020303, 0xdbff0403, 0x01014300, 0x01010101, 0x01010201,
  443. 0x03040602, 0x06060604, 0x06060606, 0x06060606, 0x06060606,
  444. 0x06060606, 0x06060606, 0x06060606, 0x06060606, 0x06060606,
  445. 0x06060606, 0x06060606, 0x06060606, 0xff060606 }
  446. };
  447. static const struct v4l2_dv_timings_cap aspeed_video_timings_cap = {
  448. .type = V4L2_DV_BT_656_1120,
  449. .bt = {
  450. .min_width = MIN_WIDTH,
  451. .max_width = MAX_WIDTH,
  452. .min_height = MIN_HEIGHT,
  453. .max_height = MAX_HEIGHT,
  454. .min_pixelclock = 6574080, /* 640 x 480 x 24Hz */
  455. .max_pixelclock = 138240000, /* 1920 x 1200 x 60Hz */
  456. .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  457. V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
  458. .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
  459. V4L2_DV_BT_CAP_REDUCED_BLANKING |
  460. V4L2_DV_BT_CAP_CUSTOM,
  461. },
  462. };
  463. static const char * const format_str[] = {"Standard JPEG",
  464. "Aspeed JPEG"};
  465. static const char * const input_str[] = {"HOST VGA", "BMC GFX"};
  466. static unsigned int debug;
  467. static bool aspeed_video_alloc_buf(struct aspeed_video *video,
  468. struct aspeed_video_addr *addr,
  469. unsigned int size);
  470. static void aspeed_video_free_buf(struct aspeed_video *video,
  471. struct aspeed_video_addr *addr);
  472. static void aspeed_video_init_jpeg_table(u32 *table, bool yuv420)
  473. {
  474. int i;
  475. unsigned int base;
  476. for (i = 0; i < ASPEED_VIDEO_JPEG_NUM_QUALITIES; i++) {
  477. base = 256 * i; /* AST HW requires this header spacing */
  478. memcpy(&table[base], aspeed_video_jpeg_header,
  479. sizeof(aspeed_video_jpeg_header));
  480. base += ASPEED_VIDEO_JPEG_HEADER_SIZE;
  481. memcpy(&table[base], aspeed_video_jpeg_dct[i],
  482. sizeof(aspeed_video_jpeg_dct[i]));
  483. base += ASPEED_VIDEO_JPEG_DCT_SIZE;
  484. memcpy(&table[base], aspeed_video_jpeg_quant,
  485. sizeof(aspeed_video_jpeg_quant));
  486. if (yuv420)
  487. table[base + 2] = 0x00220103;
  488. }
  489. }
  490. // just update jpeg dct table per 420/444
  491. static void aspeed_video_update_jpeg_table(u32 *table, bool yuv420)
  492. {
  493. int i;
  494. unsigned int base;
  495. for (i = 0; i < ASPEED_VIDEO_JPEG_NUM_QUALITIES; i++) {
  496. base = 256 * i; /* AST HW requires this header spacing */
  497. base += ASPEED_VIDEO_JPEG_HEADER_SIZE +
  498. ASPEED_VIDEO_JPEG_DCT_SIZE;
  499. table[base + 2] = (yuv420) ? 0x00220103 : 0x00110103;
  500. }
  501. }
  502. static void aspeed_video_update(struct aspeed_video *video, u32 reg, u32 clear,
  503. u32 bits)
  504. {
  505. u32 t = readl(video->base + reg);
  506. u32 before = t;
  507. t &= ~clear;
  508. t |= bits;
  509. writel(t, video->base + reg);
  510. v4l2_dbg(3, debug, &video->v4l2_dev, "update %03x[%08x -> %08x]\n",
  511. reg, before, readl(video->base + reg));
  512. }
  513. static u32 aspeed_video_read(struct aspeed_video *video, u32 reg)
  514. {
  515. u32 t = readl(video->base + reg);
  516. v4l2_dbg(3, debug, &video->v4l2_dev, "read %03x[%08x]\n", reg, t);
  517. return t;
  518. }
  519. static void aspeed_video_write(struct aspeed_video *video, u32 reg, u32 val)
  520. {
  521. writel(val, video->base + reg);
  522. v4l2_dbg(3, debug, &video->v4l2_dev, "write %03x[%08x]\n", reg,
  523. readl(video->base + reg));
  524. }
  525. static void update_perf(struct aspeed_video_perf *p)
  526. {
  527. struct aspeed_video *v = container_of(p, struct aspeed_video,
  528. perf);
  529. p->duration =
  530. ktime_to_ms(ktime_sub(ktime_get(), p->last_sample));
  531. p->totaltime += p->duration;
  532. p->duration_max = max(p->duration, p->duration_max);
  533. p->duration_min = min(p->duration, p->duration_min);
  534. v4l2_dbg(2, debug, &v->v4l2_dev, "time consumed: %d ms\n",
  535. p->duration);
  536. }
  537. static int aspeed_video_start_frame(struct aspeed_video *video)
  538. {
  539. dma_addr_t addr;
  540. unsigned long flags;
  541. struct aspeed_video_buffer *buf;
  542. u32 seq_ctrl = aspeed_video_read(video, VE_SEQ_CTRL);
  543. bool bcd_buf_need = (video->format != VIDEO_FMT_STANDARD);
  544. if (video->v4l2_input_status) {
  545. v4l2_dbg(1, debug, &video->v4l2_dev, "No signal; don't start frame\n");
  546. return 0;
  547. }
  548. if (!(seq_ctrl & VE_SEQ_CTRL_COMP_BUSY) ||
  549. !(seq_ctrl & VE_SEQ_CTRL_CAP_BUSY)) {
  550. v4l2_dbg(1, debug, &video->v4l2_dev, "Engine busy; don't start frame\n");
  551. return -EBUSY;
  552. }
  553. if (bcd_buf_need && !video->bcd.size) {
  554. if (!aspeed_video_alloc_buf(video, &video->bcd,
  555. VE_BCD_BUFF_SIZE)) {
  556. dev_err(video->dev, "Failed to allocate BCD buffer\n");
  557. dev_err(video->dev, "don't start frame\n");
  558. return -ENOMEM;
  559. }
  560. aspeed_video_write(video, VE_BCD_ADDR, video->bcd.dma);
  561. v4l2_dbg(1, debug, &video->v4l2_dev, "bcd addr(%pad) size(%d)\n",
  562. &video->bcd.dma, video->bcd.size);
  563. } else if (!bcd_buf_need && video->bcd.size) {
  564. aspeed_video_free_buf(video, &video->bcd);
  565. }
  566. if (video->input == VIDEO_INPUT_GFX) {
  567. u32 val;
  568. // update input buffer address as gfx's
  569. regmap_read(video->gfx, GFX_DISPLAY_ADDR, &val);
  570. aspeed_video_write(video, VE_TGS_0, val);
  571. }
  572. spin_lock_irqsave(&video->lock, flags);
  573. buf = list_first_entry_or_null(&video->buffers,
  574. struct aspeed_video_buffer, link);
  575. if (!buf) {
  576. spin_unlock_irqrestore(&video->lock, flags);
  577. v4l2_dbg(1, debug, &video->v4l2_dev, "No buffers; don't start frame\n");
  578. return -EPROTO;
  579. }
  580. set_bit(VIDEO_FRAME_INPRG, &video->flags);
  581. addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
  582. spin_unlock_irqrestore(&video->lock, flags);
  583. aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0);
  584. aspeed_video_write(video, VE_COMP_OFFSET, 0);
  585. aspeed_video_write(video, VE_COMP_ADDR, addr);
  586. aspeed_video_update(video, VE_INTERRUPT_CTRL, 0,
  587. VE_INTERRUPT_COMP_COMPLETE);
  588. video->perf.last_sample = ktime_get();
  589. aspeed_video_update(video, VE_SEQ_CTRL, 0,
  590. VE_SEQ_CTRL_TRIG_CAPTURE | VE_SEQ_CTRL_TRIG_COMP);
  591. return 0;
  592. }
  593. static void aspeed_video_enable_mode_detect(struct aspeed_video *video)
  594. {
  595. /* Enable mode detect interrupts */
  596. aspeed_video_update(video, VE_INTERRUPT_CTRL, 0,
  597. VE_INTERRUPT_MODE_DETECT);
  598. /* Disable mode detect in order to re-trigger */
  599. aspeed_video_update(video, VE_SEQ_CTRL,
  600. VE_SEQ_CTRL_TRIG_MODE_DET, 0);
  601. /* Trigger mode detect */
  602. aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_TRIG_MODE_DET);
  603. }
  604. static void aspeed_video_off(struct aspeed_video *video)
  605. {
  606. if (!test_bit(VIDEO_CLOCKS_ON, &video->flags))
  607. return;
  608. /* Disable interrupts */
  609. aspeed_video_write(video, VE_INTERRUPT_CTRL, 0);
  610. aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff);
  611. /* Turn off the relevant clocks */
  612. clk_disable(video->eclk);
  613. clk_disable(video->vclk);
  614. clear_bit(VIDEO_CLOCKS_ON, &video->flags);
  615. }
  616. static void aspeed_video_on(struct aspeed_video *video)
  617. {
  618. if (test_bit(VIDEO_CLOCKS_ON, &video->flags))
  619. return;
  620. /* Turn on the relevant clocks */
  621. clk_enable(video->vclk);
  622. clk_enable(video->eclk);
  623. set_bit(VIDEO_CLOCKS_ON, &video->flags);
  624. }
  625. static void aspeed_video_reset(struct aspeed_video *v)
  626. {
  627. reset_control_assert(v->reset);
  628. usleep_range(100, 150);
  629. reset_control_deassert(v->reset);
  630. }
  631. static void aspeed_video_bufs_done(struct aspeed_video *video,
  632. enum vb2_buffer_state state)
  633. {
  634. unsigned long flags;
  635. struct aspeed_video_buffer *buf;
  636. spin_lock_irqsave(&video->lock, flags);
  637. list_for_each_entry(buf, &video->buffers, link)
  638. vb2_buffer_done(&buf->vb.vb2_buf, state);
  639. INIT_LIST_HEAD(&video->buffers);
  640. spin_unlock_irqrestore(&video->lock, flags);
  641. }
  642. static void aspeed_video_irq_res_change(struct aspeed_video *video, ulong delay)
  643. {
  644. v4l2_dbg(1, debug, &video->v4l2_dev, "Resolution changed; resetting\n");
  645. set_bit(VIDEO_RES_CHANGE, &video->flags);
  646. clear_bit(VIDEO_FRAME_INPRG, &video->flags);
  647. video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
  648. aspeed_video_write(video, VE_INTERRUPT_CTRL, 0);
  649. aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff);
  650. aspeed_video_reset(video);
  651. aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR);
  652. schedule_delayed_work(&video->res_work, delay);
  653. }
  654. static void aspeed_video_swap_src_buf(struct aspeed_video *v)
  655. {
  656. if (v->format == VIDEO_FMT_STANDARD)
  657. return;
  658. /* Reset bcd buffer to have a full frame update every 8 frames. */
  659. if (IS_ALIGNED(v->sequence, 8))
  660. memset((u8 *)v->bcd.virt, 0x00, VE_BCD_BUFF_SIZE);
  661. if (v->sequence & 0x01) {
  662. aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[1].dma);
  663. aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[0].dma);
  664. } else {
  665. aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[0].dma);
  666. aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[1].dma);
  667. }
  668. }
  669. static irqreturn_t aspeed_video_irq(int irq, void *arg)
  670. {
  671. struct aspeed_video *video = arg;
  672. u32 sts = aspeed_video_read(video, VE_INTERRUPT_STATUS);
  673. /*
  674. * Hardware sometimes asserts interrupts that we haven't actually
  675. * enabled; ignore them if so.
  676. */
  677. sts &= aspeed_video_read(video, VE_INTERRUPT_CTRL);
  678. v4l2_dbg(2, debug, &video->v4l2_dev, "irq sts=%#x %s%s%s%s\n", sts,
  679. sts & VE_INTERRUPT_MODE_DETECT_WD ? ", unlock" : "",
  680. sts & VE_INTERRUPT_MODE_DETECT ? ", lock" : "",
  681. sts & VE_INTERRUPT_CAPTURE_COMPLETE ? ", capture-done" : "",
  682. sts & VE_INTERRUPT_COMP_COMPLETE ? ", comp-done" : "");
  683. /*
  684. * Resolution changed or signal was lost; reset the engine and
  685. * re-initialize
  686. */
  687. if (sts & VE_INTERRUPT_MODE_DETECT_WD) {
  688. aspeed_video_irq_res_change(video, 0);
  689. return IRQ_HANDLED;
  690. }
  691. if (sts & VE_INTERRUPT_MODE_DETECT) {
  692. if (test_bit(VIDEO_RES_DETECT, &video->flags)) {
  693. aspeed_video_update(video, VE_INTERRUPT_CTRL,
  694. VE_INTERRUPT_MODE_DETECT, 0);
  695. aspeed_video_write(video, VE_INTERRUPT_STATUS,
  696. VE_INTERRUPT_MODE_DETECT);
  697. sts &= ~VE_INTERRUPT_MODE_DETECT;
  698. set_bit(VIDEO_MODE_DETECT_DONE, &video->flags);
  699. wake_up_interruptible_all(&video->wait);
  700. } else {
  701. /*
  702. * Signal acquired while NOT doing resolution
  703. * detection; reset the engine and re-initialize
  704. */
  705. aspeed_video_irq_res_change(video,
  706. RESOLUTION_CHANGE_DELAY);
  707. return IRQ_HANDLED;
  708. }
  709. }
  710. if (sts & VE_INTERRUPT_COMP_COMPLETE) {
  711. struct aspeed_video_buffer *buf;
  712. bool empty = true;
  713. u32 frame_size = aspeed_video_read(video,
  714. video->comp_size_read);
  715. update_perf(&video->perf);
  716. spin_lock(&video->lock);
  717. clear_bit(VIDEO_FRAME_INPRG, &video->flags);
  718. buf = list_first_entry_or_null(&video->buffers,
  719. struct aspeed_video_buffer,
  720. link);
  721. if (buf) {
  722. vb2_set_plane_payload(&buf->vb.vb2_buf, 0, frame_size);
  723. /*
  724. * aspeed_jpeg requires continuous update.
  725. * On the contrary, standard jpeg can keep last buffer
  726. * to always have the latest result.
  727. */
  728. if (video->format == VIDEO_FMT_STANDARD &&
  729. list_is_last(&buf->link, &video->buffers)) {
  730. empty = false;
  731. v4l2_dbg(1, debug, &video->v4l2_dev, "skip to keep last frame updated\n");
  732. } else {
  733. buf->vb.vb2_buf.timestamp = ktime_get_ns();
  734. buf->vb.sequence = video->sequence++;
  735. buf->vb.field = V4L2_FIELD_NONE;
  736. vb2_buffer_done(&buf->vb.vb2_buf,
  737. VB2_BUF_STATE_DONE);
  738. list_del(&buf->link);
  739. empty = list_empty(&video->buffers);
  740. }
  741. }
  742. spin_unlock(&video->lock);
  743. aspeed_video_update(video, VE_SEQ_CTRL,
  744. VE_SEQ_CTRL_TRIG_CAPTURE |
  745. VE_SEQ_CTRL_FORCE_IDLE |
  746. VE_SEQ_CTRL_TRIG_COMP, 0);
  747. aspeed_video_update(video, VE_INTERRUPT_CTRL,
  748. VE_INTERRUPT_COMP_COMPLETE, 0);
  749. aspeed_video_write(video, VE_INTERRUPT_STATUS,
  750. VE_INTERRUPT_COMP_COMPLETE);
  751. sts &= ~VE_INTERRUPT_COMP_COMPLETE;
  752. aspeed_video_swap_src_buf(video);
  753. if (test_bit(VIDEO_STREAMING, &video->flags) && !empty)
  754. aspeed_video_start_frame(video);
  755. }
  756. return sts ? IRQ_NONE : IRQ_HANDLED;
  757. }
  758. static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
  759. {
  760. int i;
  761. int hsync_counter = 0;
  762. int vsync_counter = 0;
  763. u32 sts, ctrl;
  764. for (i = 0; i < NUM_POLARITY_CHECKS; ++i) {
  765. sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS);
  766. if (sts & VE_MODE_DETECT_STATUS_VSYNC)
  767. vsync_counter--;
  768. else
  769. vsync_counter++;
  770. if (sts & VE_MODE_DETECT_STATUS_HSYNC)
  771. hsync_counter--;
  772. else
  773. hsync_counter++;
  774. }
  775. ctrl = aspeed_video_read(video, VE_CTRL);
  776. if (hsync_counter < 0) {
  777. ctrl |= VE_CTRL_HSYNC_POL;
  778. video->detected_timings.polarities &=
  779. ~V4L2_DV_HSYNC_POS_POL;
  780. } else {
  781. ctrl &= ~VE_CTRL_HSYNC_POL;
  782. video->detected_timings.polarities |=
  783. V4L2_DV_HSYNC_POS_POL;
  784. }
  785. if (vsync_counter < 0) {
  786. ctrl |= VE_CTRL_VSYNC_POL;
  787. video->detected_timings.polarities &=
  788. ~V4L2_DV_VSYNC_POS_POL;
  789. } else {
  790. ctrl &= ~VE_CTRL_VSYNC_POL;
  791. video->detected_timings.polarities |=
  792. V4L2_DV_VSYNC_POS_POL;
  793. }
  794. aspeed_video_write(video, VE_CTRL, ctrl);
  795. }
  796. static bool aspeed_video_alloc_buf(struct aspeed_video *video,
  797. struct aspeed_video_addr *addr,
  798. unsigned int size)
  799. {
  800. addr->virt = dma_alloc_coherent(video->dev, size, &addr->dma,
  801. GFP_KERNEL);
  802. if (!addr->virt)
  803. return false;
  804. addr->size = size;
  805. return true;
  806. }
  807. static void aspeed_video_free_buf(struct aspeed_video *video,
  808. struct aspeed_video_addr *addr)
  809. {
  810. dma_free_coherent(video->dev, addr->size, addr->virt, addr->dma);
  811. addr->size = 0;
  812. addr->dma = 0ULL;
  813. addr->virt = NULL;
  814. }
  815. /*
  816. * Get the minimum HW-supported compression buffer size for the frame size.
  817. * Assume worst-case JPEG compression size is 1/8 raw size. This should be
  818. * plenty even for maximum quality; any worse and the engine will simply return
  819. * incomplete JPEGs.
  820. */
  821. static void aspeed_video_calc_compressed_size(struct aspeed_video *video,
  822. unsigned int frame_size)
  823. {
  824. int i, j;
  825. u32 compression_buffer_size_reg = 0;
  826. unsigned int size;
  827. const unsigned int num_compression_packets = 4;
  828. const unsigned int compression_packet_size = 1024;
  829. const unsigned int max_compressed_size = frame_size / 2; /* 4bpp / 8 */
  830. video->max_compressed_size = UINT_MAX;
  831. for (i = 0; i < 6; ++i) {
  832. for (j = 0; j < 8; ++j) {
  833. size = (num_compression_packets << i) *
  834. (compression_packet_size << j);
  835. if (size < max_compressed_size)
  836. continue;
  837. if (size < video->max_compressed_size) {
  838. compression_buffer_size_reg = (i << 3) | j;
  839. video->max_compressed_size = size;
  840. }
  841. }
  842. }
  843. aspeed_video_write(video, VE_STREAM_BUF_SIZE,
  844. compression_buffer_size_reg);
  845. v4l2_dbg(1, debug, &video->v4l2_dev, "Max compressed size: %#x\n",
  846. video->max_compressed_size);
  847. }
  848. /*
  849. * Update v4l2_bt_timings per current status.
  850. * frame_top/frame_bottom/frame_left/frame_right need to be ready.
  851. *
  852. * The following registers start counting from sync's rising edge:
  853. * 1. VR090: frame edge's left and right
  854. * 2. VR094: frame edge's top and bottom
  855. * 3. VR09C: counting from sync's rising edge to falling edge
  856. *
  857. * [Vertical timing]
  858. * +--+ +-------------------+ +--+
  859. * | | | v i d e o | | |
  860. * +--+ +-----+ +-----+ +---+
  861. * vsync+--+
  862. * frame_top+--------+
  863. * frame_bottom+----------------------------+
  864. *
  865. * +-------------------+
  866. * | v i d e o |
  867. * +--+ +-----+ +-----+ +---+
  868. * | | | |
  869. * +--+ +--+
  870. * vsync+-------------------------------+
  871. * frame_top+-----+
  872. * frame_bottom+-------------------------+
  873. *
  874. * [Horizontal timing]
  875. * +--+ +-------------------+ +--+
  876. * | | | v i d e o | | |
  877. * +--+ +-----+ +-----+ +---+
  878. * hsync+--+
  879. * frame_left+--------+
  880. * frame_right+----------------------------+
  881. *
  882. * +-------------------+
  883. * | v i d e o |
  884. * +--+ +-----+ +-----+ +---+
  885. * | | | |
  886. * +--+ +--+
  887. * hsync+-------------------------------+
  888. * frame_left+-----+
  889. * frame_right+-------------------------+
  890. *
  891. * @v: the struct of aspeed_video
  892. * @det: v4l2_bt_timings to be updated.
  893. */
  894. static void aspeed_video_get_timings(struct aspeed_video *v,
  895. struct v4l2_bt_timings *det)
  896. {
  897. u32 mds, sync, htotal, vtotal, vsync, hsync;
  898. mds = aspeed_video_read(v, VE_MODE_DETECT_STATUS);
  899. sync = aspeed_video_read(v, VE_SYNC_STATUS);
  900. htotal = aspeed_video_read(v, VE_H_TOTAL_PIXELS);
  901. vtotal = FIELD_GET(VE_MODE_DETECT_V_LINES, mds);
  902. vsync = FIELD_GET(VE_SYNC_STATUS_VSYNC, sync);
  903. hsync = FIELD_GET(VE_SYNC_STATUS_HSYNC, sync);
  904. /*
  905. * This is a workaround for polarity detection.
  906. * Because ast-soc counts sync from sync's rising edge, the reg value
  907. * of sync would be larger than video's active area if negative.
  908. */
  909. if (vsync > det->height)
  910. det->polarities &= ~V4L2_DV_VSYNC_POS_POL;
  911. else
  912. det->polarities |= V4L2_DV_VSYNC_POS_POL;
  913. if (hsync > det->width)
  914. det->polarities &= ~V4L2_DV_HSYNC_POS_POL;
  915. else
  916. det->polarities |= V4L2_DV_HSYNC_POS_POL;
  917. if (det->polarities & V4L2_DV_VSYNC_POS_POL) {
  918. det->vbackporch = v->frame_top - vsync;
  919. det->vfrontporch = vtotal - v->frame_bottom;
  920. det->vsync = vsync;
  921. } else {
  922. det->vbackporch = v->frame_top;
  923. det->vfrontporch = vsync - v->frame_bottom;
  924. det->vsync = vtotal - vsync;
  925. }
  926. if (det->polarities & V4L2_DV_HSYNC_POS_POL) {
  927. det->hbackporch = v->frame_left - hsync;
  928. det->hfrontporch = htotal - v->frame_right;
  929. det->hsync = hsync;
  930. } else {
  931. det->hbackporch = v->frame_left;
  932. det->hfrontporch = hsync - v->frame_right;
  933. det->hsync = htotal - hsync;
  934. }
  935. }
  936. static void aspeed_video_get_resolution_gfx(struct aspeed_video *video,
  937. struct v4l2_bt_timings *det)
  938. {
  939. u32 h_val, v_val;
  940. regmap_read(video->gfx, GFX_H_DISPLAY, &h_val);
  941. regmap_read(video->gfx, GFX_V_DISPLAY, &v_val);
  942. det->width = FIELD_GET(GFX_H_DISPLAY_DE, h_val) + 1;
  943. det->height = FIELD_GET(GFX_V_DISPLAY_DE, v_val) + 1;
  944. video->v4l2_input_status = 0;
  945. }
  946. #define res_check(v) test_and_clear_bit(VIDEO_MODE_DETECT_DONE, &(v)->flags)
  947. static void aspeed_video_get_resolution_vga(struct aspeed_video *video,
  948. struct v4l2_bt_timings *det)
  949. {
  950. bool invalid_resolution = true;
  951. int rc;
  952. int tries = 0;
  953. u32 mds;
  954. u32 src_lr_edge;
  955. u32 src_tb_edge;
  956. det->width = MIN_WIDTH;
  957. det->height = MIN_HEIGHT;
  958. video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
  959. memset(&video->perf, 0, sizeof(video->perf));
  960. do {
  961. if (tries) {
  962. set_current_state(TASK_INTERRUPTIBLE);
  963. if (schedule_timeout(INVALID_RESOLUTION_DELAY))
  964. return;
  965. }
  966. set_bit(VIDEO_RES_DETECT, &video->flags);
  967. aspeed_video_update(video, VE_CTRL,
  968. VE_CTRL_VSYNC_POL | VE_CTRL_HSYNC_POL, 0);
  969. aspeed_video_enable_mode_detect(video);
  970. rc = wait_event_interruptible_timeout(video->wait,
  971. res_check(video),
  972. MODE_DETECT_TIMEOUT);
  973. if (!rc) {
  974. v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out; first mode detect\n");
  975. clear_bit(VIDEO_RES_DETECT, &video->flags);
  976. return;
  977. }
  978. mds = aspeed_video_read(video, VE_MODE_DETECT_STATUS);
  979. // try detection again if current signal isn't stable
  980. if (!(mds & VE_MODE_DETECT_H_STABLE) ||
  981. !(mds & VE_MODE_DETECT_V_STABLE) ||
  982. (mds & VE_MODE_DETECT_EXTSRC_ADC))
  983. continue;
  984. aspeed_video_check_and_set_polarity(video);
  985. aspeed_video_enable_mode_detect(video);
  986. rc = wait_event_interruptible_timeout(video->wait,
  987. res_check(video),
  988. MODE_DETECT_TIMEOUT);
  989. clear_bit(VIDEO_RES_DETECT, &video->flags);
  990. if (!rc) {
  991. v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out; second mode detect\n");
  992. return;
  993. }
  994. src_lr_edge = aspeed_video_read(video, VE_SRC_LR_EDGE_DET);
  995. src_tb_edge = aspeed_video_read(video, VE_SRC_TB_EDGE_DET);
  996. video->frame_bottom = FIELD_GET(VE_SRC_TB_EDGE_DET_BOT, src_tb_edge);
  997. video->frame_top = FIELD_GET(VE_SRC_TB_EDGE_DET_TOP, src_tb_edge);
  998. if (video->frame_top > video->frame_bottom)
  999. continue;
  1000. video->frame_right = FIELD_GET(VE_SRC_LR_EDGE_DET_RT, src_lr_edge);
  1001. video->frame_left = FIELD_GET(VE_SRC_LR_EDGE_DET_LEFT, src_lr_edge);
  1002. if (video->frame_left > video->frame_right)
  1003. continue;
  1004. invalid_resolution = false;
  1005. } while (invalid_resolution && (tries++ < INVALID_RESOLUTION_RETRIES));
  1006. if (invalid_resolution) {
  1007. v4l2_dbg(1, debug, &video->v4l2_dev, "Invalid resolution detected\n");
  1008. return;
  1009. }
  1010. det->height = (video->frame_bottom - video->frame_top) + 1;
  1011. det->width = (video->frame_right - video->frame_left) + 1;
  1012. video->v4l2_input_status = 0;
  1013. aspeed_video_get_timings(video, det);
  1014. /* Enable mode-detect watchdog, resolution-change watchdog */
  1015. aspeed_video_update(video, VE_INTERRUPT_CTRL, 0,
  1016. VE_INTERRUPT_MODE_DETECT_WD);
  1017. aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_EN_WATCHDOG);
  1018. }
  1019. static void aspeed_video_get_resolution(struct aspeed_video *video)
  1020. {
  1021. struct v4l2_bt_timings *det = &video->detected_timings;
  1022. if (video->input == VIDEO_INPUT_GFX)
  1023. aspeed_video_get_resolution_gfx(video, det);
  1024. else
  1025. aspeed_video_get_resolution_vga(video, det);
  1026. v4l2_dbg(1, debug, &video->v4l2_dev, "Got resolution: %dx%d\n",
  1027. det->width, det->height);
  1028. }
  1029. static void aspeed_video_set_resolution(struct aspeed_video *video)
  1030. {
  1031. struct v4l2_bt_timings *act = &video->active_timings;
  1032. unsigned int size = act->width * ALIGN(act->height, 8);
  1033. /* Set capture/compression frame sizes */
  1034. aspeed_video_calc_compressed_size(video, size);
  1035. if (!IS_ALIGNED(act->width, 64)) {
  1036. /*
  1037. * This is a workaround to fix a AST2500 silicon bug on A1 and
  1038. * A2 revisions. Since it doesn't break capturing operation of
  1039. * other revisions, use it for all revisions without checking
  1040. * the revision ID. It picked new width which is a very next
  1041. * 64-pixels aligned value to minimize memory bandwidth
  1042. * and to get better access speed from video engine.
  1043. */
  1044. u32 width = ALIGN(act->width, 64);
  1045. aspeed_video_write(video, VE_CAP_WINDOW, width << 16 | act->height);
  1046. size = width * ALIGN(act->height, 8);
  1047. } else {
  1048. aspeed_video_write(video, VE_CAP_WINDOW,
  1049. act->width << 16 | act->height);
  1050. }
  1051. aspeed_video_write(video, VE_COMP_WINDOW,
  1052. act->width << 16 | act->height);
  1053. aspeed_video_write(video, VE_SRC_SCANLINE_OFFSET, act->width * 4);
  1054. /* Don't use direct mode below 1024 x 768 (irqs don't fire) */
  1055. if (video->input == VIDEO_INPUT_VGA && size < DIRECT_FETCH_THRESHOLD) {
  1056. v4l2_dbg(1, debug, &video->v4l2_dev, "Capture: Sync Mode\n");
  1057. aspeed_video_write(video, VE_TGS_0,
  1058. FIELD_PREP(VE_TGS_FIRST,
  1059. video->frame_left - 1) |
  1060. FIELD_PREP(VE_TGS_LAST,
  1061. video->frame_right));
  1062. aspeed_video_write(video, VE_TGS_1,
  1063. FIELD_PREP(VE_TGS_FIRST, video->frame_top) |
  1064. FIELD_PREP(VE_TGS_LAST,
  1065. video->frame_bottom + 1));
  1066. aspeed_video_update(video, VE_CTRL,
  1067. VE_CTRL_INT_DE | VE_CTRL_DIRECT_FETCH,
  1068. VE_CTRL_INT_DE);
  1069. } else {
  1070. u32 ctrl, val, bpp;
  1071. v4l2_dbg(1, debug, &video->v4l2_dev, "Capture: Direct Mode\n");
  1072. ctrl = VE_CTRL_DIRECT_FETCH;
  1073. if (video->input == VIDEO_INPUT_GFX) {
  1074. regmap_read(video->gfx, GFX_CTRL, &val);
  1075. bpp = FIELD_GET(GFX_CTRL_FMT, val) ? 32 : 16;
  1076. if (bpp == 16)
  1077. ctrl |= VE_CTRL_INT_DE;
  1078. aspeed_video_write(video, VE_TGS_1, act->width * (bpp >> 3));
  1079. }
  1080. aspeed_video_update(video, VE_CTRL,
  1081. VE_CTRL_INT_DE | VE_CTRL_DIRECT_FETCH,
  1082. ctrl);
  1083. }
  1084. size *= 4;
  1085. if (size != video->srcs[0].size) {
  1086. if (video->srcs[0].size)
  1087. aspeed_video_free_buf(video, &video->srcs[0]);
  1088. if (video->srcs[1].size)
  1089. aspeed_video_free_buf(video, &video->srcs[1]);
  1090. if (!aspeed_video_alloc_buf(video, &video->srcs[0], size))
  1091. goto err_mem;
  1092. if (!aspeed_video_alloc_buf(video, &video->srcs[1], size))
  1093. goto err_mem;
  1094. v4l2_dbg(1, debug, &video->v4l2_dev, "src buf0 addr(%pad) size(%d)\n",
  1095. &video->srcs[0].dma, video->srcs[0].size);
  1096. v4l2_dbg(1, debug, &video->v4l2_dev, "src buf1 addr(%pad) size(%d)\n",
  1097. &video->srcs[1].dma, video->srcs[1].size);
  1098. aspeed_video_write(video, VE_SRC0_ADDR, video->srcs[0].dma);
  1099. aspeed_video_write(video, VE_SRC1_ADDR, video->srcs[1].dma);
  1100. }
  1101. return;
  1102. err_mem:
  1103. dev_err(video->dev, "Failed to allocate source buffers\n");
  1104. if (video->srcs[0].size)
  1105. aspeed_video_free_buf(video, &video->srcs[0]);
  1106. }
  1107. /*
  1108. * Update relative parameters when timing changed.
  1109. *
  1110. * @video: the struct of aspeed_video
  1111. * @timings: the new timings
  1112. */
  1113. static void aspeed_video_update_timings(struct aspeed_video *video, struct v4l2_bt_timings *timings)
  1114. {
  1115. video->active_timings = *timings;
  1116. aspeed_video_set_resolution(video);
  1117. video->pix_fmt.width = timings->width;
  1118. video->pix_fmt.height = timings->height;
  1119. video->pix_fmt.sizeimage = video->max_compressed_size;
  1120. }
  1121. static void aspeed_video_update_regs(struct aspeed_video *video)
  1122. {
  1123. u8 jpeg_hq_quality = clamp((int)video->jpeg_hq_quality - 1, 0,
  1124. ASPEED_VIDEO_JPEG_NUM_QUALITIES - 1);
  1125. u32 comp_ctrl = FIELD_PREP(VE_COMP_CTRL_DCT_LUM, video->jpeg_quality) |
  1126. FIELD_PREP(VE_COMP_CTRL_DCT_CHR, video->jpeg_quality | 0x10) |
  1127. FIELD_PREP(VE_COMP_CTRL_EN_HQ, video->hq_mode) |
  1128. FIELD_PREP(VE_COMP_CTRL_HQ_DCT_LUM, jpeg_hq_quality) |
  1129. FIELD_PREP(VE_COMP_CTRL_HQ_DCT_CHR, jpeg_hq_quality | 0x10);
  1130. u32 ctrl = 0;
  1131. u32 seq_ctrl = 0;
  1132. v4l2_dbg(1, debug, &video->v4l2_dev, "input(%s)\n",
  1133. input_str[video->input]);
  1134. v4l2_dbg(1, debug, &video->v4l2_dev, "framerate(%d)\n",
  1135. video->frame_rate);
  1136. v4l2_dbg(1, debug, &video->v4l2_dev, "jpeg format(%s) subsample(%s)\n",
  1137. format_str[video->format],
  1138. video->yuv420 ? "420" : "444");
  1139. v4l2_dbg(1, debug, &video->v4l2_dev, "compression quality(%d)\n",
  1140. video->jpeg_quality);
  1141. v4l2_dbg(1, debug, &video->v4l2_dev, "hq_mode(%s) hq_quality(%d)\n",
  1142. video->hq_mode ? "on" : "off", video->jpeg_hq_quality);
  1143. if (video->format == VIDEO_FMT_ASPEED)
  1144. aspeed_video_update(video, VE_BCD_CTRL, 0, VE_BCD_CTRL_EN_BCD);
  1145. else
  1146. aspeed_video_update(video, VE_BCD_CTRL, VE_BCD_CTRL_EN_BCD, 0);
  1147. if (video->input == VIDEO_INPUT_VGA)
  1148. ctrl |= VE_CTRL_AUTO_OR_CURSOR;
  1149. if (video->frame_rate)
  1150. ctrl |= FIELD_PREP(VE_CTRL_FRC, video->frame_rate);
  1151. if (video->format == VIDEO_FMT_STANDARD) {
  1152. comp_ctrl &= ~FIELD_PREP(VE_COMP_CTRL_EN_HQ, video->hq_mode);
  1153. seq_ctrl |= video->jpeg_mode;
  1154. }
  1155. if (video->yuv420)
  1156. seq_ctrl |= VE_SEQ_CTRL_YUV420;
  1157. if (video->jpeg.virt)
  1158. aspeed_video_update_jpeg_table(video->jpeg.virt, video->yuv420);
  1159. /* Set control registers */
  1160. aspeed_video_update(video, VE_SEQ_CTRL,
  1161. video->jpeg_mode | VE_SEQ_CTRL_YUV420,
  1162. seq_ctrl);
  1163. aspeed_video_update(video, VE_CTRL,
  1164. VE_CTRL_FRC | VE_CTRL_AUTO_OR_CURSOR |
  1165. VE_CTRL_SOURCE, ctrl);
  1166. aspeed_video_update(video, VE_COMP_CTRL,
  1167. VE_COMP_CTRL_DCT_LUM | VE_COMP_CTRL_DCT_CHR |
  1168. VE_COMP_CTRL_EN_HQ | VE_COMP_CTRL_HQ_DCT_LUM |
  1169. VE_COMP_CTRL_HQ_DCT_CHR | VE_COMP_CTRL_VQ_4COLOR |
  1170. VE_COMP_CTRL_VQ_DCT_ONLY,
  1171. comp_ctrl);
  1172. }
  1173. static void aspeed_video_init_regs(struct aspeed_video *video)
  1174. {
  1175. u32 ctrl = VE_CTRL_AUTO_OR_CURSOR |
  1176. FIELD_PREP(VE_CTRL_CAPTURE_FMT, VIDEO_CAP_FMT_YUV_FULL_SWING);
  1177. /* Unlock VE registers */
  1178. aspeed_video_write(video, VE_PROTECTION_KEY, VE_PROTECTION_KEY_UNLOCK);
  1179. /* Disable interrupts */
  1180. aspeed_video_write(video, VE_INTERRUPT_CTRL, 0);
  1181. aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff);
  1182. /* Clear the offset */
  1183. aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0);
  1184. aspeed_video_write(video, VE_COMP_OFFSET, 0);
  1185. aspeed_video_write(video, VE_JPEG_ADDR, video->jpeg.dma);
  1186. /* Set control registers */
  1187. aspeed_video_write(video, VE_SEQ_CTRL, VE_SEQ_CTRL_AUTO_COMP);
  1188. aspeed_video_write(video, VE_CTRL, ctrl);
  1189. aspeed_video_write(video, VE_COMP_CTRL, VE_COMP_CTRL_RSVD);
  1190. /* Don't downscale */
  1191. aspeed_video_write(video, VE_SCALING_FACTOR, 0x10001000);
  1192. aspeed_video_write(video, VE_SCALING_FILTER0, 0x00200000);
  1193. aspeed_video_write(video, VE_SCALING_FILTER1, 0x00200000);
  1194. aspeed_video_write(video, VE_SCALING_FILTER2, 0x00200000);
  1195. aspeed_video_write(video, VE_SCALING_FILTER3, 0x00200000);
  1196. /* Set mode detection defaults */
  1197. aspeed_video_write(video, VE_MODE_DETECT,
  1198. FIELD_PREP(VE_MODE_DT_HOR_TOLER, 2) |
  1199. FIELD_PREP(VE_MODE_DT_VER_TOLER, 2) |
  1200. FIELD_PREP(VE_MODE_DT_HOR_STABLE, 6) |
  1201. FIELD_PREP(VE_MODE_DT_VER_STABLE, 6) |
  1202. FIELD_PREP(VE_MODE_DT_EDG_THROD, 0x65));
  1203. aspeed_video_write(video, VE_BCD_CTRL, 0);
  1204. }
  1205. static void aspeed_video_start(struct aspeed_video *video)
  1206. {
  1207. aspeed_video_on(video);
  1208. aspeed_video_init_regs(video);
  1209. /* Resolution set to 640x480 if no signal found */
  1210. aspeed_video_get_resolution(video);
  1211. /* Set timings since the device is being opened for the first time */
  1212. aspeed_video_update_timings(video, &video->detected_timings);
  1213. }
  1214. static void aspeed_video_stop(struct aspeed_video *video)
  1215. {
  1216. set_bit(VIDEO_STOPPED, &video->flags);
  1217. cancel_delayed_work_sync(&video->res_work);
  1218. aspeed_video_off(video);
  1219. if (video->srcs[0].size)
  1220. aspeed_video_free_buf(video, &video->srcs[0]);
  1221. if (video->srcs[1].size)
  1222. aspeed_video_free_buf(video, &video->srcs[1]);
  1223. if (video->bcd.size)
  1224. aspeed_video_free_buf(video, &video->bcd);
  1225. video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
  1226. video->flags = 0;
  1227. }
  1228. static int aspeed_video_querycap(struct file *file, void *fh,
  1229. struct v4l2_capability *cap)
  1230. {
  1231. strscpy(cap->driver, DEVICE_NAME, sizeof(cap->driver));
  1232. strscpy(cap->card, "Aspeed Video Engine", sizeof(cap->card));
  1233. snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
  1234. DEVICE_NAME);
  1235. return 0;
  1236. }
  1237. static int aspeed_video_enum_format(struct file *file, void *fh,
  1238. struct v4l2_fmtdesc *f)
  1239. {
  1240. struct aspeed_video *video = video_drvdata(file);
  1241. if (f->index)
  1242. return -EINVAL;
  1243. f->pixelformat = video->pix_fmt.pixelformat;
  1244. return 0;
  1245. }
  1246. static int aspeed_video_get_format(struct file *file, void *fh,
  1247. struct v4l2_format *f)
  1248. {
  1249. struct aspeed_video *video = video_drvdata(file);
  1250. f->fmt.pix = video->pix_fmt;
  1251. return 0;
  1252. }
  1253. static int aspeed_video_set_format(struct file *file, void *fh,
  1254. struct v4l2_format *f)
  1255. {
  1256. struct aspeed_video *video = video_drvdata(file);
  1257. if (vb2_is_busy(&video->queue))
  1258. return -EBUSY;
  1259. switch (f->fmt.pix.pixelformat) {
  1260. case V4L2_PIX_FMT_JPEG:
  1261. video->format = VIDEO_FMT_STANDARD;
  1262. break;
  1263. case V4L2_PIX_FMT_AJPG:
  1264. video->format = VIDEO_FMT_ASPEED;
  1265. break;
  1266. default:
  1267. return -EINVAL;
  1268. }
  1269. video->pix_fmt.pixelformat = f->fmt.pix.pixelformat;
  1270. return 0;
  1271. }
  1272. static int aspeed_video_enum_input(struct file *file, void *fh,
  1273. struct v4l2_input *inp)
  1274. {
  1275. struct aspeed_video *video = video_drvdata(file);
  1276. if (inp->index >= VIDEO_INPUT_MAX)
  1277. return -EINVAL;
  1278. sprintf(inp->name, "%s capture", input_str[inp->index]);
  1279. inp->type = V4L2_INPUT_TYPE_CAMERA;
  1280. inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
  1281. inp->status = video->v4l2_input_status;
  1282. return 0;
  1283. }
  1284. static int aspeed_video_get_input(struct file *file, void *fh, unsigned int *i)
  1285. {
  1286. struct aspeed_video *video = video_drvdata(file);
  1287. *i = video->input;
  1288. return 0;
  1289. }
  1290. static int aspeed_video_set_input(struct file *file, void *fh, unsigned int i)
  1291. {
  1292. struct aspeed_video *video = video_drvdata(file);
  1293. if (i >= VIDEO_INPUT_MAX)
  1294. return -EINVAL;
  1295. if (i == video->input)
  1296. return 0;
  1297. if (vb2_is_busy(&video->queue))
  1298. return -EBUSY;
  1299. if (IS_ERR(video->scu)) {
  1300. v4l2_dbg(1, debug, &video->v4l2_dev,
  1301. "%s: scu isn't ready for input-control\n", __func__);
  1302. return -EINVAL;
  1303. }
  1304. if (IS_ERR(video->gfx) && i == VIDEO_INPUT_GFX) {
  1305. v4l2_dbg(1, debug, &video->v4l2_dev,
  1306. "%s: gfx isn't ready for GFX input\n", __func__);
  1307. return -EINVAL;
  1308. }
  1309. video->input = i;
  1310. if (video->version == 6) {
  1311. /* modify dpll source per current input */
  1312. if (video->input == VIDEO_INPUT_VGA)
  1313. regmap_update_bits(video->scu, SCU_MISC_CTRL,
  1314. SCU_DPLL_SOURCE, 0);
  1315. else
  1316. regmap_update_bits(video->scu, SCU_MISC_CTRL,
  1317. SCU_DPLL_SOURCE, SCU_DPLL_SOURCE);
  1318. }
  1319. aspeed_video_update_regs(video);
  1320. /* update signal status */
  1321. aspeed_video_get_resolution(video);
  1322. if (!video->v4l2_input_status)
  1323. aspeed_video_update_timings(video, &video->detected_timings);
  1324. return 0;
  1325. }
  1326. static int aspeed_video_get_parm(struct file *file, void *fh,
  1327. struct v4l2_streamparm *a)
  1328. {
  1329. struct aspeed_video *video = video_drvdata(file);
  1330. a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
  1331. a->parm.capture.readbuffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ;
  1332. a->parm.capture.timeperframe.numerator = 1;
  1333. if (!video->frame_rate)
  1334. a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE;
  1335. else
  1336. a->parm.capture.timeperframe.denominator = video->frame_rate;
  1337. return 0;
  1338. }
  1339. static int aspeed_video_set_parm(struct file *file, void *fh,
  1340. struct v4l2_streamparm *a)
  1341. {
  1342. unsigned int frame_rate = 0;
  1343. struct aspeed_video *video = video_drvdata(file);
  1344. a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
  1345. a->parm.capture.readbuffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ;
  1346. if (a->parm.capture.timeperframe.numerator)
  1347. frame_rate = a->parm.capture.timeperframe.denominator /
  1348. a->parm.capture.timeperframe.numerator;
  1349. if (!frame_rate || frame_rate > MAX_FRAME_RATE) {
  1350. frame_rate = 0;
  1351. a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE;
  1352. a->parm.capture.timeperframe.numerator = 1;
  1353. }
  1354. if (video->frame_rate != frame_rate) {
  1355. video->frame_rate = frame_rate;
  1356. aspeed_video_update(video, VE_CTRL, VE_CTRL_FRC,
  1357. FIELD_PREP(VE_CTRL_FRC, frame_rate));
  1358. }
  1359. return 0;
  1360. }
  1361. static int aspeed_video_enum_framesizes(struct file *file, void *fh,
  1362. struct v4l2_frmsizeenum *fsize)
  1363. {
  1364. struct aspeed_video *video = video_drvdata(file);
  1365. if (fsize->index)
  1366. return -EINVAL;
  1367. if (fsize->pixel_format != V4L2_PIX_FMT_JPEG)
  1368. return -EINVAL;
  1369. fsize->discrete.width = video->pix_fmt.width;
  1370. fsize->discrete.height = video->pix_fmt.height;
  1371. fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
  1372. return 0;
  1373. }
  1374. static int aspeed_video_enum_frameintervals(struct file *file, void *fh,
  1375. struct v4l2_frmivalenum *fival)
  1376. {
  1377. struct aspeed_video *video = video_drvdata(file);
  1378. if (fival->index)
  1379. return -EINVAL;
  1380. if (fival->width != video->detected_timings.width ||
  1381. fival->height != video->detected_timings.height)
  1382. return -EINVAL;
  1383. if (fival->pixel_format != V4L2_PIX_FMT_JPEG)
  1384. return -EINVAL;
  1385. fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
  1386. fival->stepwise.min.denominator = MAX_FRAME_RATE;
  1387. fival->stepwise.min.numerator = 1;
  1388. fival->stepwise.max.denominator = 1;
  1389. fival->stepwise.max.numerator = 1;
  1390. fival->stepwise.step = fival->stepwise.max;
  1391. return 0;
  1392. }
  1393. static int aspeed_video_set_dv_timings(struct file *file, void *fh,
  1394. struct v4l2_dv_timings *timings)
  1395. {
  1396. struct aspeed_video *video = video_drvdata(file);
  1397. if (timings->bt.width == video->active_timings.width &&
  1398. timings->bt.height == video->active_timings.height)
  1399. return 0;
  1400. if (vb2_is_busy(&video->queue))
  1401. return -EBUSY;
  1402. aspeed_video_update_timings(video, &timings->bt);
  1403. timings->type = V4L2_DV_BT_656_1120;
  1404. v4l2_dbg(1, debug, &video->v4l2_dev, "set new timings(%dx%d)\n",
  1405. timings->bt.width, timings->bt.height);
  1406. return 0;
  1407. }
  1408. static int aspeed_video_get_dv_timings(struct file *file, void *fh,
  1409. struct v4l2_dv_timings *timings)
  1410. {
  1411. struct aspeed_video *video = video_drvdata(file);
  1412. timings->type = V4L2_DV_BT_656_1120;
  1413. timings->bt = video->active_timings;
  1414. return 0;
  1415. }
  1416. static int aspeed_video_query_dv_timings(struct file *file, void *fh,
  1417. struct v4l2_dv_timings *timings)
  1418. {
  1419. int rc;
  1420. struct aspeed_video *video = video_drvdata(file);
  1421. /*
  1422. * This blocks only if the driver is currently in the process of
  1423. * detecting a new resolution; in the event of no signal or timeout
  1424. * this function is woken up.
  1425. */
  1426. if (file->f_flags & O_NONBLOCK) {
  1427. if (test_bit(VIDEO_RES_CHANGE, &video->flags))
  1428. return -EAGAIN;
  1429. } else {
  1430. rc = wait_event_interruptible(video->wait,
  1431. !test_bit(VIDEO_RES_CHANGE,
  1432. &video->flags));
  1433. if (rc)
  1434. return -EINTR;
  1435. }
  1436. timings->type = V4L2_DV_BT_656_1120;
  1437. timings->bt = video->detected_timings;
  1438. return video->v4l2_input_status ? -ENOLINK : 0;
  1439. }
  1440. static int aspeed_video_enum_dv_timings(struct file *file, void *fh,
  1441. struct v4l2_enum_dv_timings *timings)
  1442. {
  1443. return v4l2_enum_dv_timings_cap(timings, &aspeed_video_timings_cap,
  1444. NULL, NULL);
  1445. }
  1446. static int aspeed_video_dv_timings_cap(struct file *file, void *fh,
  1447. struct v4l2_dv_timings_cap *cap)
  1448. {
  1449. *cap = aspeed_video_timings_cap;
  1450. return 0;
  1451. }
  1452. static int aspeed_video_sub_event(struct v4l2_fh *fh,
  1453. const struct v4l2_event_subscription *sub)
  1454. {
  1455. switch (sub->type) {
  1456. case V4L2_EVENT_SOURCE_CHANGE:
  1457. return v4l2_src_change_event_subscribe(fh, sub);
  1458. }
  1459. return v4l2_ctrl_subscribe_event(fh, sub);
  1460. }
  1461. static const struct v4l2_ioctl_ops aspeed_video_ioctl_ops = {
  1462. .vidioc_querycap = aspeed_video_querycap,
  1463. .vidioc_enum_fmt_vid_cap = aspeed_video_enum_format,
  1464. .vidioc_g_fmt_vid_cap = aspeed_video_get_format,
  1465. .vidioc_s_fmt_vid_cap = aspeed_video_set_format,
  1466. .vidioc_try_fmt_vid_cap = aspeed_video_get_format,
  1467. .vidioc_reqbufs = vb2_ioctl_reqbufs,
  1468. .vidioc_querybuf = vb2_ioctl_querybuf,
  1469. .vidioc_qbuf = vb2_ioctl_qbuf,
  1470. .vidioc_expbuf = vb2_ioctl_expbuf,
  1471. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  1472. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  1473. .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
  1474. .vidioc_streamon = vb2_ioctl_streamon,
  1475. .vidioc_streamoff = vb2_ioctl_streamoff,
  1476. .vidioc_enum_input = aspeed_video_enum_input,
  1477. .vidioc_g_input = aspeed_video_get_input,
  1478. .vidioc_s_input = aspeed_video_set_input,
  1479. .vidioc_g_parm = aspeed_video_get_parm,
  1480. .vidioc_s_parm = aspeed_video_set_parm,
  1481. .vidioc_enum_framesizes = aspeed_video_enum_framesizes,
  1482. .vidioc_enum_frameintervals = aspeed_video_enum_frameintervals,
  1483. .vidioc_s_dv_timings = aspeed_video_set_dv_timings,
  1484. .vidioc_g_dv_timings = aspeed_video_get_dv_timings,
  1485. .vidioc_query_dv_timings = aspeed_video_query_dv_timings,
  1486. .vidioc_enum_dv_timings = aspeed_video_enum_dv_timings,
  1487. .vidioc_dv_timings_cap = aspeed_video_dv_timings_cap,
  1488. .vidioc_subscribe_event = aspeed_video_sub_event,
  1489. .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
  1490. };
  1491. static int aspeed_video_set_ctrl(struct v4l2_ctrl *ctrl)
  1492. {
  1493. struct aspeed_video *video = container_of(ctrl->handler,
  1494. struct aspeed_video,
  1495. ctrl_handler);
  1496. switch (ctrl->id) {
  1497. case V4L2_CID_JPEG_COMPRESSION_QUALITY:
  1498. video->jpeg_quality = ctrl->val;
  1499. if (test_bit(VIDEO_STREAMING, &video->flags))
  1500. aspeed_video_update_regs(video);
  1501. break;
  1502. case V4L2_CID_JPEG_CHROMA_SUBSAMPLING:
  1503. video->yuv420 = (ctrl->val == V4L2_JPEG_CHROMA_SUBSAMPLING_420);
  1504. if (test_bit(VIDEO_STREAMING, &video->flags))
  1505. aspeed_video_update_regs(video);
  1506. break;
  1507. case V4L2_CID_ASPEED_HQ_MODE:
  1508. video->hq_mode = ctrl->val;
  1509. if (test_bit(VIDEO_STREAMING, &video->flags))
  1510. aspeed_video_update_regs(video);
  1511. break;
  1512. case V4L2_CID_ASPEED_HQ_JPEG_QUALITY:
  1513. video->jpeg_hq_quality = ctrl->val;
  1514. if (test_bit(VIDEO_STREAMING, &video->flags))
  1515. aspeed_video_update_regs(video);
  1516. break;
  1517. default:
  1518. return -EINVAL;
  1519. }
  1520. return 0;
  1521. }
  1522. static const struct v4l2_ctrl_ops aspeed_video_ctrl_ops = {
  1523. .s_ctrl = aspeed_video_set_ctrl,
  1524. };
  1525. static const struct v4l2_ctrl_config aspeed_ctrl_HQ_mode = {
  1526. .ops = &aspeed_video_ctrl_ops,
  1527. .id = V4L2_CID_ASPEED_HQ_MODE,
  1528. .name = "Aspeed HQ Mode",
  1529. .type = V4L2_CTRL_TYPE_BOOLEAN,
  1530. .min = false,
  1531. .max = true,
  1532. .step = 1,
  1533. .def = false,
  1534. };
  1535. static const struct v4l2_ctrl_config aspeed_ctrl_HQ_jpeg_quality = {
  1536. .ops = &aspeed_video_ctrl_ops,
  1537. .id = V4L2_CID_ASPEED_HQ_JPEG_QUALITY,
  1538. .name = "Aspeed HQ Quality",
  1539. .type = V4L2_CTRL_TYPE_INTEGER,
  1540. .min = 1,
  1541. .max = ASPEED_VIDEO_JPEG_NUM_QUALITIES,
  1542. .step = 1,
  1543. .def = 1,
  1544. };
  1545. static void aspeed_video_resolution_work(struct work_struct *work)
  1546. {
  1547. struct delayed_work *dwork = to_delayed_work(work);
  1548. struct aspeed_video *video = container_of(dwork, struct aspeed_video,
  1549. res_work);
  1550. aspeed_video_on(video);
  1551. /* Exit early in case no clients remain */
  1552. if (test_bit(VIDEO_STOPPED, &video->flags))
  1553. goto done;
  1554. aspeed_video_init_regs(video);
  1555. aspeed_video_update_regs(video);
  1556. aspeed_video_get_resolution(video);
  1557. if (video->detected_timings.width != video->active_timings.width ||
  1558. video->detected_timings.height != video->active_timings.height) {
  1559. static const struct v4l2_event ev = {
  1560. .type = V4L2_EVENT_SOURCE_CHANGE,
  1561. .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
  1562. };
  1563. v4l2_dbg(1, debug, &video->v4l2_dev, "fire source change event\n");
  1564. v4l2_event_queue(&video->vdev, &ev);
  1565. } else if (test_bit(VIDEO_STREAMING, &video->flags)) {
  1566. /* No resolution change so just restart streaming */
  1567. aspeed_video_start_frame(video);
  1568. }
  1569. done:
  1570. clear_bit(VIDEO_RES_CHANGE, &video->flags);
  1571. wake_up_interruptible_all(&video->wait);
  1572. }
  1573. static int aspeed_video_open(struct file *file)
  1574. {
  1575. int rc;
  1576. struct aspeed_video *video = video_drvdata(file);
  1577. mutex_lock(&video->video_lock);
  1578. rc = v4l2_fh_open(file);
  1579. if (rc) {
  1580. mutex_unlock(&video->video_lock);
  1581. return rc;
  1582. }
  1583. if (v4l2_fh_is_singular_file(file))
  1584. aspeed_video_start(video);
  1585. mutex_unlock(&video->video_lock);
  1586. return 0;
  1587. }
  1588. static int aspeed_video_release(struct file *file)
  1589. {
  1590. int rc;
  1591. struct aspeed_video *video = video_drvdata(file);
  1592. mutex_lock(&video->video_lock);
  1593. if (v4l2_fh_is_singular_file(file))
  1594. aspeed_video_stop(video);
  1595. rc = _vb2_fop_release(file, NULL);
  1596. mutex_unlock(&video->video_lock);
  1597. return rc;
  1598. }
  1599. static const struct v4l2_file_operations aspeed_video_v4l2_fops = {
  1600. .owner = THIS_MODULE,
  1601. .read = vb2_fop_read,
  1602. .poll = vb2_fop_poll,
  1603. .unlocked_ioctl = video_ioctl2,
  1604. .mmap = vb2_fop_mmap,
  1605. .open = aspeed_video_open,
  1606. .release = aspeed_video_release,
  1607. };
  1608. static int aspeed_video_queue_setup(struct vb2_queue *q,
  1609. unsigned int *num_buffers,
  1610. unsigned int *num_planes,
  1611. unsigned int sizes[],
  1612. struct device *alloc_devs[])
  1613. {
  1614. struct aspeed_video *video = vb2_get_drv_priv(q);
  1615. if (*num_planes) {
  1616. if (sizes[0] < video->max_compressed_size)
  1617. return -EINVAL;
  1618. return 0;
  1619. }
  1620. *num_planes = 1;
  1621. sizes[0] = video->max_compressed_size;
  1622. return 0;
  1623. }
  1624. static int aspeed_video_buf_prepare(struct vb2_buffer *vb)
  1625. {
  1626. struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue);
  1627. if (vb2_plane_size(vb, 0) < video->max_compressed_size)
  1628. return -EINVAL;
  1629. return 0;
  1630. }
  1631. static int aspeed_video_start_streaming(struct vb2_queue *q,
  1632. unsigned int count)
  1633. {
  1634. int rc;
  1635. struct aspeed_video *video = vb2_get_drv_priv(q);
  1636. video->sequence = 0;
  1637. video->perf.duration_max = 0;
  1638. video->perf.duration_min = 0xffffffff;
  1639. aspeed_video_update_regs(video);
  1640. rc = aspeed_video_start_frame(video);
  1641. if (rc) {
  1642. aspeed_video_bufs_done(video, VB2_BUF_STATE_QUEUED);
  1643. return rc;
  1644. }
  1645. set_bit(VIDEO_STREAMING, &video->flags);
  1646. return 0;
  1647. }
  1648. static void aspeed_video_stop_streaming(struct vb2_queue *q)
  1649. {
  1650. int rc;
  1651. struct aspeed_video *video = vb2_get_drv_priv(q);
  1652. clear_bit(VIDEO_STREAMING, &video->flags);
  1653. rc = wait_event_timeout(video->wait,
  1654. !test_bit(VIDEO_FRAME_INPRG, &video->flags),
  1655. STOP_TIMEOUT);
  1656. if (!rc) {
  1657. v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out when stopping streaming\n");
  1658. /*
  1659. * Need to force stop any DMA and try and get HW into a good
  1660. * state for future calls to start streaming again.
  1661. */
  1662. aspeed_video_reset(video);
  1663. aspeed_video_init_regs(video);
  1664. aspeed_video_get_resolution(video);
  1665. }
  1666. aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR);
  1667. }
  1668. static void aspeed_video_buf_queue(struct vb2_buffer *vb)
  1669. {
  1670. bool empty;
  1671. struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue);
  1672. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  1673. struct aspeed_video_buffer *avb = to_aspeed_video_buffer(vbuf);
  1674. unsigned long flags;
  1675. spin_lock_irqsave(&video->lock, flags);
  1676. empty = list_empty(&video->buffers);
  1677. list_add_tail(&avb->link, &video->buffers);
  1678. spin_unlock_irqrestore(&video->lock, flags);
  1679. if (test_bit(VIDEO_STREAMING, &video->flags) &&
  1680. !test_bit(VIDEO_FRAME_INPRG, &video->flags) && empty)
  1681. aspeed_video_start_frame(video);
  1682. }
  1683. static const struct vb2_ops aspeed_video_vb2_ops = {
  1684. .queue_setup = aspeed_video_queue_setup,
  1685. .buf_prepare = aspeed_video_buf_prepare,
  1686. .start_streaming = aspeed_video_start_streaming,
  1687. .stop_streaming = aspeed_video_stop_streaming,
  1688. .buf_queue = aspeed_video_buf_queue,
  1689. };
  1690. #ifdef CONFIG_DEBUG_FS
  1691. static int aspeed_video_debugfs_show(struct seq_file *s, void *data)
  1692. {
  1693. struct aspeed_video *v = s->private;
  1694. u32 val08;
  1695. seq_puts(s, "\n");
  1696. seq_puts(s, "Capture:\n");
  1697. val08 = aspeed_video_read(v, VE_CTRL);
  1698. if (FIELD_GET(VE_CTRL_DIRECT_FETCH, val08)) {
  1699. seq_printf(s, " %-20s:\tDirect fetch\n", "Mode");
  1700. seq_printf(s, " %-20s:\t%s\n", "Input", input_str[v->input]);
  1701. seq_printf(s, " %-20s:\t%s\n", "VGA bpp mode",
  1702. FIELD_GET(VE_CTRL_INT_DE, val08) ? "16" : "32");
  1703. } else {
  1704. seq_printf(s, " %-20s:\tSync\n", "Mode");
  1705. seq_printf(s, " %-20s:\t%s\n", "Video source",
  1706. FIELD_GET(VE_CTRL_SOURCE, val08) ?
  1707. "external" : "internal");
  1708. seq_printf(s, " %-20s:\t%s\n", "DE source",
  1709. FIELD_GET(VE_CTRL_INT_DE, val08) ?
  1710. "internal" : "external");
  1711. seq_printf(s, " %-20s:\t%s\n", "Cursor overlay",
  1712. FIELD_GET(VE_CTRL_AUTO_OR_CURSOR, val08) ?
  1713. "Without" : "With");
  1714. }
  1715. seq_printf(s, " %-20s:\t%s\n", "Signal",
  1716. v->v4l2_input_status ? "Unlock" : "Lock");
  1717. seq_printf(s, " %-20s:\t%d\n", "Width", v->pix_fmt.width);
  1718. seq_printf(s, " %-20s:\t%d\n", "Height", v->pix_fmt.height);
  1719. seq_printf(s, " %-20s:\t%d\n", "FRC", v->frame_rate);
  1720. seq_puts(s, "\n");
  1721. seq_puts(s, "Compression:\n");
  1722. seq_printf(s, " %-20s:\t%s\n", "Format", format_str[v->format]);
  1723. seq_printf(s, " %-20s:\t%s\n", "Subsampling",
  1724. v->yuv420 ? "420" : "444");
  1725. seq_printf(s, " %-20s:\t%d\n", "Quality", v->jpeg_quality);
  1726. if (v->format == VIDEO_FMT_ASPEED) {
  1727. seq_printf(s, " %-20s:\t%s\n", "HQ Mode",
  1728. v->hq_mode ? "on" : "off");
  1729. seq_printf(s, " %-20s:\t%d\n", "HQ Quality",
  1730. v->hq_mode ? v->jpeg_hq_quality : 0);
  1731. }
  1732. seq_puts(s, "\n");
  1733. seq_puts(s, "Performance:\n");
  1734. seq_printf(s, " %-20s:\t%d\n", "Frame#", v->sequence);
  1735. seq_printf(s, " %-20s:\n", "Frame Duration(ms)");
  1736. seq_printf(s, " %-18s:\t%d\n", "Now", v->perf.duration);
  1737. seq_printf(s, " %-18s:\t%d\n", "Min", v->perf.duration_min);
  1738. seq_printf(s, " %-18s:\t%d\n", "Max", v->perf.duration_max);
  1739. seq_printf(s, " %-20s:\t%d\n", "FPS",
  1740. (v->perf.totaltime && v->sequence) ?
  1741. 1000 / (v->perf.totaltime / v->sequence) : 0);
  1742. return 0;
  1743. }
  1744. DEFINE_SHOW_ATTRIBUTE(aspeed_video_debugfs);
  1745. static struct dentry *debugfs_entry;
  1746. static void aspeed_video_debugfs_remove(struct aspeed_video *video)
  1747. {
  1748. debugfs_remove_recursive(debugfs_entry);
  1749. debugfs_entry = NULL;
  1750. }
  1751. static void aspeed_video_debugfs_create(struct aspeed_video *video)
  1752. {
  1753. debugfs_entry = debugfs_create_file(DEVICE_NAME, 0444, NULL,
  1754. video,
  1755. &aspeed_video_debugfs_fops);
  1756. }
  1757. #else
  1758. static void aspeed_video_debugfs_remove(struct aspeed_video *video) { }
  1759. static void aspeed_video_debugfs_create(struct aspeed_video *video) { }
  1760. #endif /* CONFIG_DEBUG_FS */
  1761. static int aspeed_video_setup_video(struct aspeed_video *video)
  1762. {
  1763. const u64 mask = ~(BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_444) |
  1764. BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_420));
  1765. struct v4l2_device *v4l2_dev = &video->v4l2_dev;
  1766. struct vb2_queue *vbq = &video->queue;
  1767. struct video_device *vdev = &video->vdev;
  1768. struct v4l2_ctrl_handler *hdl = &video->ctrl_handler;
  1769. int rc;
  1770. video->pix_fmt.pixelformat = V4L2_PIX_FMT_JPEG;
  1771. video->pix_fmt.field = V4L2_FIELD_NONE;
  1772. video->pix_fmt.colorspace = V4L2_COLORSPACE_SRGB;
  1773. video->pix_fmt.quantization = V4L2_QUANTIZATION_FULL_RANGE;
  1774. video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
  1775. rc = v4l2_device_register(video->dev, v4l2_dev);
  1776. if (rc) {
  1777. dev_err(video->dev, "Failed to register v4l2 device\n");
  1778. return rc;
  1779. }
  1780. v4l2_ctrl_handler_init(hdl, 4);
  1781. v4l2_ctrl_new_std(hdl, &aspeed_video_ctrl_ops,
  1782. V4L2_CID_JPEG_COMPRESSION_QUALITY, 0,
  1783. ASPEED_VIDEO_JPEG_NUM_QUALITIES - 1, 1, 0);
  1784. v4l2_ctrl_new_std_menu(hdl, &aspeed_video_ctrl_ops,
  1785. V4L2_CID_JPEG_CHROMA_SUBSAMPLING,
  1786. V4L2_JPEG_CHROMA_SUBSAMPLING_420, mask,
  1787. V4L2_JPEG_CHROMA_SUBSAMPLING_444);
  1788. v4l2_ctrl_new_custom(hdl, &aspeed_ctrl_HQ_mode, NULL);
  1789. v4l2_ctrl_new_custom(hdl, &aspeed_ctrl_HQ_jpeg_quality, NULL);
  1790. rc = hdl->error;
  1791. if (rc) {
  1792. v4l2_ctrl_handler_free(&video->ctrl_handler);
  1793. v4l2_device_unregister(v4l2_dev);
  1794. dev_err(video->dev, "Failed to init controls: %d\n", rc);
  1795. return rc;
  1796. }
  1797. v4l2_dev->ctrl_handler = hdl;
  1798. vbq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1799. vbq->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
  1800. vbq->dev = v4l2_dev->dev;
  1801. vbq->lock = &video->video_lock;
  1802. vbq->ops = &aspeed_video_vb2_ops;
  1803. vbq->mem_ops = &vb2_dma_contig_memops;
  1804. vbq->drv_priv = video;
  1805. vbq->buf_struct_size = sizeof(struct aspeed_video_buffer);
  1806. vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1807. vbq->min_queued_buffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ;
  1808. rc = vb2_queue_init(vbq);
  1809. if (rc) {
  1810. v4l2_ctrl_handler_free(&video->ctrl_handler);
  1811. v4l2_device_unregister(v4l2_dev);
  1812. dev_err(video->dev, "Failed to init vb2 queue\n");
  1813. return rc;
  1814. }
  1815. vdev->queue = vbq;
  1816. vdev->fops = &aspeed_video_v4l2_fops;
  1817. vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
  1818. V4L2_CAP_STREAMING;
  1819. vdev->v4l2_dev = v4l2_dev;
  1820. strscpy(vdev->name, DEVICE_NAME, sizeof(vdev->name));
  1821. vdev->vfl_type = VFL_TYPE_VIDEO;
  1822. vdev->vfl_dir = VFL_DIR_RX;
  1823. vdev->release = video_device_release_empty;
  1824. vdev->ioctl_ops = &aspeed_video_ioctl_ops;
  1825. vdev->lock = &video->video_lock;
  1826. video_set_drvdata(vdev, video);
  1827. rc = video_register_device(vdev, VFL_TYPE_VIDEO, 0);
  1828. if (rc) {
  1829. v4l2_ctrl_handler_free(&video->ctrl_handler);
  1830. v4l2_device_unregister(v4l2_dev);
  1831. dev_err(video->dev, "Failed to register video device\n");
  1832. return rc;
  1833. }
  1834. return 0;
  1835. }
  1836. /*
  1837. * Get regmap without checking res, such as clk/reset, that could lead to
  1838. * conflict.
  1839. */
  1840. static struct regmap *aspeed_regmap_lookup(struct device_node *np, const char *property)
  1841. {
  1842. struct device_node *syscon_np __free(device_node) = of_parse_phandle(np, property, 0);
  1843. if (!syscon_np)
  1844. return ERR_PTR(-ENODEV);
  1845. return device_node_to_regmap(syscon_np);
  1846. }
  1847. static int aspeed_video_init(struct aspeed_video *video)
  1848. {
  1849. int irq;
  1850. int rc;
  1851. struct device *dev = video->dev;
  1852. video->scu = aspeed_regmap_lookup(dev->of_node, "aspeed,scu");
  1853. video->gfx = aspeed_regmap_lookup(dev->of_node, "aspeed,gfx");
  1854. irq = irq_of_parse_and_map(dev->of_node, 0);
  1855. if (!irq) {
  1856. dev_err(dev, "Unable to find IRQ\n");
  1857. return -ENODEV;
  1858. }
  1859. rc = devm_request_threaded_irq(dev, irq, NULL, aspeed_video_irq,
  1860. IRQF_ONESHOT, DEVICE_NAME, video);
  1861. if (rc < 0) {
  1862. dev_err(dev, "Unable to request IRQ %d\n", irq);
  1863. return rc;
  1864. }
  1865. dev_info(video->dev, "irq %d\n", irq);
  1866. video->reset = devm_reset_control_get(dev, NULL);
  1867. if (IS_ERR(video->reset)) {
  1868. dev_err(dev, "Unable to get reset\n");
  1869. return PTR_ERR(video->reset);
  1870. }
  1871. video->eclk = devm_clk_get(dev, "eclk");
  1872. if (IS_ERR(video->eclk)) {
  1873. dev_err(dev, "Unable to get ECLK\n");
  1874. return PTR_ERR(video->eclk);
  1875. }
  1876. rc = clk_prepare(video->eclk);
  1877. if (rc)
  1878. return rc;
  1879. video->vclk = devm_clk_get(dev, "vclk");
  1880. if (IS_ERR(video->vclk)) {
  1881. dev_err(dev, "Unable to get VCLK\n");
  1882. rc = PTR_ERR(video->vclk);
  1883. goto err_unprepare_eclk;
  1884. }
  1885. rc = clk_prepare(video->vclk);
  1886. if (rc)
  1887. goto err_unprepare_eclk;
  1888. of_reserved_mem_device_init(dev);
  1889. rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
  1890. if (rc) {
  1891. dev_err(dev, "Failed to set DMA mask\n");
  1892. goto err_release_reserved_mem;
  1893. }
  1894. if (!aspeed_video_alloc_buf(video, &video->jpeg,
  1895. VE_JPEG_HEADER_SIZE)) {
  1896. dev_err(dev, "Failed to allocate DMA for JPEG header\n");
  1897. rc = -ENOMEM;
  1898. goto err_release_reserved_mem;
  1899. }
  1900. dev_info(video->dev, "alloc mem size(%d) at %pad for jpeg header\n",
  1901. VE_JPEG_HEADER_SIZE, &video->jpeg.dma);
  1902. aspeed_video_init_jpeg_table(video->jpeg.virt, video->yuv420);
  1903. return 0;
  1904. err_release_reserved_mem:
  1905. of_reserved_mem_device_release(dev);
  1906. clk_unprepare(video->vclk);
  1907. err_unprepare_eclk:
  1908. clk_unprepare(video->eclk);
  1909. return rc;
  1910. }
  1911. static const struct of_device_id aspeed_video_of_match[] = {
  1912. { .compatible = "aspeed,ast2400-video-engine", .data = &ast2400_config },
  1913. { .compatible = "aspeed,ast2500-video-engine", .data = &ast2500_config },
  1914. { .compatible = "aspeed,ast2600-video-engine", .data = &ast2600_config },
  1915. {}
  1916. };
  1917. MODULE_DEVICE_TABLE(of, aspeed_video_of_match);
  1918. static int aspeed_video_probe(struct platform_device *pdev)
  1919. {
  1920. const struct aspeed_video_config *config;
  1921. struct aspeed_video *video;
  1922. int rc;
  1923. video = devm_kzalloc(&pdev->dev, sizeof(*video), GFP_KERNEL);
  1924. if (!video)
  1925. return -ENOMEM;
  1926. video->base = devm_platform_ioremap_resource(pdev, 0);
  1927. if (IS_ERR(video->base))
  1928. return PTR_ERR(video->base);
  1929. config = of_device_get_match_data(&pdev->dev);
  1930. if (!config)
  1931. return -ENODEV;
  1932. video->version = config->version;
  1933. video->jpeg_mode = config->jpeg_mode;
  1934. video->comp_size_read = config->comp_size_read;
  1935. video->frame_rate = 30;
  1936. video->jpeg_hq_quality = 1;
  1937. video->dev = &pdev->dev;
  1938. spin_lock_init(&video->lock);
  1939. mutex_init(&video->video_lock);
  1940. init_waitqueue_head(&video->wait);
  1941. INIT_DELAYED_WORK(&video->res_work, aspeed_video_resolution_work);
  1942. INIT_LIST_HEAD(&video->buffers);
  1943. rc = aspeed_video_init(video);
  1944. if (rc)
  1945. return rc;
  1946. rc = aspeed_video_setup_video(video);
  1947. if (rc) {
  1948. aspeed_video_free_buf(video, &video->jpeg);
  1949. clk_unprepare(video->vclk);
  1950. clk_unprepare(video->eclk);
  1951. return rc;
  1952. }
  1953. aspeed_video_debugfs_create(video);
  1954. return 0;
  1955. }
  1956. static void aspeed_video_remove(struct platform_device *pdev)
  1957. {
  1958. struct device *dev = &pdev->dev;
  1959. struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
  1960. struct aspeed_video *video = to_aspeed_video(v4l2_dev);
  1961. aspeed_video_off(video);
  1962. aspeed_video_debugfs_remove(video);
  1963. clk_unprepare(video->vclk);
  1964. clk_unprepare(video->eclk);
  1965. vb2_video_unregister_device(&video->vdev);
  1966. v4l2_ctrl_handler_free(&video->ctrl_handler);
  1967. v4l2_device_unregister(v4l2_dev);
  1968. aspeed_video_free_buf(video, &video->jpeg);
  1969. of_reserved_mem_device_release(dev);
  1970. }
  1971. static struct platform_driver aspeed_video_driver = {
  1972. .driver = {
  1973. .name = DEVICE_NAME,
  1974. .of_match_table = aspeed_video_of_match,
  1975. },
  1976. .probe = aspeed_video_probe,
  1977. .remove = aspeed_video_remove,
  1978. };
  1979. module_platform_driver(aspeed_video_driver);
  1980. module_param(debug, int, 0644);
  1981. MODULE_PARM_DESC(debug, "Debug level (0=off,1=info,2=debug,3=reg ops)");
  1982. MODULE_DESCRIPTION("ASPEED Video Engine Driver");
  1983. MODULE_AUTHOR("Eddie James");
  1984. MODULE_LICENSE("GPL v2");