vpx3220.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * vpx3220a, vpx3216b & vpx3214c video decoder driver version 0.0.1
  4. *
  5. * Copyright (C) 2001 Laurent Pinchart <lpinchart@freegates.be>
  6. */
  7. #include <linux/module.h>
  8. #include <linux/init.h>
  9. #include <linux/delay.h>
  10. #include <linux/types.h>
  11. #include <linux/slab.h>
  12. #include <linux/uaccess.h>
  13. #include <linux/i2c.h>
  14. #include <linux/videodev2.h>
  15. #include <media/v4l2-device.h>
  16. #include <media/v4l2-ctrls.h>
  17. MODULE_DESCRIPTION("vpx3220a/vpx3216b/vpx3214c video decoder driver");
  18. MODULE_AUTHOR("Laurent Pinchart");
  19. MODULE_LICENSE("GPL");
  20. static int debug;
  21. module_param(debug, int, 0);
  22. MODULE_PARM_DESC(debug, "Debug level (0-1)");
  23. #define VPX_TIMEOUT_COUNT 10
  24. /* ----------------------------------------------------------------------- */
  25. struct vpx3220 {
  26. struct v4l2_subdev sd;
  27. struct v4l2_ctrl_handler hdl;
  28. unsigned char reg[255];
  29. v4l2_std_id norm;
  30. int input;
  31. int enable;
  32. };
  33. static inline struct vpx3220 *to_vpx3220(struct v4l2_subdev *sd)
  34. {
  35. return container_of(sd, struct vpx3220, sd);
  36. }
  37. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  38. {
  39. return &container_of(ctrl->handler, struct vpx3220, hdl)->sd;
  40. }
  41. static char *inputs[] = { "internal", "composite", "svideo" };
  42. /* ----------------------------------------------------------------------- */
  43. static inline int vpx3220_write(struct v4l2_subdev *sd, u8 reg, u8 value)
  44. {
  45. struct i2c_client *client = v4l2_get_subdevdata(sd);
  46. struct vpx3220 *decoder = i2c_get_clientdata(client);
  47. decoder->reg[reg] = value;
  48. return i2c_smbus_write_byte_data(client, reg, value);
  49. }
  50. static inline int vpx3220_read(struct v4l2_subdev *sd, u8 reg)
  51. {
  52. struct i2c_client *client = v4l2_get_subdevdata(sd);
  53. return i2c_smbus_read_byte_data(client, reg);
  54. }
  55. static int vpx3220_fp_status(struct v4l2_subdev *sd)
  56. {
  57. unsigned char status;
  58. unsigned int i;
  59. for (i = 0; i < VPX_TIMEOUT_COUNT; i++) {
  60. status = vpx3220_read(sd, 0x29);
  61. if (!(status & 4))
  62. return 0;
  63. udelay(10);
  64. if (need_resched())
  65. cond_resched();
  66. }
  67. return -1;
  68. }
  69. static int vpx3220_fp_write(struct v4l2_subdev *sd, u8 fpaddr, u16 data)
  70. {
  71. struct i2c_client *client = v4l2_get_subdevdata(sd);
  72. /* Write the 16-bit address to the FPWR register */
  73. if (i2c_smbus_write_word_data(client, 0x27, swab16(fpaddr)) == -1) {
  74. v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
  75. return -1;
  76. }
  77. if (vpx3220_fp_status(sd) < 0)
  78. return -1;
  79. /* Write the 16-bit data to the FPDAT register */
  80. if (i2c_smbus_write_word_data(client, 0x28, swab16(data)) == -1) {
  81. v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
  82. return -1;
  83. }
  84. return 0;
  85. }
  86. static int vpx3220_fp_read(struct v4l2_subdev *sd, u16 fpaddr)
  87. {
  88. struct i2c_client *client = v4l2_get_subdevdata(sd);
  89. s16 data;
  90. /* Write the 16-bit address to the FPRD register */
  91. if (i2c_smbus_write_word_data(client, 0x26, swab16(fpaddr)) == -1) {
  92. v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
  93. return -1;
  94. }
  95. if (vpx3220_fp_status(sd) < 0)
  96. return -1;
  97. /* Read the 16-bit data from the FPDAT register */
  98. data = i2c_smbus_read_word_data(client, 0x28);
  99. if (data == -1) {
  100. v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
  101. return -1;
  102. }
  103. return swab16(data);
  104. }
  105. static int vpx3220_write_block(struct v4l2_subdev *sd, const u8 *data, unsigned int len)
  106. {
  107. u8 reg;
  108. int ret = -1;
  109. while (len >= 2) {
  110. reg = *data++;
  111. ret = vpx3220_write(sd, reg, *data++);
  112. if (ret < 0)
  113. break;
  114. len -= 2;
  115. }
  116. return ret;
  117. }
  118. static int vpx3220_write_fp_block(struct v4l2_subdev *sd,
  119. const u16 *data, unsigned int len)
  120. {
  121. u8 reg;
  122. int ret = 0;
  123. while (len > 1) {
  124. reg = *data++;
  125. ret |= vpx3220_fp_write(sd, reg, *data++);
  126. len -= 2;
  127. }
  128. return ret;
  129. }
  130. /* ---------------------------------------------------------------------- */
  131. static const unsigned short init_ntsc[] = {
  132. 0x1c, 0x00, /* NTSC tint angle */
  133. 0x88, 17, /* Window 1 vertical */
  134. 0x89, 240, /* Vertical lines in */
  135. 0x8a, 240, /* Vertical lines out */
  136. 0x8b, 000, /* Horizontal begin */
  137. 0x8c, 640, /* Horizontal length */
  138. 0x8d, 640, /* Number of pixels */
  139. 0x8f, 0xc00, /* Disable window 2 */
  140. 0xf0, 0x73, /* 13.5 MHz transport, Forced
  141. * mode, latch windows */
  142. 0xf2, 0x13, /* NTSC M, composite input */
  143. 0xe7, 0x1e1, /* Enable vertical standard
  144. * locking @ 240 lines */
  145. };
  146. static const unsigned short init_pal[] = {
  147. 0x88, 23, /* Window 1 vertical begin */
  148. 0x89, 288, /* Vertical lines in (16 lines
  149. * skipped by the VFE) */
  150. 0x8a, 288, /* Vertical lines out (16 lines
  151. * skipped by the VFE) */
  152. 0x8b, 16, /* Horizontal begin */
  153. 0x8c, 768, /* Horizontal length */
  154. 0x8d, 784, /* Number of pixels
  155. * Must be >= Horizontal begin + Horizontal length */
  156. 0x8f, 0xc00, /* Disable window 2 */
  157. 0xf0, 0x77, /* 13.5 MHz transport, Forced
  158. * mode, latch windows */
  159. 0xf2, 0x3d1, /* PAL B,G,H,I, composite input */
  160. 0xe7, 0x241, /* PAL/SECAM set to 288 lines */
  161. };
  162. static const unsigned short init_secam[] = {
  163. 0x88, 23, /* Window 1 vertical begin */
  164. 0x89, 288, /* Vertical lines in (16 lines
  165. * skipped by the VFE) */
  166. 0x8a, 288, /* Vertical lines out (16 lines
  167. * skipped by the VFE) */
  168. 0x8b, 16, /* Horizontal begin */
  169. 0x8c, 768, /* Horizontal length */
  170. 0x8d, 784, /* Number of pixels
  171. * Must be >= Horizontal begin + Horizontal length */
  172. 0x8f, 0xc00, /* Disable window 2 */
  173. 0xf0, 0x77, /* 13.5 MHz transport, Forced
  174. * mode, latch windows */
  175. 0xf2, 0x3d5, /* SECAM, composite input */
  176. 0xe7, 0x241, /* PAL/SECAM set to 288 lines */
  177. };
  178. static const unsigned char init_common[] = {
  179. 0xf2, 0x00, /* Disable all outputs */
  180. 0x33, 0x0d, /* Luma : VIN2, Chroma : CIN
  181. * (clamp off) */
  182. 0xd8, 0xa8, /* HREF/VREF active high, VREF
  183. * pulse = 2, Odd/Even flag */
  184. 0x20, 0x03, /* IF compensation 0dB/oct */
  185. 0xe0, 0xff, /* Open up all comparators */
  186. 0xe1, 0x00,
  187. 0xe2, 0x7f,
  188. 0xe3, 0x80,
  189. 0xe4, 0x7f,
  190. 0xe5, 0x80,
  191. 0xe6, 0x00, /* Brightness set to 0 */
  192. 0xe7, 0xe0, /* Contrast to 1.0, noise shaping
  193. * 10 to 8 2-bit error diffusion */
  194. 0xe8, 0xf8, /* YUV422, CbCr binary offset,
  195. * ... (p.32) */
  196. 0xea, 0x18, /* LLC2 connected, output FIFO
  197. * reset with VACTintern */
  198. 0xf0, 0x8a, /* Half full level to 10, bus
  199. * shuffler [7:0, 23:16, 15:8] */
  200. 0xf1, 0x18, /* Single clock, sync mode, no
  201. * FE delay, no HLEN counter */
  202. 0xf8, 0x12, /* Port A, PIXCLK, HF# & FE#
  203. * strength to 2 */
  204. 0xf9, 0x24, /* Port B, HREF, VREF, PREF &
  205. * ALPHA strength to 4 */
  206. };
  207. static const unsigned short init_fp[] = {
  208. 0x59, 0,
  209. 0xa0, 2070, /* ACC reference */
  210. 0xa3, 0,
  211. 0xa4, 0,
  212. 0xa8, 30,
  213. 0xb2, 768,
  214. 0xbe, 27,
  215. 0x58, 0,
  216. 0x26, 0,
  217. 0x4b, 0x298, /* PLL gain */
  218. };
  219. static int vpx3220_init(struct v4l2_subdev *sd, u32 val)
  220. {
  221. struct vpx3220 *decoder = to_vpx3220(sd);
  222. vpx3220_write_block(sd, init_common, sizeof(init_common));
  223. vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
  224. if (decoder->norm & V4L2_STD_NTSC)
  225. vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
  226. else if (decoder->norm & V4L2_STD_PAL)
  227. vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
  228. else if (decoder->norm & V4L2_STD_SECAM)
  229. vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
  230. else
  231. vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
  232. return 0;
  233. }
  234. static int vpx3220_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)
  235. {
  236. int res = V4L2_IN_ST_NO_SIGNAL, status;
  237. v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL;
  238. status = vpx3220_fp_read(sd, 0x0f3);
  239. v4l2_dbg(1, debug, sd, "status: 0x%04x\n", status);
  240. if (status < 0)
  241. return status;
  242. if ((status & 0x20) == 0) {
  243. res = 0;
  244. switch (status & 0x18) {
  245. case 0x00:
  246. case 0x10:
  247. case 0x14:
  248. case 0x18:
  249. std &= V4L2_STD_PAL;
  250. break;
  251. case 0x08:
  252. std &= V4L2_STD_SECAM;
  253. break;
  254. case 0x04:
  255. case 0x0c:
  256. case 0x1c:
  257. std &= V4L2_STD_NTSC;
  258. break;
  259. }
  260. } else {
  261. std = V4L2_STD_UNKNOWN;
  262. }
  263. if (pstd)
  264. *pstd = std;
  265. if (pstatus)
  266. *pstatus = res;
  267. return 0;
  268. }
  269. static int vpx3220_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  270. {
  271. v4l2_dbg(1, debug, sd, "querystd\n");
  272. return vpx3220_status(sd, NULL, std);
  273. }
  274. static int vpx3220_g_input_status(struct v4l2_subdev *sd, u32 *status)
  275. {
  276. v4l2_dbg(1, debug, sd, "g_input_status\n");
  277. return vpx3220_status(sd, status, NULL);
  278. }
  279. static int vpx3220_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  280. {
  281. struct vpx3220 *decoder = to_vpx3220(sd);
  282. int temp_input;
  283. /* Here we back up the input selection because it gets
  284. overwritten when we fill the registers with the
  285. chosen video norm */
  286. temp_input = vpx3220_fp_read(sd, 0xf2);
  287. v4l2_dbg(1, debug, sd, "s_std %llx\n", (unsigned long long)std);
  288. if (std & V4L2_STD_NTSC) {
  289. vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
  290. v4l2_dbg(1, debug, sd, "norm switched to NTSC\n");
  291. } else if (std & V4L2_STD_PAL) {
  292. vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
  293. v4l2_dbg(1, debug, sd, "norm switched to PAL\n");
  294. } else if (std & V4L2_STD_SECAM) {
  295. vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
  296. v4l2_dbg(1, debug, sd, "norm switched to SECAM\n");
  297. } else {
  298. return -EINVAL;
  299. }
  300. decoder->norm = std;
  301. /* And here we set the backed up video input again */
  302. vpx3220_fp_write(sd, 0xf2, temp_input | 0x0010);
  303. udelay(10);
  304. return 0;
  305. }
  306. static int vpx3220_s_routing(struct v4l2_subdev *sd,
  307. u32 input, u32 output, u32 config)
  308. {
  309. int data;
  310. /* RJ: input = 0: ST8 (PCTV) input
  311. input = 1: COMPOSITE input
  312. input = 2: SVHS input */
  313. static const int input_vals[3][2] = {
  314. {0x0c, 0},
  315. {0x0d, 0},
  316. {0x0e, 1}
  317. };
  318. if (input > 2)
  319. return -EINVAL;
  320. v4l2_dbg(1, debug, sd, "input switched to %s\n", inputs[input]);
  321. vpx3220_write(sd, 0x33, input_vals[input][0]);
  322. data = vpx3220_fp_read(sd, 0xf2) & ~(0x0020);
  323. if (data < 0)
  324. return data;
  325. /* 0x0010 is required to latch the setting */
  326. vpx3220_fp_write(sd, 0xf2,
  327. data | (input_vals[input][1] << 5) | 0x0010);
  328. udelay(10);
  329. return 0;
  330. }
  331. static int vpx3220_s_stream(struct v4l2_subdev *sd, int enable)
  332. {
  333. v4l2_dbg(1, debug, sd, "s_stream %s\n", enable ? "on" : "off");
  334. vpx3220_write(sd, 0xf2, (enable ? 0x1b : 0x00));
  335. return 0;
  336. }
  337. static int vpx3220_s_ctrl(struct v4l2_ctrl *ctrl)
  338. {
  339. struct v4l2_subdev *sd = to_sd(ctrl);
  340. switch (ctrl->id) {
  341. case V4L2_CID_BRIGHTNESS:
  342. vpx3220_write(sd, 0xe6, ctrl->val);
  343. return 0;
  344. case V4L2_CID_CONTRAST:
  345. /* Bit 7 and 8 is for noise shaping */
  346. vpx3220_write(sd, 0xe7, ctrl->val + 192);
  347. return 0;
  348. case V4L2_CID_SATURATION:
  349. vpx3220_fp_write(sd, 0xa0, ctrl->val);
  350. return 0;
  351. case V4L2_CID_HUE:
  352. vpx3220_fp_write(sd, 0x1c, ctrl->val);
  353. return 0;
  354. }
  355. return -EINVAL;
  356. }
  357. /* ----------------------------------------------------------------------- */
  358. static const struct v4l2_ctrl_ops vpx3220_ctrl_ops = {
  359. .s_ctrl = vpx3220_s_ctrl,
  360. };
  361. static const struct v4l2_subdev_core_ops vpx3220_core_ops = {
  362. .init = vpx3220_init,
  363. };
  364. static const struct v4l2_subdev_video_ops vpx3220_video_ops = {
  365. .s_std = vpx3220_s_std,
  366. .s_routing = vpx3220_s_routing,
  367. .s_stream = vpx3220_s_stream,
  368. .querystd = vpx3220_querystd,
  369. .g_input_status = vpx3220_g_input_status,
  370. };
  371. static const struct v4l2_subdev_ops vpx3220_ops = {
  372. .core = &vpx3220_core_ops,
  373. .video = &vpx3220_video_ops,
  374. };
  375. /* -----------------------------------------------------------------------
  376. * Client management code
  377. */
  378. static int vpx3220_probe(struct i2c_client *client)
  379. {
  380. struct vpx3220 *decoder;
  381. struct v4l2_subdev *sd;
  382. const char *name = NULL;
  383. u8 ver;
  384. u16 pn;
  385. /* Check if the adapter supports the needed features */
  386. if (!i2c_check_functionality(client->adapter,
  387. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
  388. return -ENODEV;
  389. decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
  390. if (decoder == NULL)
  391. return -ENOMEM;
  392. sd = &decoder->sd;
  393. v4l2_i2c_subdev_init(sd, client, &vpx3220_ops);
  394. decoder->norm = V4L2_STD_PAL;
  395. decoder->input = 0;
  396. decoder->enable = 1;
  397. v4l2_ctrl_handler_init(&decoder->hdl, 4);
  398. v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
  399. V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
  400. v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
  401. V4L2_CID_CONTRAST, 0, 63, 1, 32);
  402. v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
  403. V4L2_CID_SATURATION, 0, 4095, 1, 2048);
  404. v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
  405. V4L2_CID_HUE, -512, 511, 1, 0);
  406. sd->ctrl_handler = &decoder->hdl;
  407. if (decoder->hdl.error) {
  408. int err = decoder->hdl.error;
  409. v4l2_ctrl_handler_free(&decoder->hdl);
  410. return err;
  411. }
  412. v4l2_ctrl_handler_setup(&decoder->hdl);
  413. ver = i2c_smbus_read_byte_data(client, 0x00);
  414. pn = (i2c_smbus_read_byte_data(client, 0x02) << 8) +
  415. i2c_smbus_read_byte_data(client, 0x01);
  416. if (ver == 0xec) {
  417. switch (pn) {
  418. case 0x4680:
  419. name = "vpx3220a";
  420. break;
  421. case 0x4260:
  422. name = "vpx3216b";
  423. break;
  424. case 0x4280:
  425. name = "vpx3214c";
  426. break;
  427. }
  428. }
  429. if (name)
  430. v4l2_info(sd, "%s found @ 0x%x (%s)\n", name,
  431. client->addr << 1, client->adapter->name);
  432. else
  433. v4l2_info(sd, "chip (%02x:%04x) found @ 0x%x (%s)\n",
  434. ver, pn, client->addr << 1, client->adapter->name);
  435. vpx3220_write_block(sd, init_common, sizeof(init_common));
  436. vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
  437. /* Default to PAL */
  438. vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
  439. return 0;
  440. }
  441. static void vpx3220_remove(struct i2c_client *client)
  442. {
  443. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  444. struct vpx3220 *decoder = to_vpx3220(sd);
  445. v4l2_device_unregister_subdev(sd);
  446. v4l2_ctrl_handler_free(&decoder->hdl);
  447. }
  448. static const struct i2c_device_id vpx3220_id[] = {
  449. { "vpx3220a" },
  450. { "vpx3216b" },
  451. { "vpx3214c" },
  452. { }
  453. };
  454. MODULE_DEVICE_TABLE(i2c, vpx3220_id);
  455. static struct i2c_driver vpx3220_driver = {
  456. .driver = {
  457. .name = "vpx3220",
  458. },
  459. .probe = vpx3220_probe,
  460. .remove = vpx3220_remove,
  461. .id_table = vpx3220_id,
  462. };
  463. module_i2c_driver(vpx3220_driver);