tvp7002.c 32 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
  3. * Digitizer with Horizontal PLL registers
  4. *
  5. * Copyright (C) 2009 Texas Instruments Inc
  6. * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
  7. *
  8. * This code is partially based upon the TVP5150 driver
  9. * written by Mauro Carvalho Chehab <mchehab@kernel.org>,
  10. * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
  11. * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by
  12. * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/i2c.h>
  16. #include <linux/slab.h>
  17. #include <linux/videodev2.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/of_graph.h>
  21. #include <linux/v4l2-dv-timings.h>
  22. #include <media/i2c/tvp7002.h>
  23. #include <media/v4l2-async.h>
  24. #include <media/v4l2-device.h>
  25. #include <media/v4l2-common.h>
  26. #include <media/v4l2-ctrls.h>
  27. #include <media/v4l2-fwnode.h>
  28. #include "tvp7002_reg.h"
  29. MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver");
  30. MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
  31. MODULE_LICENSE("GPL");
  32. /* I2C retry attempts */
  33. #define I2C_RETRY_COUNT (5)
  34. /* End of registers */
  35. #define TVP7002_EOR 0x5c
  36. /* Read write definition for registers */
  37. #define TVP7002_READ 0
  38. #define TVP7002_WRITE 1
  39. #define TVP7002_RESERVED 2
  40. /* Interlaced vs progressive mask and shift */
  41. #define TVP7002_IP_SHIFT 5
  42. #define TVP7002_INPR_MASK (0x01 << TVP7002_IP_SHIFT)
  43. /* Shift for CPL and LPF registers */
  44. #define TVP7002_CL_SHIFT 8
  45. #define TVP7002_CL_MASK 0x0f
  46. /* Debug functions */
  47. static bool debug;
  48. module_param(debug, bool, 0644);
  49. MODULE_PARM_DESC(debug, "Debug level (0-2)");
  50. /* Structure for register values */
  51. struct i2c_reg_value {
  52. u8 reg;
  53. u8 value;
  54. u8 type;
  55. };
  56. /*
  57. * Register default values (according to tvp7002 datasheet)
  58. * In the case of read-only registers, the value (0xff) is
  59. * never written. R/W functionality is controlled by the
  60. * writable bit in the register struct definition.
  61. */
  62. static const struct i2c_reg_value tvp7002_init_default[] = {
  63. { TVP7002_CHIP_REV, 0xff, TVP7002_READ },
  64. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  65. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  66. { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  67. { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE },
  68. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  69. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  70. { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE },
  71. { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE },
  72. { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE },
  73. { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE },
  74. { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  75. { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  76. { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
  77. { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE },
  78. { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE },
  79. { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE },
  80. { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE },
  81. { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
  82. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  83. { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ },
  84. { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE },
  85. { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
  86. { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
  87. { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
  88. { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
  89. { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
  90. { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
  91. { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
  92. { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
  93. { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE },
  94. { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE },
  95. { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE },
  96. { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE },
  97. { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE },
  98. { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  99. { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  100. { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
  101. { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE },
  102. { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ },
  103. { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE },
  104. { 0x29, 0x08, TVP7002_RESERVED },
  105. { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE },
  106. /* PWR_CTL is controlled only by the probe and reset functions */
  107. { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED },
  108. { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE },
  109. { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
  110. { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE },
  111. { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE },
  112. { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE },
  113. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  114. { 0x32, 0x18, TVP7002_RESERVED },
  115. { 0x33, 0x60, TVP7002_RESERVED },
  116. { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED },
  117. { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE },
  118. { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE },
  119. { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ },
  120. { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ },
  121. { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ },
  122. { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ },
  123. { TVP7002_HSYNC_W, 0xff, TVP7002_READ },
  124. { TVP7002_VSYNC_W, 0xff, TVP7002_READ },
  125. { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE },
  126. { 0x3e, 0x60, TVP7002_RESERVED },
  127. { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE },
  128. { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE },
  129. { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
  130. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  131. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
  132. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  133. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  134. { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE },
  135. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  136. { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
  137. { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  138. { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE },
  139. { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE },
  140. { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE },
  141. { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE },
  142. { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE },
  143. { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE },
  144. { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE },
  145. { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE },
  146. { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE },
  147. { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE },
  148. { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE },
  149. { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE },
  150. { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE },
  151. { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE },
  152. { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE },
  153. { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE },
  154. { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE },
  155. { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE },
  156. /* This signals end of register values */
  157. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  158. };
  159. /* Register parameters for 480P */
  160. static const struct i2c_reg_value tvp7002_parms_480P[] = {
  161. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
  162. { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
  163. { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
  164. { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
  165. { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  166. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE },
  167. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  168. { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE },
  169. { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE },
  170. { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE },
  171. { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE },
  172. { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
  173. { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
  174. { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
  175. { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
  176. { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
  177. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  178. };
  179. /* Register parameters for 576P */
  180. static const struct i2c_reg_value tvp7002_parms_576P[] = {
  181. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE },
  182. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
  183. { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE },
  184. { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE },
  185. { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  186. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE },
  187. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
  188. { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
  189. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  190. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  191. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  192. { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
  193. { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
  194. { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
  195. { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
  196. { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
  197. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  198. };
  199. /* Register parameters for 1080I60 */
  200. static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
  201. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
  202. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
  203. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  204. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  205. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  206. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  207. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  208. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  209. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  210. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  211. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  212. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  213. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  214. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  215. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  216. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  217. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  218. };
  219. /* Register parameters for 1080P60 */
  220. static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
  221. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
  222. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
  223. { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
  224. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  225. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  226. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  227. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  228. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  229. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  230. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  231. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  232. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  233. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  234. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  235. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  236. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  237. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  238. };
  239. /* Register parameters for 1080I50 */
  240. static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
  241. { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE },
  242. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
  243. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  244. { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
  245. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  246. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
  247. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
  248. { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
  249. { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
  250. { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
  251. { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
  252. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  253. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  254. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  255. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  256. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  257. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  258. };
  259. /* Register parameters for 720P60 */
  260. static const struct i2c_reg_value tvp7002_parms_720P60[] = {
  261. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
  262. { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
  263. { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
  264. { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
  265. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  266. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
  267. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
  268. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  269. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  270. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  271. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  272. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  273. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  274. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  275. { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
  276. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  277. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  278. };
  279. /* Register parameters for 720P50 */
  280. static const struct i2c_reg_value tvp7002_parms_720P50[] = {
  281. { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
  282. { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
  283. { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
  284. { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
  285. { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
  286. { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
  287. { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
  288. { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
  289. { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
  290. { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
  291. { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
  292. { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
  293. { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
  294. { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
  295. { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
  296. { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
  297. { TVP7002_EOR, 0xff, TVP7002_RESERVED }
  298. };
  299. /* Timings definition for handling device operation */
  300. struct tvp7002_timings_definition {
  301. struct v4l2_dv_timings timings;
  302. const struct i2c_reg_value *p_settings;
  303. enum v4l2_colorspace color_space;
  304. enum v4l2_field scanmode;
  305. u16 progressive;
  306. u16 lines_per_frame;
  307. u16 cpl_min;
  308. u16 cpl_max;
  309. };
  310. /* Struct list for digital video timings */
  311. static const struct tvp7002_timings_definition tvp7002_timings[] = {
  312. {
  313. V4L2_DV_BT_CEA_1280X720P60,
  314. tvp7002_parms_720P60,
  315. V4L2_COLORSPACE_REC709,
  316. V4L2_FIELD_NONE,
  317. 1,
  318. 0x2EE,
  319. 135,
  320. 153
  321. },
  322. {
  323. V4L2_DV_BT_CEA_1920X1080I60,
  324. tvp7002_parms_1080I60,
  325. V4L2_COLORSPACE_REC709,
  326. V4L2_FIELD_INTERLACED,
  327. 0,
  328. 0x465,
  329. 181,
  330. 205
  331. },
  332. {
  333. V4L2_DV_BT_CEA_1920X1080I50,
  334. tvp7002_parms_1080I50,
  335. V4L2_COLORSPACE_REC709,
  336. V4L2_FIELD_INTERLACED,
  337. 0,
  338. 0x465,
  339. 217,
  340. 245
  341. },
  342. {
  343. V4L2_DV_BT_CEA_1280X720P50,
  344. tvp7002_parms_720P50,
  345. V4L2_COLORSPACE_REC709,
  346. V4L2_FIELD_NONE,
  347. 1,
  348. 0x2EE,
  349. 163,
  350. 183
  351. },
  352. {
  353. V4L2_DV_BT_CEA_1920X1080P60,
  354. tvp7002_parms_1080P60,
  355. V4L2_COLORSPACE_REC709,
  356. V4L2_FIELD_NONE,
  357. 1,
  358. 0x465,
  359. 90,
  360. 102
  361. },
  362. {
  363. V4L2_DV_BT_CEA_720X480P59_94,
  364. tvp7002_parms_480P,
  365. V4L2_COLORSPACE_SMPTE170M,
  366. V4L2_FIELD_NONE,
  367. 1,
  368. 0x20D,
  369. 0xffff,
  370. 0xffff
  371. },
  372. {
  373. V4L2_DV_BT_CEA_720X576P50,
  374. tvp7002_parms_576P,
  375. V4L2_COLORSPACE_SMPTE170M,
  376. V4L2_FIELD_NONE,
  377. 1,
  378. 0x271,
  379. 0xffff,
  380. 0xffff
  381. }
  382. };
  383. #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings)
  384. /* Device definition */
  385. struct tvp7002 {
  386. struct v4l2_subdev sd;
  387. struct v4l2_ctrl_handler hdl;
  388. const struct tvp7002_config *pdata;
  389. int ver;
  390. int streaming;
  391. const struct tvp7002_timings_definition *current_timings;
  392. struct media_pad pad;
  393. };
  394. /*
  395. * to_tvp7002 - Obtain device handler TVP7002
  396. * @sd: ptr to v4l2_subdev struct
  397. *
  398. * Returns device handler tvp7002.
  399. */
  400. static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd)
  401. {
  402. return container_of(sd, struct tvp7002, sd);
  403. }
  404. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  405. {
  406. return &container_of(ctrl->handler, struct tvp7002, hdl)->sd;
  407. }
  408. /*
  409. * tvp7002_read - Read a value from a register in an TVP7002
  410. * @sd: ptr to v4l2_subdev struct
  411. * @addr: TVP7002 register address
  412. * @dst: pointer to 8-bit destination
  413. *
  414. * Returns value read if successful, or non-zero (-1) otherwise.
  415. */
  416. static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
  417. {
  418. struct i2c_client *c = v4l2_get_subdevdata(sd);
  419. int retry;
  420. int error;
  421. for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
  422. error = i2c_smbus_read_byte_data(c, addr);
  423. if (error >= 0) {
  424. *dst = (u8)error;
  425. return 0;
  426. }
  427. msleep_interruptible(10);
  428. }
  429. v4l2_err(sd, "TVP7002 read error %d\n", error);
  430. return error;
  431. }
  432. /*
  433. * tvp7002_read_err() - Read a register value with error code
  434. * @sd: pointer to standard V4L2 sub-device structure
  435. * @reg: destination register
  436. * @val: value to be read
  437. * @err: pointer to error value
  438. *
  439. * Read a value in a register and save error value in pointer.
  440. * Also update the register table if successful
  441. */
  442. static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg,
  443. u8 *dst, int *err)
  444. {
  445. if (!*err)
  446. *err = tvp7002_read(sd, reg, dst);
  447. }
  448. /*
  449. * tvp7002_write() - Write a value to a register in TVP7002
  450. * @sd: ptr to v4l2_subdev struct
  451. * @addr: TVP7002 register address
  452. * @value: value to be written to the register
  453. *
  454. * Write a value to a register in an TVP7002 decoder device.
  455. * Returns zero if successful, or non-zero otherwise.
  456. */
  457. static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value)
  458. {
  459. struct i2c_client *c;
  460. int retry;
  461. int error;
  462. c = v4l2_get_subdevdata(sd);
  463. for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
  464. error = i2c_smbus_write_byte_data(c, addr, value);
  465. if (error >= 0)
  466. return 0;
  467. v4l2_warn(sd, "Write: retry ... %d\n", retry);
  468. msleep_interruptible(10);
  469. }
  470. v4l2_err(sd, "TVP7002 write error %d\n", error);
  471. return error;
  472. }
  473. /*
  474. * tvp7002_write_err() - Write a register value with error code
  475. * @sd: pointer to standard V4L2 sub-device structure
  476. * @reg: destination register
  477. * @val: value to be written
  478. * @err: pointer to error value
  479. *
  480. * Write a value in a register and save error value in pointer.
  481. * Also update the register table if successful
  482. */
  483. static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg,
  484. u8 val, int *err)
  485. {
  486. if (!*err)
  487. *err = tvp7002_write(sd, reg, val);
  488. }
  489. /*
  490. * tvp7002_write_inittab() - Write initialization values
  491. * @sd: ptr to v4l2_subdev struct
  492. * @regs: ptr to i2c_reg_value struct
  493. *
  494. * Write initialization values.
  495. * Returns zero or -EINVAL if read operation fails.
  496. */
  497. static int tvp7002_write_inittab(struct v4l2_subdev *sd,
  498. const struct i2c_reg_value *regs)
  499. {
  500. int error = 0;
  501. /* Initialize the first (defined) registers */
  502. while (TVP7002_EOR != regs->reg) {
  503. if (TVP7002_WRITE == regs->type)
  504. tvp7002_write_err(sd, regs->reg, regs->value, &error);
  505. regs++;
  506. }
  507. return error;
  508. }
  509. static int tvp7002_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
  510. struct v4l2_dv_timings *dv_timings)
  511. {
  512. struct tvp7002 *device = to_tvp7002(sd);
  513. const struct v4l2_bt_timings *bt = &dv_timings->bt;
  514. int i;
  515. if (pad != 0)
  516. return -EINVAL;
  517. if (dv_timings->type != V4L2_DV_BT_656_1120)
  518. return -EINVAL;
  519. for (i = 0; i < NUM_TIMINGS; i++) {
  520. const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt;
  521. if (!memcmp(bt, t, &bt->standards - &bt->width)) {
  522. device->current_timings = &tvp7002_timings[i];
  523. return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings);
  524. }
  525. }
  526. return -EINVAL;
  527. }
  528. static int tvp7002_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
  529. struct v4l2_dv_timings *dv_timings)
  530. {
  531. struct tvp7002 *device = to_tvp7002(sd);
  532. if (pad != 0)
  533. return -EINVAL;
  534. *dv_timings = device->current_timings->timings;
  535. return 0;
  536. }
  537. /*
  538. * tvp7002_s_ctrl() - Set a control
  539. * @ctrl: ptr to v4l2_ctrl struct
  540. *
  541. * Set a control in TVP7002 decoder device.
  542. * Returns zero when successful or -EINVAL if register access fails.
  543. */
  544. static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl)
  545. {
  546. struct v4l2_subdev *sd = to_sd(ctrl);
  547. int error = 0;
  548. switch (ctrl->id) {
  549. case V4L2_CID_GAIN:
  550. tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error);
  551. tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error);
  552. tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error);
  553. return error;
  554. }
  555. return -EINVAL;
  556. }
  557. /*
  558. * tvp7002_query_dv() - query DV timings
  559. * @sd: pointer to standard V4L2 sub-device structure
  560. * @index: index into the tvp7002_timings array
  561. *
  562. * Returns the current DV timings detected by TVP7002. If no active input is
  563. * detected, returns -EINVAL
  564. */
  565. static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index)
  566. {
  567. const struct tvp7002_timings_definition *timings = tvp7002_timings;
  568. u8 progressive;
  569. u32 lpfr;
  570. u32 cpln;
  571. int error = 0;
  572. u8 lpf_lsb;
  573. u8 lpf_msb;
  574. u8 cpl_lsb;
  575. u8 cpl_msb;
  576. /* Return invalid index if no active input is detected */
  577. *index = NUM_TIMINGS;
  578. /* Read standards from device registers */
  579. tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
  580. tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error);
  581. if (error < 0)
  582. return error;
  583. tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error);
  584. tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error);
  585. if (error < 0)
  586. return error;
  587. /* Get lines per frame, clocks per line and interlaced/progresive */
  588. lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT);
  589. cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT);
  590. progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT;
  591. /* Do checking of video modes */
  592. for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++)
  593. if (lpfr == timings->lines_per_frame &&
  594. progressive == timings->progressive) {
  595. if (timings->cpl_min == 0xffff)
  596. break;
  597. if (cpln >= timings->cpl_min && cpln <= timings->cpl_max)
  598. break;
  599. }
  600. if (*index == NUM_TIMINGS) {
  601. v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
  602. lpfr, cpln);
  603. return -ENOLINK;
  604. }
  605. /* Update lines per frame and clocks per line info */
  606. v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index);
  607. return 0;
  608. }
  609. static int tvp7002_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
  610. struct v4l2_dv_timings *timings)
  611. {
  612. int index;
  613. int err;
  614. if (pad != 0)
  615. return -EINVAL;
  616. err = tvp7002_query_dv(sd, &index);
  617. if (err)
  618. return err;
  619. *timings = tvp7002_timings[index].timings;
  620. return 0;
  621. }
  622. #ifdef CONFIG_VIDEO_ADV_DEBUG
  623. /*
  624. * tvp7002_g_register() - Get the value of a register
  625. * @sd: ptr to v4l2_subdev struct
  626. * @reg: ptr to v4l2_dbg_register struct
  627. *
  628. * Get the value of a TVP7002 decoder device register.
  629. * Returns zero when successful, -EINVAL if register read fails or
  630. * access to I2C client fails.
  631. */
  632. static int tvp7002_g_register(struct v4l2_subdev *sd,
  633. struct v4l2_dbg_register *reg)
  634. {
  635. u8 val;
  636. int ret;
  637. ret = tvp7002_read(sd, reg->reg & 0xff, &val);
  638. if (ret < 0)
  639. return ret;
  640. reg->val = val;
  641. reg->size = 1;
  642. return 0;
  643. }
  644. /*
  645. * tvp7002_s_register() - set a control
  646. * @sd: ptr to v4l2_subdev struct
  647. * @reg: ptr to v4l2_dbg_register struct
  648. *
  649. * Get the value of a TVP7002 decoder device register.
  650. * Returns zero when successful, -EINVAL if register read fails.
  651. */
  652. static int tvp7002_s_register(struct v4l2_subdev *sd,
  653. const struct v4l2_dbg_register *reg)
  654. {
  655. return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff);
  656. }
  657. #endif
  658. /*
  659. * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream
  660. * @sd: pointer to standard V4L2 sub-device structure
  661. * @enable: streaming enable or disable
  662. *
  663. * Sets streaming to enable or disable, if possible.
  664. */
  665. static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable)
  666. {
  667. struct tvp7002 *device = to_tvp7002(sd);
  668. int error;
  669. if (device->streaming == enable)
  670. return 0;
  671. /* low impedance: on, high impedance: off */
  672. error = tvp7002_write(sd, TVP7002_MISC_CTL_2, enable ? 0x00 : 0x03);
  673. if (error) {
  674. v4l2_dbg(1, debug, sd, "Fail to set streaming\n");
  675. return error;
  676. }
  677. device->streaming = enable;
  678. return 0;
  679. }
  680. /*
  681. * tvp7002_log_status() - Print information about register settings
  682. * @sd: ptr to v4l2_subdev struct
  683. *
  684. * Log register values of a TVP7002 decoder device.
  685. * Returns zero or -EINVAL if read operation fails.
  686. */
  687. static int tvp7002_log_status(struct v4l2_subdev *sd)
  688. {
  689. struct tvp7002 *device = to_tvp7002(sd);
  690. const struct v4l2_bt_timings *bt;
  691. int detected;
  692. /* Find my current timings */
  693. tvp7002_query_dv(sd, &detected);
  694. bt = &device->current_timings->timings.bt;
  695. v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height);
  696. if (detected == NUM_TIMINGS) {
  697. v4l2_info(sd, "Detected DV Timings: None\n");
  698. } else {
  699. bt = &tvp7002_timings[detected].timings.bt;
  700. v4l2_info(sd, "Detected DV Timings: %ux%u\n",
  701. bt->width, bt->height);
  702. }
  703. v4l2_info(sd, "Streaming enabled: %s\n",
  704. device->streaming ? "yes" : "no");
  705. /* Print the current value of the gain control */
  706. v4l2_ctrl_handler_log_status(&device->hdl, sd->name);
  707. return 0;
  708. }
  709. static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd,
  710. struct v4l2_enum_dv_timings *timings)
  711. {
  712. if (timings->pad != 0)
  713. return -EINVAL;
  714. /* Check requested format index is within range */
  715. if (timings->index >= NUM_TIMINGS)
  716. return -EINVAL;
  717. timings->timings = tvp7002_timings[timings->index].timings;
  718. return 0;
  719. }
  720. static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {
  721. .s_ctrl = tvp7002_s_ctrl,
  722. };
  723. /*
  724. * tvp7002_enum_mbus_code() - Enum supported digital video format on pad
  725. * @sd: pointer to standard V4L2 sub-device structure
  726. * @sd_state: V4L2 subdev state
  727. * @code: pointer to subdev enum mbus code struct
  728. *
  729. * Enumerate supported digital video formats for pad.
  730. */
  731. static int
  732. tvp7002_enum_mbus_code(struct v4l2_subdev *sd,
  733. struct v4l2_subdev_state *sd_state,
  734. struct v4l2_subdev_mbus_code_enum *code)
  735. {
  736. /* Check requested format index is within range */
  737. if (code->index != 0)
  738. return -EINVAL;
  739. code->code = MEDIA_BUS_FMT_YUYV10_1X20;
  740. return 0;
  741. }
  742. /*
  743. * tvp7002_get_pad_format() - get video format on pad
  744. * @sd: pointer to standard V4L2 sub-device structure
  745. * @sd_state: V4L2 subdev state
  746. * @fmt: pointer to subdev format struct
  747. *
  748. * get video format for pad.
  749. */
  750. static int
  751. tvp7002_get_pad_format(struct v4l2_subdev *sd,
  752. struct v4l2_subdev_state *sd_state,
  753. struct v4l2_subdev_format *fmt)
  754. {
  755. struct tvp7002 *tvp7002 = to_tvp7002(sd);
  756. fmt->format.code = MEDIA_BUS_FMT_YUYV10_1X20;
  757. fmt->format.width = tvp7002->current_timings->timings.bt.width;
  758. fmt->format.height = tvp7002->current_timings->timings.bt.height;
  759. fmt->format.field = tvp7002->current_timings->scanmode;
  760. fmt->format.colorspace = tvp7002->current_timings->color_space;
  761. return 0;
  762. }
  763. /*
  764. * tvp7002_set_pad_format() - set video format on pad
  765. * @sd: pointer to standard V4L2 sub-device structure
  766. * @sd_state: V4L2 subdev state
  767. * @fmt: pointer to subdev format struct
  768. *
  769. * set video format for pad.
  770. */
  771. static int
  772. tvp7002_set_pad_format(struct v4l2_subdev *sd,
  773. struct v4l2_subdev_state *sd_state,
  774. struct v4l2_subdev_format *fmt)
  775. {
  776. return tvp7002_get_pad_format(sd, sd_state, fmt);
  777. }
  778. /* V4L2 core operation handlers */
  779. static const struct v4l2_subdev_core_ops tvp7002_core_ops = {
  780. .log_status = tvp7002_log_status,
  781. #ifdef CONFIG_VIDEO_ADV_DEBUG
  782. .g_register = tvp7002_g_register,
  783. .s_register = tvp7002_s_register,
  784. #endif
  785. };
  786. /* Specific video subsystem operation handlers */
  787. static const struct v4l2_subdev_video_ops tvp7002_video_ops = {
  788. .s_stream = tvp7002_s_stream,
  789. };
  790. /* media pad related operation handlers */
  791. static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = {
  792. .enum_mbus_code = tvp7002_enum_mbus_code,
  793. .get_fmt = tvp7002_get_pad_format,
  794. .set_fmt = tvp7002_set_pad_format,
  795. .g_dv_timings = tvp7002_g_dv_timings,
  796. .s_dv_timings = tvp7002_s_dv_timings,
  797. .query_dv_timings = tvp7002_query_dv_timings,
  798. .enum_dv_timings = tvp7002_enum_dv_timings,
  799. };
  800. /* V4L2 top level operation handlers */
  801. static const struct v4l2_subdev_ops tvp7002_ops = {
  802. .core = &tvp7002_core_ops,
  803. .video = &tvp7002_video_ops,
  804. .pad = &tvp7002_pad_ops,
  805. };
  806. static struct tvp7002_config *
  807. tvp7002_get_pdata(struct i2c_client *client)
  808. {
  809. struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
  810. struct tvp7002_config *pdata = NULL;
  811. struct device_node *endpoint;
  812. unsigned int flags;
  813. if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
  814. return client->dev.platform_data;
  815. endpoint = of_graph_get_endpoint_by_regs(client->dev.of_node, 0, -1);
  816. if (!endpoint)
  817. return NULL;
  818. if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg))
  819. goto done;
  820. pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
  821. if (!pdata)
  822. goto done;
  823. flags = bus_cfg.bus.parallel.flags;
  824. if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
  825. pdata->hs_polarity = 1;
  826. if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
  827. pdata->vs_polarity = 1;
  828. if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
  829. pdata->clk_polarity = 1;
  830. if (flags & V4L2_MBUS_FIELD_EVEN_HIGH)
  831. pdata->fid_polarity = 1;
  832. if (flags & V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH)
  833. pdata->sog_polarity = 1;
  834. done:
  835. of_node_put(endpoint);
  836. return pdata;
  837. }
  838. /*
  839. * tvp7002_probe - Probe a TVP7002 device
  840. * @c: ptr to i2c_client struct
  841. * @id: ptr to i2c_device_id struct
  842. *
  843. * Initialize the TVP7002 device
  844. * Returns zero when successful, -EINVAL if register read fails or
  845. * -EIO if i2c access is not available.
  846. */
  847. static int tvp7002_probe(struct i2c_client *c)
  848. {
  849. struct tvp7002_config *pdata = tvp7002_get_pdata(c);
  850. struct v4l2_subdev *sd;
  851. struct tvp7002 *device;
  852. struct v4l2_dv_timings timings;
  853. int polarity_a;
  854. int polarity_b;
  855. u8 revision;
  856. int error;
  857. if (pdata == NULL) {
  858. dev_err(&c->dev, "No platform data\n");
  859. return -EINVAL;
  860. }
  861. /* Check if the adapter supports the needed features */
  862. if (!i2c_check_functionality(c->adapter,
  863. I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
  864. return -EIO;
  865. device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL);
  866. if (!device)
  867. return -ENOMEM;
  868. sd = &device->sd;
  869. device->pdata = pdata;
  870. device->current_timings = tvp7002_timings;
  871. /* Tell v4l2 the device is ready */
  872. v4l2_i2c_subdev_init(sd, c, &tvp7002_ops);
  873. v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n",
  874. c->addr, c->adapter->name);
  875. error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision);
  876. if (error < 0)
  877. return error;
  878. /* Get revision number */
  879. v4l2_info(sd, "Rev. %02x detected.\n", revision);
  880. if (revision != 0x02)
  881. v4l2_info(sd, "Unknown revision detected.\n");
  882. /* Initializes TVP7002 to its default values */
  883. error = tvp7002_write_inittab(sd, tvp7002_init_default);
  884. if (error < 0)
  885. return error;
  886. /* Set polarity information after registers have been set */
  887. polarity_a = 0x20 | device->pdata->hs_polarity << 5
  888. | device->pdata->vs_polarity << 2;
  889. error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a);
  890. if (error < 0)
  891. return error;
  892. polarity_b = 0x01 | device->pdata->fid_polarity << 2
  893. | device->pdata->sog_polarity << 1
  894. | device->pdata->clk_polarity;
  895. error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b);
  896. if (error < 0)
  897. return error;
  898. /* Set registers according to default video mode */
  899. timings = device->current_timings->timings;
  900. error = tvp7002_s_dv_timings(sd, 0, &timings);
  901. #if defined(CONFIG_MEDIA_CONTROLLER)
  902. device->pad.flags = MEDIA_PAD_FL_SOURCE;
  903. device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  904. device->sd.entity.function = MEDIA_ENT_F_ATV_DECODER;
  905. error = media_entity_pads_init(&device->sd.entity, 1, &device->pad);
  906. if (error < 0)
  907. return error;
  908. #endif
  909. v4l2_ctrl_handler_init(&device->hdl, 1);
  910. v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops,
  911. V4L2_CID_GAIN, 0, 255, 1, 0);
  912. sd->ctrl_handler = &device->hdl;
  913. if (device->hdl.error) {
  914. error = device->hdl.error;
  915. goto error;
  916. }
  917. v4l2_ctrl_handler_setup(&device->hdl);
  918. error = v4l2_async_register_subdev(&device->sd);
  919. if (error)
  920. goto error;
  921. return 0;
  922. error:
  923. v4l2_ctrl_handler_free(&device->hdl);
  924. #if defined(CONFIG_MEDIA_CONTROLLER)
  925. media_entity_cleanup(&device->sd.entity);
  926. #endif
  927. return error;
  928. }
  929. /*
  930. * tvp7002_remove - Remove TVP7002 device support
  931. * @c: ptr to i2c_client struct
  932. *
  933. * Reset the TVP7002 device
  934. * Returns zero.
  935. */
  936. static void tvp7002_remove(struct i2c_client *c)
  937. {
  938. struct v4l2_subdev *sd = i2c_get_clientdata(c);
  939. struct tvp7002 *device = to_tvp7002(sd);
  940. v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter"
  941. "on address 0x%x\n", c->addr);
  942. v4l2_async_unregister_subdev(&device->sd);
  943. #if defined(CONFIG_MEDIA_CONTROLLER)
  944. media_entity_cleanup(&device->sd.entity);
  945. #endif
  946. v4l2_ctrl_handler_free(&device->hdl);
  947. }
  948. /* I2C Device ID table */
  949. static const struct i2c_device_id tvp7002_id[] = {
  950. { "tvp7002" },
  951. { }
  952. };
  953. MODULE_DEVICE_TABLE(i2c, tvp7002_id);
  954. #if IS_ENABLED(CONFIG_OF)
  955. static const struct of_device_id tvp7002_of_match[] = {
  956. { .compatible = "ti,tvp7002", },
  957. { /* sentinel */ },
  958. };
  959. MODULE_DEVICE_TABLE(of, tvp7002_of_match);
  960. #endif
  961. /* I2C driver data */
  962. static struct i2c_driver tvp7002_driver = {
  963. .driver = {
  964. .of_match_table = of_match_ptr(tvp7002_of_match),
  965. .name = TVP7002_MODULE_NAME,
  966. },
  967. .probe = tvp7002_probe,
  968. .remove = tvp7002_remove,
  969. .id_table = tvp7002_id,
  970. };
  971. module_i2c_driver(tvp7002_driver);