ov2685.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ov2685 driver
  4. *
  5. * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/i2c.h>
  12. #include <linux/module.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <linux/sysfs.h>
  16. #include <media/media-entity.h>
  17. #include <media/v4l2-async.h>
  18. #include <media/v4l2-ctrls.h>
  19. #include <media/v4l2-fwnode.h>
  20. #include <media/v4l2-subdev.h>
  21. #define CHIP_ID 0x2685
  22. #define OV2685_REG_CHIP_ID 0x300a
  23. #define OV2685_XVCLK_FREQ 24000000
  24. #define REG_SC_CTRL_MODE 0x0100
  25. #define SC_CTRL_MODE_STANDBY 0x0
  26. #define SC_CTRL_MODE_STREAMING BIT(0)
  27. #define OV2685_REG_EXPOSURE 0x3500
  28. #define OV2685_EXPOSURE_MIN 4
  29. #define OV2685_EXPOSURE_STEP 1
  30. #define OV2685_REG_VTS 0x380e
  31. #define OV2685_VTS_MAX 0x7fff
  32. #define OV2685_REG_GAIN 0x350a
  33. #define OV2685_GAIN_MIN 0
  34. #define OV2685_GAIN_MAX 0x07ff
  35. #define OV2685_GAIN_STEP 0x1
  36. #define OV2685_GAIN_DEFAULT 0x0036
  37. #define OV2685_REG_TEST_PATTERN 0x5080
  38. #define OV2685_TEST_PATTERN_DISABLED 0x00
  39. #define OV2685_TEST_PATTERN_COLOR_BAR 0x80
  40. #define OV2685_TEST_PATTERN_RANDOM 0x81
  41. #define OV2685_TEST_PATTERN_COLOR_BAR_FADE 0x88
  42. #define OV2685_TEST_PATTERN_BW_SQUARE 0x92
  43. #define OV2685_TEST_PATTERN_COLOR_SQUARE 0x82
  44. #define REG_NULL 0xFFFF
  45. #define OV2685_REG_VALUE_08BIT 1
  46. #define OV2685_REG_VALUE_16BIT 2
  47. #define OV2685_REG_VALUE_24BIT 3
  48. #define OV2685_NATIVE_WIDTH 1616
  49. #define OV2685_NATIVE_HEIGHT 1216
  50. #define OV2685_LANES 1
  51. #define OV2685_BITS_PER_SAMPLE 10
  52. static const char * const ov2685_supply_names[] = {
  53. "avdd", /* Analog power */
  54. "dovdd", /* Digital I/O power */
  55. "dvdd", /* Digital core power */
  56. };
  57. #define OV2685_NUM_SUPPLIES ARRAY_SIZE(ov2685_supply_names)
  58. struct regval {
  59. u16 addr;
  60. u8 val;
  61. };
  62. struct ov2685_mode {
  63. u32 width;
  64. u32 height;
  65. u32 exp_def;
  66. u32 hts_def;
  67. u32 vts_def;
  68. const struct v4l2_rect *analog_crop;
  69. const struct regval *reg_list;
  70. };
  71. struct ov2685 {
  72. struct i2c_client *client;
  73. struct clk *xvclk;
  74. struct gpio_desc *reset_gpio;
  75. struct regulator_bulk_data supplies[OV2685_NUM_SUPPLIES];
  76. struct mutex mutex;
  77. struct v4l2_subdev subdev;
  78. struct media_pad pad;
  79. struct v4l2_ctrl *anal_gain;
  80. struct v4l2_ctrl *exposure;
  81. struct v4l2_ctrl *hblank;
  82. struct v4l2_ctrl *vblank;
  83. struct v4l2_ctrl *test_pattern;
  84. struct v4l2_ctrl_handler ctrl_handler;
  85. const struct ov2685_mode *cur_mode;
  86. };
  87. #define to_ov2685(sd) container_of(sd, struct ov2685, subdev)
  88. /* PLL settings bases on 24M xvclk */
  89. static struct regval ov2685_1600x1200_regs[] = {
  90. {0x0103, 0x01},
  91. {0x0100, 0x00},
  92. {0x3002, 0x00},
  93. {0x3016, 0x1c},
  94. {0x3018, 0x44},
  95. {0x301d, 0xf0},
  96. {0x3020, 0x00},
  97. {0x3082, 0x37},
  98. {0x3083, 0x03},
  99. {0x3084, 0x09},
  100. {0x3085, 0x04},
  101. {0x3086, 0x00},
  102. {0x3087, 0x00},
  103. {0x3501, 0x4e},
  104. {0x3502, 0xe0},
  105. {0x3503, 0x27},
  106. {0x350b, 0x36},
  107. {0x3600, 0xb4},
  108. {0x3603, 0x35},
  109. {0x3604, 0x24},
  110. {0x3605, 0x00},
  111. {0x3620, 0x24},
  112. {0x3621, 0x34},
  113. {0x3622, 0x03},
  114. {0x3628, 0x10},
  115. {0x3705, 0x3c},
  116. {0x370a, 0x21},
  117. {0x370c, 0x50},
  118. {0x370d, 0xc0},
  119. {0x3717, 0x58},
  120. {0x3718, 0x80},
  121. {0x3720, 0x00},
  122. {0x3721, 0x09},
  123. {0x3722, 0x06},
  124. {0x3723, 0x59},
  125. {0x3738, 0x99},
  126. {0x3781, 0x80},
  127. {0x3784, 0x0c},
  128. {0x3789, 0x60},
  129. {0x3800, 0x00},
  130. {0x3801, 0x00},
  131. {0x3802, 0x00},
  132. {0x3803, 0x00},
  133. {0x3804, 0x06},
  134. {0x3805, 0x4f},
  135. {0x3806, 0x04},
  136. {0x3807, 0xbf},
  137. {0x3808, 0x06},
  138. {0x3809, 0x40},
  139. {0x380a, 0x04},
  140. {0x380b, 0xb0},
  141. {0x380c, 0x06},
  142. {0x380d, 0xa4},
  143. {0x380e, 0x05},
  144. {0x380f, 0x0e},
  145. {0x3810, 0x00},
  146. {0x3811, 0x08},
  147. {0x3812, 0x00},
  148. {0x3813, 0x08},
  149. {0x3814, 0x11},
  150. {0x3815, 0x11},
  151. {0x3819, 0x04},
  152. {0x3820, 0xc0},
  153. {0x3821, 0x00},
  154. {0x3a06, 0x01},
  155. {0x3a07, 0x84},
  156. {0x3a08, 0x01},
  157. {0x3a09, 0x43},
  158. {0x3a0a, 0x24},
  159. {0x3a0b, 0x60},
  160. {0x3a0c, 0x28},
  161. {0x3a0d, 0x60},
  162. {0x3a0e, 0x04},
  163. {0x3a0f, 0x8c},
  164. {0x3a10, 0x05},
  165. {0x3a11, 0x0c},
  166. {0x4000, 0x81},
  167. {0x4001, 0x40},
  168. {0x4008, 0x02},
  169. {0x4009, 0x09},
  170. {0x4300, 0x00},
  171. {0x430e, 0x00},
  172. {0x4602, 0x02},
  173. {0x481b, 0x40},
  174. {0x481f, 0x40},
  175. {0x4837, 0x18},
  176. {0x5000, 0x1f},
  177. {0x5001, 0x05},
  178. {0x5002, 0x30},
  179. {0x5003, 0x04},
  180. {0x5004, 0x00},
  181. {0x5005, 0x0c},
  182. {0x5280, 0x15},
  183. {0x5281, 0x06},
  184. {0x5282, 0x06},
  185. {0x5283, 0x08},
  186. {0x5284, 0x1c},
  187. {0x5285, 0x1c},
  188. {0x5286, 0x20},
  189. {0x5287, 0x10},
  190. {REG_NULL, 0x00}
  191. };
  192. #define OV2685_LINK_FREQ_330MHZ 330000000
  193. static const s64 link_freq_menu_items[] = {
  194. OV2685_LINK_FREQ_330MHZ
  195. };
  196. static const char * const ov2685_test_pattern_menu[] = {
  197. "Disabled",
  198. "Color Bar",
  199. "Color Bar FADE",
  200. "Random Data",
  201. "Black White Square",
  202. "Color Square"
  203. };
  204. static const int ov2685_test_pattern_val[] = {
  205. OV2685_TEST_PATTERN_DISABLED,
  206. OV2685_TEST_PATTERN_COLOR_BAR,
  207. OV2685_TEST_PATTERN_COLOR_BAR_FADE,
  208. OV2685_TEST_PATTERN_RANDOM,
  209. OV2685_TEST_PATTERN_BW_SQUARE,
  210. OV2685_TEST_PATTERN_COLOR_SQUARE,
  211. };
  212. static const struct v4l2_rect ov2685_analog_crop = {
  213. .left = 8,
  214. .top = 8,
  215. .width = 1600,
  216. .height = 1200,
  217. };
  218. static const struct ov2685_mode supported_modes[] = {
  219. {
  220. .width = 1600,
  221. .height = 1200,
  222. .exp_def = 0x04ee,
  223. .hts_def = 0x06a4,
  224. .vts_def = 0x050e,
  225. .analog_crop = &ov2685_analog_crop,
  226. .reg_list = ov2685_1600x1200_regs,
  227. },
  228. };
  229. /* Write registers up to 4 at a time */
  230. static int ov2685_write_reg(struct i2c_client *client, u16 reg,
  231. u32 len, u32 val)
  232. {
  233. u32 val_i, buf_i;
  234. u8 buf[6];
  235. u8 *val_p;
  236. __be32 val_be;
  237. if (len > 4)
  238. return -EINVAL;
  239. buf[0] = reg >> 8;
  240. buf[1] = reg & 0xff;
  241. val_be = cpu_to_be32(val);
  242. val_p = (u8 *)&val_be;
  243. buf_i = 2;
  244. val_i = 4 - len;
  245. while (val_i < 4)
  246. buf[buf_i++] = val_p[val_i++];
  247. if (i2c_master_send(client, buf, len + 2) != len + 2)
  248. return -EIO;
  249. return 0;
  250. }
  251. static int ov2685_write_array(struct i2c_client *client,
  252. const struct regval *regs)
  253. {
  254. int ret = 0;
  255. u32 i;
  256. for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
  257. ret = ov2685_write_reg(client, regs[i].addr,
  258. OV2685_REG_VALUE_08BIT, regs[i].val);
  259. return ret;
  260. }
  261. /* Read registers up to 4 at a time */
  262. static int ov2685_read_reg(struct i2c_client *client, u16 reg,
  263. u32 len, u32 *val)
  264. {
  265. struct i2c_msg msgs[2];
  266. u8 *data_be_p;
  267. __be32 data_be = 0;
  268. __be16 reg_addr_be = cpu_to_be16(reg);
  269. int ret;
  270. if (len > 4)
  271. return -EINVAL;
  272. data_be_p = (u8 *)&data_be;
  273. /* Write register address */
  274. msgs[0].addr = client->addr;
  275. msgs[0].flags = 0;
  276. msgs[0].len = 2;
  277. msgs[0].buf = (u8 *)&reg_addr_be;
  278. /* Read data from register */
  279. msgs[1].addr = client->addr;
  280. msgs[1].flags = I2C_M_RD;
  281. msgs[1].len = len;
  282. msgs[1].buf = &data_be_p[4 - len];
  283. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  284. if (ret != ARRAY_SIZE(msgs))
  285. return -EIO;
  286. *val = be32_to_cpu(data_be);
  287. return 0;
  288. }
  289. static void ov2685_fill_fmt(const struct ov2685_mode *mode,
  290. struct v4l2_mbus_framefmt *fmt)
  291. {
  292. fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
  293. fmt->width = mode->width;
  294. fmt->height = mode->height;
  295. fmt->field = V4L2_FIELD_NONE;
  296. }
  297. static int ov2685_set_fmt(struct v4l2_subdev *sd,
  298. struct v4l2_subdev_state *sd_state,
  299. struct v4l2_subdev_format *fmt)
  300. {
  301. struct ov2685 *ov2685 = to_ov2685(sd);
  302. struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
  303. /* only one mode supported for now */
  304. ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt);
  305. return 0;
  306. }
  307. static int ov2685_get_fmt(struct v4l2_subdev *sd,
  308. struct v4l2_subdev_state *sd_state,
  309. struct v4l2_subdev_format *fmt)
  310. {
  311. struct ov2685 *ov2685 = to_ov2685(sd);
  312. struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
  313. ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt);
  314. return 0;
  315. }
  316. static int ov2685_enum_mbus_code(struct v4l2_subdev *sd,
  317. struct v4l2_subdev_state *sd_state,
  318. struct v4l2_subdev_mbus_code_enum *code)
  319. {
  320. if (code->index >= ARRAY_SIZE(supported_modes))
  321. return -EINVAL;
  322. code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
  323. return 0;
  324. }
  325. static int ov2685_enum_frame_sizes(struct v4l2_subdev *sd,
  326. struct v4l2_subdev_state *sd_state,
  327. struct v4l2_subdev_frame_size_enum *fse)
  328. {
  329. int index = fse->index;
  330. if (index >= ARRAY_SIZE(supported_modes))
  331. return -EINVAL;
  332. fse->code = MEDIA_BUS_FMT_SBGGR10_1X10;
  333. fse->min_width = supported_modes[index].width;
  334. fse->max_width = supported_modes[index].width;
  335. fse->max_height = supported_modes[index].height;
  336. fse->min_height = supported_modes[index].height;
  337. return 0;
  338. }
  339. static const struct v4l2_rect *
  340. __ov2685_get_pad_crop(struct ov2685 *ov2685,
  341. struct v4l2_subdev_state *state, unsigned int pad,
  342. enum v4l2_subdev_format_whence which)
  343. {
  344. const struct ov2685_mode *mode = ov2685->cur_mode;
  345. switch (which) {
  346. case V4L2_SUBDEV_FORMAT_TRY:
  347. return v4l2_subdev_state_get_crop(state, pad);
  348. case V4L2_SUBDEV_FORMAT_ACTIVE:
  349. return mode->analog_crop;
  350. }
  351. return NULL;
  352. }
  353. static int ov2685_get_selection(struct v4l2_subdev *sd,
  354. struct v4l2_subdev_state *sd_state,
  355. struct v4l2_subdev_selection *sel)
  356. {
  357. struct ov2685 *ov2685 = to_ov2685(sd);
  358. switch (sel->target) {
  359. case V4L2_SEL_TGT_CROP:
  360. mutex_lock(&ov2685->mutex);
  361. sel->r = *__ov2685_get_pad_crop(ov2685, sd_state, sel->pad,
  362. sel->which);
  363. mutex_unlock(&ov2685->mutex);
  364. break;
  365. case V4L2_SEL_TGT_NATIVE_SIZE:
  366. case V4L2_SEL_TGT_CROP_BOUNDS:
  367. sel->r.top = 0;
  368. sel->r.left = 0;
  369. sel->r.width = OV2685_NATIVE_WIDTH;
  370. sel->r.height = OV2685_NATIVE_HEIGHT;
  371. break;
  372. case V4L2_SEL_TGT_CROP_DEFAULT:
  373. sel->r = ov2685_analog_crop;
  374. break;
  375. default:
  376. return -EINVAL;
  377. }
  378. return 0;
  379. }
  380. /* Calculate the delay in us by clock rate and clock cycles */
  381. static inline u32 ov2685_cal_delay(u32 cycles)
  382. {
  383. return DIV_ROUND_UP(cycles, OV2685_XVCLK_FREQ / 1000 / 1000);
  384. }
  385. static int __ov2685_power_on(struct ov2685 *ov2685)
  386. {
  387. int ret;
  388. u32 delay_us;
  389. struct device *dev = &ov2685->client->dev;
  390. ret = clk_prepare_enable(ov2685->xvclk);
  391. if (ret < 0) {
  392. dev_err(dev, "Failed to enable xvclk\n");
  393. return ret;
  394. }
  395. gpiod_set_value_cansleep(ov2685->reset_gpio, 1);
  396. ret = regulator_bulk_enable(OV2685_NUM_SUPPLIES, ov2685->supplies);
  397. if (ret < 0) {
  398. dev_err(dev, "Failed to enable regulators\n");
  399. goto disable_clk;
  400. }
  401. /* The minimum delay between power supplies and reset rising can be 0 */
  402. gpiod_set_value_cansleep(ov2685->reset_gpio, 0);
  403. /* 8192 xvclk cycles prior to the first SCCB transaction */
  404. delay_us = ov2685_cal_delay(8192);
  405. usleep_range(delay_us, delay_us * 2);
  406. /* HACK: ov2685 would output messy data after reset(R0103),
  407. * writing register before .s_stream() as a workaround
  408. */
  409. ret = ov2685_write_array(ov2685->client, ov2685->cur_mode->reg_list);
  410. if (ret) {
  411. dev_err(dev, "Failed to set regs for power on\n");
  412. goto disable_supplies;
  413. }
  414. return 0;
  415. disable_supplies:
  416. regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies);
  417. disable_clk:
  418. clk_disable_unprepare(ov2685->xvclk);
  419. return ret;
  420. }
  421. static void __ov2685_power_off(struct ov2685 *ov2685)
  422. {
  423. /* 512 xvclk cycles after the last SCCB transaction or MIPI frame end */
  424. u32 delay_us = ov2685_cal_delay(512);
  425. usleep_range(delay_us, delay_us * 2);
  426. clk_disable_unprepare(ov2685->xvclk);
  427. gpiod_set_value_cansleep(ov2685->reset_gpio, 1);
  428. regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies);
  429. }
  430. static int ov2685_s_stream(struct v4l2_subdev *sd, int on)
  431. {
  432. struct ov2685 *ov2685 = to_ov2685(sd);
  433. struct i2c_client *client = ov2685->client;
  434. int ret = 0;
  435. mutex_lock(&ov2685->mutex);
  436. if (on) {
  437. ret = pm_runtime_resume_and_get(&ov2685->client->dev);
  438. if (ret < 0)
  439. goto unlock_and_return;
  440. ret = __v4l2_ctrl_handler_setup(&ov2685->ctrl_handler);
  441. if (ret) {
  442. pm_runtime_put(&client->dev);
  443. goto unlock_and_return;
  444. }
  445. ret = ov2685_write_reg(client, REG_SC_CTRL_MODE,
  446. OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STREAMING);
  447. if (ret) {
  448. pm_runtime_put(&client->dev);
  449. goto unlock_and_return;
  450. }
  451. } else {
  452. ov2685_write_reg(client, REG_SC_CTRL_MODE,
  453. OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STANDBY);
  454. pm_runtime_put(&ov2685->client->dev);
  455. }
  456. unlock_and_return:
  457. mutex_unlock(&ov2685->mutex);
  458. return ret;
  459. }
  460. static int ov2685_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  461. {
  462. struct ov2685 *ov2685 = to_ov2685(sd);
  463. struct v4l2_mbus_framefmt *try_fmt;
  464. mutex_lock(&ov2685->mutex);
  465. try_fmt = v4l2_subdev_state_get_format(fh->state, 0);
  466. /* Initialize try_fmt */
  467. ov2685_fill_fmt(&supported_modes[0], try_fmt);
  468. mutex_unlock(&ov2685->mutex);
  469. return 0;
  470. }
  471. static int __maybe_unused ov2685_runtime_resume(struct device *dev)
  472. {
  473. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  474. struct ov2685 *ov2685 = to_ov2685(sd);
  475. return __ov2685_power_on(ov2685);
  476. }
  477. static int __maybe_unused ov2685_runtime_suspend(struct device *dev)
  478. {
  479. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  480. struct ov2685 *ov2685 = to_ov2685(sd);
  481. __ov2685_power_off(ov2685);
  482. return 0;
  483. }
  484. static const struct dev_pm_ops ov2685_pm_ops = {
  485. SET_RUNTIME_PM_OPS(ov2685_runtime_suspend,
  486. ov2685_runtime_resume, NULL)
  487. };
  488. static int ov2685_set_ctrl(struct v4l2_ctrl *ctrl)
  489. {
  490. struct ov2685 *ov2685 = container_of(ctrl->handler,
  491. struct ov2685, ctrl_handler);
  492. struct i2c_client *client = ov2685->client;
  493. s64 max_expo;
  494. int ret;
  495. /* Propagate change of current control to all related controls */
  496. switch (ctrl->id) {
  497. case V4L2_CID_VBLANK:
  498. /* Update max exposure while meeting expected vblanking */
  499. max_expo = ov2685->cur_mode->height + ctrl->val - 4;
  500. __v4l2_ctrl_modify_range(ov2685->exposure,
  501. ov2685->exposure->minimum, max_expo,
  502. ov2685->exposure->step,
  503. ov2685->exposure->default_value);
  504. break;
  505. }
  506. if (!pm_runtime_get_if_in_use(&client->dev))
  507. return 0;
  508. switch (ctrl->id) {
  509. case V4L2_CID_EXPOSURE:
  510. ret = ov2685_write_reg(ov2685->client, OV2685_REG_EXPOSURE,
  511. OV2685_REG_VALUE_24BIT, ctrl->val << 4);
  512. break;
  513. case V4L2_CID_ANALOGUE_GAIN:
  514. ret = ov2685_write_reg(ov2685->client, OV2685_REG_GAIN,
  515. OV2685_REG_VALUE_16BIT, ctrl->val);
  516. break;
  517. case V4L2_CID_VBLANK:
  518. ret = ov2685_write_reg(ov2685->client, OV2685_REG_VTS,
  519. OV2685_REG_VALUE_16BIT,
  520. ctrl->val + ov2685->cur_mode->height);
  521. break;
  522. case V4L2_CID_TEST_PATTERN:
  523. ret = ov2685_write_reg(ov2685->client, OV2685_REG_TEST_PATTERN,
  524. OV2685_REG_VALUE_08BIT,
  525. ov2685_test_pattern_val[ctrl->val]);
  526. break;
  527. default:
  528. dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
  529. __func__, ctrl->id, ctrl->val);
  530. ret = -EINVAL;
  531. break;
  532. }
  533. pm_runtime_put(&client->dev);
  534. return ret;
  535. }
  536. static const struct v4l2_subdev_video_ops ov2685_video_ops = {
  537. .s_stream = ov2685_s_stream,
  538. };
  539. static const struct v4l2_subdev_pad_ops ov2685_pad_ops = {
  540. .enum_mbus_code = ov2685_enum_mbus_code,
  541. .enum_frame_size = ov2685_enum_frame_sizes,
  542. .get_fmt = ov2685_get_fmt,
  543. .set_fmt = ov2685_set_fmt,
  544. .get_selection = ov2685_get_selection,
  545. .set_selection = ov2685_get_selection,
  546. };
  547. static const struct v4l2_subdev_ops ov2685_subdev_ops = {
  548. .video = &ov2685_video_ops,
  549. .pad = &ov2685_pad_ops,
  550. };
  551. static const struct v4l2_subdev_internal_ops ov2685_internal_ops = {
  552. .open = ov2685_open,
  553. };
  554. static const struct v4l2_ctrl_ops ov2685_ctrl_ops = {
  555. .s_ctrl = ov2685_set_ctrl,
  556. };
  557. static int ov2685_initialize_controls(struct ov2685 *ov2685)
  558. {
  559. const struct ov2685_mode *mode;
  560. struct v4l2_ctrl_handler *handler;
  561. struct v4l2_ctrl *ctrl;
  562. struct v4l2_fwnode_device_properties props;
  563. u64 exposure_max;
  564. u32 pixel_rate, h_blank;
  565. int ret;
  566. handler = &ov2685->ctrl_handler;
  567. mode = ov2685->cur_mode;
  568. ret = v4l2_ctrl_handler_init(handler, 10);
  569. if (ret)
  570. return ret;
  571. handler->lock = &ov2685->mutex;
  572. ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
  573. 0, 0, link_freq_menu_items);
  574. if (ctrl)
  575. ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  576. pixel_rate = (link_freq_menu_items[0] * 2 * OV2685_LANES) /
  577. OV2685_BITS_PER_SAMPLE;
  578. v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
  579. 0, pixel_rate, 1, pixel_rate);
  580. h_blank = mode->hts_def - mode->width;
  581. ov2685->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
  582. h_blank, h_blank, 1, h_blank);
  583. if (ov2685->hblank)
  584. ov2685->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  585. ov2685->vblank = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
  586. V4L2_CID_VBLANK, mode->vts_def - mode->height,
  587. OV2685_VTS_MAX - mode->height, 1,
  588. mode->vts_def - mode->height);
  589. exposure_max = mode->vts_def - 4;
  590. ov2685->exposure = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
  591. V4L2_CID_EXPOSURE, OV2685_EXPOSURE_MIN,
  592. exposure_max, OV2685_EXPOSURE_STEP,
  593. mode->exp_def);
  594. ov2685->anal_gain = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
  595. V4L2_CID_ANALOGUE_GAIN, OV2685_GAIN_MIN,
  596. OV2685_GAIN_MAX, OV2685_GAIN_STEP,
  597. OV2685_GAIN_DEFAULT);
  598. ov2685->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
  599. &ov2685_ctrl_ops, V4L2_CID_TEST_PATTERN,
  600. ARRAY_SIZE(ov2685_test_pattern_menu) - 1,
  601. 0, 0, ov2685_test_pattern_menu);
  602. /* set properties from fwnode (e.g. rotation, orientation) */
  603. ret = v4l2_fwnode_device_parse(&ov2685->client->dev, &props);
  604. if (ret)
  605. goto err_free_handler;
  606. ret = v4l2_ctrl_new_fwnode_properties(handler, &ov2685_ctrl_ops, &props);
  607. if (ret)
  608. goto err_free_handler;
  609. if (handler->error) {
  610. ret = handler->error;
  611. dev_err(&ov2685->client->dev,
  612. "Failed to init controls(%d)\n", ret);
  613. goto err_free_handler;
  614. }
  615. ov2685->subdev.ctrl_handler = handler;
  616. return 0;
  617. err_free_handler:
  618. v4l2_ctrl_handler_free(handler);
  619. return ret;
  620. }
  621. static int ov2685_check_sensor_id(struct ov2685 *ov2685,
  622. struct i2c_client *client)
  623. {
  624. struct device *dev = &ov2685->client->dev;
  625. int ret;
  626. u32 id = 0;
  627. ret = ov2685_read_reg(client, OV2685_REG_CHIP_ID,
  628. OV2685_REG_VALUE_16BIT, &id);
  629. if (id != CHIP_ID) {
  630. dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
  631. return ret;
  632. }
  633. dev_info(dev, "Detected OV%04x sensor\n", CHIP_ID);
  634. return 0;
  635. }
  636. static int ov2685_configure_regulators(struct ov2685 *ov2685)
  637. {
  638. int i;
  639. for (i = 0; i < OV2685_NUM_SUPPLIES; i++)
  640. ov2685->supplies[i].supply = ov2685_supply_names[i];
  641. return devm_regulator_bulk_get(&ov2685->client->dev,
  642. OV2685_NUM_SUPPLIES,
  643. ov2685->supplies);
  644. }
  645. static int ov2685_probe(struct i2c_client *client)
  646. {
  647. struct device *dev = &client->dev;
  648. struct ov2685 *ov2685;
  649. int ret;
  650. ov2685 = devm_kzalloc(dev, sizeof(*ov2685), GFP_KERNEL);
  651. if (!ov2685)
  652. return -ENOMEM;
  653. ov2685->client = client;
  654. ov2685->cur_mode = &supported_modes[0];
  655. ov2685->xvclk = devm_v4l2_sensor_clk_get_legacy(dev, "xvclk", true,
  656. OV2685_XVCLK_FREQ);
  657. if (IS_ERR(ov2685->xvclk))
  658. return dev_err_probe(dev, PTR_ERR(ov2685->xvclk),
  659. "Failed to get xvclk\n");
  660. if (clk_get_rate(ov2685->xvclk) != OV2685_XVCLK_FREQ)
  661. dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
  662. ov2685->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
  663. if (IS_ERR(ov2685->reset_gpio)) {
  664. dev_err(dev, "Failed to get reset-gpios\n");
  665. return -EINVAL;
  666. }
  667. ret = ov2685_configure_regulators(ov2685);
  668. if (ret) {
  669. dev_err(dev, "Failed to get power regulators\n");
  670. return ret;
  671. }
  672. mutex_init(&ov2685->mutex);
  673. v4l2_i2c_subdev_init(&ov2685->subdev, client, &ov2685_subdev_ops);
  674. ret = ov2685_initialize_controls(ov2685);
  675. if (ret)
  676. goto err_destroy_mutex;
  677. ret = __ov2685_power_on(ov2685);
  678. if (ret)
  679. goto err_free_handler;
  680. ret = ov2685_check_sensor_id(ov2685, client);
  681. if (ret)
  682. goto err_power_off;
  683. ov2685->subdev.internal_ops = &ov2685_internal_ops;
  684. ov2685->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  685. ov2685->pad.flags = MEDIA_PAD_FL_SOURCE;
  686. ov2685->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  687. ret = media_entity_pads_init(&ov2685->subdev.entity, 1, &ov2685->pad);
  688. if (ret < 0)
  689. goto err_power_off;
  690. ret = v4l2_async_register_subdev(&ov2685->subdev);
  691. if (ret) {
  692. dev_err(dev, "v4l2 async register subdev failed\n");
  693. goto err_clean_entity;
  694. }
  695. pm_runtime_set_active(dev);
  696. pm_runtime_enable(dev);
  697. pm_runtime_idle(dev);
  698. return 0;
  699. err_clean_entity:
  700. media_entity_cleanup(&ov2685->subdev.entity);
  701. err_power_off:
  702. __ov2685_power_off(ov2685);
  703. err_free_handler:
  704. v4l2_ctrl_handler_free(&ov2685->ctrl_handler);
  705. err_destroy_mutex:
  706. mutex_destroy(&ov2685->mutex);
  707. return ret;
  708. }
  709. static void ov2685_remove(struct i2c_client *client)
  710. {
  711. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  712. struct ov2685 *ov2685 = to_ov2685(sd);
  713. v4l2_async_unregister_subdev(sd);
  714. media_entity_cleanup(&sd->entity);
  715. v4l2_ctrl_handler_free(&ov2685->ctrl_handler);
  716. mutex_destroy(&ov2685->mutex);
  717. pm_runtime_disable(&client->dev);
  718. if (!pm_runtime_status_suspended(&client->dev))
  719. __ov2685_power_off(ov2685);
  720. pm_runtime_set_suspended(&client->dev);
  721. }
  722. #if IS_ENABLED(CONFIG_OF)
  723. static const struct of_device_id ov2685_of_match[] = {
  724. { .compatible = "ovti,ov2685" },
  725. {},
  726. };
  727. MODULE_DEVICE_TABLE(of, ov2685_of_match);
  728. #endif
  729. static struct i2c_driver ov2685_i2c_driver = {
  730. .driver = {
  731. .name = "ov2685",
  732. .pm = &ov2685_pm_ops,
  733. .of_match_table = of_match_ptr(ov2685_of_match),
  734. },
  735. .probe = ov2685_probe,
  736. .remove = ov2685_remove,
  737. };
  738. module_i2c_driver(ov2685_i2c_driver);
  739. MODULE_DESCRIPTION("OmniVision ov2685 sensor driver");
  740. MODULE_LICENSE("GPL v2");