imx208.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2021 Intel Corporation
  3. #include <linux/acpi.h>
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/i2c.h>
  7. #include <linux/module.h>
  8. #include <linux/pm_runtime.h>
  9. #include <linux/unaligned.h>
  10. #include <media/v4l2-ctrls.h>
  11. #include <media/v4l2-device.h>
  12. #define IMX208_REG_MODE_SELECT 0x0100
  13. #define IMX208_MODE_STANDBY 0x00
  14. #define IMX208_MODE_STREAMING 0x01
  15. /* Chip ID */
  16. #define IMX208_REG_CHIP_ID 0x0000
  17. #define IMX208_CHIP_ID 0x0208
  18. /* V_TIMING internal */
  19. #define IMX208_REG_VTS 0x0340
  20. #define IMX208_VTS_60FPS 0x0472
  21. #define IMX208_VTS_BINNING 0x0239
  22. #define IMX208_VTS_60FPS_MIN 0x0458
  23. #define IMX208_VTS_BINNING_MIN 0x0230
  24. #define IMX208_VTS_MAX 0xffff
  25. /* HBLANK control - read only */
  26. #define IMX208_PPL_384MHZ 2248
  27. #define IMX208_PPL_96MHZ 2248
  28. /* Exposure control */
  29. #define IMX208_REG_EXPOSURE 0x0202
  30. #define IMX208_EXPOSURE_MIN 4
  31. #define IMX208_EXPOSURE_STEP 1
  32. #define IMX208_EXPOSURE_DEFAULT 0x190
  33. #define IMX208_EXPOSURE_MAX 65535
  34. /* Analog gain control */
  35. #define IMX208_REG_ANALOG_GAIN 0x0204
  36. #define IMX208_ANA_GAIN_MIN 0
  37. #define IMX208_ANA_GAIN_MAX 0x00e0
  38. #define IMX208_ANA_GAIN_STEP 1
  39. #define IMX208_ANA_GAIN_DEFAULT 0x0
  40. /* Digital gain control */
  41. #define IMX208_REG_GR_DIGITAL_GAIN 0x020e
  42. #define IMX208_REG_R_DIGITAL_GAIN 0x0210
  43. #define IMX208_REG_B_DIGITAL_GAIN 0x0212
  44. #define IMX208_REG_GB_DIGITAL_GAIN 0x0214
  45. #define IMX208_DIGITAL_GAIN_SHIFT 8
  46. /* Orientation */
  47. #define IMX208_REG_ORIENTATION_CONTROL 0x0101
  48. /* Test Pattern Control */
  49. #define IMX208_REG_TEST_PATTERN_MODE 0x0600
  50. #define IMX208_TEST_PATTERN_DISABLE 0x0
  51. #define IMX208_TEST_PATTERN_SOLID_COLOR 0x1
  52. #define IMX208_TEST_PATTERN_COLOR_BARS 0x2
  53. #define IMX208_TEST_PATTERN_GREY_COLOR 0x3
  54. #define IMX208_TEST_PATTERN_PN9 0x4
  55. #define IMX208_TEST_PATTERN_FIX_1 0x100
  56. #define IMX208_TEST_PATTERN_FIX_2 0x101
  57. #define IMX208_TEST_PATTERN_FIX_3 0x102
  58. #define IMX208_TEST_PATTERN_FIX_4 0x103
  59. #define IMX208_TEST_PATTERN_FIX_5 0x104
  60. #define IMX208_TEST_PATTERN_FIX_6 0x105
  61. /* OTP Access */
  62. #define IMX208_OTP_BASE 0x3500
  63. #define IMX208_OTP_SIZE 40
  64. struct imx208_reg {
  65. u16 address;
  66. u8 val;
  67. };
  68. struct imx208_reg_list {
  69. u32 num_of_regs;
  70. const struct imx208_reg *regs;
  71. };
  72. /* Link frequency config */
  73. struct imx208_link_freq_config {
  74. u32 pixels_per_line;
  75. /* PLL registers for this link frequency */
  76. struct imx208_reg_list reg_list;
  77. };
  78. /* Mode : resolution and related config&values */
  79. struct imx208_mode {
  80. /* Frame width */
  81. u32 width;
  82. /* Frame height */
  83. u32 height;
  84. /* V-timing */
  85. u32 vts_def;
  86. u32 vts_min;
  87. /* Index of Link frequency config to be used */
  88. u32 link_freq_index;
  89. /* Default register values */
  90. struct imx208_reg_list reg_list;
  91. };
  92. static const struct imx208_reg pll_ctrl_reg[] = {
  93. {0x0305, 0x02},
  94. {0x0307, 0x50},
  95. {0x303C, 0x3C},
  96. };
  97. static const struct imx208_reg mode_1936x1096_60fps_regs[] = {
  98. {0x0340, 0x04},
  99. {0x0341, 0x72},
  100. {0x0342, 0x04},
  101. {0x0343, 0x64},
  102. {0x034C, 0x07},
  103. {0x034D, 0x90},
  104. {0x034E, 0x04},
  105. {0x034F, 0x48},
  106. {0x0381, 0x01},
  107. {0x0383, 0x01},
  108. {0x0385, 0x01},
  109. {0x0387, 0x01},
  110. {0x3048, 0x00},
  111. {0x3050, 0x01},
  112. {0x30D5, 0x00},
  113. {0x3301, 0x00},
  114. {0x3318, 0x62},
  115. {0x0202, 0x01},
  116. {0x0203, 0x90},
  117. {0x0205, 0x00},
  118. };
  119. static const struct imx208_reg mode_968_548_60fps_regs[] = {
  120. {0x0340, 0x02},
  121. {0x0341, 0x39},
  122. {0x0342, 0x08},
  123. {0x0343, 0xC8},
  124. {0x034C, 0x03},
  125. {0x034D, 0xC8},
  126. {0x034E, 0x02},
  127. {0x034F, 0x24},
  128. {0x0381, 0x01},
  129. {0x0383, 0x03},
  130. {0x0385, 0x01},
  131. {0x0387, 0x03},
  132. {0x3048, 0x01},
  133. {0x3050, 0x02},
  134. {0x30D5, 0x03},
  135. {0x3301, 0x10},
  136. {0x3318, 0x75},
  137. {0x0202, 0x01},
  138. {0x0203, 0x90},
  139. {0x0205, 0x00},
  140. };
  141. static const s64 imx208_discrete_digital_gain[] = {
  142. 1, 2, 4, 8, 16,
  143. };
  144. static const char * const imx208_test_pattern_menu[] = {
  145. "Disabled",
  146. "Solid Color",
  147. "100% Color Bar",
  148. "Fade to Grey Color Bar",
  149. "PN9",
  150. "Fixed Pattern1",
  151. "Fixed Pattern2",
  152. "Fixed Pattern3",
  153. "Fixed Pattern4",
  154. "Fixed Pattern5",
  155. "Fixed Pattern6"
  156. };
  157. static const int imx208_test_pattern_val[] = {
  158. IMX208_TEST_PATTERN_DISABLE,
  159. IMX208_TEST_PATTERN_SOLID_COLOR,
  160. IMX208_TEST_PATTERN_COLOR_BARS,
  161. IMX208_TEST_PATTERN_GREY_COLOR,
  162. IMX208_TEST_PATTERN_PN9,
  163. IMX208_TEST_PATTERN_FIX_1,
  164. IMX208_TEST_PATTERN_FIX_2,
  165. IMX208_TEST_PATTERN_FIX_3,
  166. IMX208_TEST_PATTERN_FIX_4,
  167. IMX208_TEST_PATTERN_FIX_5,
  168. IMX208_TEST_PATTERN_FIX_6,
  169. };
  170. /* Configurations for supported link frequencies */
  171. #define IMX208_MHZ (1000 * 1000ULL)
  172. #define IMX208_LINK_FREQ_384MHZ (384ULL * IMX208_MHZ)
  173. #define IMX208_LINK_FREQ_96MHZ (96ULL * IMX208_MHZ)
  174. #define IMX208_DATA_RATE_DOUBLE 2
  175. #define IMX208_NUM_OF_LANES 2
  176. #define IMX208_PIXEL_BITS 10
  177. enum {
  178. IMX208_LINK_FREQ_384MHZ_INDEX,
  179. IMX208_LINK_FREQ_96MHZ_INDEX,
  180. };
  181. /*
  182. * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
  183. * data rate => double data rate; number of lanes => 2; bits per pixel => 10
  184. */
  185. static u64 link_freq_to_pixel_rate(u64 f)
  186. {
  187. f *= IMX208_DATA_RATE_DOUBLE * IMX208_NUM_OF_LANES;
  188. do_div(f, IMX208_PIXEL_BITS);
  189. return f;
  190. }
  191. /* Menu items for LINK_FREQ V4L2 control */
  192. static const s64 link_freq_menu_items[] = {
  193. [IMX208_LINK_FREQ_384MHZ_INDEX] = IMX208_LINK_FREQ_384MHZ,
  194. [IMX208_LINK_FREQ_96MHZ_INDEX] = IMX208_LINK_FREQ_96MHZ,
  195. };
  196. /* Link frequency configs */
  197. static const struct imx208_link_freq_config link_freq_configs[] = {
  198. [IMX208_LINK_FREQ_384MHZ_INDEX] = {
  199. .pixels_per_line = IMX208_PPL_384MHZ,
  200. .reg_list = {
  201. .num_of_regs = ARRAY_SIZE(pll_ctrl_reg),
  202. .regs = pll_ctrl_reg,
  203. }
  204. },
  205. [IMX208_LINK_FREQ_96MHZ_INDEX] = {
  206. .pixels_per_line = IMX208_PPL_96MHZ,
  207. .reg_list = {
  208. .num_of_regs = ARRAY_SIZE(pll_ctrl_reg),
  209. .regs = pll_ctrl_reg,
  210. }
  211. },
  212. };
  213. /* Mode configs */
  214. static const struct imx208_mode supported_modes[] = {
  215. {
  216. .width = 1936,
  217. .height = 1096,
  218. .vts_def = IMX208_VTS_60FPS,
  219. .vts_min = IMX208_VTS_60FPS_MIN,
  220. .reg_list = {
  221. .num_of_regs = ARRAY_SIZE(mode_1936x1096_60fps_regs),
  222. .regs = mode_1936x1096_60fps_regs,
  223. },
  224. .link_freq_index = IMX208_LINK_FREQ_384MHZ_INDEX,
  225. },
  226. {
  227. .width = 968,
  228. .height = 548,
  229. .vts_def = IMX208_VTS_BINNING,
  230. .vts_min = IMX208_VTS_BINNING_MIN,
  231. .reg_list = {
  232. .num_of_regs = ARRAY_SIZE(mode_968_548_60fps_regs),
  233. .regs = mode_968_548_60fps_regs,
  234. },
  235. .link_freq_index = IMX208_LINK_FREQ_96MHZ_INDEX,
  236. },
  237. };
  238. struct imx208 {
  239. struct device *dev;
  240. struct clk *clk;
  241. struct v4l2_subdev sd;
  242. struct media_pad pad;
  243. struct v4l2_ctrl_handler ctrl_handler;
  244. /* V4L2 Controls */
  245. struct v4l2_ctrl *link_freq;
  246. struct v4l2_ctrl *pixel_rate;
  247. struct v4l2_ctrl *vblank;
  248. struct v4l2_ctrl *hblank;
  249. struct v4l2_ctrl *vflip;
  250. struct v4l2_ctrl *hflip;
  251. /* Current mode */
  252. const struct imx208_mode *cur_mode;
  253. /*
  254. * Mutex for serialized access:
  255. * Protect sensor set pad format and start/stop streaming safely.
  256. * Protect access to sensor v4l2 controls.
  257. */
  258. struct mutex imx208_mx;
  259. /* OTP data */
  260. bool otp_read;
  261. char otp_data[IMX208_OTP_SIZE];
  262. /* True if the device has been identified */
  263. bool identified;
  264. };
  265. static inline struct imx208 *to_imx208(struct v4l2_subdev *_sd)
  266. {
  267. return container_of(_sd, struct imx208, sd);
  268. }
  269. /* Get bayer order based on flip setting. */
  270. static u32 imx208_get_format_code(struct imx208 *imx208)
  271. {
  272. /*
  273. * Only one bayer order is supported.
  274. * It depends on the flip settings.
  275. */
  276. static const u32 codes[2][2] = {
  277. { MEDIA_BUS_FMT_SRGGB10_1X10, MEDIA_BUS_FMT_SGRBG10_1X10, },
  278. { MEDIA_BUS_FMT_SGBRG10_1X10, MEDIA_BUS_FMT_SBGGR10_1X10, },
  279. };
  280. return codes[imx208->vflip->val][imx208->hflip->val];
  281. }
  282. /* Read registers up to 4 at a time */
  283. static int imx208_read_reg(struct imx208 *imx208, u16 reg, u32 len, u32 *val)
  284. {
  285. struct i2c_client *client = v4l2_get_subdevdata(&imx208->sd);
  286. struct i2c_msg msgs[2];
  287. u8 addr_buf[2] = { reg >> 8, reg & 0xff };
  288. u8 data_buf[4] = { 0, };
  289. int ret;
  290. if (len > 4)
  291. return -EINVAL;
  292. /* Write register address */
  293. msgs[0].addr = client->addr;
  294. msgs[0].flags = 0;
  295. msgs[0].len = ARRAY_SIZE(addr_buf);
  296. msgs[0].buf = addr_buf;
  297. /* Read data from register */
  298. msgs[1].addr = client->addr;
  299. msgs[1].flags = I2C_M_RD;
  300. msgs[1].len = len;
  301. msgs[1].buf = &data_buf[4 - len];
  302. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  303. if (ret != ARRAY_SIZE(msgs))
  304. return -EIO;
  305. *val = get_unaligned_be32(data_buf);
  306. return 0;
  307. }
  308. /* Write registers up to 4 at a time */
  309. static int imx208_write_reg(struct imx208 *imx208, u16 reg, u32 len, u32 val)
  310. {
  311. struct i2c_client *client = v4l2_get_subdevdata(&imx208->sd);
  312. u8 buf[6];
  313. if (len > 4)
  314. return -EINVAL;
  315. put_unaligned_be16(reg, buf);
  316. put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
  317. if (i2c_master_send(client, buf, len + 2) != len + 2)
  318. return -EIO;
  319. return 0;
  320. }
  321. /* Write a list of registers */
  322. static int imx208_write_regs(struct imx208 *imx208,
  323. const struct imx208_reg *regs, u32 len)
  324. {
  325. unsigned int i;
  326. int ret;
  327. for (i = 0; i < len; i++) {
  328. ret = imx208_write_reg(imx208, regs[i].address, 1,
  329. regs[i].val);
  330. if (ret) {
  331. dev_err_ratelimited(imx208->dev,
  332. "Failed to write reg 0x%4.4x. error = %d\n",
  333. regs[i].address, ret);
  334. return ret;
  335. }
  336. }
  337. return 0;
  338. }
  339. /* Open sub-device */
  340. static int imx208_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  341. {
  342. struct v4l2_mbus_framefmt *try_fmt =
  343. v4l2_subdev_state_get_format(fh->state, 0);
  344. /* Initialize try_fmt */
  345. try_fmt->width = supported_modes[0].width;
  346. try_fmt->height = supported_modes[0].height;
  347. try_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
  348. try_fmt->field = V4L2_FIELD_NONE;
  349. return 0;
  350. }
  351. static int imx208_update_digital_gain(struct imx208 *imx208, u32 len, u32 val)
  352. {
  353. int ret;
  354. val = imx208_discrete_digital_gain[val] << IMX208_DIGITAL_GAIN_SHIFT;
  355. ret = imx208_write_reg(imx208, IMX208_REG_GR_DIGITAL_GAIN, 2, val);
  356. if (ret)
  357. return ret;
  358. ret = imx208_write_reg(imx208, IMX208_REG_GB_DIGITAL_GAIN, 2, val);
  359. if (ret)
  360. return ret;
  361. ret = imx208_write_reg(imx208, IMX208_REG_R_DIGITAL_GAIN, 2, val);
  362. if (ret)
  363. return ret;
  364. return imx208_write_reg(imx208, IMX208_REG_B_DIGITAL_GAIN, 2, val);
  365. }
  366. static int imx208_set_ctrl(struct v4l2_ctrl *ctrl)
  367. {
  368. struct imx208 *imx208 =
  369. container_of(ctrl->handler, struct imx208, ctrl_handler);
  370. int ret;
  371. /*
  372. * Applying V4L2 control value only happens
  373. * when power is up for streaming
  374. */
  375. if (!pm_runtime_get_if_in_use(imx208->dev))
  376. return 0;
  377. switch (ctrl->id) {
  378. case V4L2_CID_ANALOGUE_GAIN:
  379. ret = imx208_write_reg(imx208, IMX208_REG_ANALOG_GAIN,
  380. 2, ctrl->val);
  381. break;
  382. case V4L2_CID_EXPOSURE:
  383. ret = imx208_write_reg(imx208, IMX208_REG_EXPOSURE,
  384. 2, ctrl->val);
  385. break;
  386. case V4L2_CID_DIGITAL_GAIN:
  387. ret = imx208_update_digital_gain(imx208, 2, ctrl->val);
  388. break;
  389. case V4L2_CID_VBLANK:
  390. /* Update VTS that meets expected vertical blanking */
  391. ret = imx208_write_reg(imx208, IMX208_REG_VTS, 2,
  392. imx208->cur_mode->height + ctrl->val);
  393. break;
  394. case V4L2_CID_TEST_PATTERN:
  395. ret = imx208_write_reg(imx208, IMX208_REG_TEST_PATTERN_MODE,
  396. 2, imx208_test_pattern_val[ctrl->val]);
  397. break;
  398. case V4L2_CID_HFLIP:
  399. case V4L2_CID_VFLIP:
  400. ret = imx208_write_reg(imx208, IMX208_REG_ORIENTATION_CONTROL,
  401. 1,
  402. imx208->hflip->val |
  403. imx208->vflip->val << 1);
  404. break;
  405. default:
  406. ret = -EINVAL;
  407. dev_err(imx208->dev,
  408. "ctrl(id:0x%x,val:0x%x) is not handled\n",
  409. ctrl->id, ctrl->val);
  410. break;
  411. }
  412. pm_runtime_put(imx208->dev);
  413. return ret;
  414. }
  415. static const struct v4l2_ctrl_ops imx208_ctrl_ops = {
  416. .s_ctrl = imx208_set_ctrl,
  417. };
  418. static const struct v4l2_ctrl_config imx208_digital_gain_control = {
  419. .ops = &imx208_ctrl_ops,
  420. .id = V4L2_CID_DIGITAL_GAIN,
  421. .name = "Digital Gain",
  422. .type = V4L2_CTRL_TYPE_INTEGER_MENU,
  423. .min = 0,
  424. .max = ARRAY_SIZE(imx208_discrete_digital_gain) - 1,
  425. .step = 0,
  426. .def = 0,
  427. .menu_skip_mask = 0,
  428. .qmenu_int = imx208_discrete_digital_gain,
  429. };
  430. static int imx208_enum_mbus_code(struct v4l2_subdev *sd,
  431. struct v4l2_subdev_state *sd_state,
  432. struct v4l2_subdev_mbus_code_enum *code)
  433. {
  434. struct imx208 *imx208 = to_imx208(sd);
  435. if (code->index > 0)
  436. return -EINVAL;
  437. code->code = imx208_get_format_code(imx208);
  438. return 0;
  439. }
  440. static int imx208_enum_frame_size(struct v4l2_subdev *sd,
  441. struct v4l2_subdev_state *sd_state,
  442. struct v4l2_subdev_frame_size_enum *fse)
  443. {
  444. struct imx208 *imx208 = to_imx208(sd);
  445. if (fse->index >= ARRAY_SIZE(supported_modes))
  446. return -EINVAL;
  447. if (fse->code != imx208_get_format_code(imx208))
  448. return -EINVAL;
  449. fse->min_width = supported_modes[fse->index].width;
  450. fse->max_width = fse->min_width;
  451. fse->min_height = supported_modes[fse->index].height;
  452. fse->max_height = fse->min_height;
  453. return 0;
  454. }
  455. static void imx208_mode_to_pad_format(struct imx208 *imx208,
  456. const struct imx208_mode *mode,
  457. struct v4l2_subdev_format *fmt)
  458. {
  459. fmt->format.width = mode->width;
  460. fmt->format.height = mode->height;
  461. fmt->format.code = imx208_get_format_code(imx208);
  462. fmt->format.field = V4L2_FIELD_NONE;
  463. }
  464. static int __imx208_get_pad_format(struct imx208 *imx208,
  465. struct v4l2_subdev_state *sd_state,
  466. struct v4l2_subdev_format *fmt)
  467. {
  468. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
  469. fmt->format = *v4l2_subdev_state_get_format(sd_state,
  470. fmt->pad);
  471. else
  472. imx208_mode_to_pad_format(imx208, imx208->cur_mode, fmt);
  473. return 0;
  474. }
  475. static int imx208_get_pad_format(struct v4l2_subdev *sd,
  476. struct v4l2_subdev_state *sd_state,
  477. struct v4l2_subdev_format *fmt)
  478. {
  479. struct imx208 *imx208 = to_imx208(sd);
  480. int ret;
  481. mutex_lock(&imx208->imx208_mx);
  482. ret = __imx208_get_pad_format(imx208, sd_state, fmt);
  483. mutex_unlock(&imx208->imx208_mx);
  484. return ret;
  485. }
  486. static int imx208_set_pad_format(struct v4l2_subdev *sd,
  487. struct v4l2_subdev_state *sd_state,
  488. struct v4l2_subdev_format *fmt)
  489. {
  490. struct imx208 *imx208 = to_imx208(sd);
  491. const struct imx208_mode *mode;
  492. s32 vblank_def;
  493. s32 vblank_min;
  494. s64 h_blank;
  495. s64 pixel_rate;
  496. s64 link_freq;
  497. mutex_lock(&imx208->imx208_mx);
  498. fmt->format.code = imx208_get_format_code(imx208);
  499. mode = v4l2_find_nearest_size(supported_modes,
  500. ARRAY_SIZE(supported_modes), width, height,
  501. fmt->format.width, fmt->format.height);
  502. imx208_mode_to_pad_format(imx208, mode, fmt);
  503. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  504. *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
  505. } else {
  506. imx208->cur_mode = mode;
  507. __v4l2_ctrl_s_ctrl(imx208->link_freq, mode->link_freq_index);
  508. link_freq = link_freq_menu_items[mode->link_freq_index];
  509. pixel_rate = link_freq_to_pixel_rate(link_freq);
  510. __v4l2_ctrl_s_ctrl_int64(imx208->pixel_rate, pixel_rate);
  511. /* Update limits and set FPS to default */
  512. vblank_def = imx208->cur_mode->vts_def -
  513. imx208->cur_mode->height;
  514. vblank_min = imx208->cur_mode->vts_min -
  515. imx208->cur_mode->height;
  516. __v4l2_ctrl_modify_range(imx208->vblank, vblank_min,
  517. IMX208_VTS_MAX - imx208->cur_mode->height,
  518. 1, vblank_def);
  519. __v4l2_ctrl_s_ctrl(imx208->vblank, vblank_def);
  520. h_blank =
  521. link_freq_configs[mode->link_freq_index].pixels_per_line
  522. - imx208->cur_mode->width;
  523. __v4l2_ctrl_modify_range(imx208->hblank, h_blank,
  524. h_blank, 1, h_blank);
  525. }
  526. mutex_unlock(&imx208->imx208_mx);
  527. return 0;
  528. }
  529. static int imx208_identify_module(struct imx208 *imx208)
  530. {
  531. int ret;
  532. u32 val;
  533. if (imx208->identified)
  534. return 0;
  535. ret = imx208_read_reg(imx208, IMX208_REG_CHIP_ID,
  536. 2, &val);
  537. if (ret) {
  538. dev_err(imx208->dev, "failed to read chip id %x\n",
  539. IMX208_CHIP_ID);
  540. return ret;
  541. }
  542. if (val != IMX208_CHIP_ID) {
  543. dev_err(imx208->dev, "chip id mismatch: %x!=%x\n",
  544. IMX208_CHIP_ID, val);
  545. return -EIO;
  546. }
  547. imx208->identified = true;
  548. return 0;
  549. }
  550. /* Start streaming */
  551. static int imx208_start_streaming(struct imx208 *imx208)
  552. {
  553. const struct imx208_reg_list *reg_list;
  554. int ret, link_freq_index;
  555. ret = imx208_identify_module(imx208);
  556. if (ret)
  557. return ret;
  558. /* Setup PLL */
  559. link_freq_index = imx208->cur_mode->link_freq_index;
  560. reg_list = &link_freq_configs[link_freq_index].reg_list;
  561. ret = imx208_write_regs(imx208, reg_list->regs, reg_list->num_of_regs);
  562. if (ret) {
  563. dev_err(imx208->dev, "%s failed to set plls\n", __func__);
  564. return ret;
  565. }
  566. /* Apply default values of current mode */
  567. reg_list = &imx208->cur_mode->reg_list;
  568. ret = imx208_write_regs(imx208, reg_list->regs, reg_list->num_of_regs);
  569. if (ret) {
  570. dev_err(imx208->dev, "%s failed to set mode\n", __func__);
  571. return ret;
  572. }
  573. /* Apply customized values from user */
  574. ret = __v4l2_ctrl_handler_setup(imx208->sd.ctrl_handler);
  575. if (ret)
  576. return ret;
  577. /* set stream on register */
  578. return imx208_write_reg(imx208, IMX208_REG_MODE_SELECT,
  579. 1, IMX208_MODE_STREAMING);
  580. }
  581. /* Stop streaming */
  582. static int imx208_stop_streaming(struct imx208 *imx208)
  583. {
  584. int ret;
  585. /* set stream off register */
  586. ret = imx208_write_reg(imx208, IMX208_REG_MODE_SELECT,
  587. 1, IMX208_MODE_STANDBY);
  588. if (ret)
  589. dev_err(imx208->dev, "%s failed to set stream\n", __func__);
  590. /*
  591. * Return success even if it was an error, as there is nothing the
  592. * caller can do about it.
  593. */
  594. return 0;
  595. }
  596. static int imx208_set_stream(struct v4l2_subdev *sd, int enable)
  597. {
  598. struct imx208 *imx208 = to_imx208(sd);
  599. int ret = 0;
  600. mutex_lock(&imx208->imx208_mx);
  601. if (enable) {
  602. ret = pm_runtime_resume_and_get(imx208->dev);
  603. if (ret) {
  604. mutex_unlock(&imx208->imx208_mx);
  605. return ret;
  606. }
  607. /*
  608. * Apply default & customized values
  609. * and then start streaming.
  610. */
  611. ret = imx208_start_streaming(imx208);
  612. if (ret)
  613. goto err_rpm_put;
  614. } else {
  615. imx208_stop_streaming(imx208);
  616. pm_runtime_put(imx208->dev);
  617. }
  618. mutex_unlock(&imx208->imx208_mx);
  619. /* vflip and hflip cannot change during streaming */
  620. v4l2_ctrl_grab(imx208->vflip, enable);
  621. v4l2_ctrl_grab(imx208->hflip, enable);
  622. return ret;
  623. err_rpm_put:
  624. pm_runtime_put(imx208->dev);
  625. mutex_unlock(&imx208->imx208_mx);
  626. return ret;
  627. }
  628. /* Verify chip ID */
  629. static const struct v4l2_subdev_video_ops imx208_video_ops = {
  630. .s_stream = imx208_set_stream,
  631. };
  632. static const struct v4l2_subdev_pad_ops imx208_pad_ops = {
  633. .enum_mbus_code = imx208_enum_mbus_code,
  634. .get_fmt = imx208_get_pad_format,
  635. .set_fmt = imx208_set_pad_format,
  636. .enum_frame_size = imx208_enum_frame_size,
  637. };
  638. static const struct v4l2_subdev_ops imx208_subdev_ops = {
  639. .video = &imx208_video_ops,
  640. .pad = &imx208_pad_ops,
  641. };
  642. static const struct v4l2_subdev_internal_ops imx208_internal_ops = {
  643. .open = imx208_open,
  644. };
  645. static int imx208_read_otp(struct imx208 *imx208)
  646. {
  647. struct i2c_client *client = v4l2_get_subdevdata(&imx208->sd);
  648. struct i2c_msg msgs[2];
  649. u8 addr_buf[2] = { IMX208_OTP_BASE >> 8, IMX208_OTP_BASE & 0xff };
  650. int ret = 0;
  651. mutex_lock(&imx208->imx208_mx);
  652. if (imx208->otp_read)
  653. goto out_unlock;
  654. ret = pm_runtime_resume_and_get(imx208->dev);
  655. if (ret)
  656. goto out_unlock;
  657. ret = imx208_identify_module(imx208);
  658. if (ret)
  659. goto out_pm_put;
  660. /* Write register address */
  661. msgs[0].addr = client->addr;
  662. msgs[0].flags = 0;
  663. msgs[0].len = ARRAY_SIZE(addr_buf);
  664. msgs[0].buf = addr_buf;
  665. /* Read data from registers */
  666. msgs[1].addr = client->addr;
  667. msgs[1].flags = I2C_M_RD;
  668. msgs[1].len = sizeof(imx208->otp_data);
  669. msgs[1].buf = imx208->otp_data;
  670. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  671. if (ret == ARRAY_SIZE(msgs)) {
  672. imx208->otp_read = true;
  673. ret = 0;
  674. }
  675. out_pm_put:
  676. pm_runtime_put(imx208->dev);
  677. out_unlock:
  678. mutex_unlock(&imx208->imx208_mx);
  679. return ret;
  680. }
  681. static ssize_t otp_read(struct file *filp, struct kobject *kobj,
  682. const struct bin_attribute *bin_attr,
  683. char *buf, loff_t off, size_t count)
  684. {
  685. struct i2c_client *client = to_i2c_client(kobj_to_dev(kobj));
  686. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  687. struct imx208 *imx208 = to_imx208(sd);
  688. int ret;
  689. ret = imx208_read_otp(imx208);
  690. if (ret)
  691. return ret;
  692. memcpy(buf, &imx208->otp_data[off], count);
  693. return count;
  694. }
  695. static const BIN_ATTR_RO(otp, IMX208_OTP_SIZE);
  696. /* Initialize control handlers */
  697. static int imx208_init_controls(struct imx208 *imx208)
  698. {
  699. struct v4l2_ctrl_handler *ctrl_hdlr = &imx208->ctrl_handler;
  700. s64 exposure_max;
  701. s64 vblank_def;
  702. s64 vblank_min;
  703. s64 pixel_rate_min;
  704. s64 pixel_rate_max;
  705. int ret;
  706. ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
  707. if (ret)
  708. return ret;
  709. mutex_init(&imx208->imx208_mx);
  710. ctrl_hdlr->lock = &imx208->imx208_mx;
  711. imx208->link_freq =
  712. v4l2_ctrl_new_int_menu(ctrl_hdlr,
  713. &imx208_ctrl_ops,
  714. V4L2_CID_LINK_FREQ,
  715. ARRAY_SIZE(link_freq_menu_items) - 1,
  716. 0, link_freq_menu_items);
  717. if (imx208->link_freq)
  718. imx208->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  719. pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
  720. pixel_rate_min =
  721. link_freq_to_pixel_rate(link_freq_menu_items[ARRAY_SIZE(link_freq_menu_items) - 1]);
  722. /* By default, PIXEL_RATE is read only */
  723. imx208->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx208_ctrl_ops,
  724. V4L2_CID_PIXEL_RATE,
  725. pixel_rate_min, pixel_rate_max,
  726. 1, pixel_rate_max);
  727. vblank_def = imx208->cur_mode->vts_def - imx208->cur_mode->height;
  728. vblank_min = imx208->cur_mode->vts_min - imx208->cur_mode->height;
  729. imx208->vblank =
  730. v4l2_ctrl_new_std(ctrl_hdlr, &imx208_ctrl_ops, V4L2_CID_VBLANK,
  731. vblank_min,
  732. IMX208_VTS_MAX - imx208->cur_mode->height, 1,
  733. vblank_def);
  734. imx208->hblank =
  735. v4l2_ctrl_new_std(ctrl_hdlr, &imx208_ctrl_ops, V4L2_CID_HBLANK,
  736. IMX208_PPL_384MHZ - imx208->cur_mode->width,
  737. IMX208_PPL_384MHZ - imx208->cur_mode->width,
  738. 1,
  739. IMX208_PPL_384MHZ - imx208->cur_mode->width);
  740. if (imx208->hblank)
  741. imx208->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  742. exposure_max = imx208->cur_mode->vts_def - 8;
  743. v4l2_ctrl_new_std(ctrl_hdlr, &imx208_ctrl_ops, V4L2_CID_EXPOSURE,
  744. IMX208_EXPOSURE_MIN, exposure_max,
  745. IMX208_EXPOSURE_STEP, IMX208_EXPOSURE_DEFAULT);
  746. imx208->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx208_ctrl_ops,
  747. V4L2_CID_HFLIP, 0, 1, 1, 0);
  748. if (imx208->hflip)
  749. imx208->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
  750. imx208->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx208_ctrl_ops,
  751. V4L2_CID_VFLIP, 0, 1, 1, 0);
  752. if (imx208->vflip)
  753. imx208->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
  754. v4l2_ctrl_new_std(ctrl_hdlr, &imx208_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
  755. IMX208_ANA_GAIN_MIN, IMX208_ANA_GAIN_MAX,
  756. IMX208_ANA_GAIN_STEP, IMX208_ANA_GAIN_DEFAULT);
  757. v4l2_ctrl_new_custom(ctrl_hdlr, &imx208_digital_gain_control, NULL);
  758. v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx208_ctrl_ops,
  759. V4L2_CID_TEST_PATTERN,
  760. ARRAY_SIZE(imx208_test_pattern_menu) - 1,
  761. 0, 0, imx208_test_pattern_menu);
  762. if (ctrl_hdlr->error) {
  763. ret = ctrl_hdlr->error;
  764. dev_err(imx208->dev, "%s control init failed (%d)\n",
  765. __func__, ret);
  766. goto error;
  767. }
  768. imx208->sd.ctrl_handler = ctrl_hdlr;
  769. return 0;
  770. error:
  771. v4l2_ctrl_handler_free(ctrl_hdlr);
  772. mutex_destroy(&imx208->imx208_mx);
  773. return ret;
  774. }
  775. static void imx208_free_controls(struct imx208 *imx208)
  776. {
  777. v4l2_ctrl_handler_free(imx208->sd.ctrl_handler);
  778. }
  779. static int imx208_probe(struct i2c_client *client)
  780. {
  781. struct imx208 *imx208;
  782. unsigned long freq;
  783. int ret;
  784. bool full_power;
  785. imx208 = devm_kzalloc(&client->dev, sizeof(*imx208), GFP_KERNEL);
  786. if (!imx208)
  787. return -ENOMEM;
  788. imx208->dev = &client->dev;
  789. imx208->clk = devm_v4l2_sensor_clk_get(imx208->dev, NULL);
  790. if (IS_ERR(imx208->clk))
  791. return dev_err_probe(imx208->dev, PTR_ERR(imx208->clk),
  792. "failed to get clock\n");
  793. freq = clk_get_rate(imx208->clk);
  794. if (freq != 19200000)
  795. return dev_err_probe(imx208->dev, -EINVAL,
  796. "external clock %lu is not supported\n",
  797. freq);
  798. /* Initialize subdev */
  799. v4l2_i2c_subdev_init(&imx208->sd, client, &imx208_subdev_ops);
  800. full_power = acpi_dev_state_d0(imx208->dev);
  801. if (full_power) {
  802. /* Check module identity */
  803. ret = imx208_identify_module(imx208);
  804. if (ret) {
  805. dev_err(imx208->dev, "failed to find sensor: %d", ret);
  806. goto error_probe;
  807. }
  808. }
  809. /* Set default mode to max resolution */
  810. imx208->cur_mode = &supported_modes[0];
  811. ret = imx208_init_controls(imx208);
  812. if (ret) {
  813. dev_err(imx208->dev, "failed to init controls: %d", ret);
  814. goto error_probe;
  815. }
  816. /* Initialize subdev */
  817. imx208->sd.internal_ops = &imx208_internal_ops;
  818. imx208->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  819. imx208->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  820. /* Initialize source pad */
  821. imx208->pad.flags = MEDIA_PAD_FL_SOURCE;
  822. ret = media_entity_pads_init(&imx208->sd.entity, 1, &imx208->pad);
  823. if (ret) {
  824. dev_err(imx208->dev, "%s failed:%d\n", __func__, ret);
  825. goto error_handler_free;
  826. }
  827. ret = v4l2_async_register_subdev_sensor(&imx208->sd);
  828. if (ret < 0)
  829. goto error_media_entity;
  830. ret = device_create_bin_file(imx208->dev, &bin_attr_otp);
  831. if (ret) {
  832. dev_err(imx208->dev, "sysfs otp creation failed\n");
  833. goto error_async_subdev;
  834. }
  835. /* Set the device's state to active if it's in D0 state. */
  836. if (full_power)
  837. pm_runtime_set_active(imx208->dev);
  838. pm_runtime_enable(imx208->dev);
  839. pm_runtime_idle(imx208->dev);
  840. return 0;
  841. error_async_subdev:
  842. v4l2_async_unregister_subdev(&imx208->sd);
  843. error_media_entity:
  844. media_entity_cleanup(&imx208->sd.entity);
  845. error_handler_free:
  846. imx208_free_controls(imx208);
  847. error_probe:
  848. mutex_destroy(&imx208->imx208_mx);
  849. return ret;
  850. }
  851. static void imx208_remove(struct i2c_client *client)
  852. {
  853. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  854. struct imx208 *imx208 = to_imx208(sd);
  855. device_remove_bin_file(imx208->dev, &bin_attr_otp);
  856. v4l2_async_unregister_subdev(sd);
  857. media_entity_cleanup(&sd->entity);
  858. imx208_free_controls(imx208);
  859. pm_runtime_disable(imx208->dev);
  860. pm_runtime_set_suspended(imx208->dev);
  861. mutex_destroy(&imx208->imx208_mx);
  862. }
  863. #ifdef CONFIG_ACPI
  864. static const struct acpi_device_id imx208_acpi_ids[] = {
  865. { "INT3478" },
  866. { /* sentinel */ }
  867. };
  868. MODULE_DEVICE_TABLE(acpi, imx208_acpi_ids);
  869. #endif
  870. static struct i2c_driver imx208_i2c_driver = {
  871. .driver = {
  872. .name = "imx208",
  873. .acpi_match_table = ACPI_PTR(imx208_acpi_ids),
  874. },
  875. .probe = imx208_probe,
  876. .remove = imx208_remove,
  877. .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
  878. };
  879. module_i2c_driver(imx208_i2c_driver);
  880. MODULE_AUTHOR("Yeh, Andy <andy.yeh@intel.com>");
  881. MODULE_AUTHOR("Chen, Ping-chung <ping-chung.chen@intel.com>");
  882. MODULE_AUTHOR("Shawn Tu");
  883. MODULE_DESCRIPTION("Sony IMX208 sensor driver");
  884. MODULE_LICENSE("GPL v2");