gc0310.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Support for GalaxyCore GC0310 VGA camera sensor.
  4. *
  5. * Copyright (c) 2013 Intel Corporation. All Rights Reserved.
  6. * Copyright (c) 2023-2025 Hans de Goede <hansg@kernel.org>
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/errno.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/i2c.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/regmap.h>
  16. #include <linux/string.h>
  17. #include <linux/types.h>
  18. #include <media/v4l2-cci.h>
  19. #include <media/v4l2-ctrls.h>
  20. #include <media/v4l2-device.h>
  21. #include <media/v4l2-fwnode.h>
  22. #define GC0310_NATIVE_WIDTH 656
  23. #define GC0310_NATIVE_HEIGHT 496
  24. /*
  25. * The actual PLL output rate is unknown, the datasheet
  26. * says that the formula for the frame-time in pixels is:
  27. * rowtime = win-width + hblank + sh-delay + 4
  28. * frametime = rowtime * (win-height + vblank)
  29. * Filling this in and multiplying by 30 fps gives:
  30. * pixelrate = (660 + 178 + 42 + 4) * (498 + 27) * 30 = 13923000
  31. */
  32. #define GC0310_PIXELRATE 13923000
  33. /* single lane, bus-format is 8 bpp, CSI-2 is double data rate */
  34. #define GC0310_LINK_FREQ (GC0310_PIXELRATE * 8 / 2)
  35. #define GC0310_MCLK_FREQ 19200000
  36. #define GC0310_FPS 30
  37. #define GC0310_SKIP_FRAMES 3
  38. #define GC0310_ID 0xa310
  39. #define GC0310_RESET_RELATED_REG CCI_REG8(0xfe)
  40. #define GC0310_REGISTER_PAGE_0 0x0
  41. #define GC0310_REGISTER_PAGE_3 0x3
  42. /*
  43. * GC0310 System control registers
  44. */
  45. #define GC0310_SW_STREAM_REG CCI_REG8(0x10)
  46. #define GC0310_START_STREAMING 0x94 /* 8-bit enable */
  47. #define GC0310_STOP_STREAMING 0x0 /* 8-bit disable */
  48. #define GC0310_SC_CMMN_CHIP_ID_REG CCI_REG16(0xf0)
  49. #define GC0310_AEC_PK_EXPO_REG CCI_REG16(0x03)
  50. #define GC0310_AGC_ADJ_REG CCI_REG8(0x48)
  51. #define GC0310_DGC_ADJ_REG CCI_REG8(0x71)
  52. #define GC0310_H_CROP_START_REG CCI_REG16(0x09)
  53. #define GC0310_V_CROP_START_REG CCI_REG16(0x0b)
  54. #define GC0310_H_OUTSIZE_REG CCI_REG16(0x0f)
  55. #define GC0310_V_OUTSIZE_REG CCI_REG16(0x0d)
  56. #define GC0310_H_BLANKING_REG CCI_REG16(0x05)
  57. /* Hblank-register + sh-delay + H-crop + 4 (from hw) */
  58. #define GC0310_H_BLANK_DEFAULT (178 + 42 + 4 + 4)
  59. #define GC0310_V_BLANKING_REG CCI_REG16(0x07)
  60. /* Vblank needs an offset compensate for the small V-crop done */
  61. #define GC0310_V_BLANK_OFFSET 2
  62. /* Vsync start time + 1 row vsync + vsync end time + offset */
  63. #define GC0310_V_BLANK_MIN (9 + 1 + 4 + GC0310_V_BLANK_OFFSET)
  64. #define GC0310_V_BLANK_DEFAULT (27 + GC0310_V_BLANK_OFFSET)
  65. #define GC0310_V_BLANK_MAX (4095 - GC0310_NATIVE_HEIGHT)
  66. #define GC0310_SH_DELAY_REG CCI_REG8(0x11)
  67. #define GC0310_VS_START_TIME_REG CCI_REG8(0x12)
  68. #define GC0310_VS_END_TIME_REG CCI_REG8(0x13)
  69. #define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd)
  70. struct gc0310_device {
  71. struct v4l2_subdev sd;
  72. struct media_pad pad;
  73. struct regmap *regmap;
  74. struct gpio_desc *reset;
  75. struct gpio_desc *powerdown;
  76. struct gc0310_ctrls {
  77. struct v4l2_ctrl_handler handler;
  78. struct v4l2_ctrl *exposure;
  79. struct v4l2_ctrl *gain;
  80. struct v4l2_ctrl *link_freq;
  81. struct v4l2_ctrl *pixel_rate;
  82. struct v4l2_ctrl *vblank;
  83. struct v4l2_ctrl *hblank;
  84. } ctrls;
  85. };
  86. struct gc0310_reg {
  87. u8 reg;
  88. u8 val;
  89. };
  90. static const struct reg_sequence gc0310_reset_register[] = {
  91. /* System registers */
  92. { 0xfe, 0xf0 },
  93. { 0xfe, 0xf0 },
  94. { 0xfe, 0x00 },
  95. { 0xfc, 0x0e }, /* 4e */
  96. { 0xfc, 0x0e }, /* 16//4e // [0]apwd [6]regf_clk_gate */
  97. { 0xf2, 0x80 }, /* sync output */
  98. { 0xf3, 0x00 }, /* 1f//01 data output */
  99. { 0xf7, 0x33 }, /* f9 */
  100. { 0xf8, 0x05 }, /* 00 */
  101. { 0xf9, 0x0e }, /* 0x8e //0f */
  102. { 0xfa, 0x11 },
  103. /* MIPI */
  104. { 0xfe, 0x03 },
  105. { 0x01, 0x03 }, /* mipi 1lane */
  106. { 0x02, 0x22 }, /* 0x33 */
  107. { 0x03, 0x94 },
  108. { 0x04, 0x01 }, /* fifo_prog */
  109. { 0x05, 0x00 }, /* fifo_prog */
  110. { 0x06, 0x80 }, /* b0 //YUV ISP data */
  111. { 0x11, 0x2a }, /* 1e //LDI set YUV422 */
  112. { 0x12, 0x90 }, /* 00 //04 //00 //04//00 //LWC[7:0] */
  113. { 0x13, 0x02 }, /* 05 //05 //LWC[15:8] */
  114. { 0x15, 0x12 }, /* 0x10 //DPHYY_MODE read_ready */
  115. { 0x17, 0x01 },
  116. { 0x40, 0x08 },
  117. { 0x41, 0x00 },
  118. { 0x42, 0x00 },
  119. { 0x43, 0x00 },
  120. { 0x21, 0x02 }, /* 0x01 */
  121. { 0x22, 0x02 }, /* 0x01 */
  122. { 0x23, 0x01 }, /* 0x05 //Nor:0x05 DOU:0x06 */
  123. { 0x29, 0x00 },
  124. { 0x2A, 0x25 }, /* 0x05 //data zero 0x7a de */
  125. { 0x2B, 0x02 },
  126. { 0xfe, 0x00 },
  127. /* CISCTL */
  128. { 0x00, 0x2f }, /* 2f//0f//02//01 */
  129. { 0x01, 0x0f }, /* 06 */
  130. { 0x02, 0x04 },
  131. { 0x4f, 0x00 }, /* AEC 0FF */
  132. { 0x03, 0x01 }, /* 0x03 //04 */
  133. { 0x04, 0xc0 }, /* 0xe8 //58 */
  134. { 0x05, 0x00 },
  135. { 0x06, 0xb2 }, /* 0x0a //HB */
  136. /* Vblank (reg 0x07 + 0x08) gets set by the vblank ctrl */
  137. { 0x09, 0x00 }, /* row start */
  138. { 0x0a, 0x00 },
  139. { 0x0b, 0x00 }, /* col start */
  140. { 0x0c, 0x00 },
  141. { 0x0d, 0x01 }, /* height */
  142. { 0x0e, 0xf2 }, /* 0xf7 //height */
  143. { 0x0f, 0x02 }, /* width */
  144. { 0x10, 0x94 }, /* 0xa0 //height */
  145. { 0x17, 0x14 },
  146. { 0x18, 0x1a }, /* 0a//[4]double reset */
  147. { 0x19, 0x14 }, /* AD pipeline */
  148. { 0x1b, 0x48 },
  149. { 0x1e, 0x6b }, /* 3b//col bias */
  150. { 0x1f, 0x28 }, /* 20//00//08//txlow */
  151. { 0x20, 0x89 }, /* 88//0c//[3:2]DA15 */
  152. { 0x21, 0x49 }, /* 48//[3] txhigh */
  153. { 0x22, 0xb0 },
  154. { 0x23, 0x04 }, /* [1:0]vcm_r */
  155. { 0x24, 0x16 }, /* 15 */
  156. { 0x34, 0x20 }, /* [6:4] rsg high//range */
  157. /* BLK */
  158. { 0x26, 0x23 }, /* [1]dark_current_en [0]offset_en */
  159. { 0x28, 0xff }, /* BLK_limie_value */
  160. { 0x29, 0x00 }, /* global offset */
  161. { 0x33, 0x18 }, /* offset_ratio */
  162. { 0x37, 0x20 }, /* dark_current_ratio */
  163. { 0x2a, 0x00 },
  164. { 0x2b, 0x00 },
  165. { 0x2c, 0x00 },
  166. { 0x2d, 0x00 },
  167. { 0x2e, 0x00 },
  168. { 0x2f, 0x00 },
  169. { 0x30, 0x00 },
  170. { 0x31, 0x00 },
  171. { 0x47, 0x80 }, /* a7 */
  172. { 0x4e, 0x66 }, /* select_row */
  173. { 0xa8, 0x02 }, /* win_width_dark, same with crop_win_width */
  174. { 0xa9, 0x80 },
  175. /* ISP */
  176. { 0x40, 0x06 }, /* 0xff //ff //48 */
  177. { 0x41, 0x00 }, /* 0x21 //00//[0]curve_en */
  178. { 0x42, 0x04 }, /* 0xcf //0a//[1]awn_en */
  179. { 0x44, 0x18 }, /* 0x18 //02 */
  180. { 0x46, 0x02 }, /* 0x03 //sync */
  181. { 0x49, 0x03 },
  182. { 0x4c, 0x20 }, /* 00[5]pretect exp */
  183. { 0x50, 0x01 }, /* crop enable */
  184. { 0x51, 0x00 },
  185. { 0x52, 0x00 },
  186. { 0x53, 0x00 },
  187. { 0x54, 0x01 },
  188. { 0x55, 0x01 }, /* crop window height */
  189. { 0x56, 0xf0 },
  190. { 0x57, 0x02 }, /* crop window width */
  191. { 0x58, 0x90 },
  192. /* Gain */
  193. { 0x70, 0x70 }, /* 70 //80//global gain */
  194. { 0x71, 0x20 }, /* pregain gain */
  195. { 0x72, 0x40 }, /* post gain */
  196. { 0x5a, 0x84 }, /* 84//analog gain 0 */
  197. { 0x5b, 0xc9 }, /* c9 */
  198. { 0x5c, 0xed }, /* ed//not use pga gain highest level */
  199. { 0x77, 0x40 }, /* R gain 0x74 //awb gain */
  200. { 0x78, 0x40 }, /* G gain */
  201. { 0x79, 0x40 }, /* B gain 0x5f */
  202. { 0x48, 0x00 },
  203. { 0xfe, 0x01 },
  204. { 0x0a, 0x45 }, /* [7]col gain mode */
  205. { 0x3e, 0x40 },
  206. { 0x3f, 0x5c },
  207. { 0x40, 0x7b },
  208. { 0x41, 0xbd },
  209. { 0x42, 0xf6 },
  210. { 0x43, 0x63 },
  211. { 0x03, 0x60 },
  212. { 0x44, 0x03 },
  213. /* Dark / Sun mode related */
  214. { 0xfe, 0x01 },
  215. { 0x45, 0xa4 }, /* 0xf7 */
  216. { 0x46, 0xf0 }, /* 0xff //f0//sun value th */
  217. { 0x48, 0x03 }, /* sun mode */
  218. { 0x4f, 0x60 }, /* sun_clamp */
  219. { 0xfe, 0x00 },
  220. };
  221. static const struct reg_sequence gc0310_VGA_30fps[] = {
  222. { 0xfe, 0x00 },
  223. { 0x0d, 0x01 }, /* height */
  224. { 0x0e, 0xf2 }, /* 0xf7 //height */
  225. { 0x0f, 0x02 }, /* width */
  226. { 0x10, 0x94 }, /* 0xa0 //height */
  227. { 0x50, 0x01 }, /* crop enable */
  228. { 0x51, 0x00 },
  229. { 0x52, 0x00 },
  230. { 0x53, 0x00 },
  231. { 0x54, 0x01 },
  232. { 0x55, 0x01 }, /* crop window height */
  233. { 0x56, 0xf0 },
  234. { 0x57, 0x02 }, /* crop window width */
  235. { 0x58, 0x90 },
  236. { 0xfe, 0x03 },
  237. { 0x12, 0x90 }, /* 00 //04 //00 //04//00 //LWC[7:0] */
  238. { 0x13, 0x02 }, /* 05 //05 //LWC[15:8] */
  239. { 0xfe, 0x00 },
  240. };
  241. static const s64 link_freq_menu_items[] = {
  242. GC0310_LINK_FREQ,
  243. };
  244. static int gc0310_gain_set(struct gc0310_device *sensor, u32 gain)
  245. {
  246. u8 again, dgain;
  247. int ret = 0;
  248. /* Taken from original driver, this never sets dgain lower then 32? */
  249. /* Change 0 - 95 to 32 - 127 */
  250. gain += 32;
  251. if (gain < 64) {
  252. again = 0x0; /* sqrt(2) */
  253. dgain = gain;
  254. } else {
  255. again = 0x2; /* 2 * sqrt(2) */
  256. dgain = gain / 2;
  257. }
  258. cci_write(sensor->regmap, GC0310_AGC_ADJ_REG, again, &ret);
  259. cci_write(sensor->regmap, GC0310_DGC_ADJ_REG, dgain, &ret);
  260. return ret;
  261. }
  262. static int gc0310_exposure_update_range(struct gc0310_device *sensor)
  263. {
  264. int exp_max = GC0310_NATIVE_HEIGHT + sensor->ctrls.vblank->val;
  265. return __v4l2_ctrl_modify_range(sensor->ctrls.exposure, 0, exp_max,
  266. 1, exp_max);
  267. }
  268. static int gc0310_s_ctrl(struct v4l2_ctrl *ctrl)
  269. {
  270. struct gc0310_device *sensor =
  271. container_of(ctrl->handler, struct gc0310_device, ctrls.handler);
  272. int ret;
  273. /* Update exposure range on vblank changes */
  274. if (ctrl->id == V4L2_CID_VBLANK) {
  275. ret = gc0310_exposure_update_range(sensor);
  276. if (ret)
  277. return ret;
  278. }
  279. /* Only apply changes to the controls if the device is powered up */
  280. if (!pm_runtime_get_if_in_use(sensor->sd.dev))
  281. return 0;
  282. switch (ctrl->id) {
  283. case V4L2_CID_EXPOSURE:
  284. ret = cci_write(sensor->regmap, GC0310_AEC_PK_EXPO_REG,
  285. ctrl->val, NULL);
  286. break;
  287. case V4L2_CID_ANALOGUE_GAIN:
  288. ret = gc0310_gain_set(sensor, ctrl->val);
  289. break;
  290. case V4L2_CID_VBLANK:
  291. ret = cci_write(sensor->regmap, GC0310_V_BLANKING_REG,
  292. ctrl->val - GC0310_V_BLANK_OFFSET,
  293. NULL);
  294. break;
  295. default:
  296. ret = -EINVAL;
  297. break;
  298. }
  299. pm_runtime_put(sensor->sd.dev);
  300. return ret;
  301. }
  302. static const struct v4l2_ctrl_ops ctrl_ops = {
  303. .s_ctrl = gc0310_s_ctrl,
  304. };
  305. /* The GC0310 currently only supports 1 fixed fmt */
  306. static void gc0310_fill_format(struct v4l2_mbus_framefmt *fmt)
  307. {
  308. memset(fmt, 0, sizeof(*fmt));
  309. fmt->width = GC0310_NATIVE_WIDTH;
  310. fmt->height = GC0310_NATIVE_HEIGHT;
  311. fmt->field = V4L2_FIELD_NONE;
  312. fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
  313. }
  314. static int gc0310_get_selection(struct v4l2_subdev *sd,
  315. struct v4l2_subdev_state *state,
  316. struct v4l2_subdev_selection *sel)
  317. {
  318. /* Only the single fixed 656x496 mode is supported, without croping */
  319. switch (sel->target) {
  320. case V4L2_SEL_TGT_CROP:
  321. case V4L2_SEL_TGT_CROP_BOUNDS:
  322. case V4L2_SEL_TGT_CROP_DEFAULT:
  323. case V4L2_SEL_TGT_NATIVE_SIZE:
  324. sel->r.top = 0;
  325. sel->r.left = 0;
  326. sel->r.width = GC0310_NATIVE_WIDTH;
  327. sel->r.height = GC0310_NATIVE_HEIGHT;
  328. break;
  329. default:
  330. return -EINVAL;
  331. }
  332. return 0;
  333. }
  334. static int gc0310_power_off(struct device *dev)
  335. {
  336. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  337. struct gc0310_device *sensor = to_gc0310_sensor(sd);
  338. gpiod_set_value_cansleep(sensor->powerdown, 1);
  339. gpiod_set_value_cansleep(sensor->reset, 1);
  340. return 0;
  341. }
  342. static int gc0310_power_on(struct device *dev)
  343. {
  344. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  345. struct gc0310_device *sensor = to_gc0310_sensor(sd);
  346. fsleep(10 * USEC_PER_MSEC);
  347. gpiod_set_value_cansleep(sensor->reset, 0);
  348. fsleep(10 * USEC_PER_MSEC);
  349. gpiod_set_value_cansleep(sensor->powerdown, 0);
  350. fsleep(10 * USEC_PER_MSEC);
  351. return 0;
  352. }
  353. static int gc0310_detect(struct gc0310_device *sensor)
  354. {
  355. struct i2c_client *client = v4l2_get_subdevdata(&sensor->sd);
  356. u64 val;
  357. int ret;
  358. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
  359. return -ENODEV;
  360. ret = cci_read(sensor->regmap, GC0310_SC_CMMN_CHIP_ID_REG, &val, NULL);
  361. if (ret < 0) {
  362. dev_err(&client->dev, "read sensor_id failed: %d\n", ret);
  363. return -ENODEV;
  364. }
  365. dev_dbg(&client->dev, "sensor ID = 0x%llx\n", val);
  366. if (val != GC0310_ID) {
  367. dev_err(&client->dev, "sensor ID error, read id = 0x%llx, target id = 0x%x\n",
  368. val, GC0310_ID);
  369. return -ENODEV;
  370. }
  371. dev_dbg(&client->dev, "detect gc0310 success\n");
  372. return 0;
  373. }
  374. static int gc0310_enable_streams(struct v4l2_subdev *sd,
  375. struct v4l2_subdev_state *state,
  376. u32 pad, u64 streams_mask)
  377. {
  378. struct gc0310_device *sensor = to_gc0310_sensor(sd);
  379. struct i2c_client *client = v4l2_get_subdevdata(sd);
  380. int ret;
  381. ret = pm_runtime_resume_and_get(&client->dev);
  382. if (ret)
  383. return ret;
  384. ret = regmap_multi_reg_write(sensor->regmap,
  385. gc0310_reset_register,
  386. ARRAY_SIZE(gc0310_reset_register));
  387. if (ret)
  388. goto error_power_down;
  389. ret = regmap_multi_reg_write(sensor->regmap,
  390. gc0310_VGA_30fps,
  391. ARRAY_SIZE(gc0310_VGA_30fps));
  392. if (ret)
  393. goto error_power_down;
  394. /* restore value of all ctrls */
  395. ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
  396. /* enable per frame MIPI and sensor ctrl reset */
  397. cci_write(sensor->regmap, GC0310_RESET_RELATED_REG, 0x30, &ret);
  398. cci_write(sensor->regmap, GC0310_RESET_RELATED_REG,
  399. GC0310_REGISTER_PAGE_3, &ret);
  400. cci_write(sensor->regmap, GC0310_SW_STREAM_REG,
  401. GC0310_START_STREAMING, &ret);
  402. cci_write(sensor->regmap, GC0310_RESET_RELATED_REG,
  403. GC0310_REGISTER_PAGE_0, &ret);
  404. error_power_down:
  405. if (ret)
  406. pm_runtime_put(&client->dev);
  407. return ret;
  408. }
  409. static int gc0310_disable_streams(struct v4l2_subdev *sd,
  410. struct v4l2_subdev_state *state,
  411. u32 pad, u64 streams_mask)
  412. {
  413. struct gc0310_device *sensor = to_gc0310_sensor(sd);
  414. struct i2c_client *client = v4l2_get_subdevdata(sd);
  415. int ret = 0;
  416. cci_write(sensor->regmap, GC0310_RESET_RELATED_REG,
  417. GC0310_REGISTER_PAGE_3, &ret);
  418. cci_write(sensor->regmap, GC0310_SW_STREAM_REG,
  419. GC0310_STOP_STREAMING, &ret);
  420. cci_write(sensor->regmap, GC0310_RESET_RELATED_REG,
  421. GC0310_REGISTER_PAGE_0, &ret);
  422. pm_runtime_put(&client->dev);
  423. return ret;
  424. }
  425. static int gc0310_enum_mbus_code(struct v4l2_subdev *sd,
  426. struct v4l2_subdev_state *sd_state,
  427. struct v4l2_subdev_mbus_code_enum *code)
  428. {
  429. /* We support only a single format */
  430. if (code->index)
  431. return -EINVAL;
  432. code->code = MEDIA_BUS_FMT_SGRBG8_1X8;
  433. return 0;
  434. }
  435. static int gc0310_enum_frame_size(struct v4l2_subdev *sd,
  436. struct v4l2_subdev_state *sd_state,
  437. struct v4l2_subdev_frame_size_enum *fse)
  438. {
  439. /* We support only a single resolution */
  440. if (fse->index)
  441. return -EINVAL;
  442. fse->min_width = GC0310_NATIVE_WIDTH;
  443. fse->max_width = GC0310_NATIVE_WIDTH;
  444. fse->min_height = GC0310_NATIVE_HEIGHT;
  445. fse->max_height = GC0310_NATIVE_HEIGHT;
  446. return 0;
  447. }
  448. static const struct v4l2_subdev_video_ops gc0310_video_ops = {
  449. .s_stream = v4l2_subdev_s_stream_helper,
  450. };
  451. static const struct v4l2_subdev_pad_ops gc0310_pad_ops = {
  452. .enum_mbus_code = gc0310_enum_mbus_code,
  453. .enum_frame_size = gc0310_enum_frame_size,
  454. .get_fmt = v4l2_subdev_get_fmt,
  455. .set_fmt = v4l2_subdev_get_fmt, /* Only 1 fixed mode supported */
  456. .get_selection = gc0310_get_selection,
  457. .set_selection = gc0310_get_selection,
  458. .enable_streams = gc0310_enable_streams,
  459. .disable_streams = gc0310_disable_streams,
  460. };
  461. static const struct v4l2_subdev_ops gc0310_ops = {
  462. .video = &gc0310_video_ops,
  463. .pad = &gc0310_pad_ops,
  464. };
  465. static int gc0310_init_state(struct v4l2_subdev *sd,
  466. struct v4l2_subdev_state *sd_state)
  467. {
  468. gc0310_fill_format(v4l2_subdev_state_get_format(sd_state, 0));
  469. return 0;
  470. }
  471. static const struct v4l2_subdev_internal_ops gc0310_internal_ops = {
  472. .init_state = gc0310_init_state,
  473. };
  474. static int gc0310_init_controls(struct gc0310_device *sensor)
  475. {
  476. struct i2c_client *client = v4l2_get_subdevdata(&sensor->sd);
  477. struct v4l2_ctrl_handler *hdl = &sensor->ctrls.handler;
  478. struct v4l2_fwnode_device_properties props;
  479. int exp_max, ret;
  480. v4l2_ctrl_handler_init(hdl, 8);
  481. /* Use the same lock for controls as for everything else */
  482. sensor->sd.ctrl_handler = hdl;
  483. exp_max = GC0310_NATIVE_HEIGHT + GC0310_V_BLANK_DEFAULT;
  484. sensor->ctrls.exposure =
  485. v4l2_ctrl_new_std(hdl, &ctrl_ops, V4L2_CID_EXPOSURE, 0,
  486. exp_max, 1, exp_max);
  487. /* 32 steps at base gain 1 + 64 half steps at base gain 2 */
  488. sensor->ctrls.gain =
  489. v4l2_ctrl_new_std(hdl, &ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 0, 95, 1, 31);
  490. sensor->ctrls.link_freq =
  491. v4l2_ctrl_new_int_menu(hdl, NULL, V4L2_CID_LINK_FREQ,
  492. 0, 0, link_freq_menu_items);
  493. sensor->ctrls.pixel_rate =
  494. v4l2_ctrl_new_std(hdl, NULL, V4L2_CID_PIXEL_RATE, 0,
  495. GC0310_PIXELRATE, 1, GC0310_PIXELRATE);
  496. sensor->ctrls.vblank =
  497. v4l2_ctrl_new_std(hdl, &ctrl_ops, V4L2_CID_VBLANK,
  498. GC0310_V_BLANK_MIN,
  499. GC0310_V_BLANK_MAX, 1,
  500. GC0310_V_BLANK_DEFAULT);
  501. sensor->ctrls.hblank =
  502. v4l2_ctrl_new_std(hdl, NULL, V4L2_CID_HBLANK,
  503. GC0310_H_BLANK_DEFAULT,
  504. GC0310_H_BLANK_DEFAULT, 1,
  505. GC0310_H_BLANK_DEFAULT);
  506. ret = v4l2_fwnode_device_parse(&client->dev, &props);
  507. if (ret)
  508. return ret;
  509. v4l2_ctrl_new_fwnode_properties(hdl, &ctrl_ops, &props);
  510. if (hdl->error)
  511. return hdl->error;
  512. sensor->ctrls.pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  513. sensor->ctrls.link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  514. sensor->ctrls.hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  515. return 0;
  516. }
  517. static void gc0310_remove(struct i2c_client *client)
  518. {
  519. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  520. struct gc0310_device *sensor = to_gc0310_sensor(sd);
  521. v4l2_async_unregister_subdev(sd);
  522. v4l2_subdev_cleanup(sd);
  523. media_entity_cleanup(&sensor->sd.entity);
  524. v4l2_ctrl_handler_free(&sensor->ctrls.handler);
  525. pm_runtime_disable(&client->dev);
  526. if (!pm_runtime_status_suspended(&client->dev)) {
  527. gc0310_power_off(&client->dev);
  528. pm_runtime_set_suspended(&client->dev);
  529. }
  530. }
  531. static int gc0310_check_hwcfg(struct device *dev)
  532. {
  533. struct v4l2_fwnode_endpoint bus_cfg = {
  534. .bus_type = V4L2_MBUS_CSI2_DPHY,
  535. };
  536. struct fwnode_handle *ep_fwnode;
  537. unsigned long link_freq_bitmap;
  538. u32 mclk;
  539. int ret;
  540. /*
  541. * Sometimes the fwnode graph is initialized by the bridge driver.
  542. * Bridge drivers doing this may also add GPIO mappings, wait for this.
  543. */
  544. ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0);
  545. if (!ep_fwnode)
  546. return dev_err_probe(dev, -EPROBE_DEFER,
  547. "waiting for fwnode graph endpoint\n");
  548. ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
  549. &mclk);
  550. if (ret) {
  551. fwnode_handle_put(ep_fwnode);
  552. return dev_err_probe(dev, ret,
  553. "reading clock-frequency property\n");
  554. }
  555. if (mclk != GC0310_MCLK_FREQ) {
  556. fwnode_handle_put(ep_fwnode);
  557. return dev_err_probe(dev, -EINVAL,
  558. "external clock %u is not supported\n",
  559. mclk);
  560. }
  561. ret = v4l2_fwnode_endpoint_alloc_parse(ep_fwnode, &bus_cfg);
  562. fwnode_handle_put(ep_fwnode);
  563. if (ret)
  564. return dev_err_probe(dev, ret, "parsing endpoint failed\n");
  565. ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
  566. bus_cfg.nr_of_link_frequencies,
  567. link_freq_menu_items,
  568. ARRAY_SIZE(link_freq_menu_items),
  569. &link_freq_bitmap);
  570. if (ret == 0 && bus_cfg.bus.mipi_csi2.num_data_lanes != 1)
  571. ret = dev_err_probe(dev, -EINVAL,
  572. "number of CSI2 data lanes %u is not supported\n",
  573. bus_cfg.bus.mipi_csi2.num_data_lanes);
  574. v4l2_fwnode_endpoint_free(&bus_cfg);
  575. return ret;
  576. }
  577. static int gc0310_probe(struct i2c_client *client)
  578. {
  579. struct gc0310_device *sensor;
  580. int ret;
  581. ret = gc0310_check_hwcfg(&client->dev);
  582. if (ret)
  583. return ret;
  584. sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);
  585. if (!sensor)
  586. return -ENOMEM;
  587. sensor->reset = devm_gpiod_get(&client->dev, "reset", GPIOD_OUT_HIGH);
  588. if (IS_ERR(sensor->reset)) {
  589. return dev_err_probe(&client->dev, PTR_ERR(sensor->reset),
  590. "getting reset GPIO\n");
  591. }
  592. sensor->powerdown = devm_gpiod_get(&client->dev, "powerdown", GPIOD_OUT_HIGH);
  593. if (IS_ERR(sensor->powerdown)) {
  594. return dev_err_probe(&client->dev, PTR_ERR(sensor->powerdown),
  595. "getting powerdown GPIO\n");
  596. }
  597. v4l2_i2c_subdev_init(&sensor->sd, client, &gc0310_ops);
  598. sensor->regmap = devm_cci_regmap_init_i2c(client, 8);
  599. if (IS_ERR(sensor->regmap))
  600. return PTR_ERR(sensor->regmap);
  601. gc0310_power_on(&client->dev);
  602. pm_runtime_set_active(&client->dev);
  603. pm_runtime_get_noresume(&client->dev);
  604. pm_runtime_enable(&client->dev);
  605. ret = gc0310_detect(sensor);
  606. if (ret)
  607. goto err_power_down;
  608. sensor->sd.internal_ops = &gc0310_internal_ops;
  609. sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  610. sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
  611. sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  612. ret = gc0310_init_controls(sensor);
  613. if (ret)
  614. goto err_power_down;
  615. ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
  616. if (ret)
  617. goto err_power_down;
  618. sensor->sd.state_lock = sensor->ctrls.handler.lock;
  619. ret = v4l2_subdev_init_finalize(&sensor->sd);
  620. if (ret)
  621. goto err_power_down;
  622. ret = v4l2_async_register_subdev_sensor(&sensor->sd);
  623. if (ret)
  624. goto err_power_down;
  625. pm_runtime_set_autosuspend_delay(&client->dev, 1000);
  626. pm_runtime_use_autosuspend(&client->dev);
  627. pm_runtime_put_autosuspend(&client->dev);
  628. return 0;
  629. err_power_down:
  630. pm_runtime_put_noidle(&client->dev);
  631. gc0310_remove(client);
  632. return ret;
  633. }
  634. static DEFINE_RUNTIME_DEV_PM_OPS(gc0310_pm_ops,
  635. gc0310_power_off, gc0310_power_on, NULL);
  636. static const struct acpi_device_id gc0310_acpi_match[] = {
  637. {"INT0310"},
  638. {},
  639. };
  640. MODULE_DEVICE_TABLE(acpi, gc0310_acpi_match);
  641. static struct i2c_driver gc0310_driver = {
  642. .driver = {
  643. .name = "gc0310",
  644. .pm = pm_sleep_ptr(&gc0310_pm_ops),
  645. .acpi_match_table = gc0310_acpi_match,
  646. },
  647. .probe = gc0310_probe,
  648. .remove = gc0310_remove,
  649. };
  650. module_i2c_driver(gc0310_driver);
  651. MODULE_AUTHOR("Lai, Angie <angie.lai@intel.com>");
  652. MODULE_AUTHOR("Hans de Goede <hansg@kernel.org>");
  653. MODULE_DESCRIPTION("A low-level driver for GalaxyCore GC0310 sensors");
  654. MODULE_LICENSE("GPL");